SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 Fault-Protected RS-485 Transceivers With Extended Common-Mode Range Check for Samples: SN65HVD1785, SN65HVD1786, SN65HVD1787, SN65HVD1791, SN65HVD1792, SN65HVD1793 FEATURES 1 * * * * Bus-Pin Fault Protection to: - > 70 V ('HVD1785, 86,91,92) - > 30 V ('HVD1787, 93) Common-Mode Voltage Range (-20 V to 25 V) More Than Doubles TIA/EIA 485 Requirement Bus I/O Protection - 16 kV JEDEC HBM Protection Reduced Unit Load for Up to 256 Nodes * * * Failsafe Receiver for Open-Circuit, Short-Circuit and Idle-Bus Conditions Low Power Consumption - Low Standby Supply Current, 1 mA Typ - ICC 5 mA Quiescent During Operation Power-Up, Power-Down Glitch-Free Operation APPLICATIONS * Designed for RS-485 and RS-422 Networks DESCRIPTION These devices are designed to survive overvoltage faults such as direct shorts to power supplies, mis-wiring faults, connector failures, cable crushes, and tool mis-applications. They are also robust to ESD events, with high levels of protection to human-body model specifications. These devices combine a differential driver and a differential receiver, which operate from a single power supply. In the 'HVD1785, 'HVD1786, and 'HVD1787, the driver differential outputs and the receiver differential inputs are connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. In the 'HVD1793, the driver differential outputs and the receiver differential inputs are separate pins, to form a bus port suitable for full-duplex (four-wire bus) communication. These ports feature a wide common-mode voltage range, making the devices suitable for multipoint applications over long cable runs. These devices are characterized from -40C to 105C. For similar features with 3.3 V supply operation, see the SN65HVD1781 (SLLS877). VFAULT up to 70 V M0092-01 PRODUCT SELECTION GUIDE PART NUMBER DUPLEX SIGNALING RATE NODES CABLE LENGTH SN65HVD1785 Half 115 kbps Up to 256 1500 m SN65HVD1786 Half 1 Mbps Up to 256 150 m SN65HVD1787 Half 10 Mbps Up to 64 50 m SN65HVD1791 Full 115 kbps Up to 256 1500 m SN65HVD1792 Full 1 Mbps Up to 256 150 m SN65HVD1793 Full 10 Mbps Up to 64 50 m 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2010, Texas Instruments Incorporated SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION DRIVER FUNCTION TABLE Input Enable Outputs D DE A H H H L Actively drive bus high L H L H Actively drive bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus high by default B RECEIVER FUNCTION TABLE Differential Input Enable Output VID = VA - VB RE R VIT+ < VID L H Receive valid bus high VIT- < VID < VIT+ L ? Indeterminate bus state VID < VIT- L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Fail-safe high output Short-circuit bus L H Fail-safe high output Idle (terminated) bus L H Fail-safe high output SN65HVD1785, 1786, 1787 D or P Package (Top View) SN65HVD1791, 1792, 1793 D Package (Top View) NC 1 14 VCC R 2 13 VCC A RE 3 12 A GND DE 4 11 B D 5 10 Z GND 6 9 Y GND 7 8 NC R 1 8 VCC RE 2 7 B DE 3 6 D 4 5 P0066-02 Logic Diagram (Positive Logic) DE D RE R 3 NC - No internal connection Pins 6 and 7 are connected together internally. Pins 13 and 14 are connected together internally. 4 2 6 1 7 A Bus Logic Diagram (Positive Logic) B S0299-01 DE D RE R 4 9 5 10 Y Z 3 12 2 11 A B S0300-01 2 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage V A, B pins -70 to 70 V 'HVD1787 A, B pins -70 to 30 V 'HVD1793 Y, Z pins -70 to 30 V -0.3 to VCC + 0.3 V Input voltage range at any logic pin Transient overvoltage pulse through 100 per TIA-485 -100 to 100 V -24 to 24 mA 170 C Receiver output current Junction temperature See Dissipation Rating Table Continuous total power dissipation IEC 60749-26 ESD (human-body model), bus terminals and GND 16 kV JEDEC Standard 22, Test Method A114 (human-body model), bus terminals and GND 16 kV JEDEC Standard 22, Test Method A114 (human-body model), all pins 4 kV JEDEC Standard 22, Test Method C101 (charged-device model), all pins 2 kV 400 V JEDEC Standard 22, Test Method A115 (machine model), all pins (1) UNIT 'HVD1785, 86, 91, 92, 93 Voltage range at bus pins TJ VALUE -0.5 to 7 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATINGS PACKAGE JEDEC THERMAL MODEL TA < 25C RATING DERATING FACTOR ABOVE TA = 25C TA = 85C RATING TA = 105C RATING High-K 905 mW 7.25 mW/C 470 mW 325 mW Low-K 516 mW 4.1 mW/C 268 mW 186 mW High-K 1315 mW 10.5 mW/C 684 mW 474 mW SOIC (D) 8-pin SOIC (D) 14-pin PDIP (P) 8-pin Low-K 744 mW 6 mW/C 387 mW 268 mW High-K 2119 mW 16.9 mW/C 1100 mW 763 mW Low-K 976 mW 7.8 mW/C 508 mW 352 mW RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 5 UNIT VCC Supply voltage 4.5 5.5 V VI Input voltage at any bus terminal (separately or common mode) (1) -20 25 V VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V VID Differential input voltage -25 25 V Output current, driver -60 60 mA Output current, receiver -8 8 mA RL Differential load resistance 54 CL Differential load capacitance IO HVD1785, HVD1791 1/tUI Signaling rate 60 50 pF 115 HVD1786, HVD1792 1 HVD1787, HVD1793 10 TA Operating free-air temperature (see application section for thermal information) -40 105 TJ Junction temperature -40 150 (1) kbps Mbps C C By convention, the least positive (most negative) limit is designated as minimum in this data sheet. Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 3 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Driver differential output voltage magnitude TEST CONDITIONS RS-485 with common-mode load, VCC > 4.75 V, see Figure 1 MIN TA 85C 1.5 TA 105C 1.4 RL = 54 , 4.75 V VCC 5.25 V RL = 100 , 4.75 V VCC 5.25 V |VOD| Change in magnitude of driver differential output RL = 54 voltage VOC(SS) Steady-state common-mode output voltage VOC Change in differential driver output common-mode voltage VOC(PP) Peak-to-peak driver common-mode output voltage COD Differential output capacitance VIT+ Positive-going receiver differential input voltage threshold VIT- Negative-going receiver differential input voltage threshold VHYS Receiver differential input voltage threshold hysteresis (VIT+ - VIT-) VOH Receiver high-level output voltage IOH = -8 mA Receiver low-level output voltage II Driver input, driver enable, and receiver enable input current IOZ Receiver output high-impedance current IOS Driver short-circuit output current II ICC Bus input current (disabled driver) Supply current (quiescent) Supply current (dynamic) 4 Submit Documentation Feedback IOL = 8 mA 2 2 2.5 -0.2 0 0.2 V 1 VCC/2 3 V -100 0 100 mV 500 mV 23 pF -10 mV -200 -150 mV 30 50 mV 2.4 VCC - 0.3 V 4 TA 85C 0.2 0.4 TA 105C 0.2 0.5 VO = 0 V or VCC, RE at VCC 85, 86, 91, 92 100 mA -1 1 mA 250 mA 87, 93 VI = 12 V VI = -7 V 75 -100 125 -40 VI = 12 V VI = -7 V V -100 -250 VCC = 4.5 to 5.5 V or VCC = 0 V, DE at 0 V UNIT V -100 VCM = -20 V to 25 V MAX 1.5 Center of two 27- load resistors, See Figure 2 IOH = -400 mA VOL TYP 500 mA -400 Driver and receiver enabled DE = VCC, RE = GND, no load 4 6 Driver enabled, receiver disabled DE = VCC, RE = VCC, no load 3 5 Driver disabled, receiver enabled DE = GND, RE = GND, no load 2 4 Driver and receiver disabled DE = GND, D = open RE = VCC, no load 0.5 5 mA mA See TYPICAL CHARACTERISTICS section Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.4 1.7 2.6 ms 0.8 2 ms 20 250 ns 0.1 5 ms DRIVER (HVD1785 AND HVD1791) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL - tPLH| tPHZ, tPLZ Driver disable time tPZH, tPZL Driver enable time RL = 54 , CL = 50 pF, See Figure 3 Receiver enabled See Figure 4 and Figure 5 Receiver disabled 0.2 3 3 12 ms DRIVER (HVD1786 AND HVD1792) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL - tPLH| tPHZ, tPLZ Driver disable time 50 RL = 54 , CL = 50 pF, See Figure 3 Receiver enabled tPZH, tPZL Driver enable time See Figure 4 and Figure 5 Receiver disabled Receiver enabled VCM > VCC 300 ns 200 ns 25 ns 3 ms 300 ns 10 ms 500 ns DRIVER (HVD1787 AND HVD1793) tr, tf Driver differential output rise/fall time tPHL, tPLH Driver propagation delay tSK(P) Driver differential output pulse skew, |tPHL - tPLH| tPHZ, tPLZ Driver disable time 3 RL = 54 , CL = 50 pF, See Figure 3 Receiver enabled tPZH, tPZL Driver enable time See Figure 4 and Figure 5 Receiver disabled Receiver enabled 30 ns 50 ns 10 ns 3 ms 300 ns 9 ms VCM > VCC 500 ns 4 15 85, 86, 91, 92 100 200 RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED) tr, tf Receiver output rise/fall time tPHL, tPLH Receiver propagation delay time tSK(P) Receiver output pulse skew, |tPHL - tPLH| tPLZ, tPHZ Receiver disable time tPZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time Copyright (c) 2008-2010, Texas Instruments Incorporated CL = 15 pF, See Figure 6 87, 93 85, 86, 91, 92 70 6 87, 93 20 5 ns ns ns Driver enabled, See Figure 7 15 100 Driver enabled, See Figure 7 80 300 ns Driver disabled, See Figure 8 3 9 ms Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 ns 5 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com THERMAL INFORMATION PARAMETER TEST CONDITIONS SOIC-8 RqJA Junction-to-ambient thermal resistance (no airflow) DIP-8 SOIC-14 RqJB Junction-to-board thermal resistance RqJC Junction-to-case thermal resistance JEDEC low-K model 242 JEDEC high-K model 59 JEDEC low-K model 128 JEDEC high-K model 95 JEDEC low-K model 168 62 DIP-8 39 SOIC-14 40 SOIC-8 61 DIP-8 61 SOIC-14 44 85, 91 86 Power dissipation 138 SOIC-8 85, 91 PD VALUE JEDEC high-K model VCC = 5.5 V, TJ = 150C, RL = 300 , CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, unterminated (1) UNIT C/W C/W C/W 290 VCC = 5.5 V, TJ = 150C, RL = 100 , CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, RS-422 load (1) 320 mW 87 85, 91 86 VCC = 5.5 V, TJ = 150C, RL = 54 , CL = 50 pF (driver), CL = 15 pF (receiver) 5-V supply, RS-485 load (1) 400 87 TSD (1) Thermal-shutdown junction temperature 170 C Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: HVD1785, 1791 at 115 kbps, HVD1786 at 1 Mbps, HVD1787 at 10 Mbps) PARAMETER MEASUREMENT INFORMATION Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 . 375 W 1% VCC DE 0 V or 3 V D A VOD 60 W 1% B + _ -20 V < V(test) < 25 V 375 W 1% S0301-01 Figure 1. Measurement of Driver Differential Output Voltage With Common-Mode Load VCC DE Input 27 W 1% A D A VA B VB VOC(PP) VOC B 27 W 1% CL = 50 pF 20% DVOC(SS) VOC CL Includes Fixture and Instrumentation Capacitance S0302-01 Figure 2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load 6 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION (continued) 3V VCC DE D Input Generator VI CL = 50 pF 20% A VOD 50 W B VI RL = 54 W 1% CL Includes Fixture and Instrumentation Capacitance 50% 50% tPLH VOD tPHL 2V 90% 90% 0V 10% 0V 10% tr -2 V tf S0303-01 Figure 3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays 3V D DE Input Generator VI 50 W A 3V S1 VO B CL = 50 pF 20% VI 50% RL = 110 W 1% CL Includes Fixture and Instrumentation Capacitance 50% VO 0V 0.5 V tPZH VOH 90% 50% 0V tPHZ S0304-01 NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output. Figure 4. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load 3V A 3V D DE Input Generator S1 RL = 110 W 1% VO 3V VI 50% 50% 0V B tPZL tPLZ CL = 50 pF 20% VI 50 W CL Includes Fixture and Instrumentation Capacitance 3V VO 50% 10% VOL S0305-01 NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output. Figure 5. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 7 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) A Input Generator VO R VI 50 W B 1.5 V CL = 15 pF 20% RE 0V CL Includes Fixture and Instrumentation Capacitance 3V VI 50% 50% 0V tPLH tPHL 90% 90% VO 50% 10% 50% 10% tr VOH VOL tf S0306-01 Figure 6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays 3V VCC DE A 0 V or 3 V D RE Input Generator VI 1 kW 1% R VO B S1 CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 50% 0V tPZH(1) tPHZ VOH 90% VO 50% D at 3 V S1 to GND 0V tPZL(1) tPLZ VCC VO 50% D at 0 V S1 to VCC 10% VOL S0307-01 Figure 7. Measurement of Receiver Enable/Disable Times With Driver Enabled 8 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION (continued) VCC A 0 V or 1.5 V R VO 1.5 V or 0 V RE Input Generator VI 1 kW 1% S1 B CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance 50 W 3V VI 50% 0V tPZH(2) VOH VO A at 1.5 V B at 0 V S1 to GND 50% GND tPZL(2) VCC VO 50% VOL A at 0 V B at 1.5 V S1 to VCC S0308-01 Figure 8. Measurement of Receiver Enable Times With Driver Disabled Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 9 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE HVD1787 RMS SUPPLY CURRENT vs SIGNALING RATE 70 50 ICC - RMS Supply Current - mA IO - Driver Output Current - mA 60 120 TA = 25C DE at VCC D at VCC RL = 54 40 30 20 10 TA = 25C RE at VCC DE at VCC RL = 54 CL = 50 pF VCC = 5 V 100 80 60 0 -10 0.0 40 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 VCC - Supply Voltage - V 5.4 0 2 4 6 8 10 Signaling Rate - Mbps G001 G002 Figure 9. Figure 10. BUS PIN CURRENT vs BUS PIN VOLTAGE 2.0 IIN - Bus Pin Current - mA 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -90 -60 -30 0 30 VIN - Bus Pin Voltage - V 60 90 G004 Figure 11. 10 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS (continued) VOD - Differential Output Voltage - V DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL LOAD CURRENT 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 Load = 100 W Load = 300 W VCC = 5.5 V VCC = 5 V Load = 60 W VCC = 4.5 V 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Idiff - Differential Load Current - mA Figure 12. Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 11 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com ADDITIONAL OPTIONS The SN65HVD17xx family also has options for J1708 applications, for always-enabled full-duplex versions (industry-standard SN65LBC179 footprint) and for inverting-polarity versions, which allow users to correct a reversal of the bus wires without re-wiring. Contact your local Texas Instruments representative for information on these options. PART NUMBER SN65HVD17xx FOOTPRINT/FUNCTION SLOW MEDIUM FAST Half-duplex (176 pinout) 85 86 87 Full-duplex no enables (179 pinout) 88 89 90 Full-duplex with enables (180 pinout) 91 92 93 Half-duplex with cable invert 94 95 96 Full-duplex with cable invert and enables 97 98 99 J1708 08 09 10 D Package (Top View) R 1 R VCC 8 1 2 RE RE 2 7 B DE 3 6 A 6 A 4 5 4 D GND D 7 B P0066-03 3 DE S0309-01 Figure 13. SN65HVD1708E Transceiver for J1708 Applications 5 D Package (Top View) Y 3 D VCC 1 8 A R D 2 7 B 3 6 Z 6 Z 8 A 2 GND 4 5 Y R 7 B P0074-01 S0310-01 Figure 14. SN65HVD17xx Always-Enabled Driver Receiver 12 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 D Package (Top View) 1 R R 1 8 VCC INV 2 7 B DE 3 6 A D 4 5 GND 2 INV 6 A 4 D 7 B 3 DE D Package (Top View) 1 RINV 1 14 VCC RINV R 2 13 VCC R RE 3 12 A DE 4 11 B D 5 10 Z GND 6 9 Y 2 12 A 11 B 3 RE GND 7 8 8 9 5 10 Y DINV DINV P0066-04 D Z 4 DE S0311-01 Figure 15. SN65HVD17xx Options With Inverting Feature to Correct for Miswired Cables APPLICATION INFORMATION Hot-Plugging These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for hot-pluggable applications are power-up, power-down glitch free operation, default disabled input/output pins, and receiver failsafe. As shown in Figure 9, an internal Power-On Reset circuit keeps the driver outputs in a high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This ensures that no spurious transitions (glitches) will occur on the bus pin outputs as the power supply turns on or turns off. As shown in the device FUNCTION TABLE, the ENABLE inputs have the feature of default disable on both the driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R pin until the associated controller actively drives the enable pins. Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 13 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com Receiver Failsafe The differential receiver is "failsafe" to invalid bus states caused by: * open bus conditions such as a disconnected connector, * shorted bus conditions such as cable damage shorting the twisted-pair together, * or idle bus conditions that occur when no driver on the bus is actively driving. In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the receiver is not indeterminate. In the HVD17xx family of RS-485 devices, receiver failsafe is accomplished by offsetting the receiver thresholds so that the "input indeterminate" range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than -200 mV. The HVD17xx receiver parameters which determine the failsafe performance are VIT+ and VIT- and VHYS. In the Electrical Characteristics table, VIT- has a typical value of -150 mV and a minimum (most negative) value of -200 mV, so differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than 200 mV will always cause a High receiver output, because the typical value of VIT+ is -100mV, and VIT+ is never more positive than -10 mV under any conditions of temperature, supply voltage, or common-mode offset. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+. For the HVD17xx devices, the typical noise immunity is typically about 150 mV, which is the negative noise level needed to exceed the VIT- threshold (VIT- TYP = -150 mV). In the worst case, the failsafe noise immunity is never less than 40 mV, which is set by the maximum positive threshold (VIT+ MAX = -10mV) plus the minimum hysteresis voltage (VHYS MIN = 30 mV). 70-V Fault-Protection The SN65HVD17xx family of RS-485 devices is designed to survive bus pin faults up to 70V. The devices designed for fast signaling rate (10 Mbps) will not survive a bus pin fault with a direct short to voltages above 30V when: 1. the device is powered on AND 2a. the driver is enabled (DE=HIGH) AND D=HIGH AND the bus fault is applied to the A pin OR 2b. the driver is enabled (DE=HIGH) AND D=LOW AND the bus fault is applied to the B pin Under other conditions, the device will survive shorts to bus pin faults up to 70V. Table 1 summarizes the conditions under which the device may be damaged, and the conditions under which the device will not be damaged. Table 1. Device Conditions 14 POWER DE D A B OFF X X -70V < VA < 70V -70V < VB < 70V Device survives ON LO X -70V < VA < 70V -70V < VB < 70V Device survives ON HI L -70V < VA < 70V -70V < VB < 30V Device survives ON HI L -70V < VA < 70V 30V < VB ON HI H -70V < VA < 30V -70V < VB < 30V Device survives ON HI H 30V < VA -70V < VB < 30V Damage may occur Submit Documentation Feedback RESULTS Damage may occur Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 www.ti.com SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 REVISION HISTORY Changes from Original (January 2008) to Revision A Page * Changed Features Bullet From: Low Standby Supply Current, 2 mA Max To: Low Standby Supply Current, 1 mA Typ ..... 1 * Deleted columns to the PRODUCT SELECTION GUIDE for Package Options and Status. ............................................... 1 * Added text: For similar features with 3.3 V supply operation... ............................................................................................ 1 * Changed the Product Selection Guide Signaling Rate for SN65HVD1787 From 20 Mbps To: 10 Mbps ............................ 1 * Changed the Product Selection Guide Signaling Rate for SN65HVD1793 From 20 Mbps To: 10 Mbps ............................ 1 * Deleted The Competitive Comparison table. ........................................................................................................................ 2 * Added |VOD| RS-485 with common-mode load TA 85C and TA 105C .......................................................................... 4 * Changed VOC From min = -0.2 mV and max 0.2 mV To: min = -100 mV and max 100 mV .............................................. 4 * Changed HVD1785/1791 Driver differential output rise/fall time max value From 2.5 ms To: 2.6 ms. .................................. 5 * Changed HVD1787/1793 Driver differential output rise/fall time max value From 1.5 ns To: 30 ns. ................................... 5 * Changed Receiver propagation delay max value From 50 ns To: 70 ns. ............................................................................ 5 * Changed tPLZ, tPHZ Receiver disable time From 3000 ns To 100 ns. .................................................................................... 5 * Deleted graph DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL LOAD CURRENT. ........................................... 10 Changes from Revision A (March 2008) to Revision B Page * Added TA 85C and TA 105C conditions and values to the Receiver low-level output voltage. ................................... 4 * Changed the max value for Supply Current (quiescent) Driver and receiver disabled, From 1 mA To 5 mA. ...................... 4 Changes from Revision B (March 2008) to Revision C * Page Changed Rec Op Table. Signaling rate, HVD1787, HVD1793 From: 20 Mbps max to 10 Mbps max. ............................... 3 Changes from Revision C (March 2008) to Revision D Page * Added Features Bullet: Power-Up, Power-Down Glitch-Free Operation .............................................................................. 1 * Changed (Preview) to part number SN65HVD1791 in the Product Selection Guide ........................................................... 1 * Changed Receiver disabled by default - Enable from X to OPEN. Output from OPEN to Z ............................................... 2 * Changed SN65HVD1791, 1792, 1793 pin out. Pin 11 from A to B, Pin 12 from B to A. ..................................................... 2 * Added section - APPLICATION INFORMATION ................................................................................................................ 13 Changes from Revision D (June 2008) to Revision E Page * Changed - Removed Product Preview label ......................................................................................................................... 1 * Changed SN65HVD1792 Removed Product Preview label ................................................................................................. 1 * Changed SN65HVD1793 Removed Product Preview label ................................................................................................. 1 Changes from Revision E (July 2008) to Revision F Page * Added to Title: With Extended Common-Mode Range ......................................................................................................... 1 * Added Receiver enabled VCM > VCC condition and values to the Driver enabled time ......................................................... 5 * Added Figure 12 ................................................................................................................................................................. 11 Copyright (c) 2008-2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 15 SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 SLLS872H - JANUARY 2008 - REVISED FEBRUARY 2010 www.ti.com Changes from Revision F (November 2008) to Revision G Page * Added Notes for pin connections. ......................................................................................................................................... 2 * Added IOH = -400 mA conditions and values to the Receiver high-level output voltage ....................................................... 4 * Added Receiver enabled VCM > VCC ..................................................................................................................................... 5 * Added Receiver Failsafe information. ................................................................................................................................. 13 * Changed the Receiver Failsafe section .............................................................................................................................. 14 Changes from Revision G (April 2009) to Revision H Page * Deleted 70-V from the data sheet title .................................................................................................................................. 1 * Changed first Features Bullet From: Bus-Pin Fault Protection to > 70 V To: Bus-Pin Fault Protection to: > 70 V ('HVD1785, 86,91,92), > 30 V ('HVD1787, 93) ................................................................................................................... 1 * Changed Voltage range at A and B inputs in the ABS MAX RATINGS table, adding seperate conditions for the different devices .................................................................................................................................................................... 3 * Changed From: Voltage input range, transient pulse, A and B, through 100 To: Transient overvoltage pulse through 100 per TIA-485 ................................................................................................................................................... 3 * Changed Figure 14 From: PW Package (Top View) To: D Package (Top View) ............................................................... 12 * Added the 70-V Fault-Protection section ............................................................................................................................ 14 16 Submit Documentation Feedback Copyright (c) 2008-2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD1785D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1785DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1785DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1785DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1785P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type SN65HVD1786D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1786DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1786DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1786DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1786P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type SN65HVD1787D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1787DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1787DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1787DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1787P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type SN65HVD1791D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1791DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1791DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1791DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1792D ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1792DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1793D ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1793DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 50 50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2010 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD1785DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD1786DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD1787DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD1791DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD1792DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD1793DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD1785DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD1786DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD1787DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD1791DR SOIC D 14 2500 346.0 346.0 33.0 SN65HVD1792DR SOIC D 14 2500 346.0 346.0 33.0 SN65HVD1793DR SOIC D 14 2500 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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