V upto70V
FAULT
M0092-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
Fault-Protected RS-485 Transceivers With Extended Common-Mode Range
Check for Samples: SN65HVD1785, SN65HVD1786,SN65HVD1787, SN65HVD1791,SN65HVD1792, SN65HVD1793
1FEATURES
• Bus-Pin Fault Protection to: • Failsafe Receiver for Open-Circuit,
Short-Circuit and Idle-Bus Conditions
– > ±70 V ('HVD1785, 86,91,92) • Low Power Consumption
– > ±30 V ('HVD1787, 93) – Low Standby Supply Current, 1 mA Typ
• Common-Mode Voltage Range (–20 V to 25 V)
More Than Doubles TIA/EIA 485 Requirement – ICC 5 mA Quiescent During Operation
• Bus I/O Protection • Power-Up, Power-Down Glitch-Free Operation
– ±16 kV JEDEC HBM Protection APPLICATIONS
• Reduced Unit Load for Up to 256 Nodes • Designed for RS-485 and RS-422 Networks
DESCRIPTION
These devices are designed to survive overvoltage faults such as direct shorts to power supplies, mis-wiring
faults, connector failures, cable crushes, and tool mis-applications. They are also robust to ESD events, with high
levels of protection to human-body model specifications.
These devices combine a differential driver and a differential receiver, which operate from a single power supply.
In the 'HVD1785, 'HVD1786, and 'HVD1787, the driver differential outputs and the receiver differential inputs are
connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. In the 'HVD1793,
the driver differential outputs and the receiver differential inputs are separate pins, to form a bus port suitable for
full-duplex (four-wire bus) communication. These ports feature a wide common-mode voltage range, making the
devices suitable for multipoint applications over long cable runs. These devices are characterized from –40°C to
105°C.
For similar features with 3.3 V supply operation, see the SN65HVD1781 (SLLS877).
PRODUCT SELECTION GUIDE
PART NUMBER DUPLEX SIGNALING RATE NODES CABLE LENGTH
SN65HVD1785 Half 115 kbps Up to 256 1500 m
SN65HVD1786 Half 1 Mbps Up to 256 150 m
SN65HVD1787 Half 10 Mbps Up to 64 50 m
SN65HVD1791 Full 115 kbps Up to 256 1500 m
SN65HVD1792 Full 1 Mbps Up to 256 150 m
SN65HVD1793 Full 10 Mbps Up to 64 50 m
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
R
RE
DE
D
VCC
B
A
GND
SN65HVD1785,1786,1787
DorP Package
(TopView)
1
2
3
4
8
7
6
5
P0066-02
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
GND
GND
Z
Y
NC
R
RE
DE
D
VCC
VCC
A
B
SN65HVD1791,1792,1793
DPackage
(TopView)
LogicDiagram(PositiveLogic)
S0299-01
1
2
3
4
6
7
A
B
R
RE
DE
D
Bus
LogicDiagram(PositiveLogic)
2
3
4
5
12
10
9
11
A
Z
Y
B
R
RE
DE
D
S0300-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
DRIVER FUNCTION TABLE
Input Enable Outputs
D DE A B
H H H L Actively drive bus high
L H L H Actively drive bus low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus high by default
RECEIVER FUNCTION TABLE
Differential Input Enable Output
VID = VA– VBRE R
VIT+ < VID L H Receive valid bus high
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output
NC - No internal connection
Pins 6 and 7 are connected together
internally.
Pins 13 and 14 are connected together
internally.
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Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
VCC Supply voltage –0.5 to 7 V
'HVD1785, 86, 91, 92, 93 A, B pins –70 to 70 V
Voltage range at bus pins 'HVD1787 A, B pins –70 to 30 V
'HVD1793 Y, Z pins –70 to 30 V
Input voltage range at any logic pin –0.3 to VCC + 0.3 V
Transient overvoltage pulse through 100 Ωper TIA-485 –100 to 100 V
Receiver output current –24 to 24 mA
TJJunction temperature 170 °C
See Dissipation
Continuous total power dissipation Rating Table
IEC 60749-26 ESD (human-body model), bus terminals and GND ±16 kV
JEDEC Standard 22, Test Method A114 (human-body model), bus terminals and GND ±16 kV
JEDEC Standard 22, Test Method A114 (human-body model), all pins ±4 kV
JEDEC Standard 22, Test Method C101 (charged-device model), all pins ±2 kV
JEDEC Standard 22, Test Method A115 (machine model), all pins ±400 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
JEDEC THERMAL TA< 25°C DERATING FACTOR TA= 85°C TA= 105°C
PACKAGE MODEL RATING ABOVE TA= 25°C RATING RATING
High-K 905 mW 7.25 mW/°C 470 mW 325 mW
SOIC (D) 8-pin Low-K 516 mW 4.1 mW/°C 268 mW 186 mW
High-K 1315 mW 10.5 mW/°C 684 mW 474 mW
SOIC (D) 14-pin Low-K 744 mW 6 mW/°C 387 mW 268 mW
High-K 2119 mW 16.9 mW/°C 1100 mW 763 mW
PDIP (P) 8-pin Low-K 976 mW 7.8 mW/°C 508 mW 352 mW
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIInput voltage at any bus terminal (separately or common mode)(1) –20 25 V
VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V
VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V
VID Differential input voltage –25 25 V
Output current, driver –60 60 mA
IOOutput current, receiver –8 8 mA
RLDifferential load resistance 54 60 Ω
CLDifferential load capacitance 50 pF
HVD1785, HVD1791 115 kbps
1/tUI Signaling rate HVD1786, HVD1792 1 Mbps
HVD1787, HVD1793 10
Operating free-air temperature (see –40 105
TA°C
application section for thermal information)
TJJunction temperature –40 150 °C
(1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RS-485 with TA≤85°C 1.5
common-mode load,
VCC > 4.75 V, see TA≤105°C 1.4
|VOD| Driver differential output voltage magnitude V
Figure 1
RL= 54 Ω, 4.75 V ≤VCC ≤5.25 V 1.5 2
RL= 100 Ω, 4.75 V ≤VCC ≤5.25 V 2 2.5
Change in magnitude of driver differential output
Δ|VOD| RL= 54 Ω–0.2 0 0.2 V
voltage
VOC(SS) Steady-state common-mode output voltage 1 VCC/2 3 V
Change in differential driver output
ΔVOC –100 0 100 mV
common-mode voltage
Peak-to-peak driver common-mode output Center of two 27-Ωload resistors, See
VOC(PP) 500 mV
voltage Figure 2
COD Differential output capacitance 23 pF
Positive-going receiver differential input voltage
VIT+ –100 –10 mV
threshold
Negative-going receiver differential input
VIT– VCM = –20 V to 25 V –200 –150 mV
voltage threshold
Receiver differential input voltage threshold
VHYS 30 50 mV
hysteresis (VIT+ – VIT–)VCC
IOH = –8 mA 2.4 – 0.3
VOH Receiver high-level output voltage V
IOH = –400 mA 4
TA≤85°C 0.2 0.4
VOL Receiver low-level output voltage IOL = 8 mA V
TA≤105°C 0.2 0.5
Driver input, driver enable, and receiver enable
II–100 100 mA
input current
IOZ Receiver output high-impedance current VO= 0 V or VCC, RE at VCC –1 1 mA
IOS Driver short-circuit output current –250 250 mA
VI= 12 V 75 125
85, 86,
91, 92 VI= –7 V –100 –40
VCC = 4.5 to 5.5 V or
IIBus input current (disabled driver) mA
VCC = 0 V, DE at 0 V VI= 12 V 500
87, 93 VI= –7 V –400
DE = VCC,
Driver and receiver RE = GND, 4 6
enabled no load
DE = VCC,
Driver enabled, RE = VCC, 3 5 mA
receiver disabled no load
ICC Supply current (quiescent) DE = GND,
Driver disabled, RE = GND, 2 4
receiver enabled no load
DE = GND,
Driver and receiver D = open 0.5 5 mA
disabled RE = VCC,
no load
Supply current (dynamic) See TYPICAL CHARACTERISTICS section
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Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER (HVD1785 AND HVD1791)
tr, tfDriver differential output rise/fall time 0.4 1.7 2.6 ms
tPHL, tPLH Driver propagation delay 0.8 2 ms
RL= 54 Ω, CL= 50 pF, See Figure 3
Driver differential output pulse skew,
tSK(P) 20 250 ns
|tPHL – tPLH|
tPHZ, tPLZ Driver disable time 0.1 5 ms
See Figure 4 and
Receiver enabled 0.2 3
Figure 5
tPZH, tPZL Driver enable time ms
Receiver disabled 3 12
DRIVER (HVD1786 AND HVD1792)
tr, tfDriver differential output rise/fall time 50 300 ns
tPHL, tPLH Driver propagation delay 200 ns
RL= 54 Ω, CL= 50 pF, See Figure 3
Driver differential output pulse skew,
tSK(P) 25 ns
|tPHL – tPLH|
tPHZ, tPLZ Driver disable time 3 ms
See Figure 4 and
Receiver enabled 300 ns
Figure 5
tPZH, tPZL Driver enable time Receiver disabled 10 ms
Receiver enabled VCM > VCC 500 ns
DRIVER (HVD1787 AND HVD1793)
tr, tfDriver differential output rise/fall time 3 30 ns
tPHL, tPLH Driver propagation delay 50 ns
RL= 54 Ω, CL= 50 pF, See Figure 3
Driver differential output pulse skew,
tSK(P) 10 ns
|tPHL – tPLH|
tPHZ, tPLZ Driver disable time 3 ms
See Figure 4 and
Receiver enabled 300 ns
Figure 5
tPZH, tPZL Driver enable time Receiver disabled 9 ms
Receiver enabled VCM > VCC 500 ns
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
tr, tfReceiver output rise/fall time 4 15 ns
85, 86, 91, 92 100 200
tPHL, tPLH Receiver propagation delay time ns
CL= 15 pF, 87, 93 70
See Figure 6 85, 86, 91, 92 6 20
Receiver output pulse skew,
tSK(P) ns
|tPHL – tPLH|87, 93 5
tPLZ, tPHZ Receiver disable time Driver enabled, See Figure 7 15 100 ns
tPZL(1), tPZH(1) Driver enabled, See Figure 7 80 300 ns
Receiver enable time
tPZL(2), tPZH(2) Driver disabled, See Figure 8 3 9 ms
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
60 1%W ±
VOD
0Vor3V
_
+–20V<V(test)<25V
DE
VCC
A
B
D
375 1%W ±
375 1%W ±
S0301-01
VOC
27 1%W ±
27 1%W ±
Input
A
B
VA
VB
VOC(PP) DVOC(SS)
VOC
C =50pF
L±20%
D
A
B
DE
VCC
C IncludesFixtureand
L
InstrumentationCapacitance
S0302-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
THERMAL INFORMATION
PARAMETER TEST CONDITIONS VALUE UNIT
JEDEC high-K model 138
SOIC-8 JEDEC low-K model 242
JEDEC high-K model 59
RqJA Junction-to-ambient thermal resistance (no airflow) DIP-8 °C/W
JEDEC low-K model 128
JEDEC high-K model 95
SOIC-14 JEDEC low-K model 168
SOIC-8 62
RqJB Junction-to-board thermal resistance DIP-8 39 °C/W
SOIC-14 40
SOIC-8 61
RqJC Junction-to-case thermal resistance DIP-8 61 °C/W
SOIC-14 44
VCC = 5.5 V, TJ= 150°C, RL= 300 Ω,
85, 91 CL= 50 pF (driver), CL= 15 pF (receiver) 290
5-V supply, unterminated(1)
85, 91 VCC = 5.5 V, TJ= 150°C, RL= 100 Ω,
CL= 50 pF (driver), CL= 15 pF (receiver)
86 320
5-V supply, RS-422 load(1)
PDPower dissipation mW
87
85, 91 VCC = 5.5 V, TJ= 150°C, RL= 54 Ω, 400
CL= 50 pF (driver), CL= 15 pF (receiver)
86 5-V supply, RS-485 load(1)
87
TSD Thermal-shutdown junction temperature 170 °C
(1) Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: HVD1785, 1791 at 115 kbps, HVD1786 at 1 Mbps,
HVD1787 at 10 Mbps)
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
Figure 1. Measurement of Driver Differential Output Voltage With Common-Mode Load
Figure 2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
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Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
VOD
RL =54
1%
W
±
50 W
tPLH tPHL
50% 50%
3V
»2V
»–2V
90%
10%
0V
VI
VOD
trtf
C =50pF 20%
L±
C IncludesFixture
L
andInstrumentation
Capacitance
DA
B
DE
VCC
VI
Input
Generator
90%
0V
10%
S0303-01
Input
Generator 50 W
3V VO
S1
3V
50%
50%
50%
tPZL tPLZ
10%
»3V
0V
VOL
VI
VO
R =110
LW
±1%
CL =50pF ±20%
C IncludesFixture
L
andInstrumentation
Capacitance
D
A
B
DE
VI
»3V
S0305-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 4. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 5. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
Input
Generator 50 W
VO
1.5V
0V
50% 50%
3V
VOH
VOL
50%
10%
50%
tPLH tPHL
tf
tr
90%
VI
VO
C =15pF 20%
L±
C IncludesFixture
andInstrumentation
Capacitance
L
A
B
RE
VI
R
0V
90%
10%
S0306-01
50 W
VO
RE
R
A
B
3V
0Vor3V
VCC
50% 50%
tPZH(1) tPHZ
50%
90%
3V
0V
VOH
»0V
VO
C =15pF 20%
L±
C IncludesFixture
andInstrumentation
Capacitance
L
VI
DE
D1k 1%W ±
VI
S1
Dat3V
S1toGND
tPZL(1) tPLZ
50%
10%
VCC
VOL
VO
Dat0V
S1toVCC
Input
Generator
S0307-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Figure 7. Measurement of Receiver Enable/Disable Times With Driver Enabled
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Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
Input
Generator 50 W
VO
RE
R
A
B
VCC
50%
50%
50%
tPZH(2)
3V
0V
VOH
GND
VI
VO
VO
0Vor1.5V
1.5Vor0V C =15pF 20%±
L
C IncludesFixture
L
andInstrumentation
Capacitance
VI
1kW ± 1%
A at1.5V
Bat0V
S1toGND
tPZL(2)
VCC
VOL
A at0V
Bat1.5V
S1toVCC
S1
S0308-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Measurement of Receiver Enable Times With Driver Disabled
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
VCC − Supply Voltage − V
−10
0
10
20
30
40
50
60
70
0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4
IO − Driver Output Current − mA
G001
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
Signaling Rate − Mbps
40
60
80
100
120
0 2 4 6 8 10
ICC − RMS Supply Current − mA
G002
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
VIN − Bus Pin Voltage − V
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
−90 −60 −30 0 30 60 90
IIN − Bus Pin Current − mA
G004
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT HVD1787 RMS SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SIGNALING RATE
Figure 9. Figure 10.
BUS PIN CURRENT
vs
BUS PIN VOLTAGE
Figure 11.
10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Idiff- DifferentialLoadCurrent-mA
V =5.5V
CC
Load=300 WLoad=100 W
Load=60 W
VOD-DifferentialOutputVoltage-V
V =5V
CC
V =4.5V
CC
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL LOAD CURRENT
Figure 12.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
R
RE
DE
D
VCC
B
A
GND
DPackage
(TopView)
1
2
3
4
8
7
6
5
P0066-03
S0309-01
1
2
3
4
6
7
A
B
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
R
D
GND
A
B
Z
Y
DPackage
(TopView)
P0074-01
2
3
8
6
5
7
A
Z
Y
B
R
D
S0310-01
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
ADDITIONAL OPTIONS
The SN65HVD17xx family also has options for J1708 applications, for always-enabled full-duplex versions
(industry-standard SN65LBC179 footprint) and for inverting-polarity versions, which allow users to correct a
reversal of the bus wires without re-wiring. Contact your local Texas Instruments representative for information
on these options.
PART NUMBER SN65HVD17xx
FOOTPRINT/FUNCTION SLOW MEDIUM FAST
Half-duplex (176 pinout) 85 86 87
Full-duplex no enables (179 pinout) 88 89 90
Full-duplex with enables (180 pinout) 91 92 93
Half-duplex with cable invert 94 95 96
Full-duplex with cable invert and enables 97 98 99
J1708 08 09 10
Figure 13. SN65HVD1708E Transceiver for J1708 Applications
Figure 14. SN65HVD17xx Always-Enabled Driver Receiver
12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
R
INV
DE
D
VCC
B
A
GND
DPackage
(TopView)
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RINV
GND
GND
Z
Y
DINV
R
RE
DE
D
VCC
VCC
A
B
DPackage
(TopView)
P0066-04
3
4
1
2
6
7
A
B
R
DE
D
INV
S0311-01
4
5
8
2
3
1
9
10
11
12
Y
Z
B
A
R
DE
D
DINV
RE
RINV
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
Figure 15. SN65HVD17xx Options With Inverting Feature to Correct for Miswired Cables
APPLICATION INFORMATION
Hot-Plugging
These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for
hot-pluggable applications are power-up, power-down glitch free operation, default disabled input/output pins,
and receiver failsafe. As shown in Figure 9, an internal Power-On Reset circuit keeps the driver outputs in a
high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This
ensures that no spurious transitions (glitches) will occur on the bus pin outputs as the power supply turns on or
turns off.
As shown in the device FUNCTION TABLE, the ENABLE inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the
R pin until the associated controller actively drives the enable pins.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together,
• or idle bus conditions that occur when no driver on the bus is actively driving.
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
In the HVD17xx family of RS-485 devices, receiver failsafe is accomplished by offsetting the receiver thresholds
so that the “input indeterminate” range does not include zero volts differential. In order to comply with the RS-422
and RS-485 standards, the receiver output must output a High when the differential input VID is more positive
than 200 mV, and must output a Low when the VID is more negative than -200 mV. The HVD17xx receiver
parameters which determine the failsafe performance are VIT+ and VIT- and VHYS. In the Electrical Characteristics
table, VIT- has a typical value of -150 mV and a minimum (most negative) value of -200 mV, so differential signals
more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive
than 200 mV will always cause a High receiver output, because the typical value of VIT+ is -100mV, and VIT+ is
never more positive than -10 mV under any conditions of temperature, supply voltage, or common-mode offset.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.
For the HVD17xx devices, the typical noise immunity is typically about 150 mV, which is the negative noise level
needed to exceed the VIT- threshold (VIT- TYP = -150 mV). In the worst case, the failsafe noise immunity is never
less than 40 mV, which is set by the maximum positive threshold (VIT+ MAX = -10mV) plus the minimum
hysteresis voltage (VHYS MIN = 30 mV).
70-V Fault-Protection
The SN65HVD17xx family of RS-485 devices is designed to survive bus pin faults up to ±70V. The devices
designed for fast signaling rate (10 Mbps) will not survive a bus pin fault with a direct short to voltages above
30V when:
1. the device is powered on AND
2a. the driver is enabled (DE=HIGH) AND D=HIGH AND the bus fault is applied to the A pin OR
2b. the driver is enabled (DE=HIGH) AND D=LOW AND the bus fault is applied to the B pin
Under other conditions, the device will survive shorts to bus pin faults up to 70V. Table 1 summarizes the
conditions under which the device may be damaged, and the conditions under which the device will not be
damaged.
Table 1. Device Conditions
POWER DE D A B RESULTS
OFF X X -70V < VA< 70V -70V < VB< 70V Device survives
ON LO X -70V < VA< 70V -70V < VB< 70V Device survives
ON HI L -70V < VA< 70V -70V < VB< 30V Device survives
ON HI L -70V < VA< 70V 30V < VBDamage may occur
ON HI H -70V < VA< 30V -70V < VB< 30V Device survives
ON HI H 30V < VA-70V < VB< 30V Damage may occur
14 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
www.ti.com
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
REVISION HISTORY
Changes from Original (January 2008) to Revision A Page
• Changed Features Bullet From: Low Standby Supply Current, 2 mA Max To: Low Standby Supply Current, 1 mA Typ ..... 1
• Deleted columns to the PRODUCT SELECTION GUIDE for Package Options and Status. ............................................... 1
• Added text: For similar features with 3.3 V supply operation... ............................................................................................ 1
• Changed the Product Selection Guide Signaling Rate for SN65HVD1787 From 20 Mbps To: 10 Mbps ............................ 1
• Changed the Product Selection Guide Signaling Rate for SN65HVD1793 From 20 Mbps To: 10 Mbps ............................ 1
• Deleted The Competitive Comparison table. ........................................................................................................................ 2
• Added |VOD| RS-485 with common-mode load TA≤85°C and TA≤105°C .......................................................................... 4
• Changed ΔVOC From min = -0.2 mV and max 0.2 mV To: min = -100 mV and max 100 mV .............................................. 4
• Changed HVD1785/1791 Driver differential output rise/fall time max value From 2.5 ms To: 2.6 ms. .................................. 5
• Changed HVD1787/1793 Driver differential output rise/fall time max value From 1.5 ns To: 30 ns. ................................... 5
• Changed Receiver propagation delay max value From 50 ns To: 70 ns. ............................................................................ 5
• Changed tPLZ, tPHZ Receiver disable time From 3000 ns To 100 ns. .................................................................................... 5
• Deleted graph DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL LOAD CURRENT. ........................................... 10
Changes from Revision A (March 2008) to Revision B Page
• Added TA≤85°C and TA≤105°C conditions and values to the Receiver low-level output voltage. ................................... 4
• Changed the max value for Supply Current (quiescent) Driver and receiver disabled, From 1 mA To 5 mA. ...................... 4
Changes from Revision B (March 2008) to Revision C Page
• Changed Rec Op Table. Signaling rate, HVD1787, HVD1793 From: 20 Mbps max to 10 Mbps max. ............................... 3
Changes from Revision C (March 2008) to Revision D Page
• Added Features Bullet: Power-Up, Power-Down Glitch-Free Operation .............................................................................. 1
• Changed (Preview) to part number SN65HVD1791 in the Product Selection Guide ........................................................... 1
• Changed Receiver disabled by default - Enable from X to OPEN. Output from OPEN to Z ............................................... 2
• Changed SN65HVD1791, 1792, 1793 pin out. Pin 11 from A to B, Pin 12 from B to A. ..................................................... 2
• Added section - APPLICATION INFORMATION ................................................................................................................ 13
Changes from Revision D (June 2008) to Revision E Page
• Changed - Removed Product Preview label ......................................................................................................................... 1
• Changed SN65HVD1792 Removed Product Preview label ................................................................................................. 1
• Changed SN65HVD1793 Removed Product Preview label ................................................................................................. 1
Changes from Revision E (July 2008) to Revision F Page
• Added to Title: With Extended Common-Mode Range ......................................................................................................... 1
• Added Receiver enabled VCM > VCC condition and values to the Driver enabled time ......................................................... 5
• Added Figure 12 ................................................................................................................................................................. 11
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
SN65HVD1785, SN65HVD1786
SN65HVD1787, SN65HVD1791
SN65HVD1792, SN65HVD1793
SLLS872H –JANUARY 2008–REVISED FEBRUARY 2010
www.ti.com
Changes from Revision F (November 2008) to Revision G Page
• Added Notes for pin connections. ......................................................................................................................................... 2
• Added IOH = –400 mA conditions and values to the Receiver high-level output voltage ....................................................... 4
• Added Receiver enabled VCM > VCC ..................................................................................................................................... 5
• Added Receiver Failsafe information. ................................................................................................................................. 13
• Changed the Receiver Failsafe section .............................................................................................................................. 14
Changes from Revision G (April 2009) to Revision H Page
• Deleted 70-V from the data sheet title .................................................................................................................................. 1
• Changed first Features Bullet From: Bus-Pin Fault Protection to > ±70 V To: Bus-Pin Fault Protection to: > ±70 V
('HVD1785, 86,91,92), > ±30 V ('HVD1787, 93) ................................................................................................................... 1
• Changed Voltage range at A and B inputs in the ABS MAX RATINGS table, adding seperate conditions for the
different devices .................................................................................................................................................................... 3
• Changed From: Voltage input range, transient pulse, A and B, through 100 ΩTo: Transient overvoltage pulse
through 100 Ωper TIA-485 ................................................................................................................................................... 3
• Changed Figure 14 From: PW Package (Top View) To: D Package (Top View) ............................................................... 12
• Added the 70-V Fault-Protection section ............................................................................................................................ 14
16 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1785, SN65HVD1786 SN65HVD1787, SN65HVD1791 SN65HVD1792, SN65HVD1793
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD1785D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1785DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1785DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1785DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1785P ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
SN65HVD1786D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1786DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1786DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1786DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1786P ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
SN65HVD1787D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1787DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1787DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1787DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1787P ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
SN65HVD1791D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1791DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1791DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1791DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1792D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1792DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1793D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD1793DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Feb-2010
Addendum-Page 1
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Feb-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD1785DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1786DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1787DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1791DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65HVD1792DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65HVD1793DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Feb-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD1785DR SOIC D 8 2500 346.0 346.0 29.0
SN65HVD1786DR SOIC D 8 2500 346.0 346.0 29.0
SN65HVD1787DR SOIC D 8 2500 346.0 346.0 29.0
SN65HVD1791DR SOIC D 14 2500 346.0 346.0 33.0
SN65HVD1792DR SOIC D 14 2500 346.0 346.0 33.0
SN65HVD1793DR SOIC D 14 2500 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Feb-2010
Pack Materials-Page 2
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