System Peripherals and
Networking
For networking, the FMAN supports one
10 Gb/s and 5x 1 Gb/s MAC controllers that
connect to PHYs, switches and backplanes
over RGMII, SGMII and XAUI. High-speed
system expansion is supported through four
PCI Express v2.0 controllers that support
a variety of lane widths. Other peripherals
include SATA, SD/MMC, I2C, UART, SPI, NOR/
NAND controller, GPIO and dual 1333 MT/s
DDR3/3L controllers.
Software and Tool Support
• Enea: Real-time operating system support
and virtualization software
• Green Hills: Comprehensive portfolio of
software and hardware development tools,
trace tools, real-time operating systems
and virtualization software
• Mentor Graphics®: Commercial-grade
Linux solution
• QNX®: Real-time OS and development tool
support
• QorIQ P5020 development system
(P5020DS)
P5020/P5010 Features List
Two (P5020) or one (P5010)
single threaded e5500 cores
built on Power Architecture®
technology
• Up to 2 GHz with 64-bit ISA support (Power Architecture V2.06 compliant)
• Three levels of instruction: User, supervisor, hypervisor
• Hybrid 32-bit mode to support legacy software and transition to 64-bit
architecture
CoreNet platform cache (CPC) • 2 MB configured as dual 1 MB blocks (1 MB only for P5010)
Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet endpoints
• QMAN fabric supporting packet-level queue management and quality of
service scheduling
Two 64-bit DDR3/3L SDRAM
memory controllers with ECC
and interleaving support
• Up to 1333 MT/s
• Memory pre-fetch engine
DPAA incorporating acceleration
for the following functions
• Packet parsing, classification and distribution (FMAN)
• QMAN for scheduling, packet sequencing and congestion management
• Hardware BMAN for buffer allocation and de-allocation
• Cryptography acceleration (SEC 4.2) at up to 40 Gb/s
• RegEx pattern matching acceleration (PME 2.1) at up to 10 Gb/s
SerDes • 18 lanes at up to 5 Gb/s
• Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA
Ethernet interfaces • One 10 Gb/s Ethernet MACs
• 5x 1 Gb/s Ethernet MACs
High-speed peripheral interfaces • Four PCI Express 2.0 controllers
• Two Serial RapidIO controllers/ports (sRIO port) V1.3-compliant with
features of V2.1
• Two serial ATA (SATA 2.0) controllers
Additional peripheral interfaces • Two USB 2.0 Full-Speed controllers with integrated PHY
• Enhanced secure digital host controller (SD/MMC/eMMC)
• Enhanced serial peripheral interface
• Four I2C controllers
• Four UARTs
• Integrated flash controller supporting NAND and NOR flash
DMA • Dual four channel
Support for hardware
virtualization and partitioning
enforcement
• Extra privileged level for hypervisor support
QorIQ trust architecture 1.1 • Secure boot, secure debug, tamper detection, volatile key storage
For more information, please visit freescale.com/QorIQ
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a
trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and
service marks licensed by Power.org. © 2012, 2014 Freescale Semiconductor,Inc.
Document Number: QP5020FS REV 6
P5 Family Comparison Chart
P5020/P5010 P5040/P5021
CPU cores 2x 64-bit e5500, 1x (P5010) 4x 64-bit e5500, 2x (P5021)
Threads 2/1 (single thread per core) 4/2 (single thread per core)
Max core frequency 1.6 to 2 GHz 1.8 to 2.2 GHz
L2 512 KB per core 512 KB per core
L3/Platform 2 MB (P5020)/1 MB (P5010) 2 MB (both P5040 and P5021)
DDR I/F 2x 64-bit DDR3 (up to 1333 MT/s)
1x 64-bit DDR3 (P5010)
2x 64-bit DDR3 (up to 1600 MT/s)
PCI Express® 4x PCIe v2.0 3x PCIe v2.0 (incl. 1 x 8)
GbE, 10 GbE 5x 1 GbE, 1x 10 GbE 10x 1 GbE, 2x 10 GbE
SRIO 2x SRIO v2.1 (supports Type 9 and 11 messaging) N/A
SerDes lanes 18 lanes 20 lanes
Package 1295-pin 37.5 x 37.5 mm FC-PBGA 1295-pin 37.5 x 37.5 mm FC-PBGA