au, igh-Performance Surface-Mount TTL Delay Modules High-Performance 5-Tap TTL Delay Modules1/s Height Tap Delays (ns) All Taps (Max.) 025. Part No. Tt | To2 | 3 | To4 | ToS | Ta | Teo 005 | ~ GCTTLDLO25AMX 5.0 | 10.0 15.0 | 20.0] 25.0] 2.0 2.0 GCTTLDLOSOAMX | 10.0 | 20.0 30.0} 40.0] 500] 2.0 2.0 GCTTLDLO75AMX | 15.0 | 30.0 45.0} 60.0] 750] 2.0 2.0 Max GCTTLDL100AMX | 20.0 | 40.0 60.0 | 80.0 | 100.0] 2.0 5.0 675 GCTTLDL125AMX | 25.0 | 50.0 75.0 | 100.0 | 125.0 | 2.0 6.0 625 GCTTLDLISOAMX | 30.0 | 60.0 90.0 | 120.0 | 150.0 | 2.0 7.0 065 GCTTLDL20Q0AMX | 40.0 | 80.0 | 120.0 | 160.0 | 200.0 | 2.0 8.0 7 020 Delay Characteristics measured @ Voc = 5.0V, 25C no load. A F aH c+ Delay Tolerance +2 ns or 5% (whichever is greater). "MAX | 020 he F Rise time measured @ 0.8V to 2.0V levels. TP $80 For minimum input-pulse width, contact factory, 100 | | i Vec TdS Tda Td3 Max (4) (12) (10) (8) a) 4 6 iN Td! Td2 GND Notes Only the pins specified in the schematics are provided with each package. Pin numbers shown are for reference only and are not necessarily marked on unit. Lead material is electro tin plated (alloy 42) or solder dipped. . . All specifications are High-Performance 5-Tap TTL Delay ModulesGull Wing subject to change without Tap Delays (ns) All Taps (Max.) notice. Part No. Tot | t2 | 13 | 14 | ToS | To | Tro GTTLDLO25MxX 5.0] 10.0] 150] 200] 250] 2.0 2.0 GTTLDLOSOMX 10.0} 200] 300} 400] 500] 20 2.0 GTTLDLO75MX 15.0} 300] 450] 60.0] 750] 2.0 2.0 GTTLDL100MX 20.0 | 40.0] 60.0 | 80.0 | 100.0] 2.0 2.0 800 GTTLDL125MX 25.0} 50.0 | 75.0 | 100.0 | 125.0] 2.0 2.0 MAX. 980 GTTLDL150MX | 30.0] 60.0} 90.0 | 120.0] 150.0] 20 | 50 300 y Secu 20_,, GTTLDL200Mx | 40.0] 80.0 | 120.0 | 160.0 | 200.0] 20 | 50 at -100) pmax] GTTLDL250MX | 50.00] 100.0 | 150.0 | 200.0 | 250.0) 20 | 9.0 fi A ra GTTLDL500MX | 100.00] 200.0 | 300.0 | 400.0 | 500.0} 2.0 9.0 14 8 | g05 fle Delay Characteristics measured @ Vo. = 5.0V, 25C no load. fe as Delay Tolerance +2 ns or 5% (whichever is greater). , : Rise time measured @ 0.8V to 2.0V levels. | For minimum input-pulse width, contact factory. Designs with 022 Q pulse widths of less than 15% of delay are available. a. an 050 a ag Veco Tdi Td3 Td5 (14) (12) (10) (8) F\/* F "| a (4) (6) (7) IN Td2 Td4 GND = Technitrol" 1952 East Allegheny Avenue, Philadelphia, PA 19134 USA 18 215-426-9105 eFax 215-426-2836High-Performance Surface-Mount TTL Delay Modulescontd. > Supports Schottky TTL, FAST and High-Performance 5-Tap TTL Delay Modules1/2 Sq. FACT-logics. All Taps > Transfer-molded packagingfor highest Tap Delays (ns) (Max.) reliability. Part No. Part No. PartNo. | Ty1 | Tp2 | Ty3 | To4 | ToS | Tro | Tro > Designed for leading edge timing. BUTTLDLO25 |GBTTLOLOZS | BITLOLOZ5 | 5.0] 10.0] 15.0/ 20.0| 25.0] 2.0 | 20 y. rae BJTTLDLOSO | GBTTLDLO50| BTTLDLOSO | 10.0 | 20.0} 30.0] 40.0] 50.0| 20 | 20 Trailing edge timing available. BJTTLDLO75 | GBTTLDLO75 | BTTLDLO7S | 15.0 | 300} 45.0| 60.0] 75.0] 20 | 20 > . TTL. FAST BJTTLOL100 | GBTTLOL100} BTTLDL100 | 20.0 | 40.0 | 60.0| 80.0}100.0| 20 | 50 Compatible with Schottiey ' , BUTTLDL125 | GBTTLDL125 | BTTLDL125 | 25.0 | 50.0 | 75.0| 100.0] 125.0] 2.0 | 6.0 FACT, TTL, ALS, AS and low-power BUTTLDL150 | GBTTLDL150| BTTLDL150 | 30.0 | 60.0} 90.0] 120.0/150.0| 2.0 | 7.0 Schottky TTL circuits. BJTTLDL200 | GBTTLDL200| BTTLDL200 | 40.0 | 80.0 } 120.0] 160.0| 200.0] 2.0 | 8.0 Delay Characteristics measured @ Voc = 5.0V, 25C, no load. > Pin compatible to 74/54 series 14 Delay Tolerance +2 ns or 5% (whichever is greater). PIN DIP. Rise time measured @ 0.8V to 2.0V levels. > For minimum input-pulse width, contact factory. - .480 MAX. Military models with temperature range 55 to +125C and ceramic a . package IC to meet Mil-Std-883C but 950 TVP.-G- 8 a not screened to that specification, add y ge pot t. Suffix M to part number. om 4-14 pb P Military models as above, but with oR oo ceramic package IC screened to Mil- ory quit wing C-Lead Std-883C and 38510. Add suffix MX BJTTLOL GBTTLOL BTTLDL to part number. Military models as MX above, but with in-house burn-in and thermal shock, add suffix MY. 005 07s O15 MIN. Aine [eles Fel, i 3 240 050 020 | s50 | jf (oso ry i 20 420 + .020 550 500 520 _ Fanout: Logic 120 loads; logic O10 BUTTLOL GBTTLDL and BTTLDL loads. Vee Td1 Td3 Td Vec TaS = Tada Ta3 . 4) 02) 10) 8) (14 02) 69 8) Temperature coefficient +2 ns or + a A A 4% (whichever is greater) at maximum T delay, 0 to 70C. a) (4) (6) (7) a) 4) 6) (7) IN Td2 Td4 GND IN TW Td2 GND High-Performance 5-Tap TTL Delay Modules3?/s" Sq. Tap Delays (ns) All Taps (Max.) C-Lead Part No. T,1 Th2 13 To4 | 15 Tro Tro CTTLOL CTTLDLO25 5.0 | 100] 15.0] 200] 250] 20 | 20 720 MAX. CTTLDLOSO 10.0 | 20.0 | 30.0] 40.0] 500] 2.0 2.0 ( \ CTTLDLO75 15.0 | 30.0 | 450] 60.0} 75.0] 2.0 2.0 ie CTTLDL100 20.0 | 40.0 | 60.0} 80.0] 100.0] 2.0 5.0 We. --6 7 b} CTTLDL125 25.0 | 50.0 | 75.0} 100.0] 125.0] 2.0 5.0 ho q- Piao CTTLDL150 30.0 | 60.0 | 90.0 | 120.0 | 150.0] 2.0 6.0 MAX. a + P f CTTLDL200 40.0 | 80.0 | 120.0 | 160.0 | 200.0] 2.0 7.0 tid po Delay Characteristics measured @ Voc = 5.0V, 25C, no load. CTTLOL do RA ve. Delay Tolerance +2 ns or 5% (whichever is greater). ice S a 138 wel ht Rise time measured @ 0.8V to 2.0V levels. + + o4oR __/ oon toe . @ PLS) For minimum input-pulse width, contact factory. A AU A 007 Notes A Vv MIN Max. Only the pins specified in the schematics are provided with each package. nS 7 Pin numbers shown are for reference only and are not necessarily marked on unit. am ia) a) oso LF sot Lead material is electro tin plated (alloy 42) or solder dipped. IN Fer 2 GND MIN. .760 MAX: All specifications are subject to change without notice. Technitrol rn 1952 East Allegheny Avenue, Philadelphia, PA 19134 USA 215-426-9105 Fax 215-426-2836 19