1
FEATURES
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
DESCRIPTION/ORDERING INFORMATION
SN74LV373A-Q1OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007www.ti.com
•Qualified for Automotive Applications•2-V to 5.5-V V
CC
Operation•Maximum t
pd
of 8.5 ns at 5 V•Typical V
OLP
(Output Ground Bounce) < 0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•Typical V
OHV
(Output V
OH
Undershoot) > 2.3 Vat V
CC
= 3.3 V, T
A
= 25 °C•Supports Mixed-Mode Voltage Operation onAll Ports•I
off
Supports Partial-Power-Down ModeOperation
•Latch-Up Performance Exceeds 250 mA PerJESD 17
The SN74LV373A device is an octal transparent D-type latch designed for 2-V to 5.5-V V
CC
operation.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Qoutputs are latched at the logic levels set up at the D inputs.
A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high orlow) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly. The high-impedance state and increased drive provide the capability to drive bus lines without needfor interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE shall be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
– 40 °C to 85 °C TSSOP – PW Reel of 2000 SN74LV373AIPWRQ1 LV373AI
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
OE 1
11
3
2
LE
1D
C1
1D
1Q
To Seven Other Channels
Absolute Maximum Ratings
(1)
SN74LV373A-Q1
OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007
FUNCTION TABLE(EACH LATCH)
INPUTS OUTPUT
OE LE D Q
L H H HL H L LL L X Q
0
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 7 VV
I
Input voltage range
(2)
– 0.5 7 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
– 0.5 7 VV
O
Output voltage range
(2) (3)
– 0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 – 20 mAI
OK
Output clamp current V
O
< 0 – 50 mAI
O
Continuous output current V
O
= 0 to V
CC
± 35 mAContinuous current through V
CC
or GND ± 70 mAθ
JA
Package thermal impedance
(4)
83 °C/WT
stg
Storage temperature range – 65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 5.5 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN74LV373A-Q1OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007
MIN MAX UNIT
V
CC
Supply voltage 2 5.5 VV
CC
= 2 V 1.5V
CC
= 2.3 V to 2.7 V V
CC
×0.7V
IH
High-level input voltage VV
CC
= 3 V to 3.6 V V
CC
×0.7V
CC
= 4.5 V to 5.5 V V
CC
×0.7V
CC
= 2 V 0.5V
CC
= 2.3 V to 2.7 V V
CC
×0.3V
IL
Low-level input voltage VV
CC
= 3 V to 3.6 V V
CC
×0.3V
CC
= 4.5 V to 5.5 V V
CC
×0.3V
I
Input voltage 0 5.5 VHigh or low state 0 V
CCV
O
Output voltage V3-state 0 5.5V
CC
= 2 V – 50 µAV
CC
= 2.3 V to 2.7 V – 2I
OH
High-level output current
V
CC
= 3 V to 3.6 V – 8 mAV
CC
= 4.5 V to 5.5 V – 16V
CC
= 2 V 50 µAV
CC
= 2.3 V to 2.7 V 2I
OL
Low-level output current
V
CC
= 3 V to 3.6 V 8 mAV
CC
= 4.5 V to 5.5 V 16V
CC
= 2.3 V to 2.7 V 200
Δt/ Δv Input transition rise or fall rate V
CC
= 3 V to 3.6 V 100 ns/VV
CC
= 4.5 V to 5.5 V 20T
A
Operating free-air temperature – 40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
OH
= – 50 µA 2 V to 5.5 V V
CC
– 0.1I
OH
= – 2 mA 2.3 V 2V
OH
VI
OH
= – 8 mA 3 V 2.48I
OH
= – 16 mA 4.5 V 3.8I
OL
= 50 µA 2 V to 5.5 V 0.1I
OL
= 2 mA 2.3 V 0.4V
OL
VI
OL
= 8 mA 3 V 0.44I
OL
= 16 mA 4.5 V 0.55I
I
V
I
= 5.5 V or GND 0 to 5.5 V ± 1 µAI
OZ
V
O
= V
CC
or GND 5.5 V ± 5 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 5.5 V 20 µAI
off
V
I
or V
O
= 0 to 5.5 V 0 5 µAC
i
V
I
= V
CC
or GND 3.3 V 2.9 pF
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
www.ti.com
Timing Requirements
Timing Requirements
Timing Requirements
Switching Characteristics
Switching Characteristics
SN74LV373A-Q1
OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007
over recommended operating free-air temperature range, V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
t
w
Pulse duration, LE high 6.5 nst
su
Setup time, data before LE ↓High or low 5 nst
h
Hold time, data after LE ↓High or low 1.5 ns
over recommended operating free-air temperature range, V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
t
w
Pulse duration, LE high 5 nst
su
Setup time, data before LE ↓High or low 4 nst
h
Hold time, data after LE ↓High or low 1 ns
over recommended operating free-air temperature range, V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
t
w
Pulse duration, LE high 5 nst
su
Setup time, data before LE ↓High or low 4 nst
h
Hold time, data after LE ↓High or low 1 ns
over recommended operating free-air temperature range, V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1 )
FROM TOPARAMETER LOAD CAPACITANCE MIN MAX UNIT(INPUT) (OUTPUT)
D Q 1 17t
pd
nsLE Q 1 19C
L
= 15 pFt
en
OE Q 1 19 nst
dis
OE Q 1 15 nsD Q 1 21t
pd
nsLE Q 1 22C
L
= 50 pFt
en
OE Q 1 22 nst
dis
OE Q 1 19 nst
sk(o)
C
L
= 50 pF 2 ns
over recommended operating free-air temperature range, V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1 )
FROM TOPARAMETER LOAD CAPACITANCE MIN MAX UNIT(INPUT) (OUTPUT)
D Q 1 13.5t
pd
nsLE Q 1 13C
L
= 15 pFt
en
OE Q 1 13.5 nst
dis
OE Q 1 12 nsD Q 1 17t
pd
nsLE Q 1 16.5C
L
= 50 pFt
en
OE Q 1 17 nst
dis
OE Q 1 15 nst
sk(o)
C
L
= 50 pF 1.5 ns
4Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
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Switching Characteristics
Noise Characteristics
(1)
Operating Characteristics
SN74LV373A-Q1OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007
over recommended operating free-air temperature range, V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1 )
FROM TOPARAMETER LOAD CAPACITANCE MIN MAX UNIT(INPUT) (OUTPUT)
D Q 1 8.5t
pd
nsLE Q 1 8.5C
L
= 15 pFt
en
OE Q 1 9.5 nst
dis
OE Q 1 8.5 nsD Q 1 10.5t
pd
nsLE Q 1 10.5C
L
= 50 pFt
en
OE Q 1 11.5 nst
dis
OE Q 1 10.5 nst
sk(o)
C
L
= 50 pF 1 ns
V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25 °C (unless otherwise noted)
MIN TYP MAX UNIT
V
OL(P)
Quiet output, maximum dynamic V
OL
0.6 0.8 VV
OL(V)
Quiet output, minimum dynamic V
OL
– 0.6 – 0.8 VV
OH(V)
Quiet output, minimum dynamic V
OH
2.9 VV
IH(D)
High-level dynamic input voltage 2.31 VV
IL(D)
Low-level dynamic input voltage 0.99 V
(1) Characteristics are for surface-mount packages only.
T
A
= 25 °C
PARAMETER TEST CONDITIONS V
CC
TYP UNIT
3.3 V 17.4C
pd
Power dissipation capacitance (outputs enabled) C
L
= 50 pF, f = 10 MHz pF5 V 19.5
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
www.ti.com
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics:PRR ≤1 MHz, ZO= 50 Ω, tr≤3 ns, tf≤3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. t and t are the same as t .
PLZ PHZ dis
F. t and t are the same as t .
PZL PZH en
G. t and t are the same as t .
PHL PLH pd
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL= 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH - 0.3 V
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
SN74LV373A-Q1
OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCLS586C – JUNE 2004 – REVISED OCTOBER 2007
Figure 1. Load Circuit and Voltage Waveforms
6Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV373AIPWRG4Q1 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV373AIPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV373A-Q1 :
•Catalog: SN74LV373A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 18-Dec-2009
Addendum-Page 1
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