MT28F320J3FS-11METTR - Micron Technology

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef80b5a323

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Q-FLASH MEMORY MT28F128J3, MT28F640J3,

MT28F320J3

Features

Memory Organization

• x8/x16

• One hundred twenty-eight 128KB erase blocks

(128Mb)

• Sixty-four 128KB erase blocks (64Mb)

• Thirty-two 128KB erase blocks (32Mb)

VCC, VCCQ, and VPEN voltages:

• 2.7V to 3.6V VCC operation

• 2.7V to 3.6V application programming

Interface Asynchronous Page Mode Reads:

• 120ns/25ns read access time (128Mb)

• 115ns/25ns read access time (64Mb)

• 110ns/25ns read access time (32Mb)

Manufacturer’s Identification Code (ManID)

•Micron

 (0x2Ch)

•Intel

 (0x89h)

Industry-standard pinout

Inputs and outputs are fully TTL-compatible

Common Flash Interface (CFI) and

Scalable Command Set

Automatic write and erase algorithm

5.6µs-per-byte effective programming time using write

buffer

128-bit protection register

• 64-bit unique device identifier

• 64-bit user-programmable OTP cells

Enhanced data protection feature with VPEN = VSS

• Flexible sector locking

• Sector erase/program lockout during power

transition

Security block features

Contact factory for availability

100,000 ERASE cycles per block

Automatic suspend options:

• Block Erase Suspend-to-Read

• Block Erase Suspend-to-Program

•Program Suspend-to-Read

Figure 1: 56-Pin TSOP Type I

Figure 2: 64-Ball FBGA

Part Number Example:

MT28F640J3RG-115ET

Options Mark

Timing

• 110ns (32Mb) -11

•115ns (64Mb)

•120ns (128Mb)

-115

-12

Operating Temperature Range

• Extended Temperature: -40°C to +85°C

Packages

• 56-pin (standard) TSOP Type I

• 56-pin (lead-free) TSOP Type I

• 64-ball (standard) FBGA (1.00mm pitch)

• 64-ball (lead-free) FBGA (1.00mm pitch)

Manufacturer’s Identification Code (ManID)

•Micron (0x2Ch)

•Intel (0x89h)

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

56-Pin TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Reset/Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Read Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

READ ARRAY Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

READ QUERY MODE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Query Structure Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Primary Vendor-Specific Extended-Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

READ IDENTIFIER CODES Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

READ STATUS REGISTER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

CLEAR STATUS REGISTER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

BLOCK ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

BLOCK ERASE SUSPEND Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WRITE-to-BUFFER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

BYTE/WORD PROGRAM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PROGRAM SUSPEND Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SET READ CONFIGURATION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

READ Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

STS CONFIGURATION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SET BLOCK LOCK BITS Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

CLEAR BLOCK LOCK BITS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PROTECTION REGISTER PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Reading the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Programming the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Locking the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Five-Line Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

STS and Block Erase, Program, and Lock Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Reducing Overshoots and Undershoots When Using Buffers or Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Vcc, Vpen, and RP# Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Power-Up/Down Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Electrical Specificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1: 56-Pin TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: 64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 3: Pin and Ball Assignment Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 6: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7: Device Identifier Code Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 8: Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 9: WRITE-to-BUFFER Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 10: BYTE/WORD PROGRAM Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 11: PROGRAM SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 12: BLOCK ERASE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 13: BLOCK ERASE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 14: SET BLOCK LOCK BITS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 15: CLEAR BLOCK LOCK BITS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 16: PROTECTION REGISTER PROGRAMMING Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 17: Transient Input/Output Reference Waveform for VccQ = 2.7V – 3.6V . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 18: Transient Equivalent Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 19: Page Mode and Standard Word/Byte READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 20: WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 21: RESET Operation4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 22: 56-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 23: 64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 2: Chip-Enable Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 3: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 4: Micron Q-Flash Memory Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5: Summary of Query-Structure Output as a Function of Device and Mode. . . . . . . . . . . . . . . . . . . . . . .16

Table 6: Example: Query Structure Output of x16- and x8-Capable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 7: Query Structure1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 8: Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 9: CFI Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 10: System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 11: Device Geometry Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 12: Device Geometry Definition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 13: Primary Vendor-Specific Extended-Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 14: Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 15: Burst READ Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 16: Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 17: Status Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 18: Extended Status Register Definitions (XSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 19: Configuration Coding Definitions1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 20: Word-Wide Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 21: Byte-Wide Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 22: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 23: Temperature and Recommended DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 24: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 25: Recommended DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 26: Test Configuration Loading Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 27: AC Characteristics–Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 28: AC Characteristics – WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 29: Block Erase, Program, and Lock Bit Configuration Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 30: RESET Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT28F128J3 is a nonvolatile, electrically block-

erasable (Flash), programmable memory containing

134,217,728 bits organized as 16,777,218 bytes (8 bits)

or 8,388,608 words (16 bits). This 128Mb device is

organized as one hundred twenty-eight 128KB erase

blocks.

The MT28F640J3 contains 67,108,864 bits organized

as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).

This 64Mb device is organized as sixty-four 128KB

erase blocks.

Similarly, the MT28F320J3 contains 33,554,432 bits

organized as 4,194,304 bytes (8 bits) or 2,097,152 words

(16 bits). This 32Mb device is organized as thirty-two

128KB erase blocks.

These three devices feature in-system block locking.

They also have common Flash interface (CFI) that per-

mits software algorithms to be used for entire families

of devices. The software is device-independent, JEDEC

ID-independent with forward and backward compati-

bility.

Additionally, the scalable command set (SCS)

allows a single, simple software driver in all host sys-

tems to work with all SCS-compliant Flash memory

devices. The SCS provides the fastest system/device

data transfer rates and minimizes the device and sys-

tem-level implementation costs.

To optimize the processor-memory interface, the

device accommodates VPEN, which is switchable dur-

ing block erase, program, or lock bit configuration, or

hard-wired to VCC, depending on the application. VPEN

is treated as an input pin to enable erasing, program-

ming, and block locking. When VPEN is lower than the

VCC lockout voltage (VLKO), all program functions are

disabled. Block erase suspend mode enables the user

to stop block erase to read data from or program data

to any other blocks. Similarly, program suspend mode

enables the user to suspend programming to read data

or execute code from any unsuspended blocks.

VPEN serves as an input with 2.7V or 3.3V for appli-

cation programming. VPEN in this Q-Flash family can

provide data protection when connected to ground.

This pin also enables program or erase lockout during

power transition.

Micron’s even-sectored Q-Flash devices offer indi-

vidual block locking that can lock and unlock a block

using the sector lock bits command sequence.

Status (STS) is a logic signal output that gives an

additional indicator of the internal state machine

(ISM) activity by providing a hardware signal of both

status and status masking. This status indicator mini-

mizes central processing unit (CPU) overhead and sys-

tem power consumption. In the default mode, STS acts

as an RY/BY# pin. When LOW, STS indicates that the

ISM is performing a block erase, program, or lock bit

configuration. When HIGH, STS indicates that the ISM

is ready for a new command.

Three chip enable (CE) pins are used for enabling

and disabling the device by activating the device’s

control logic, input buffer, decoders, and sense ampli-

fiers.

BYTE# enables the device to be used in x8 or x16

read/write mode; BYTE# = 0 selects an 8-bit mode,

with address A0 selecting between the LOW and HIGH

byte, while BYTE# = 1 selects a 16-bit mode. When

BYTE# = 1, A1 becomes the lowest-order address line

with A0 being a no connect.

RP# is used to reset the device. When the device is

disabled and RP# is at VCC, the standby mode is

enabled. A reset time (tRWH) is required after RP#

switches HIGH until outputs are valid. Likewise, the

device has a wake time (

tRS) from RP# HIGH until

writes to the command user interface (CUI) are recog-

nized. When RP# is at GND, it provides write protec-

tion, resets the ISM, and clears the status register.

Variants of the MT28F320J3 and MT28F640J3

support the new security block lock features for

additional code security. (Contact factory for

availability.)

The MT28F320J3 is manufactured using 0.18µm

process technology, the MT28F128J3 and the

MT28F640J3 are manufactured using 0.15µm process

technology.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Pin and Ball Assignment Diagrams

56-Pin TSOP Type I 64-Ball FBGA

NOTE:

1. A22 only exists on the 64Mb and 128Mb devices. On the 32Mb, this pin/ball is a no connect (NC).

2. A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball is NC.

3. The # symbol indicates that the signal is active LOW.

A22

CE1

A21

A20

A19

A18

A17

A16

VCC

A15

A14

A13

A12

CE0

VPEN

RP#

A11

A10

VSS

WE#

OE#

STS

DQ15

DQ7

DQ14

DQ6

VSS

DQ13

DQ5

DQ12

DQ4

VCCQ

VSS

DQ11

DQ3

DQ10

DQ2

VCC

DQ9

DQ1

DQ8

DQ0

BYTE#

A23

CE2

1 2 3 4 5 6 7 8

?Top View

(Ball? Down)

VPEN

CE0

A12

RP#

DQ3

DQ11

VCCQ

VSS

A10

A11

DQ9

DQ10

DQ2

VCC

DQ8

BYTE#

A23

CE2

VCC

A25

DNU

DQ6

VSS

A18

A19

A20

A16

DQ15

DNU

DQ14

DQ7

A22

CE1

A21

A17

STS

OE#

WE#

A13

A14

A15

DNU

DQ4

DQ12

DQ5

DQ13

VSS

DQ1

DQ0

DNU

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Part Numbering Information

Micron’s Flash devices are available with several

different combinations of features (see Figure 4).

Figure 4: Part Number Chart

NOTE:

1. Lead-free packages are available. Contact factory for details.

Valid Part Number Combinations

After building the part number from the part num-

ber chart above, please go to Micron’s Part Marking

Decoder Web site at www.micron.com/partsearch to

verify that the part number is offered and valid. If the

device required is not on this list, please contact the

factory.

Device Marking

Due to the size of the package, the Micron standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross-referenced to the Micron part

numbers at www.micron.com/partsearch. To view the

location of the abbreviated mark on the device, please

refer to customer service note CSN-11, “Product Mark/

Label,” at www.micron.com/csn.

MT 28F

320 J3 RG -11 ET

Micron Technology

Flash Family

28F = Dual-Supply

Density/Organization

XXX = x8/x16 selectable

(XXX = 320, 640, 128)

Access Time

-11 = 110ns

-115 =115ns

-12 = 120ns

Voltage/Block Organization

J3 = Smart 3 (2.70V–3.60V V

CC/

2.70V–3.60V)

Even sectored, compatible with Intel StrataFlash

“J3”

Package Code

TSOP

RG = 56-pin (standard) TSOP Type I RP = 56-pin (lead-free) TSOP Type I

FBGA (standard)

FS = 64-ball (standard) FBGA BS = 64-ball (lead-free) FBGA

(8 x 8 grid, 1.00mm pitch, 10mm x 13mm) (8 x 8 grid, 1.00mm pitch, 10mm x 13mm)

(Compatible with Intel‘s Easy BGA package) (Compatible with Intel’s Easy BGA package)

Operating Temperature Range

ET = Extended (-40ºC to +85ºC)

Manufacturer’s Identification Code

None = Intel (89h)

M = Micron (2Ch)

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 5: Functional Block Diagram

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Addr.

Buffer/

Latch

Power

(Current)

Control

Addr.

Counter

Command

Execution

Logic

I/O

Control

Logic

VPP

Switch/

Pump

Status

Identification

Y -

Decoder

X - Decoder/Block Erase Control

State

Machine

A[MAX:0]

OE#

WE#

RP#

VPEN

DQ0–DQ15

CE2

Output

Buffer

Input

Buffer

Write

Buffer

STS

128KB Memory Block (0)

128KB Memory Block (n)

128KB Memory Block (1)

128KB Memory Block (2)

128KB Memory Block (n-2)

128KB Memory Block (n-1)

Query

CE1

CE0

CE Logic

A (MAX)DENSITY n

128Mb

64Mb

32Mb

A23

A22

A21

127

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 1: Pin/Ball Descriptions

56-PIN TSOP

NUMBERS

64-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

55 G8 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is

LOW, the cycle is either a WRITE to the command execution logic

(CEL) or to the memory array. Addresses and data are latched on

the rising edge of the WE# pulse.

14, 2, 29 B4, B8, H1 CE0, CE1,

CE2

Input Chip Enable: Three CE pins enable the use of multiple Flash devices

in the system without requiring additional logic. The device can be

configured to use a single CE signal by tying CE1 and CE2 to

ground and then using CE0 as CE. Device selection occurs with the

first edge of CE0, CE1, or CE2 (CEx) that enables the device. Device

deselection occurs with the first edge of CEx that disables the

device (see Table 2 on page 11).

16 D4 RP# Input Reset/Power-Down: When LOW, RP# clears the status register, sets

the ISM to the array read mode, and places the device in deep

power-down mode. All inputs, including CEx, are “Don’t Care,”

and all outputs are High-Z. RP# must be held at VIH during all

other modes of operation.

54 F8 OE# Input Output Enables: Enables data ouput buffers when LOW. When

OE# is HIGH, the output buffers are disabled.

32, 28, 27, 26,

25, 24, 23, 22,

20, 19, 18, 17,

13, 12, 11, 10, 8,

7, 6, 5, 4, 3, 1,

G2, A1, B1, C1,

D1, D2, A2, C2,

A3, B3, C3, D3,

C4, A5, B5, C5,

D7, D8, A7, B7,

C7, C8, A8, G1

A0A21/

(A22)

(A23)

Input Address inputs during READ and WRITE operations.

A0 is only used in x8 mode and will be a NC in x16 mode (the input

buffer is turned off when BYTE = HIGH).

A22 (pin 1, ball A8) is only available on the 64Mb and 128Mb

devices.

A23 (pin 30, ball G1) is only available on the 128Mb device.

31 F1 BYTE# Input BYTE# low places the device in the x8 mode. BYTE# high places the

device in the x16 mode and turns off the A0 input buffer. Address

A1 becomes the lowest order address in x16 mode.

15 A4 VPEN Input Necessary voltage for erasing blocks, programming data, or

configuring lock bits. Typically, VPEN is connected to VCC. When

VPEN  VPENLK, this pin enables hardware write protect.

33, 35, 38, 40,

44, 46, 49, 51,

34, 36, 39, 41,

45, 47, 50, 52

F2, E2, G3, E4,

E5, G5, G6, H7,

E1, E3, F3, F4,

F5, H5, G7, E7

DQ0–

DQ15

Input/

Output

Data I/O: Data output pins during any READ operation or data

input pins during a WRITE. DQ8–DQ15 are not used in byte mode

(BYTE = LOW).

53 E8 STSOutput Status: Indicates the status of the ISM. When configured in level

mode (default), STS acts as a RY/BY# pin. When configured in its

pulse mode, it can pulse to indicate program and/or erase

completion. Tie STS to VCCQ through a pull-up resistor.

43 G4 VCCQSupply VCCQ controls the output voltages. To obtain output voltage

compatible with system data bus voltages, connect VCCQ to the

system supply voltage.

9, 37 H3, A6 VCC Supply Power Supply: 2.7V to 3.6V.

21, 42, 48 B2, H4, H6 VSS Supply Ground.

1, 30, 56 A1, G1, H8 NC — No Connect: These may be driven or left unconnected. Pin 1 and

ball A8 are NCs on the 32Mb device. Pin 30 and ball G1 are NCs on

the 32Mb and 64Mb devices.

— B6, C6, D5, D6,

E6, F6, F7, H2

DNU — Do Not Use: Must float to minimize noise.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Memory Architecture

The MT28F128J3, MT28F640J3, and MT28F320J3

memory array architecture is divided into one hun-

dred twenty-eight, sixty-four, or thirty-two 128KB

blocks, respectively (see Figure 6). The internal archi-

tecture allows greater flexibility when updating data

because individual code portions can be updated

independently of the rest of the code.

Figure 6: Memory Map

Read

Information can be read from any block, query,

identifier codes, or status register, regardless of the

VPEN voltage. The device automatically resets to read

array mode upon initial device power-up or after exit

from reset/power-down mode. To access other read

mode commands (READ ARRAY, READ QUERY, READ

IDENTIFIER CODES, or READ STATUS REGISTER),

these commands should be issued to the CUI. Six con-

trol pins dictate the data flow in and out of the device:

CE0, CE1, CE2, OE#, WE#, and RP#. In system designs

using multiple Q-Flash devices, CE0, CE1, and CE2

(CEx) select the memory device (see Table 2). To drive

data out of the device and onto the I/O bus, OE# must

be active and WE# must be inactive (VIH).

NOTE:

For single-chip applications, CE2 and CE1 can be con-

nected to GND.

When reading information in read array mode, the

device defaults to asynchronous page mode, thus pro-

viding a high data transfer rate for memory sub-

systems. In this state, data is internally read and stored

in a high-speed page buffer. A0–A2 select data in the

page buffer. Asynchronous page mode, with a page

size of four words or eight bytes, is supported with no

additional commands required and can be used to

access all blocks. Page mode can be used to access reg-

ister information, but only one word is loaded into the

page buffer.

Output Disable

The device outputs are disabled with OE# at a logic

HIGH level (VIH). Output pins DQ0–DQ15 are placed

in High-Z.

Standby

CE0, CE1, and CE2 can disable the device (see

Table 2) and place it in standby mode, which substan-

tially reduces device power consumption. DQ0–DQ15

outputs are placed in High-Z, independent of OE#. If

deselected during block erase, program, or lock bit

configuration, the ISM continues functioning and con-

suming active power until the operation completes.

Reset/Power-Down

RP# puts the device into the reset/power-down

mode when set to VIL.

During read, RP# LOW deselects the memory,

places output drivers in High-Z, and turns off internal

circuitry. RP# must be held LOW for a minimum of

tPLPH. tRWH is required after return from reset mode

until initial memory access outputs are valid. After this

Table 2: Chip-Enable Truth Table

CE2 CE1 CE0 DEVICE

VIL VIL VIL Enabled

VIL VIL VIH Disabled

VIL VIH VIL Disabled

VIL VIH VIH Disabled

VIH VIL VIL Enabled

VIH VIL VIH Enabled

VIH VIH VIL Enabled

VIH VIH VIH Disabled

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

wake-up interval, normal operation is restored. The

command execution logic (CEL) is reset to the read

array mode and the status register is set to 80h.

During block erase, program, or lock bit configura-

tion, RP# LOW aborts the operation. In default mode,

STS transitions LOW and remains LOW for a maxi-

mum time of tPLPH + tPHRH, until the RESET opera-

tion is complete. Any memory content changes are no

longer valid; the data may be partially corrupted after a

program or partially changed after an erase or lock bit

configuration. After RP# goes to logic HIGH (VIH), and

after tRS, another command can be written.

It is important to assert RP# during system reset.

After coming out of reset, the system expects to read

from the Flash memory. During block erase, program,

or lock bit configuration mode, automated Flash

memories provide status information when accessed.

When a CPU reset occurs with no Flash memory reset,

proper initialization may not occur because the Flash

memory may be providing status information instead

of array data. Micron Flash memories allow proper ini-

tialization following a system reset through the use of

the RP# input. RP# should be controlled by the same

RESET# signal that resets the system CPU.

Read Query

The READ QUERY operation produces block status

information, CFI ID string, system interface informa-

tion, device geometry information, and extended

query information. READ QUERY information is only

accessed by executing a single-word READ.

Read Identifier Codes

The READ IDENTIFIER CODES operation produces

the manufacturer code, device code, and the block

lock configuration codes for each block (see Figure 7).

The block lock configuration codes identify locked and

unlocked blocks.

Write

Writing commands to the CEL allows reading of

device data, query, identifier codes, and reading and

clearing of the status register. In addition, when VPEN =

VPENH, block erasure, program, and lock bit configura-

tion can also be performed.

The BLOCK ERASE command requires suitable

command data and an address within the block. The

BYTE/WORD PROGRAM command requires the com-

mand and address of the location to be written to. The

CLEAR BLOCK LOCK BITS command requires the

command and any address within the device. Set

BLOCK LOCK BITS command requires the command

and the block to be locked. The CEL does not occupy

an addressable memory location. It is written to when

the device is enabled and WE# is LOW. The address

and data needed to execute a command are latched on

the rising edge of WE# or the first edge of CEx that dis-

ables the device (see Table 2 on page 11). Standard

microprocessor write timings are used.

Figure 7: Device Identifier Code

Memory Map

NOTE:

When obtaining these identifier codes, A0 is not used in

either x8 or x16 modes. Data is always given on the

LOW byte in x16 mode (upper byte contains 00h).

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Bus Operation

All bus cycles to and from the Flash memory must

conform to the standard microprocessor bus cycles.

The local CPU reads and writes Flash memory

in-system.

NOTE:

1. See Table 2 on page 11 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH.

4. High-Z is VOH with an external pull-up resistor.

5. When Vpen £ Vpenlk, memory contents can be read, but not altered. Refer to the Recommended DC Electrical Char-

acteristics table on page 43.

6. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and

VPENH voltages.

7. In default mode, STS is VOL when the ISM is executing internal block erase, program, or lock bit configuration algo-

rithms. It is VOH when the ISM is not busy, in block erase suspend mode (with programming inactive), program sus-

pend mode, or reset/power-down mode.

8. See Read Identifier Codes section for read identifier code data.

9. See Read Query Mode Command section for read query data.

10. Command writes involving block erase, program, or lock bit configuration are reliably executed when VPEN = VPENH

and VCC is within specification.

11. Refer to Table 4 on page 14 for valid DIN during a WRITE operation.

Table 3: Bus Operations

MODE RP#

CE0, CE1,

CE21OE#2WE#2ADDRESS VPEN DQ3STS DEFAULT

MODE NOTES

Read Array VIH Enabled VIL VIH XXDOUT High-Z45, 6, 7

Output Disable VIH Enabled VIH VIH XXHigh-ZX

Standby VIH Disabled X X X X High-Z X

Reset/Power-down

Mode

VIL XXXXXHigh-Z

High-Z4

Read Identifier Codes VIH Enabled VIL VIH See Figure 7 X High-Z48

Read Query VIH Enabled VIL VIH See Table 7 X High-Z49

Read Status (ISM off) VIH Enabled VIL VIH XX

Read Status (ISM On)

DQ 7

DQ15–DQ8

DQ6–DQ0

VIH Enabled VIL VIH XX

DOUT

High-Z

Write VIH Enabled VIH VIL XVPENH DIN X7, 10, 11

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Command Definitions

When the Vpen voltage is < Vpenlk, only READ

operations from the status register, query, identifier

codes, or blocks are enabled. Placing Vpenh on Vpen

enables BLOCK ERASE, PROGRAM, and LOCK BIT

CONFIGURATION operations. Device operations are

selected by writing specific commands into the CEL, as

seen in Table 4.

Table 4: Micron Q-Flash Memory Command Set Definitions

Note 1; notes appear on following page

COMMAND

SCALABLE

OR BASIC

COMMAND

SET2

BUS

CYCLES

REQ’D

FIRST BUS CYCLE SECOND BUS CYCLE

NOTESOPER3ADDR4DATA5,

6OPER3ADDR4DATA5,

READ ARRAY SCS/BCS1WRITEX FFh

READ IDENTIFIER

CODES

SCS/BCS2 WRITE X 90h READ IA ID 7

READ QUERY SCS 2 WRITE X 98h READ QA QD

READ STATUS

SCS/BCS2 WRITE X 70h READ X SRD 8

CLEAR STATUS

SCS/BCS1 WRITE X 50h

WRITE TO BUFFER SCS/BCS> 2 WRITE BA E8h WRITE BA N 9, 10, 11

WORD/BYTE

PROGRAM

SCS/BCS2 WRITE X 40h or

10h

WRITE PA PD 12, 13

BLOCK ERASESCS/BCS2 WRITE BA 20h WRITE BA D0h 11, 12

BLOCK ERASE/

PROGRAM SUSPEND

SCS/BCS1 WRITE X B0h 14

BLOCK ERASE/

PROGRAM RESUME

SCS/BCS1 WRITE X D0h 12

CONFIGURATION SCS2 WRITE X B8h WRITE X CC

SET BLOCK LOCK BITSSCS2 WRITE X 60h WRITE BA 01h

CLEAR BLOCK LOCK

BITS

SCS2 WRITE X 60h WRITE X D0h

PROTECTION

PROGRAM

2 WRITE X C0h WRITE PA PD

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Commands other than those shown in Table 4 on page 14 are reserved for future device implementations and

should not be used.

2. The SCS is also referred to as the extended command set.

3. Bus operations are defined in Table 3 on page 13.

4. X = Any valid address within the device

BA = Address within the block

IA = Identifier code address; see Figure 7 on page 12 and Table 16 on page 23

QA = Query data base address

PA = Address of memory location to be programmed

5. ID = Data read from identifier codes

QD = Data read from query data base

SRD = Data read from status register; see Table 17 on page 24 for a description of the status register bits

PD = Data to be programmed at location PA; data is latched on the rising edge of WE#

CC = Configuration code

6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.

7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock

codes. See Block Status Register section for read identifier code data.

8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 are placed in High-Z.

9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.

10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count

ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third

and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command

(D0h) is expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the

WRITE-to-BUFFER operation. Please see Figure 9 on page 31, WRITE-to-BUFFER Flowchart, for additional informa-

tion.

11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.

12. Attempts to issue a block erase or program to a locked block will fail.

13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.

14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.

The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.

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Q-FLASH MEMORY

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READ ARRAY Command

The device defaults to read array mode upon initial

device power-up and after exiting reset/power-down

mode. The read configuration register defaults to

asynchronous read page mode. Until another com-

mand is written, the READ ARRAY command also

causes the device to enter read array mode. When the

ISM has started a block erase, program, or lock bit con-

figuration, the device does not recognize the READ

ARRAY command until the ISM completes its opera-

tion, unless the ISM is suspended via an ERASE or

PROGRAM SUSPEND command. The READ ARRAY

command functions independently of the VPEN volt-

age.

READ QUERY MODE Command

This section is related to the definition of the data

structure or “data base” returned by the CFI QUERY

command. System software should retain this struc-

ture to gain critical information such as block size,

density, x8/x16, and electrical specifications. When

this information has been obtained, the software

knows which command sets to use to enable Flash

writes or block erases, and otherwise control the Flash

component.

Query Structure Output

The query “data base” enables system software to

obtain information about controlling the Flash com-

ponent. The device’s CFI-compliant interface allows

the host system to access query data. Query data are

always located on the lowest-order data outputs

(DQ0–DQ7) only. The numerical offset value is the

address relative to the maximum bus width supported

by the device. On this family of devices, the query table

device starting address is a 10h, which is a word

address for x16 devices.

For a x16 organization, the first two bytes of the

query structure, “Q” and “R” in ASCII, appear on the

low byte at word addresses 10h and 11h. This CFI-

compliant device outputs 00h data on upper bytes,

thus making the device output ASCII “Q” on the LOW

byte (DQ7–DQ0) and 00h on the HIGH byte (DQ15–

DQ8). At query addresses containing two or more

bytes of information, the least significant data byte is

located at the lower address, and the most significant

data byte is located at the higher address. This is sum-

marized in Table 5. A more detailed example is pro-

vided in Table 6.

NOTE:

1. The system must drive the lowest-order addresses to access all the device’s array data when the device is configured

in x8 mode. Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applica-

ble” for x8-configured devices.

Table 5: Summary of Query-Structure Output as a Function of Device and Mode

DEVICE

TYPE/MODE

QUERY START LOCATION IN

MAXIMUM DEVICE BUS WIDTH

ADDRESSES

QUERY DATA WITH MAXIMUM

DEVICE BUS WIDTH

ADDRESSING

QUERY DATA WITH BYTE

ADDRESSING

HEX

OFFSET

HEX

CODE

ASCII

VALUE

HEX

OFFSET

HEX

CODE

ASCII

VALUE

x16 device

x16 mode

10h 10

0051

0052

0059

Null

x16 device

x8 mode N/A1N/A120

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Q-FLASH MEMORY

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Query Structure Overview

The QUERY command makes the Flash component

display the CFI query structure or data base. The struc-

ture subsections and address locations are outlined in

Table 7.

NOTE:

1. In word mode, A0 is not driven, so 0010h means that Address A5 = 1.

NOTE:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a func-

tion of device bus width and mode.

2. BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64K-

word).

3. Offset 15 defines “P,” which points to the Primary Extended Query Table.

Table 6: Example: Query Structure Output of x16- and x8-Capable Devices

WORD ADDRESSING BYTE ADDRESSING

OFFSET1HEX CODE VALUE OFFSET HEX CODE VALUE

A16–A1 DQ15–DQ0 A7–A0 DQ7–DQ0

0010h 0051 Q 20h 51 Q

0011h 0052 R 21h 51 Q

0012h 0059 Y 22h 52 R

0013h P_ID LO PrVendor 23h 52 R

0014h P_ID HI ID# 24h 59 Y

0015h P LO PrVendor 25h 59 Y

0016h P HI TblAdr 26h P_ID LO PrVendor

0017h A_ID LO AltVendor 27h P_ID LO PrVendor

0018h A_ID HI ID# 28h P_ID HI ID#

. . . . . . . . . . . . . . . . . .

Table 7: Query Structure1

OFFSET SUBSECTION NAME DESCRIPTION

00h Manufacturer compatibility code

01h Device code

(BA+2)h2Block Status Register Block-specific information

03–0Fh Reserved Reserved for vendor-specific information

10h CFI Query Identification String Reserved for vendor-specific information

1Bh System Interface Information Command-set ID and vendor data offset

27h Device Geometry Definition Flash device layout

P3Primary Extended Query Table Vendor-defined additional information specific to the primary

vendor algorithm

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CFI Query Identification String

The CFI query identification string verifies whether

the component supports the CFI specification. Addi-

tionally, it indicates the specification version and sup-

ported vendor-specified command set(s).

NOTE:

1. BA = the beginning location of a block address (i.e., 010000h is block one’s [64K-word] beginning location in word

mode).

Table 8: Block Status Register

OFFSET LENGTH DESCRIPTION ADDRESS1VALUE

(BA+2)h11Block Lock Status Register (BA+2)h

BSR0 Block Lock Status

0 = Unlocked

1 = Locked

(BA+2)h (Bit 0) 0 or 1

BSR1–7 Reserved for Future Use (BA+2)h (Bit 1–7) 0

Table 9: CFI Identification

OFFSET LENGTH DESCRIPTION ADDRESS

HEX

CODE VALUE

10h 3 Query-unique ASCII string “QRY” 10h

11h

12h

13h 2 Primary vendor command set and control interface ID code. 16-

bit ID code for vendor-specified algorithms

13h

14h

15h 2 Extended query table primary algorithm 15h

16h

17h 2 Alternate vendor command set and control interface ID code;

0000h means no second vendor-specified algorithm exists

17h

18h

19h 2 Secondary algorithm extended query table address; 0000h

means none exists

19h

1Ah

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System Interface Information

Table 10 provides useful information about opti-

mizing system interface software.

Table 10: System Interface Information

OFFSET LENGTH DESCRIPTION ADDRESS

HEX

CODE VALUE

1Bh 1 VCC logic supply minimum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 BCD volts

1Bh 27 2.7V

1Ch 1 VCC logic supply maximum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 BCD volts

1Ch 36 3.6V

1Dh 1 VPP [programming] supply minimum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 Hex volts

1Dh 00 0.0V

1Eh 1 VPP [programming] supply maximum program/erase voltage

Bits 0–3 BCD 100mV

Bits 4–7 Hex volts

1Eh 00 0.0V

1Fh 1 “n” such that typical single word program timeout = 2nµs 1Fh 07 128µs

20h 1 “n” such that typical max. buffer write timeout = 2nms 20h 07 128µs

21h 1 “n” such that typical block erase timeout = 2nµs 21h 0A 1s

22h 1 “n” such that typical full chip erase timeout = 2nms 22h 00 N/A

23h 1 “n” such that word program timeout = 2n times typical 23h 04 2ms

24h 1 “n” such that typical max. buffer write timeout = 2n times

typical

24h 04 2ms

25h 1 “n” such that maximum block erase timeout = 2n times typical 25h 04 16s

26h 1 “n” such that maximum chip erase timeout = 2n times typical 26h 00 N/A

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Device Geometry Definition

Tables 11 and 12 provide important details about

the device geometry.

Table 11: Device Geometry Definitions

OFFSET LENGTH DESCRIPTION

CODE

(see table 12 below)

27h 1 “n” such that device size= 2n in number of bytes 27h

28h 2 Flash device interface: x8 async, x16 async, x8/x16 async; 28:00

29:00, 28:01 29:00, 28:02 29:00

28h

29h

x8/x16

2Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2Ah

2Bh

2Ch 1 Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions with

one or more contiguous same-size erase blocks

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

2Ch 01 1

2Dh 4 Erase Block Region 1 Information

Bits 0–15 = y; y + 1 = number of identical-size erase blocks

Bits 16–31 = z; region erase block(s) size are z x 256 bytes

2Dh

2Eh

2Fh

30h

Table 12: Device Geometry Definition Codes

ADDRESS 32Mb 64Mb 128Mb

27h 16 17 18

28h 02 02 02

29h 00 00 00

2Ah050505

2Bh000000

2Ch010101

2Dh1F3F7F

2Eh 00 00 00

2Fh000000

30h 02 02 02

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Primary Vendor-Specific Extended-

Query Table

Table 13 includes information about optional Flash

features and commands and other similar information.

NOTE:

1. The variable “P” is a pointer which is defined at CFI offset 15h.

Table 13: Primary Vendor-Specific Extended-Query

OFFSET1

P = 31h

DESCRIPTION

(OPTIONAL FLASH FEATURES AND COMMANDS) ADDRESS

HEX

CODE VALUE

(P+0)h

(P+1)h

(P+2)h

Primary extended query table

Unique ASCII string, PRI

31h

32h

33h

(P+3)h Major version number, ASCII 34h 31 1

(P+4)h Minor version number, ASCII 35h 31 1

(P+5)h

(P+6)h

(P+7)h

(P+8)h

Optional feature and command support (1 = yes, 0 = no) bits 9–31are

reserved; undefined bits are “0.” If bit 31 is “1,” then another 31-bit field

of optional features follows at the end of the bit 30 field.

Bit 0 Chip erase supported = no = 0

Bit 1 Suspend erase supported = yes = 1

Bit 2 Suspend program supported = yes = 1

Bit 3 Legacy lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant Individual block locking supported = no = 0

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

36h

37h

38h

39h

C6h

(P+9)h Supported functions after suspend: read array, status, query

Other supported operations:

Bits 1–7 Reserved; undefined bits are “0”

Bit 0 Program supported after erase suspend = yes = 1

3Ah 01

(P+A)h

(P+B)h

Block status register mask

Bits 2–15 Reserved; undefined bits are “0”

Bit 0 Block lock bit status register active = yes = 1

Bit 1 Block lock down bit status active = no = 0

3Bh

3Ch

(P+C)h VCC logic supply highest-performance program/erase voltage

Bits 0–3 BCD value in 100mV

Bits 4–7 BCD value in volts

3Dh 33 3.3V

(P+D)h VPP optimum program/erase supply voltage

Bits 0–3 BCD value in 100mV

Bits 4–7 Hex value in volts

3Eh 00 0.0V

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NOTE:

1. The variable “P” is a pointer which is defined at CFI offset 15h.

NOTE:

1. The variable “P” is a pointer which is defined at CFI offset 15h.

Table 14: Protection Register Information

OFFSET1

P = 31h

DESCRIPTION

(Optional Flash Features and Commands) ADDRESS HEX

VALUE

CODE

(P+E)h Number of protection register fields in JEDEC ID space. “00h” indicates

that 256 protection bytes are available.

3Fh 01 01

(P+F)h

(P+10)h

(P+11)h

(P+12)h

Protection Field 1: Protection Description

This field describes user-available, one-time programmable (OTP)

protection register bytes. Some are pre-programmed with device-unique

serial numbers; others are user-programmable. Bits 0–15 point to the

protection register lock byte, the section’s first byte.

The following bytes are factory-pre-programmed and user-programmable.

Bits 0–7 Lock/bytes JEDEC-plane physical low address

Bits 8–15 Lock/bytes JEDEC-plane physical high address

Bits 16–23 “n” such that 2n = factory pre-programmed bytes

Bits 24–31 “n” such that 2n = user-programmable bytes

40h 00 00h

Table 15: Burst READ Information

OFFSET1

P = 31h

DESCRIPTION

(Optional Flash Features and Commands) ADDRESS HEX

VALUE

CODE

(P+13)h Page Mode Read Capability

Bits 0–7 = “n” such that 2n Hex value represents the number of read page

bytes. See offset 28h for device word width to determine page mode data

output width. 00h indicates no read page buffer.

44h 03 8 byte

(P+14)h Number of synchronous mode read configuration fields that follow. 00h

indicates no burst capability.

45h 00

(P+15)h Reserved for future use. 46h

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READ IDENTIFIER CODES Command

Writing the READ IDENTIFIER CODES command

initiates the IDENTIFIER CODE operation. Following

the writing of the command, READ cycles from

addresses shown in Figure 7 on page 12 retrieve the

manufacturer, device, and block lock configuration

codes (see Table 16 on page 23 for identifier code val-

ues). Page mode READs are not supported in this read

mode. To terminate the operation, write another valid

command. The READ IDENTIFIER CODES command

functions independently of the VPEN voltage. This

command is valid only when the ISM is off or the

device is suspended. See Table 16 on page 23 for read

identifier codes.

READ STATUS REGISTER Command

The status register may be read one of two ways:

either issue a discrete READ STATUS REGISTER com-

mand or when the ISM is running, a READ of the

device will provide valid status register data. Once the

device is in this mode, all subsequent READ opera-

tions output data from the status register until another

valid command is written. Page mode READs are not

supported in this read mode.

The status register contents are latched on the fall-

ing edge of OE# or the first edge of CEx that enables the

device (see Table 2 on page 11). To update the status

must be disabled before further READs. The READ

STATUS REGISTER command functions indepen-

dently of the VPEN voltage. During a program, block

erase, set block lock bits, or clear block lock bits com-

mand sequence, only SR7 is valid until the ISM com-

pletes or suspends the operation. Device I/O pins

DQ0–DQ6 and DQ8–DQ15 are placed in High-Z. When

the operation completes or suspends (check status

valid during a READ.

NOTE:

1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest-order address line is A1.

Data is always presented on the low byte in x16 mode (upper byte contains 00h).

2. Different ManID devices are ordered via separate part numbers. See Figure 4 on page 8 for details.

3. X selects the specific block’s lock configuration code. See Figure 6 on page 11 for the device identifier code memory

map.

Table 16: Identifier Codes

CODE ADDRESS1DATA

Manufacturer’s Identification Code2

• Intel ManID

• Micron ManID

X00000h (00) 89

(00) 2C

Device Code

•32Mb

•64Mb

•128Mb

X00001h (00) 16

(00) 17

(00) 18

Block Lock Configuration

• Block is Unlocked

• Block is Locked

• Reserved for Future Use

XX0002h3DQ0 = 0

DQ0 = 1

DQ1–DQ7

128Mb, 64Mb, 32Mb

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Table 17: Status Register Definitions

ISMS ESS ECLBS PSLBS VPENS PSS DPS R

76543210

HIGH-Z

WHEN

BUSY? STATUS REGISTER BITS NOTES

No SR7 = WRITE STATE MACHINE STATUS (ISMS)

1 = Ready

0 = Busy

Check STS or SR7 to determine block erase,

program, or lock bit configuration

completion. SR6–SR0 are not driven while

SR7 = 0.

Yes SR6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

Yes SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS)

1 = Error in Block Erasure or Clear Block Bits

0 = Successful Block Erase or Clear Lock Bits

If both SR5 and SR4 are “1s” after a block

erase, program, writer buffer command, or

lock bit configuration attempt, an improper

command sequence was entered.

Yes SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)

1 = Error in Programming or Setting Block Lock Bits

0 = Successful Program or Set Block Lock Bits

Yes SR3 = PROGRAMMING VOLTAGE STATUS (VPENS)

1 = Low Programming Voltage Detected,

Operation Aborted

0 = Programming Voltage OK

SR3 does not provide a continuous voltage

level indication. The ISM interrogates and

indicates the programming voltage level

only after block erase, program, set block

lock bits, or clear block lock bits command

sequences.

Yes SR2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

Yes SR1 DEVICE PROTECTSTATUS (DPS)

1 = Block Lock Bit Detected, Operation Aborted

0 = Unlock

SR1 does not provide a continuous

indication of block lock bit values. The ISM

interrogates the block lock bits only after

block erase, program, or lock bit

configuration command sequences. It

informs the system, depending on the

attempted operation, if the block lock bit is

set. Read the block lock configuration codes

using the READ IDENTIFIER CODES command

to determine block lock bits status. SR0 is

reserved for future use and should be

masked when polling the status register.

Yes SR0 = RESERVED FOR FUTURE ENHANCEMENTS

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CLEAR STATUS REGISTER Command

The ISM sets the status register bits SR5, SR4, SR3,

and SR1 to “1s.” These bits, which indicate various fail-

ure conditions, can only be reset by the CLEAR STA-

TUS REGISTER command. Allowing system software

to reset these bits can perform several operations

(such as cumulatively erasing or locking multiple

blocks or writing several bytes in sequence). To deter-

mine if an error occurred during the sequence, the sta-

tus register may be polled. To clear the status register,

the CLEAR STATUS REGISTER command (50h) is writ-

ten. The CLEAR STATUS REGISTER command func-

tions independently of the applied VPEN voltage and is

only valid when the ISM is off or the device is sus-

pended.

BLOCK ERASE Command

The BLOCK ERASE command is a two-cycle com-

mand that erases one block. First, a block erase setup

is written, followed by a block erase confirm. This

command sequence requires an appropriate address

within the block to be erased. The ISM handles all

block preconditioning, erase, and verify. Time tWB

after the two-cycle block erase sequence is written, the

device automatically outputs status register data when

read. The CPU can detect block erase completion by

analyzing the output of the STS pin or status register

bit SR7. Toggle OE# or CEx to update the status regis-

ter. Upon block erase completion, status register bit

SR5 should be checked to detect any block erase error.

When an error is detected, the status register should be

cleared before system software attempts corrective

actions. The CEL remains in read status register mode

until a new command is issued. This two-step setup

command sequence ensures that block contents are

not accidentally erased. An invalid block erase com-

mand sequence results in status register bits SR4 and

SR5 being set to “1.” Also, reliable block erasure can

only occur when VCC is valid and VPEN = VPENH. Note

that SR3 and SR5 are set to “1” if block erase is

attempted while VPEN  VPENLK. Successful block erase

requires that the corresponding block lock bit be

cleared. Similarly, SR1 and SR5 are set to “1” if block

erase is attempted when the corresponding block lock

bit is set.

BLOCK ERASE SUSPEND Command

The BLOCK ERASE SUSPEND command allows

block erase interruption in order to read or program

data in another block of memory. Writing the BLOCK

ERASE SUSPEND command immediately after starting

the block erase process requests that the ISM suspend

the block erase sequence at an appropriate point in

the algorithm. When reading after the BLOCK ERASE

SUSPEND command is written, the device outputs sta-

tus register data. Polling status register bit SR7, fol-

lowed by SR6, shows when the BLOCK ERASE

operation has been suspended. In the default mode,

STS also transitions to VOH. tLES defines the block

erase suspend latency. At this point, a READ ARRAY

command can be written to read data from blocks

other than that which is suspended. During erase sus-

pend to program data in other blocks, a program com-

mand sequence can also be issued. During a

PROGRAM operation with block erase suspended, sta-

tus register bit SR7 returns to “0” and STS output (in

default mode) transitions to VOL. However, SR6

remains “1” to indicate block erase suspend status.

Using the PROGRAM SUSPEND command, a program

operation can also be suspended. Resuming a SUS-

PENDED programming operation by issuing the Pro-

gram Resume command enables the suspended

programming operation to continue. To resume the

suspended erase, the user must wait for the program-

ming operation to complete before issuing the Block

ERASE RESUME command. While block erase is sus-

pended, the only other valid commands are READ

QUERY, READ STATUS REGISTER, CLEAR STATUS

RESUME. After a BLOCK ERASE RESUME command to

the Flash memory is completed, the ISM continues the

block erase process. Status register bits SR6 and SR7

automatically clear and STS (in default mode) returns

to VOL. After the ERASE RESUME command is com-

pleted, the device automatically outputs status register

data when read. VPEN must remain at VPENH (the same

VPEN level used for block erase) during block erase sus-

pension. Block erase cannot resume during block

erase suspend until PROGRAM operations are com-

plete.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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WRITE-to-BUFFER Command

The write-to-buffer command sequence is initiated

to program the Flash device via the write buffer. A

buffer can be loaded with a variable number of bytes,

up to the buffer size, before writing to the Flash device.

First, the WRITE-to-BUFFER SETUP command is

issued, along with the block address (see Figure 9 on

page 31). Then, the extended status register (XSR; see

Table 18) information is loaded and XSR7 indicates

“buffer available” status. If XSR7 = 0, the write buffer is

not available. To retry, issue the Write-to-Buffer setup

command with the block address and continue moni-

toring XSR7 until XSR7 = 1. When XSR7 transitions to

“1,” the buffer is ready for loading new data. Then the

part is given a word/byte count with the block address.

On the next write, a device start address is given, along

with the write buffer data. Depending on the count,

subsequent writes provide additional device addresses

and data. All subsequent addresses must lie within the

start address plus the count.

The device internally programs many Flash cells in

parallel. Due to this parallel programming, maximum

programming performance and lower power are

obtained by aligning the start address at the beginning

of a write buffer boundary (i.e., A0–A4 of the start

address = 0).

When the final buffer data is given, a WRITE CON-

FIRM command is issued, thus programming the ISM

to begin copying the buffer data to the Flash array. If

the device receives a command other than WRITE

CONFIRM, an invalid command/sequence error is

generated and status register bits SR5 and SR4 are set

to “1.” For additional BUFFER WRITEs, issue another

WRITE-to-BUFFER SETUP command and check XSR7.

If an error occurs during a write, the device stops

writing, and status register bit SR4 is set to a “1” to

indicate a program failure. The ISM only detects errors

for “1s” that do not successfully program to “0s.” When

a program error is detected, the status register should

be cleared. Note that the device does not accept any

more WRITE-to-BUFFER commands any time SR4

and/or SR5 is set. In addition, if the user attempts to

program past an erase block boundary with a WRITE-

to-BUFFER command, the device aborts the WRITE-

to-BUFFER operation and generates an invalid com-

mand/sequence error, and status register bits SR5 and

SR4 are set to “1.”

Reliable BUFFERED WRITEs can only occur when

VPEN = VPENH. If a BUFFERED WRITE is attempted

while VPEN  VPENLK, status register bits SR4 and SR3

are set to “1.” Buffered write attempts with invalid VCC

and VPEN voltages produce spurious results and

should not be attempted. Finally, the corresponding

block lock bit should be reset for successful program-

ming. When a BUFFERED WRITE is attempted while

the corresponding block lock bit is set, SR1 and SR4 are

set to “1.”

NOTE:

To access the XSR data, issue only a READ to the device.

Table 18: Extended Status Register Definitions (XSR)

WBS RESERVED

76–0

HIGH-Z WHEN

BUSY? STATUS REGISTER BITS NOTES

No XSR7 = WRITE BUFFER STATUS (WBS)

1 = Write Buffer Available

0 = Write Buffer Not Available

After a BUFFER WRITE command, ZXSR7 = 1

indicates that a write buffer is available.

Yes XSR6–XSR0 = RESERVED FOR FUTURE ENHANCEMENTSSR6–SR0 are reserved for future use and

should be masked when polling the status

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

BYTE/WORD PROGRAM Commands

A two-cycle command sequence executes a byte/

word program setup. This program setup (standard

40h or alternate 10h) is written, followed by a second

write that specifies the address and data (latched on

the rising edge of WE#). Next, the ISM takes over to

internally control the programming and program ver-

ify algorithms. When the program sequence is written,

the device automatically outputs status register data

when read (see Figure 10 on page 32). The CPU can

detect the completion of the program event by analyz-

ing the STS pin or status register bit SR7.

Upon program completion, status register bit SR4

should be checked. The status register should be

cleared if a program error is detected. The ISM only

detects errors for “1s” that do not successfully program

to “0s.” The CEL remains in read status register mode

until it receives another command.

Reliable byte/word programs can only occur when

VCC and VPEN are valid. Status register bits SR4 and

SR3 are set to “1” if a byte/word program is attempted

while VPEN  VPENLK. The corresponding block lock bit

should be cleared for successful byte/word programs.

If BYTE/WORD is attempted while the corresponding

block lock bit is set, SR1 and SR4 are set to “1.”

PROGRAM SUSPEND Command

The PROGRAM SUSPEND command enables pro-

gram interruption to read data in other Flash memory

locations. After starting the programming process,

writing the PROGRAM SUSPEND command requests

that the ISM suspend the program sequence at a pre-

determined point in the algorithm. When the PRO-

GRAM SUSPEND command is written, the device

continues to output status register data when read.

Polling status register bit SR7 can determine when the

programming operation has been suspended. When

SR7 = 1, SR2 is also set to “1” to indicate that the device

is in the program suspend mode. STS in RY/BY# level

mode also transitions to VOH. Note that tLPS defines

the program suspend latency.

Hence, a READ ARRAY command can be written to

read data from unsuspended locations. While pro-

gramming is suspended, the only other valid com-

mands are READ QUERY, READ STATUS REGISTER,

CLEAR STATUS REGISTER, CONFIGURE, and PRO-

GRAM RESUME. When the PROGRAM RESUME com-

mand is written, the ISM continues the programming

process. Status register bits SR2 and SR7 automatically

clear and STS in RY/BY# mode returns to VOL. After the

PROGRAM RESUME command is written, the device

automatically outputs status register data when read.

VPEN must remain at VPENH and VCC must remain at

valid VCC levels (the same VPEN and VCC levels used for

programming) while in program suspend mode. Refer

to Figure 11 on page 33 (PROGRAM SUSPEND/

RESUME Flowchart).

SET READ CONFIGURATION Command

Q-Flash memory does not support the SET READ

CONFIGURATION command. The devices default to

the asynchronous page mode. If this command is

given, the operation of the device will not be affected.

READ Configuration

Micron’s Q-Flash devices support both asynchro-

nous page mode and standard word/byte READs with-

out configuration requirement. Status register and

identifier only support standard word/byte single

READ operations.

STS CONFIGURATION Command

Using the CONFIGURATION command, the STS

pin can be configured to different states. Once config-

ured, the STS pin remains in that configuration until

another configuration command is issued, RP# is

asserted low, or the device is powered down. Initially,

the STS pin defaults to RY/BY# operation where RY/

BY# goes LOW to indicate that the state machine is

busy. When HIGH, RY/BY# indicates that either the

state machine is ready for a new operation or it is sus-

pended. Table 19 on page 28, Configuration Coding

Definitions, shows the possible STS configurations. To

change the STS pin to other modes, the CONFIGURA-

TION command is given, followed by the desired con-

figuration code. The three alternate configurations are

all pulse modes and may be used as a system interrupt.

With these configurations, bit 0 controls erase com-

plete interrupt pulse, and bit 1 controls program com-

plete interrupt pulse. Providing the 00h configuration

code with the CONFIGURATION command resets the

STS pin to the default RY/BY# level mode. Table 19 on

page 28 describes possible configurations and usage.

The CONFIGURATION command can only be given

when the device is not busy or suspended. When con-

figured in one of the pulse modes, the STS pin pulses

LOW with a typical pulse width of 250ns. Check SR7 for

device status. An invalid configuration code results in

status register bits SR4 and SR5 being set to “1.”

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. An invalid configuration code will result in both SR4 and SR5 being set.

2. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of

250ns.

SET BLOCK LOCK BITS Command

A flexible block locking and unlocking scheme is

enabled via a combination of block lock bits. The block

lock bits gate PROGRAM and ERASE operations. Using

the SET BLOCK LOCK BITS command, individual

block lock bits can be set. This command is invalid

when the ISM is running or when the device is sus-

pended. SET BLOCK LOCK BITS commands are exe-

cuted by a two-cycle sequence. The set block lock bits

setup, along with appropriate block address, is fol-

lowed by the set block lock bits confirm and an

address within the block to be locked. The ISM then

controls the set lock bit algorithm. When the sequence

is written, the device automatically outputs status reg-

ister data when read (see Figure 14 on page 36). The

CPU can detect the completion of the set block lock bit

event by analyzing the STS pin output or status register

bit SR7. Upon completion of set block lock bits opera-

tion, status register bit SR4 should be checked for

error. If an error is detected, the status register should

be cleared. The CEL remains in read status register

mode until a new command is issued. This two-step

sequence of setup followed by execution ensures that

lock bits are not accidentally set. An invalid SET

BLOCK LOCK BITS command results in status register

bits SR4 and SR5 being set to “1.”

CLEAR BLOCK LOCK BITS Command

The CLEAR BLOCK LOCK BITS command can clear

all set block lock bits in parallel. This command is

invalid when the ISM is running or the device is sus-

pended. The CLEAR BLOCK LOCK BITS command is

executed by a two-cycle sequence. First, a clear block

lock bits setup is written, followed by a CLEAR BLOCK

LOCK BITS CONFIRM command. Then the device

automatically outputs status register data when read

(see Figure 14 on page 36). The CPU can detect com-

pletion of the clear block lock bits event by analyzing

the STS pin output or the status register bit SR7. When

the operation is completed, status register bit SR5

should be checked. If a clear block lock bits error is

detected, the status register should be cleared. The

CEL remains in read status register mode until another

command is issued.

This two-step setup sequence ensures that block

lock bits are not accidentally cleared. An invalid

CLEAR BLOCK LOCK BITS command sequence results

in status register bits SR4 and SR5 being set to “1.”

Also, a reliable CLEAR BLOCK LOCK BITS operation

can only occur when VCC and VPEN are valid. If a clear

block lock bits operation is attempted when VPEN 

VPENLK, SR3 and SR5 are set to “1.” If a CLEAR BLOCK

LOCK BITS operation is aborted due to VPEN or VCC

transitioning out of valid range, block lock bit values

Table 19: Configuration Coding Definitions1

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

RESERVED

PULSE ON

PROGRAM

COMPLETE2

PULSE ON

ERASE

COMPLETE2

DQ1–DQ0 = STS Configuration Codes NOTES

00 = Default, RY/BY# level mode (device

ready) indication

Used to control HOLD to a memory controller to prevent accessing a Flash

memory subsystem while any Flash device’s ISM is busy.

01 = Pulse on Erase Complete Used to generate a system interrupt pulse when any Flash device is an array

has completed a BLOCK ERASE or sequence of queued BLOCK ERASEs;

helpful for reformatting blocks after file system free space reclamation or

“clean-up.”

10 = Pulse on Program Complete Used to generate a system interrupt pulse when any Flash device in an array

has completed a PROGRAM operation. Provides highest performance for

enabling continuous BUFFER WRITE operations.

11 = Pulse on Erase or Program Complete Used to generate system interrupts to trigger enabling of Flash arrays when

either ERASE or PROGRAM operations are completed and a common

interrupt service routine is desired.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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are left in an undetermined state. To initialize block

lock bit contents to known values, a repeat of CLEAR

BLOCK LOCK BITS is required.

PROTECTION REGISTER PROGRAM

Command

The 3V Q-Flash memory includes a 128-bit protec-

tion register to increase the security of a system

design. For example, the number contained in the pro-

tection register can be used for the Flash component

to communicate with other system components, such

as the CPU or ASIC, to prevent device substitution. The

128 bits of the protection register are divided into two

64-bit segments. One of the segments is programmed

at the Micron factory with a unique and unchangeable

64-bit number. The other segment is left blank for cus-

tomers to program as needed. After the customer seg-

ment is programmed, it can be locked to prevent

reprogramming.

Reading the Protection Register

The protection register is read in the identification

read mode. The device is switched to identification

read mode by writing the READ IDENTIFIER com-

mand (90h). When in this mode, READ cycles from

addresses shown in Table 20 on page 30 or Table 21 on

page 30 retrieve the specified information. To return to

read array mode, the READ ARRAY command (FFh)

must be written.

Programming the Protection Register

The protection register bits are programmed with

two-cycle PROTECTION PROGRAM commands.

The 64-bit number is programmed 16 bits at a time

for word-wide parts and eight bits at a time for byte-

wide parts. First, the PROTECTION PROGRAM SETUP

command, C0h, is written. The next write to the device

latches in addresses and data, and programs the speci-

fied location. The allowable addresses are shown in

Table 20 on page 30 and Table 21 on page 30. Any

attempt to address PROTECTION PROGRAM com-

mands outside the defined protection register address

space results in a status register error (program error

bit SR4 is set to “1”). Attempting to program a locked

protection register segment results in a status register

error (program error bit SR4 and lock error bit SR1 are

set to “1”).

Locking the Protection Register

By programming bit 1 of the PR-LOCK location to

“0,” the user-programmable segment of the protection

ber, bit 0 of this location is programmed to “0” at the

Micron factory. Bit 1 is set using the PROTECTION

PROGRAM command to program “FFFDh” to the PR-

LOCK location. When these bits have been pro-

grammed, no further changes can be made to the val-

ues stored in the protection register. PROTECTION

PROGRAM commands to a locked section will result in

a status register error (program error bit SR4 and lock

error bit SR1 are set to “1”). Note that the protection

Figure 8: Protection Register Memory

Map

NOTE:

A0 is not used in x16 mode when accessing the protec-

tion register map (see Table 20 on page 30 for x16

addressing). A0 is used for x8 mode (see Table 21 on

page 30 for x8 addressing).

4 Words

Factory-Programmed

4 Words

User-Programmed

1 Word Lock

88h

85h

84h

81h

80h 0

Word

ddress

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

All address lines not specified in the above tables must be “0”when accessing the protection register (i.e., A24–A9 = 0).

Table 20: Word-Wide Protection Register Addressing

WORD USE A8 A7 A6 A5 A4 A3 A2 A1

LOCK Both 10000000

0 Factory 10000001

1 Factory 10000010

2 Factory 10000011

3 Factory 10000100

4 User 10000101

5 User 10000110

6 User 10000111

7 User 10001000

Table 21: Byte-Wide Protection Register Addressing

BYTE USE A8 A7 A6 A5 A4 A3 A2 A1 A0

LOCKBoth 100000000

0 Factory 100000010

1 Factory 100000011

2 Factory 100000100

3 Factory 100000101

4 Factory 100000110

5 Factory 100000111

6 Factory 100001000

7 Factory 100001001

8 User 100001010

9 User 100001011

A User 100001100

B User 100001101

C User 100001110

D User 100001111

E User 100010000

F User 100010001

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 9: WRITE-to-BUFFER Flowchart

NOTE:

1. Issuing a READ STATUS REGISTER command (70h) will result in an invalid WRITE BUFFER command.

2. Byte or word count values on DQ0–DQ7 are loaded into the count register. Count ranges on this device for byte

mode are n = 00h to 1Fh and for word mode are n = 0000h to 000Fh.

3. The device now outputs the status register when read (XSR is no longer available).

4. Write buffer contents will be programmed at the device start address or destination Flash address.

5. Align the start address on a write buffer boundary for maximum programming performance (i.e., A4–A0 of the

start address = 0).

6. The device aborts the WRITE-to-BUFFER command if the current address is outside of the original block address.

7. The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Fol-

low this with a CLEAR STATUS REGISTER command.

8. Toggling OE# (LOW to HIGH to LOW) updates the status register. This must be done in place of issuing the READ

STATUS REGISTER command.

Write Word or

Byte Count N,

Block Address

Write Buffer Data,

Start Address

X = 0

Write Next Buffer

Data, Device Address

Abort

WRITE-to-BUFFER

Command?

Check

X = N?

Another

WRITE-to-BUFFER

Read Status Register

SR7 =

Read Extended

Status Register

XSR7 =

Yes

Write to Buffer

Aborted

Yes

Full Status

Check if Desired

Issue

WRITE-to-BUFFER

Command E8h,

Block Address

Write to Another

Block Address

WRITE-to-

BUFFER Timeout?

Set Timeout

Issue

READ STATUS

Command

Yes

Start

Programming

Complete

X = X + 1

Program Buffer to

Flash Confirm D0h

BUS

OPERATION COMMAND COMMENTS NOTES

WRITE WRITE-to-

BUFFER

Data = E8h

Block Address

READ XSR7 = Valid

Addr = Block Address

STANDBY Check XSR7

1 = Write Buffer Available

0 = Write Buffer Not

Available

WRITE Data = N = Word/Byte

Count

N = 0 Corresponds to Count

= 1

Addr = Block Address

2, 3

WRITE Data = Write Buffer Data

Addr = Device Start

Address

4, 5

WRITE Data = Write Buffer Data

Addr = Device Address

6, 7

WRITE Program

Buffer to

Flash

Confirm

Data = D0h

Addr = Block Address

READ Status register data with

the device enabled, OE#

LOW updates the SR

Addr = Block Address

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

Full status check can be done after all erase and write sequences

complete. Write FFh after the last operation to reset the device

to read array mode.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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Figure 10: BYTE/WORD PROGRAM

Flowchart

Full Status

Check if Desired

SR7 =

Start

Byte/Word

Program Successful

Device Protect Error

Voltage Range Error

Programming Error

FULL STATUS CHECK PROCEDURE

Read Status

SR3 =

Byte/Word

Program Complete

Read Status Register

Data (see above)

SR1 =

SR4 =

Write 40h,

Address

Write Data and

Address

BUS

OPERATION COMMAND COMMENTS

WRITE SETUP BYTE/

WORD

PROGRAM

Data = 40h

Addr = Location to be

programmed

WRITE BYTE/WORD

PROGRAM

Data = Data to be

programmed

Addr = Location to be

programmed

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

Toggling OE# (LOW to HIGH to LOW) updates the status register.

To ensure the availability of correct status, please follow the

timings shown in Figure 20 on page 50. This can be done in

place of issuing the READ STATUS REGISTER command. Repeat

for subsequent programming operations.

After each program operation or after a sequence of

programming operations, an SR full status check can be done.

Write FFh after the last program operation to place the device in

read array mode.

BUS

OPERATION COMMAND COMMENTS

WRITE SETUP BYTE/

WORD

PROGRAM

Check SR3

1 = Programming to

Voltage Error Detect

WRITE BYTE/WORD

PROGRAM

Check SR1

1 = Device Protect Detect

RP# = VIH, Block Lock Bit is

Set

Only required for systems

implementing lock bit

configuration

READ Status Register Data

STANDBY Check SR4

1 = Programming Error

Toggling OE# (LOW to HIGH to LOW) updates the status register.

This can be done in place of issuing the READ STATUS REGISTER

command. Repeat for subsequent programming operations.

SR4, SR3, and SR1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed

before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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Figure 11: PROGRAM SUSPEND/RESUME

Flowchart

SR7 =

SR2 =

Yes

Done Reading

Write FFh

Start

Read Status

Programming

Resumed

Programming

Completed

Write B0h

Write D0h

Read Data Array

Write FFh

Read Data Array

BUS OPERATION COMMAND COMMENTS

WRITE PROGRAM

SUSPEND

Data = B0h

Addr = X

READ Status Register Data

Addr = X

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

STANDBY Check SR6

1 = Programming Suspend

0 = Programming

Completed

WRITE READ ARRAY Data = FFh

Addr = X

READ Read array locations other

than that being

programmed

WRITE PROGRAM

RESUME

Data = D0h

Addr =X

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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Figure 12: BLOCK ERASE Flowchart

Yes

SR7 = Suspend Erase

Suspend

Erase Loop

Full Status

Check if Desired

Start

Write Confirm D0h

Block Address

Read Status

Erase Flash

Block(s) Complete

Issue Single BLOCK

ERASE Command 20h,

Block Address

BUS OPERATION COMMAND COMMENTS

WRITE ERASE BLOCK Data = 20h

Addr = Block Address

WRITE ERASE

CONFIRM

Data = D0h

Addr = Block Address

READ Status register data with

the device enabled; OE#

LOW updates SR

Addr = X

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

Toggling OE# (LOW to HIGH to LOW) updates the status register.

To ensure the availability of correct status, please follow the

timings shown in Figure 20 on page 50. This can be done in place

of issuing the READ STATUS REGISTER command. Repeat for

subsequent ERASE operations.

The erase confirm byte must follow erase setup.

This device does not support erase queuing.

Full status check can be done after all erase and write sequences

complete. Write FFh after the last operation to reset the device

to read array mode.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 13: BLOCK ERASE SUSPEND/

RESUME Flowchart

SR7 =

SR6 =

Read or

Program?

Read Program

Yes

Done?

Start

Read Status

BLOCK ERASE

Resumed

BLOCK ERASE

Completed

Write B0h

Write D0h

Read Data Array

Write FFh

Read Array

Data

Program

Loop

BUS

OPERATION COMMAND COMMENTS

WRITE ERASE SUSPEND Data = B0h

Addr = X

READ Status Register Data

Addr = X

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

STANDBY Check SR6

1 = Block Erase Suspend

0 = Block Erase Completed

WRITE ERASE RESUME Data = D0h

Addr = X

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 14: SET BLOCK LOCK BITS

Flowchart

Full Status

Check if Desired

SR7 =

Start

SET BLOCK LOCK BITS

Successful

Command Sequence

Error

Voltage Range Error

SET BLOCK LOCK BITS

Error

FULL STATUS CHECK PROCEDURE

Read Status

SR3 =

SET BLOCK LOCK BITs

Complete

Read Status Register

Data (see above)

SR4,5 =

SR4 =

Write 60h,

Block Address

Write 01h,

Block Address

BUS

OPERATION COMMAND COMMENTS

WRITE SET BLOCK

LOCK BITS

SETUP

Data = 60h

Addr = Block Address

WRITE SET BLOCK

LOCK BITS

CONFIRM

Data = 01h

Addr = Block Address

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

Repeat for subsequent lock bit operations.

Full status check can be done after each lock bit set operation or

after a sequence of lock bit set operations.

Write FFh after the last lock bit set operation to place device in read

array mode.

BUS

OPERATION COMMAND COMMENTS

STANDBY Check SR3

1= Programming Voltage

Error Detect

STANDBY Check SR4, SR5

Both 1 = Command

Sequence Error

STANDBY Check SR4

1 = Set Block Lock Bits Error

SR5, SR4, and SR3 are only cleared by the Clear Status Register

command in cases where multiple lock bits are set before full

status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 15: CLEAR BLOCK LOCK BITS

Flowchart

Full Status

Check if Desired

SR7 =

Start

CLEAR BLOCK LOCK

BITS Successful

Command Sequence

Error

CLEAR BLOCK LOCK

BITS Error

Voltage Range Error

FULL STATUS CHECK PROCEDURE

Read Status

SR3 =

CLEAR BLOCK LOCK

BITS Complete

Read Status Register

Data (see above)

SR4,5 =

SR5 =

Write 60h

Write D0h

BUS

OPERATION COMMAND COMMENTS

WRITE CLEAR BLOCK

LOCK BITS

SETUP

Data = 60h

Addr = X

WRITE CLEAR BLOCK

LOCK BITS

CONFIRM

Data = D0h

Addr = X

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

Write FFh after the CLEAR BLOCK LOCK BITS operation to place

device in read array mode.

BUS

OPERATION COMMAND COMMENTS

STANDBY Check SR3

1= Programming Voltage

Error Detect

STANDBY Check SR4, SR5

Both 1 = Command

Sequence Error

STANDBY Check SR4

1 = Clear Block Lock Bits

Error

SR5, SR4, and SR3 are only cleared by the Clear Status Register

command.

If an error is detected, clear the status register before

attempting retry or other error recovery.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 16: PROTECTION REGISTER

PROGRAMMING Flowchart

Yes

1, 1

0, 1

1, 1

Full Status

Check if Desired

SR7 = 1

Start

PROGRAM

Successful

PROTECTION REGISTER

PROGRAMMING Error

Attempted Program to

Locked Register –

Aborted

VPEN Range Error

FULL STATUS CHECK PROCEDURE

Read Status

SR3, SR4 =

PROGRAM

Complete

Read Status Register

Data (see above)

SR1, SR4 =

Write C0h

(Protection Register

Program Setup)

Write Protect Register

Address/Data

BUS OPERATION COMMAND COMMENTS

WRITE PROTECTION

PROGRAM

SETUP

Data = C0h

WRITE PROTECTION

PROGRAM

Data = Data to Program

Addr = Location to Program

READ Status Register Data

Toggle CE# or OE# to

update status register data

STANDBY Check SR7

1 = ISM Ready

0 = ISM Busy

PROTECTION PROGRAM operations can only be addressed within

the protection register address space. Addresses outside the

defined space will return an error.

Repeat for subsequent programming operations.

SR full status check can be done after each program or after a

sequence of program operations.

Write FFh after the last program operation to reset device to

read array mode.

BUS OPERATION COMMAND

COMMENTS

SR1 SR3 SR4

STANDBY 0 xxx1 xxx1 xxvVPEN LOW

STANDBY 0 xxx1 xxx1 xxvProtection

Program

Error

STANDBY 1 xxx0 xxx1 xxvRegister

Locked:

Aborted

SR3, if set during a program attempt, MUST be cleared before

further attempts are allowed by the ISM.

SR1, SR3, and SR4 are only cleared by the CLEAR STATUS

program operations, before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Design Considerations

Five-Line Output Control

Micron provides five control inputs (CE0, CE1, CE2,

OE#, and RP#) to accommodate multiple memory

connections in large memory arrays. This control pro-

vides the lowest possible memory power dissipation

and ensures that data bus contention does not occur.

To efficiently use these control inputs, an address

decoder should enable the device (see Table 2 on

page 11) while OE# is connected to all memory devices

and the system’s READ# control line. This ensures that

only selected memory devices have active outputs

while deselected memory devices are in standby

mode. During system power transitions, RP# should

be connected to the system POWERGOOD signal to

prevent unintended writes. POWERGOOD should also

toggle during system reset.

STS and Block Erase, Program, and Lock

Bit Configuration

Polling

As an open drain output, STS should be connected

to VCCQ by a pull-up resistor to provide a hardware

method of detecting block erase, program, and lock bit

configuration completion. It is recommended that a

2.5K resistor be used between STS# and VCCQ. In

default mode, it transitions low after block erase, pro-

gram, or lock bit configuration commands and returns

to High-Z when the ISM has finished executing the

internal algorithm. See the CONFIGURATION com-

mand for alternate configurations of the STS pin. STS

can be connected to an interrupt input of the system

CPU or controller. STS is active at all times. In default

mode, it is also High-Z when the device is in block

erase suspend (with programming inactive), program

suspend, or reset/power-down mode.

Power Supply Decoupling

Device decoupling is required for Flash memory

power switching characteristics. There are three sup-

ply current issues to consider: standby current levels,

active current levels, and transient peaks produced by

falling and rising edges of CEx and OE#. Transient cur-

rent magnitudes depend on the device outputs’ capac-

itive and inductive loading. Two-line control and

proper decoupling capacitor selection suppresses

transient voltage peaks. Because Micron Q-Flash

memory devices draw their power from three VCC pins

(these devices do not include a VPP pin), it is recom-

mended that systems without separate power and

ground planes attach a 0.1µF ceramic capacitor

between each of the device’s three VCC pins (this

includes VCCQ) and GND. These high-frequency, low-

inductance capacitors should be placed as close as

possible to package leads on each Micron Q-Flash

memory device. Additionally, for every eight devices, a

4.7µF electrolytic capacitor should be placed between

VCC and GND at the array’s power supply connection.

Reducing Overshoots and Undershoots

When Using Buffers or Transceivers

Overshoots and undershoots can sometimes cause

input signals to exceed Flash memory specifications as

faster, high-drive devices such as transceivers or buff-

ers drive input signals to Flash memory devices. Many

buffer/transceiver vendors now carry bus-interface

devices with internal output-damping resistors or

reduced-drive outputs. Internal output-damping

resistors diminish the nominal output drive currents,

while still leaving sufficient drive capability for most

applications. These internal output-damping resistors

help reduce unnecessary overshoots and undershoots

by diminishing output-drive currents. When consider-

ing a buffer/transceiver interface design to Flash,

devices with internal output-damping resistors or

reduced-drive outputs should be used to minimize

overshoots and undershoots.

VCC, VPEN, and RP# Transitions

If VPEN or VCC falls outside of the specified operat-

ing ranges, or RP# is not set to VIH, block erase, pro-

gram, and lock bit configuration are not guaranteed. If

RP# transitions to VIL during block erase, program, or

lock bit configuration, STS (in default mode) will

remain LOW for a maximum time of tPLPH + tPHRH,

until the RESET operation is complete and the device

enters reset/power-down mode. The aborted opera-

tion may leave data partially corrupted after program-

ming, or partially altered after an erase or lock bit

configuration. Therefore, block erase and lock bit con-

figuration commands must be repeated after normal

operation is restored. Device power-off or RP# = VIL

clears the status register. The CEL latches commands

issued by system software and is not altered by VPEN or

CEx transitions, or ISM actions. Its state is read array

mode upon power-up, upon exiting reset/power-

down mode, or after VCC transitions below VLKO. VCC

must be kept at or above VPEN during VCC transitions.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

After block erase, program, or lock bit configura-

tion, and after VPEN transitions to VPENLK, the CEL

must be placed in read array mode via the READ

ARRAY command if subsequent access to the memory

array is desired. During VPEN transitions, VPEN must be

kept at or below VCC.

Power-Up/Down Protection

During power transition, the device itself provides

protection against accidental block erasure, program-

ming, or lock bit configuration. Internal circuitry

resets the CEL to read array mode at power-up. A sys-

tem designer must watch out for spurious writes for

VCC voltages above VLKO when VPEN is active. Because

WE# must be low and the device enabled (see Table 2

on page 11) for a command write, driving WE# to VIH

or disabling the device inhibits WRITEs. The CEL’s

two-step command sequence architecture provides

added protection against data alteration. In-system

block lock and unlock capability protects the device

against inadvertent programming. The device is dis-

abled when RP# = VIL regardless of its control inputs.

Keeping VPEN below VPENLK prevents inadvertent data

change.

Power Dissipation

Designers must consider battery power consump-

tion not only during device operation, but also for data

retention during system idle time. Flash memory’s

non-volatility increases usable battery life because

data is retained when system power is removed.

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Electrical Specificatons

NOTE:

1. Stresses greater than those listed in Table 22 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect reliability.

2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC

and VPEN pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on

input/output pins, VCC, and VPEN is VCC +0.5V which, during transitions, may overshoot to VCC +2.0V for periods

<20ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

Table 22: Absolute Maximum Ratings

Note 1

VOLTAGE MIN MAX UNITS NOTES

Temperature under bias expanded -40 +85 °C

Storage Temperature -65 +125 °C

For VCCQ = +2.7V to +3.6V

Voltage on any pin -2.0V +5.0 V 2

Short Circuit Output Current 100 mA 3

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and

speeds).

2. Sampled, not 100 percent tested.

3. Includes STS.

Table 23: Temperature and Recommended DC Operating Conditions

Extended temperature (-40ºC  TA  +85ºC)

PARAMATER SYMBOL MIN MAX UNITS NOTES

VCC Supply Voltage (2.7V–3.6V) Vcc 2.7 3.6 V

VCCQ Supply Voltage (2.7V–3.6V) VccQ 2.7 3.6 V

Input and VPEN Load Current

VCC = VCC (MAX); VCCQ = VCCQ (MAX)

VIN = VCCQ or GND

ILI ±1 µA 1

Output Leakage Current

VCC = VCC (MAX); VCCQ = VCCQ (MAX)

VIN = VCCQ or GND

ILO ±10 µA 1

Input Low Voltage VIL -0.5 0.8 V 2

Input High Voltage VIH 2VCCQ + 0.5 V 2

Output Low Voltage (2.7V–3.6V)

VCCQ = VccQ (MIN)

IOL = 2mA VOL

0.4 V

2, 3

VCCQ = VccQ (MIN)

IOL = 100µA 0.2 V

Output High Voltage (2.7V–3.6V)

VCCQ = VCCQ (MIN)

IOH = -2.5mA VOH

0.85 x VCCQV

VCCQ = VCCQ (MIN)

IOH = -100µA VCCQ – 0.2 V

Table 24: Capacitance

TA = +25ºC; f = 1MHz

PARAMETER/CONDITION SYMBOL TYP MAX UNITS

Input Capacitance BYTE# 32Mb C 10 12 pF

64Mb and 128Mb 14 16 pF

All other pins 58pF

Output Capacitance COUT 512pF

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

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Table 25: Recommended DC Electrical Characteristics

Notes appear on page 44; extended temperature (-40ºC  TA  +85ºC)

DESCRIPTION CONDITIONS SYM DENSITY TYP MAX UNITS NOTES

VCC Standby Current CMOS Inputs; VCC = VCC (MAX);

Device is enabled; RP# = VCCQ ±0.2V

ICC1 32Mb 75 120 µA 1, 2, 3

64Mb 75

128Mb 50

TTL inputs; VCC = VCC (MAX): Device

is enabled; RP# = VIH

32Mb 100 2,000 µA

64Mb 100

128Mb 90

VCC Power-Down Current RP# = GND ±0.2V; IOUT (STS) = 0mA ICC2 32Mb 75 120 µA 1, 3

64Mb 75

128Mb 50

VCC Page Mode Read Current CMOS inputs; VCC = VCC (MAX);

VCCQ = VCCQ (MAX) using standard

4-word page mode READs; Device is

enabled; f = 5 MHz; IOUT = 0mA

ICC3 All 15 20 mA

CMOS inputs; VCC = VCC (MAX);

VCCQ = VCCQ (MAX) using standard

4-word page mode READs; Device is

enabled; f = 33 MHz; IOUT = 0mA

25 29

VCC Asynchronous Mode Read

Current

CMOS inputs; VCC = VCC (MAX);

VCCQ = VCCQ (MAX) using standard

word/byte single READs; Device is

enabled;

f = 5 MHz; IOUT = 0mA

ICC4 All 9 50 mA 1, 3

VCC Program or Set Lock Bits

Current

CMOS inputs, VPEN = VCC ICC5 32Mb 24 60 mA 1, 4

64Mb 24 60

128Mb 17 60

TTL inputs, VPEN = VCC 32Mb 24 70

64Mb 24 70

128Mb 17 70

VCC Block Erase or Clear Block

Lock Bits Current

CMOS inputs, VPEN = VCC ICC6 32Mb 26 70 mA 1, 4

64Mb 26 70

128Mb 17 70

TTL inputs, VPEN = VCC 32Mb 26 80

64Mb 26 80

128Mb 17 80

VCC Program Suspend or Block

Erase Suspend Current

Device is disabled ICC7All 10mA1

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and

speeds).

2. Includes STS.

3. CMOS inputs are either VCC ±0.2V or VSS ±0.2V. TTL inputs are either VIL or VIH with a minimum of -0.2V.

4. Sampled, not 100 percent tested.

5. ICCWS and ICCES are specified with the device deselected. If the device is read or written while in erase suspend

mode, the device’s current draw is ICCR or ICCW.

6. Block erase, programming, and lock bit configurations are inhibited when VPEN  VPENLK, and they are not guaran-

teed in the range between VPENLK (MAX) and VPENH (MIN), or above VPENH (MAX).

7. Typically, VPEN is connected to VCC.

8. Block erase, programming, and lock bit configurations are inhibited when VCC < VLKO, and they are not guaranteed

in the range between VLKO (MIN) and VCC (MIN), or above VCC (MAX).

9. VPENH (MIN) = 2.7V.

Figure 17: Transient Input/Output Reference Waveform for VccQ = 2.7V – 3.6V

NOTE:

AC test inputs are driven at VCCQ for a logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends, at

VCCQ/2V (50 percent of VCCQ). Input rise and fall times (10 percent to 90 percent) < 5ns.

VPEN Lockout during

PROGRAM, ERASE, and LOCK

BIT Operations

VPENLK All 0.8 V 5, 6, 7

VPEN during BLOCK ERASE,

PROGRAM, or LOCK BIT

Operations

VPENH All 3.6 V 6, 7, 9

VCC Lockout Voltage VLKO All 2.2 V 4, 8

Table 25: Recommended DC Electrical Characteristics

Notes appear on page 44; extended temperature (-40ºC  TA  +85ºC)

DESCRIPTION CONDITIONS SYM DENSITY TYP MAX UNITS NOTES

Test PointsInput V

Q/2 V

Q/2 Output

0.0

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 18: Transient Equivalent Test Load Circuit

NOTE:

CL includes jig capacitance.

Table 26: Test Configuration Loading Value

TEST CONFIGURATION CL (pF)

VCCQ = VCC = 2.7V – 3.6V 30

Device

Under Test Out

RL = 3.3KΩ

1.3V

1N914

Table 27: AC Characteristics–Read-Only Operations

Notes: 1, 2, 4; extended temperature (-40ºC TA  +85ºC)

PARAMETER SYMBOL DENSITY

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITS NOTESMIN MAX

Read/Write Cycle Time tRC 32Mb 110 ns

64Mb 115

128Mb 120

Address to Output Delay tAA 32Mb 110 ns

64Mb 115

128Mb 120

CEx to Output Delay tACE 32Mb 110 ns

64Mb 115

128Mb 120

OE# to Non-Array Output Delay tAOE All 50 ns 3, 5

OE# to Array Output Delay tAOA All 25 ns 5

RP# High to Output Delay tRWH 32Mb 150 ns

64Mb 180

128Mb 210

CEx to Output in Low-Z tOEC All 0 ns 6

OE# to Output in Low-Z tOEO All 0 ns 6

CEx HIGH to Output in High-Z tODC All 35 ns 6

OE# HIGH to Output in High-Z tODO All 15 ns 6

Output Hold from Address,

CEx, or OE# Change, whichever occurs first

tOH All 0 ns 6

CEx LOW to BYTE# HIGH or LOW tCB All 10 ns 6

BYTE# to Output Delay tABY All 1,000 ns 6

BYTE# to Output in High-Z tODB All 1,000 ns 6

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first

edge of CE0, CE1, or CE2 that disables the device (see Table 2).

2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

3. OE# may be delayed up to tACE–AOE after the first edge of CEx that enables the device (see Table 2) without

impact on tACE .

4. See Figure 17 on page 44, Transient Input/Output Reference Waveform, for VCCQ = 2.7V – 3.6V, and Figure 18 on

page 45, Transient Equivalent Testing Load Circuit, for testing characteristics.

5. When reading the Flash array, a faster tAOE applies. Non-array READs refer to status register READs, QUERY READs,

or DEVICE IDENTIFIER READs.

6. Sampled, not 100 percent tested.

CEx HIGH to CEx LOW tCWH All 0 ns 6

Page Address Access Time tAPA All 25 ns

Table 27: AC Characteristics–Read-Only Operations

Notes: 1, 2, 4; extended temperature (-40ºC TA  +85ºC)

PARAMETER SYMBOL DENSITY

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITS NOTESMIN MAX

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 19: Page Mode and Standard Word/Byte READ Operations

Timing Parameters

NOTE:

1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first

edge of CE0, CE1, or CE2 that disables the device.

Disabled

CEx

Enabled

ADDRESSES

(A2–A0)

OE#

DQ0–DQ15

WE#

RP#

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

tRC

VALID

ADDRESS

BYTE

tCWH

tAA

tACE

tAOE/

tAOA

tOEO

tODB

tRWH

tOEC

tCB tABY

tODC

tODO

ADDRESSES

(A22–A3)

tOH

tAPA

UNDEFINED

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

High-ZHigh-Z

SYMBOL

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITSMIN MAX

tRC (32Mb) 110 ns

tRC (64Mb) 115 ns

tRC (128Mb) 120 ns

tAA (32Mb) 110 ns

tAA (64Mb) 115 ns

tAA (128Mb) 120 ns

tACE (32Mb) 110 ns

tACE (64Mb) 115 ns

tACE (128Mb) 120 ns

tAOE 50 ns

tAOA 25 ns

tRWH (32Mb) 150 ns

tRWH (64Mb) 180 ns

tRWH (128Mb) 210 ns

tOEC 0ns

tOEO 0ns

tODC 35 ns

tODO 15 ns

tOH 0ns

tCB 10 ns

tABY 1,000 ns

tODB 1,000 ns

tCWH 0ns

tAPA 25 ns

SYMBOL

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITSMIN MAX

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first

edge of CE0, CE1, or CE2 that disables the device.

2. Read timing characteristics during BLOCK ERASE, PROGRAM, and LOCK BIT CONFIGURATION operations are the

same as during read-only operations. Refer to AC Characteristics – Read-Only Operations.

3. A WRITE operation can be initiated and terminated with either CEX or WE#.

4. Sampled, not 100 percent tested.

5. Write pulse width (tWP) is defined from CEx or WE# going LOW (whichever goes LOW last) to CEx or WE# going

HIGH (whichever goes HIGH first).

6. Refer to Table 4 on page 14 for valid AIN and DIN for block erase, program, or lock bit configuration.

7. Write pulse width high (tWPH) is defined from CEx or WE# going HIGH (whichever goes HIGH first) to CEx or WE#

going LOW (whichever goes LOW first).

8. For array access, tAA is required in addition to tWR for any accesses after a WRITE.

9. STS timings are based on STS configured in its RY/BY# default mode.

10. VPEN should be held at VPENH until determination of block erase, program, or lock bit configuration success

(SR1/3/4/5 = 0).

Table 28: AC Characteristics – WRITE Operations

Notes: 1, 2, 3; extended temperature (-40ºC  TA  +85ºC)

PARAMETER SYMBOL

32Mb, 64Mb, 128Mb

UNITS NOTESMIN MAX

RP# High Recovery to WE# (CEx) Going LOW tRS1µs4

CEx (WE#) LOW to WE# (CEx) Going LOW tCS (tWS)0ns5

Write Pulse Width tWP (tCP) 70 ns 5

Data Setup to WE# (CEx) Going HIGH tDS50 ns 6

Address Setup to WE# (CEx) Going HIGH tAS55 ns 6

CEx (WE#) Hold from WE# (CEx) HIGH tCH (tWH) 0ns

Data Hold from WE# (CEx) HIGH tDH 0ns

Address Hold from WE# (CEx) HIGH tAH 0ns

Write Pulse Width HIGH tWPH (tCPH) 30 ns 7

VPEN Setup to WE# (CEx) Going HIGH tVPS0ns4

Write Recovery Before Read tWR 35 ns 8

WE# (CEx) HIGH to STS Going LOW tSTS200 ns 9

VPEN Hold from Valid SRD, STS Going HIGH tVPH 0 ns 4, 9, 10

WE# (CEx) HIGH to Status Register Busy tWB 200 ns 4

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Typical values measured at TA = +25ºC and nominal voltages. Assumes corresponding lock bits are not set. Subject to

change based on device characterization.

2. These performance numbers are valid for all speed versions.

3. Sampled, but not 100 percent tested.

4. Excludes system-level overhead.

5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.

6. Effective per-byte program time is 5.6µs/byte (typical).

7. Effective per-word program time is 11.2µs/word (typical).

8. MAX values are measured at worst-case temperature and VCC corner after 100,000 cycles.

Table 29: Block Erase, Program, and Lock Bit Configuration Performance

Notes: 1, 2, 3; extended temperature (-40ºC  TA  +85ºC)

PARAMETER SYM

32Mb

64Mb 128Mb

UNITS NOTESTYP MAX8TYP MAX8

Write Buffer Byte Program Time

(Time to Program 32 bytes/16 words)

tWED1 200 654 180 654 µs 4, 5,

6, 7

Byte/Word Program Time (Using WORD/BYTE PROGRAM

Command)

tWED2 12.5 630 11.2 630 µs 4

Block Program Time (Using WRITE-to-BUFFER Command) tWED3 0.8 1.7 0.7 1.7 sec 4

Block Erase Time tWED4 0.7550.755 sec 4

Set Lock Bits Time tWED5 14 75 10 75 µs 4

Clear Block Lock Bits Time tWED6 0.5 0.7 0.5 0.7 sec 5

Program Suspend Latency Time to Read tLPS25 30 25 30 µs

Erase Suspend Latency Time to Read tLES26 35 25 35 µs

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 20: WRITE Operations

Timing Parameters

NOTE:

1. CEx low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx high is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2 on page 11). STS is shown in its default mode (RY/BY#).

2. VCC power-up and standby.

3. Write block erase, write buffer, or program setup.

4. Write block erase or write buffer confirm, or valid address and data.

5. Automated erase delay.

6. Read status register or query data.

7. WRITE READ ARRAY command.

8. For valid status data, tWB always overrides tWR after a state machine operation.

Disabled

CEx (WE#)

Enabled

Addresses

OE#

DQ0–DQ15

UNDEFINED

Disabled

WE# (CEx)

Enabled

VIH

VIL

AIN

VPEN

RP#

VIH

VIL

VPENLK

VPENH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

AIN

DIN DIN

tAS

Note 3Note 2 Note 4 Note 5 Note 6 Note 7

tRStCH

tWR

tAH

tCS

tWPH

tWP

tSTS

tDS

tDH

tWB

VIL

STS

VOH

VOL

VALID

READY SRD

VALID

BUSY SRD

DIN

tVPStVPH

Note 8

SYMBOL

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITSMIN MAX

tRS1µs

tCS0ns

tWP 70 ns

tDS50 ns

tAS55 ns

tCH 0ns

tDH 0ns

tAH 0ns

tWPH 30 ns

tVPS0ns

tWR 35 ns

tSTS200 ns

tVPH 0ns

tWB 200 ns

SYMBOL

VCC = 2.7V–3.6V

VCCQ = 2.7V–3.6V

UNITSMIN MAX

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 21: RESET Operation4

NOTE:

1. STS is shown in its default mode (RY/BY#).

2. These specifications are valid for all product versions (packages and speeds).

3. If RP# is asserted while a BLOCK ERASE, PROGRAM, or LOCK BIT CONFIGURATION operation is not executing, then

the minimum required RP# pulse LOW time is 100ns.

4. A reset time, tRWH, is required from the latter of STS (in RY/BY# mode) or RP# going HIGH until outputs are valid.

Table 30: RESET Specifications

Note 1; extended temperature (-40ºC  TA  +85ºC)

PARAMETER SYMBOL MIN MAX UNITS NOTES

RP# Pulse Low Time

(If RP# is tied to VCC, this specification is not applicable) tPLPH 35 µs 2, 3

RP# High to Reset during Block Erase, Program, or Lock

Bit Configuration tPHRH 100 ns 2, 4

RP#

VIH

VIL

STS

VIH

VIL

PHRH

PLPH

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 22: 56-Pin TSOP Type 1

NOTE:

1. All dimensions in millimeters.

SEE DETAIL A

0.50 TYP

14.00 ±0.08

0.25

1.20 MAX

18.40 ±0.08

20.00 ±0.25

0.20 ± 0.05

DETAIL A

0.50 ± 0.10

0.80 TYP

0.10+0.10

-0.05

0.10

0.25

PLANE

GAGE

0.15+0.03

-0.02

PIN #1 INDEX

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

PLATED LEAD FINISH: 90% Sn, 10% Pb, OR 100% Sn

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.25 PER SIDE

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice..

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, the Micron logo, and Q-Flash are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 23: 64-Ball FBGA

NOTE:

All dimensions in millimeters.

0.10 C

SEATING PLANE

0.850 ±0.075

64X ∅0.45

BALL A8

7.00

3.50 ±0.05

3.50 ±0.05 5.00 ±0.05

13.00 ±0.10

6.50 ±0.05

BALL A1 ID BALL A1 ID

1.20 MAX

BALL A1

1.00 TYP

7.00

10.00 ±0.10

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3% Ag, 0.5% Cu

SOLDER BALL PAD: Ø 0.33 NON SOLDER MASK DEFINED

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.40

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Revision History

Rev. N................................................................................................................................................................................3/05

• Removed all references to 256Mb Q-Flash

Rev. M ...............................................................................................................................................................................9/04

• Clarified byte capacitance (page 42)

•Updated I

CC3 currents (page 43)

Rev. L.................................................................................................................................................................................4/04

• Corrected Maximun Voltage Range on VccQ in Table 22 on page 41 and VIL in Table 23 on page 42

• Removed 64Mb -12 speed option

• Added references to 0.15µm 64Mb die shrink

• Added 256Mb specification

Rev. K ................................................................................................................................................................................2/04

• Removed commercial temperature range (0°C to +70°C)

• Clarification of Page Mode Access

• Added pin/ball for 256Mb- and 512Mb-density devices.

• Added Note 1 to Figure 6 on page 17 referencing Offset.

• Removed 128Mb -15 speed option

• Removed commercial temperature range (0°C to +70°C)

• Clarification of Page Mode Access

Rev. J ...............................................................................................................................................................................11/03

• Added in lead-free package options

• Clarified STATUS READ operation

•Updated V

PENLK value

Rev. I .................................................................................................................................................................................6/03

• Removed PRELIMINARY designation from the MT28F128J3

•Removed “F” option

Rev. H................................................................................................................................................................................5/03

• Addition of speed grades: -115 (64Mb) and -12 (128Mb)

• Addition of optional Micron ManID (0x2Ch)

•Updated I

CC1, ICC2, ICC3, ICC4, ICC5, and ICC6 currents

• Update to Capacitance table and WRITE Operations table

•Removal of RESUME Operations timing diagram

• Clarification of address decode on Identifier Code Space

• Updated 56-pin TSOP I package drawing

• Changed CFI Table address 36h to 6Ch

Rev. 7...............................................................................................................................................................................11/02

• Removed PRELIMINARY designation from the MT28F320J3

• Fixed a typographical error on the 64-ball FBGA package drawing

Rev. 6.................................................................................................................................................................................8/02

• Updated commercial temperature range

• Updated Configuration Coding Definitions table

• Removed 3.0V–3.6V VccQ voltage range option

•Updated V

LKO, VPENLK, tAOA, tODC, tAPA, tCH (tWH), tSTS, and tWB

• Added RESUME Operations timing diagram

Rev. 5.................................................................................................................................................................................3/03

• Updated MT28F320J3 information

Rev. 4.................................................................................................................................................................................2/02

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

09005aef80b5a323 Micron Technology, Inc., reserves the right to change products or specifications without notice.

•Added VCCQ = 4.5V–5.5V parameter for 32Mb and 64Mb devices

• Updated erase and program timing parameters

• Removed Block Erase Status bit

Rev. 3.................................................................................................................................................................................6/01

• Updated package drawing and corresponding notes

Rev. 2.................................................................................................................................................................................5/01

• Added 128Mb device information

• Added 64-ball FBGA (1.0mm pitch) package

Original document, Rev. 1, Advance ............................................................................................................................12/00