10-Bit, 105 MSPS, 3 V, Dual ADC
Enhanced Product
AD9218-EP
Rev. 0 Document Feedback
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FEATURES
Dual, 10-bit, 105 MSPS ADC
Low power: 275 mW at 105 MSPS per channel
On-chip reference and track-and-hold
300 MHz analog bandwidth for each channel
SNR = 54 dB at 51 MHz, encode = 105 MSPS
1 V p-p analog input range for each channel
3.0 V single-supply operation (2.7 V to 3.6 V)
Power-down mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
–75 dBc crosstalk between channels
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications
(AQEC standard)
Extended industrial temperature range: −55°C to +105°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
Radar
Avionics
Unmanned systems
Military communications
Missiles and munitions
GENERAL DESCRIPTION
The AD9218-EP is a dual, 10-bit, monolithic sampling analog-
to-digital converter (ADC) with on-chip track-and-hold
circuits. The product is low cost, low power, and is small and
easy to use. The AD9218-EP operates at a 105 MSPS conversion
rate with dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and a clock for full operation. No external reference or
driver components are required for many applications. The
digital outputs are transistor-to-transistor logic (TTL)/
complementary metal-oxide semiconductor (CMOS)
compatible, and a separate output power supply pin supports
interfacing with 3.3 V or 2.5 V logic.
The clock input is TTL/CMOS compatible and the 10-bit digital
outputs can be operated from a 3.0 V (2.5 V to 3.6 V) supply.
User-selectable options offer a combination of power-down
modes, digital data formats, and digital data timing schemes.
In power-down mode, the digital outputs are driven to a high
impedance state.
The AD9218-EP is fabricated on an advanced CMOS process
and is available in a 48-lead, 7 mm × 7 mm, low profile quad
flat package (LQFP), and is specified over the extended
industrial temperature range of −55°C to +105°C.
Additional application and technical information can be found
in the AD9218 data sheet.
FUNCTIONAL BLOCK DIAGRAM
AD9218-EP
REF
TIMINGENCA
/
10 /
10
/
10
/
10
GND
AINAD9ATO D0A
S1
S2
DFS/GAIN
D9BTO D0B
AINA
AINB
AINB
REFINA
REFINB
REFOUT
ENCBTIMING
T/H
T/H
ADC
ADC
OUTPUT
REGISTER
OUTPUT
REGISTER
VDVDD
17309-001
Figure 1.
AD9218-EP Enhanced Product
Rev. 0 | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications .......................................................................... 5
Switching Specifications ...............................................................6
Timing Diagrams ..........................................................................6
Absolute Maximum Ratings ............................................................8
Explanation of Test Levels ............................................................8
Thermal Resistance .......................................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions ..............................9
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
12/2018—Revision 0: Initial Version
Enhanced Product AD9218-EP
Rev. 0 | Page 3 of 11
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 1.
Parameter Temperature Test Level Min Typ Max Unit
RESOLUTION 10 Bits
ACCURACY
No Missing Codes1 Full VI Guaranteed, not tested
Offset Error2 25°C I –18 +2 +18 LSB
Gain Error2 25°C I –2 +3.5 +8 % FS
Differential Nonlinearity
(DNL)
25°C I –1 ±0.8 +1.7 LSB
Full VI ±0.9 LSB
Integral Nonlinearity (INL) 25°C I –2.7 ±2 +2.7 LSB
Full VI ±2.3 LSB
TEMPERATURE DRIFT
Offset Error Full V 4 ppm/°C
Gain Error2 Full V 100 ppm/°C
Reference Full V 40 ppm/°C
REFERENCE
Internal Reference Voltage 25°C I 1.18 1.24 1.28 V
(REFOUT)
Input Resistance (REF
IN
A, REF
IN
B)
Full
VI
9
11
13
kΩ
ANALOG INPUTS
Differential Input Voltage Range (AINx, AINx)3 Full V 1 V
Common-Mode Voltage3 Full V VD/3 V
Input Resistance Full VI 7 10 16 kΩ
Input Capacitance 25°C V 3 pF
POWER SUPPLY
VD Full IV 2.7 3 3.6 V
VDD Full IV 2.5 3 3.6 V
Supply Currents
IVD (VD = 3.0 V)4 Full VI 183 188 mA
IV
DD
(V
DD
= 3.0 V)
4
25°C
V
17
mA
Power Dissipation DC5 Full VI 550 565 mW
IVD Power-Down Current6 Full VI 22 mA
Power Supply Rejection Ratio 25°C I ±1 mV/V
1 No missing codes at room temperature guaranteed.
2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) in 1 V p-p range.
3 (AINx – AINx) = ±0.5 V in 1 V range (full-scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven externally by a low impedance source
by ±300 mV (differential drive, gain = 1).
4 AC power dissipation measured with rated encode and a 10 MHz analog input at 0.5 dBFS, CLOAD = 5 pF.
5 DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0).
6 In power-down state, IVDD = ±10 µA typical.
AD9218-EP Enhanced Product
Rev. 0 | Page 4 of 11
DIGITAL SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 2.
Parameter Temperature Test Level Min Typ Max Unit
DIGITAL INPUTS
Encode Input Common Mode Full V VD/2 V
Encode 1 Voltage Full VI 2 V
Encode 0 Voltage Full VI 0.8 V
Encode Input Resistance Full VI 1.75 2.0 2.4 kΩ
Logic 1 Voltage—S1, S2, DFS
Full
VI
2
V
Logic 0 Voltage—S1, S2, DFS Full VI 0.8 V
Logic 1 Current—S1 Full VI –50 ±0 50 µA
Logic 0 Current—S1 Full VI –400 –230 –50 µA
Logic 1 Current—S2 Full VI 50 230 400 µA
Logic 0 Current—S2 Full VI –50 ±0 50 µA
Logic 1 Current—DFS
Full
VI
30
100
200
µA
Logic 0 Current—DFS Full VI –400 –230 –50 µA
Input Capacitance—S1, S2, Encode Inputs 25°C V 2 pF
Input Capacitance DFS 25°C V 4.5 pF
DIGITAL OUTPUTS
Logic 1 Voltage Full VI 2.45 V
Logic 0 Voltage Full VI 0.05 V
Output Coding Twos complement or offset binary
Enhanced Product AD9218-EP
Rev. 0 | Page 5 of 11
AC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 3.
Parameter Temperature Test Level Min Typ Max Unit
DYNAMIC PERFORMANCE1
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10 MHz 25°C I 53 55 dB
fIN = Nyquist2 25°C I 52 54 dB
Signal-to-Noise and Distortion (SINAD)
(With Harmonics)
fIN = 10 MHz 25°C I 52 53 dB
fIN = Nyquist2 25°C I 51 53 dB
Effective Number of Bits
fIN = 10 MHz 25°C I 8.4 8.6 Bits
f
IN
= Nyquist
2
25°C
I
8.3
8.6
Bits
Second Harmonic Distortion
fIN = 10 MHz 25°C I –60 –68 dBc
fIN = Nyquist2 25°C I –57 –66 dBc
Third Harmonic Distortion
fIN = 10 MHz 25°C I –57 –63 dBc
fIN = Nyquist2 25°C I –57 –69 dBc
Spurious Free Dynamic Range (SFDR)
fIN = 10 MHz 25°C I –57 –62 dBc
fIN = Nyquist2 25°C I –57 –63 dBc
Two-Tone Intermodulation Distortion (IMD)
f
IN1
= 30 MHz, f
IN2
= 31 MHz at –7 dBFS
25°C
V
–67
dBc
Analog Bandwidth, Full Power 25°C V 300 MHz
Crosstalk 25°C V –75 dBc
1 AC specifications based on an analog input voltage of –0.5 dBFS at 10.0 MHz, unless otherwise noted. AC specifications are tested in 1 V p-p range and driven
differentially.
2 Tested close to Nyquist: 51 MHz.
AD9218-EP Enhanced Product
Rev. 0 | Page 6 of 11
SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4.
Parameter Temperature Test Level Min Typ Max Unit
ENCODE INPUT PARAMETERS
Maximum Encode Rate Full VI 105 MSPS
Minimum Encode Rate Full IV 20 MSPS
Encode Pulse Width High (tEH) Full IV 3.8 ns
Encode Pulse Width Low (tEL) Full IV 3.8 ns
Aperture Delay (t
A
)
25°C
V
2
ns
Aperture Uncertainty (Jitter) 25°C V 3 ps rms
DIGITAL OUTPUT PARAMETERS
Output Valid Time (t
V
)
1
Full
VI
2.5
ns
Output Propagation Delay (tPD)1 Full VI 4.5 6 ns
Output Rise Time (tR) 25°C V 1.0 ns
Output Fall Time (tF) 25°C V 1.2 ns
Out-of-Range Recovery Time 25°C V 5 ns
Transient Response Time 25°C V 5 ns
Recovery Time from Power-Down 25°C V 10 Cycles
Pipeline Delay Full IV 5 Cycles
1 tV and tPD are measured from the 1.5 level of the ENCx input to the 50%/50% levels of the digital outputs swing. The digital output load during test must not exceed an
ac load of 5 pF or a dc current of ±40 µA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS
1/fS
tA
tEH tEL
tPD tV
SAMPLE N
ENC
A
ENC
B
D9
A
TO D0
A
D9
B
TO D0
B
A
IN
A
A
IN
B
DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N
SAMPLE
N + 1 SAMPLE
N + 5 SAMPLE
N + 6
SAMPLE
N + 2 SAMPLE
N + 3 SAMPLE
N + 4
17309-002
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
Enhanced Product AD9218-EP
Rev. 0 | Page 7 of 11
1/f
S
t
A
t
EH
t
EL
t
PD
t
V
SAMPLE
N
ENC
A
ENC
B
D9
A
TO D0
A
D9
B
TO D0
B
A
IN
A
A
IN
B
DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
SAMPLE
N + 1 SAMPLE
N + 2 SAMPLE
N + 7 SAMPLE
N + 8
SAMPLE
N + 3 SAMPLE
N + 4 SAMPLE
N + 5 SAMPLE
N + 6
17309-003
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
1/f
S
t
A
t
EH
t
EL
t
PD
t
V
SAMPLE
N
ENCA
ENCB
D9ATO D0A
D9BTO D0B
AINA
AINB
DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N
DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
SAMPLE
N + 1 SAMPLE
N + 2 SAMPLE
N + 7 SAMPLE
N + 8
SAMPLE
N + 3 SAMPLE
N + 4 SAMPLE
N + 5 SAMPLE
N + 6
DATA N + 2
17309-004
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
AD9218-EP Enhanced Product
Rev. 0 | Page 8 of 11
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VD, VDD 4 V
Analog Inputs
–0.5 V to V
D
+ 0.5 V
Digital Inputs –0.5 V to VDD + 0.5 V
REFIN Inputs –0.5 V to VD + 0.5 V
Digital Output Current 20 mA
Operating Temperature Range –55°C to +105°C
Storage Temperature Range –65°C to +150°C
Junction Temperature
150°C
Operating 115°C
Case Temperature 150°C
Operating 105°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
EXPLANATION OF TEST LEVELS
Test Level Description
I 100% production tested.
II 100% production tested at 25°C and sample tested
at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by
design and characterization testing for extended
industrial temperature range.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
ST-481 73 12 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board. See JEDEC JESD-51.
ESD CAUTION
Enhanced Product AD9218-EP
Rev. 0 | Page 9 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
V
D
ENC
A
V
DD
GND
D9
A
(MSB)
D8
A
D7
A
D6
A
D5
A
D4
A
D3
A
D2
A
V
D
ENC
B
V
DD
GND
(MSB) D9
B
D8
B
D7
B
D6
B
D5
B
D4
B
D3
B
D2
B
S1
S2
GND
A
IN
A
A
IN
A
DFS/GAIN
A
IN
B
A
IN
B
REF
IN
A
REF
IN
B
D1
A
GND
V
DD
D1
B
D0
A
GND
GND
D0
B
GND
V
D
REF
OUT
V
D
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AD9218-EP
TOP VIEW
(No t t o Scal e)
17309-005
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number Mnemonic Description
1, 12, 16, 27, 29,
32, 34, 45
GND Ground.
2
A
IN
A
Analog Input for Channel A.
3
AA
IN
Analog Input for Channel A (Complementary).
4 DFS/GAIN Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p
supported; high = twos complement output available, 1 V p-p supported.
5 REFINA Reference Voltage Input for Channel A.
6 REFOUT Internal Reference Voltage.
7 REFINB Reference Voltage Input for Channel B.
8
S1
User Select 1.
9 S2 User Select 2.
10
BA
IN
Analog Input for Channel B (Complementary).
11 AINB Analog Input for Channel B.
13, 30, 31, 48 VD Analog Supply.
14 ENCB Encode B. Clock input for Channel B.
15, 28, 33, 46 VDD Digital Supply.
17 to 26
D9
B
to D0
B
Digital Output for Channel B (D9
B
= MSB).
35 to 44 D0A to D9A Digital Output for Channel A (D9A = MSB).
47 ENCA Encode A. Clock input for Channel A.
AD9218-EP Enhanced Product
Rev. 0 | Page 10 of 11
TYPICAL PERFORMANCE CHARACTERISTICS
1.17
1.19
1.21
1.23
1.25
1.27
1.29
–55 –35 –15 5 25 45 65 85 105
TEMPERATURE (°C)
V
REF
OUTPUT VO LTAGE (V)
Figure 6. VREF Output Voltage vs. Temperature (ILOAD = 300 μA)
TEMPERATURE (°C)
17309-036
2.0
2.5
3.0
3.5
4.0
4.5
–55 –35 –15 5 25 45 65 85 105
GAIN ERROR (%
f
S
)
Figure 7. Gain Error vs. Temperature, AIN = 10 MHz, 1 V p-p
SNR, SI NAD, SFDR (dB)
TEMPERATURE (°C)
17309-037
50
52
54
56
58
60
62
64
66
68
–55 –35 –15 5 25 45 65 85 105
SNR
SINAD
SFDR
Figure 8. SNR, SINAD, SFDR vs. Temperature, AIN = 10 MHz, 1 V p-p
Enhanced Product AD9218-EP
Rev. 0 | Page 11 of 11
OUTLINE DIMENSIONS
1
12 13 25
24
36
37
48
COMPLIANT TO JEDE C S TANDARDS MS-026-BBC
01-17-2018-A
VIEW A
1.60
MAX
0.75
0.60
0.45
1.00 REF
0.27
0.22
0.17
PKG-005430
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
TOP VIEW
SIDE VIEW
0.08 M AX
COPLANARITY
7°
0°
VIEW A
ROT ATED 9 0 ° CCW
1.45
1.40
1.35
0.15
0.10
0.05
0.20
0.15
0.09
SEATING
PLANE
0.50
BSC
Figure 9. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
AD9218SSTZ-105-EP –55°C to +105°C 48-Lead Low Profile Quad Flat Pack [LQFP] ST-48
AD9218SSTZ-105EPRL
−55°C to +105°C
48-Lead Low Profile Quad Flat Pack [LQFP]
ST-48
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17309-0-12/18(0)
