Freescale Semiconductor Document Number: WCT100XADS
Data Sheet Rev. 1.0, 08/2014
Automotive Wireless Transmitter
Controller
Features
• Confor ms to the late st versio n WPC “Qi” spec ification
• Supports wide DC input voltage range of 6 V (limited
duration at Start/Stop operation) to 16 V for automotive
battery input
• Supports Foreign Object Detection (FOD)
• Low-power system standby available using Freescale
Touch technology
• Provides free positioning solutions by using WPC A or
B type multi-coil technology
• Uses rail voltage control or phase shift control with
fixed operating frequenc y t o control power transfer to
help alleviate a utomotive syste m interference
• Supports the key FOB avoidance function
• Supports the operation frequency dithering technology
to eliminate the AM band interference
• Improved EMC performance for automotive
certification
• Supports C AN/ LIN/IIC/SCI/SP I interfaces
• LED for system status indication
• Over-voltage/current/temperature protection
• Software based solution to provide maximum design
freedom and product differentiation
• AEC-Q100 grade 2 cer tification
• Dual-mode capable
Applications
• Automotive Wir e le ss Power Transmitter
o WPC co mplia nt
Overview Description
The WCT100xA is a wireless power transmitter controller
that integrate s all required functions for WPC “Qi”
compliant wireless power trans mitter design. T he
WCT100xA transmitter IC ma nages the power transfer by
receiving commands from the r eceiver. Receivers are
detected by using either standard protocol methods or
Freescale touch se ns or technology. Once the mobile device
is detected, the WCT100xA controls the power transfer by
adjusting rail voltage or phase shift of power s tage according
to message packets sent by mobile device.
To maximize the design freedom and product differentiation,
the WCT100xA supports any 5W coil topology capable of
supporting WPC Qi-based implementatio n. In addition, the
system supports both WPC and PMA protocols.
The WCT100xA also includes CAN/LIN/IIC/SCI/SPI
interfaces, over-voltage/current/temperature protection and
FOD method to protect from o verheating by misplaced
metallic foreign objects. It al so handles any system fault and
operation status, and provides comprehensive indicator
outputs for rob us t syst em d esi gn.
Wireless Charging System Functional Diagram
© Freescale Semiconductor, Inc., 2014. All rights reserved.
_______________________________________________________________________
Contents
1 Absolute Maximum Ratings .................................................................................................................... 4
1.1 Electrical Operating Ratings .................................................................................................................................... 4
1.2 Thermal Handling Ratings ....................................................................................................................................... 5
1.3 ESD Handling Ratings .............................................................................................................................................. 5
1.4 Moisture Handling Ratings ...................................................................................................................................... 5
2 Electrical Characteristics ......................................................................................................................... 5
2.1 General Characteristics ........................................................................................................................................... 5
2.2 Device Characteristics ............................................................................................................................................. 8
2.3 Thermal Operating Characteristics ........................................................................................................................ 21
3 Typical Performance Characteristics ............................................................................................... 21
3.1 System Efficiency .................................................................................................................................................. 21
3.2 Standby Power ...................................................................................................................................................... 22
3.3 Digital Demodulation ............................................................................................................................................ 23
3.4 Foreign Object Detection ...................................................................................................................................... 23
4 Device Information ................................................................................................................................. 23
4.1 Functional Block Diagram ...................................................................................................................................... 23
4.2 Product Features Overview ................................................................................................................................... 24
4.3 Pinout Diagram ..................................................................................................................................................... 25
4.4 Pin Function Description ....................................................................................................................................... 25
4.5 Ordering Information ............................................................................................................................................ 35
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
2 Freescale Semiconductor
4.6 Package Outline Drawing ...................................................................................................................................... 36
5 Software Library ...................................................................................................................................... 36
5.1 Memory Map ........................................................................................................................................................ 36
5.2 Software Library and API Description .................................................................................................................... 36
6 Design Considerations ........................................................................................................................... 36
6.1 Electrical Design Considerations............................................................................................................................ 36
6.2 PCB Layout Considerations .................................................................................................................................... 38
6.3 Thermal Design Considerations ............................................................................................................................. 38
7 References and Links ............................................................................................................................. 38
7.1 References ............................................................................................................................................................ 38
7.2 Useful Links ........................................................................................................................................................... 39
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 3
1 Absolute Ma ximum Ratings
1.1 Electrical Operating Rating s
Table 1. Absolute Maximum Electrical Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic Symbol Notes1 Min. Max. Unit
Supply Voltage Range VDD –0.3 4.0 V
Analog Supply Voltage Range VDDA –0.3 4.0 V
ADC High Voltage Reference VREFHx –0.3 4.0 V
Voltage difference VDD to VDDA ΔVDD –0.3 0.3 V
Voltage difference VSS to VSSA ΔVss –0.3 0.3 V
Digital Input Voltage Range VIN Pin Group 1 –0.3 5.5 V
RESET
Input Voltage Range VIN_RESET Pin Group 2 –0.3 4.0 V
Oscillator Input Voltage Range VOSC Pin Group 4 –0.4 4.0 V
Analog Input Voltage Range VINA Pin Group 3 –0.3 4.0 V
Input clamp curr ent, per pin (VIN < VSS – 0.3 V)2, 3 VIC – –5.0 mA
Output clamp current, per pin4 VOC – ±20.0 mA
Contiguous pin DC injection current—re g io nal li mit
sum of 16 contiguous pins IIcont –25 25 mA
Output Voltage Range (normal push-pull mode) VOUT Pin Group 1,2 –0.3 4.0 V
Output Voltage Range (open drain mode) VOUTOD Pin Group 1 –0.3 5.5 V
RESET
Output Voltage Range VOUTOD_RESET Pin Group 2 –0.3 4.0 V
DAC Output Voltage Range VOUT_DAC Pin Group 5 –0.3 4.0 V
Ambient Temperature TA –40 105 °C
Storage Temperature Range TSTG –55 150 °C
1. Default Mode:
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Continuous clamp current.
3. All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD.
If VIN greater than VDIO_MIN (=VSS –0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this
limit cannot be observed, then a current limiting resistor is required.
4. I/O is configured as push-pull mode.
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4 Freescale Semiconductor
1.2 Thermal Handling Ratings
Table 2. Therma l Handling Ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperat ure, lead-free – 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
1.3 ESD Handling Ratings
Table 3. ESD Handling Ratings
Characteristic1 Min. Max. Unit
ESD for Human Body Model (HBM) -2000 +2000 V
ESD for Machine Model (MM) -200 +200 V
ESD for Charge Device Model (CDM) -500 +500 V
Latch-up current at TA= 85°C (ILAT) -100 +100 mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless
otherwise noted.
1.4 Moisture Handling Ratings
Table 4. Moisture Handling Ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level – 3 – 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
2 Electrical Characteristics
2.1 General Characteristics
Table 5. General Electrical Characteristics
Recommended Operating Conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V)
Characteristic Symbol Notes Min. Typ. Max. Unit Test
Conditions
Supply Voltage2 VDD ,VDDA 2.7 3.3 3.6 V -
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Freescale Semiconductor 5
ADC (Cyclic) Reference
Voltage High
VREFHA
VREFHB 3.0 VDDA V -
ADC (SAR) Reference
Voltage High VREFHC 3 2.0 VDDA V
Voltage diffe rence VDD to VDDA ΔVDD -0.1 0 0.1 V -
Voltage difference VSS to VSSA ΔVss -0.1 0 0.1 V -
Input Voltage High (digital
inputs) VIH 1 (Pin Group 1) 0.7×VDD 5.5 V -
RESET
Voltage High VIH_RESET 1 (Pin Group 2) 0.7×VDD - VDD V -
Input Voltage Low (digital
inputs) VIL 1 (Pin Group 1,2) 0.35×VDD V -
Oscillator Input Voltage High
XTAL driven by an external
clock source
VIHOSC 1 (Pin Group 4) 2.0 VDD + 0.3 V -
Oscillator Input Voltage Low VILOSC 1 (Pin Group 4) -0.3 0.8 V -
Output Source Current High
(at VOH min.) 4,5
• Programmed for low
drive strength
• Programmed for high
drive strength
IOH
1 (Pin Group 1)
1 (Pin Group 1)
-
-
-2
-9
mA -
Output Source Current Low
(at VOL max.) 4,5
• Programmed for low
drive strength
• Programmed for high
drive strength
IOL
1 (Pin Group 1,2)
1 (Pin Group 1,2)
-
-
2
9
mA -
Output Voltage High VOH 1 (Pin Group 1) VDD - 0.5 - - V IOH = IOHmax
Output Voltage Low VOL 1 (Pin Group 1,2) - - 0.5 V IOL = IOLmax
Digital Input Current High
pull-up enabled or disabled IIH 1 (Pin Group 1) - 0 +/-2.5 µA
VIN = 2.4 V
to 5.5 V
1 (Pin Group 2) VIN = 2.4 V
to VDD
Comparator Input Current
High IIHC 1 (Pin Group 3) 0 +/-2 µA VIN = VDDA
Oscillator Input Current High IIHOSC 1 (Pin Group 4) - 0 +/-2 µA VIN = VDDA
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6 Freescale Semiconductor
Internal Pull-Up Resistance RPull-Up 20 - 50 kΩ -
Internal Pull-D own Resistanc e RPull-Down 20 - 50 kΩ -
Comparator Input Current
Low IILC 1 (Pin Group 3) - 0 +/-2 µA VIN = 0V
Oscillator Input Current Low IILOSC 1 (Pin Group 4) - 0 +/-2 µA VIN = 0V
DAC Output Voltage Range VDAC 1 (Pin Group 5) VSSA +
0.04 - VDDA -
0.04 V RLD = 3 kΩ,
CLD = 400
pF
Output Current1 High
Impedance State IOZ 1 (Pin Group 1,2) - 0 +/-1 µA -
Schmitt Trigger Input
Hysteresis VHYS 1 (Pin Group 1,2) 0.06×VDD - - V -
Input capacitance CIN - 10 - pF -
Output capacitance COUT - 10 - pF -
GPIO pin interrupt pulse
width6 TINT_Pulse 7 1.5 - - Bus
clock -
Port rise and fall time (high
drive strength). Slew
disabled. TPort_H_DIS 8 5.5 - 15.1 ns 2.7 ≤ VDD ≤
3.6 V
Port rise and fall time (high
drive strength). Slew enabled. TPort_H_EN 8 1.5 - 6.8 ns 2.7 ≤ VDD ≤
3.6 V
Port rise and fall time (low
drive strength). Slew
disabled. TPort_L_DIS 9 8.2 - 17.8 ns 2.7 ≤ VDD ≤
3.6 V
Port rise and fall time (low
drive strength). Slew enabled. TPort_L_EN 9 3.2 - 9.2 ns 2.7 ≤ VDD ≤
3.6 V
Device (system and core)
clock frequency fSYSCLK 0 - 100 MHz -
Bus clock fBUS 10 - - 50/100 MHz -
1. Default Mode
o Pin Group 1: GPIO, TDI, TDO, TMS, TCK
o Pin Group 2: RESET
o Pin Group 3: ADC and Comparator Analog Inputs
o Pin Group 4: XTAL, EXTAL
o Pin Group 5: DAC analog output
2. ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V.
3. ADC (SAR) is only on WCT1003A device.
4. Total chip source or sink current cannot exceed 75 mA.
5. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive injection
currents of 16 contiguous pins—is 25 mA.
6. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR
and GPIOn_IENR.
7. The greater synchronous and asynchronous timing must be met.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 7
8. 75 pF load
9. 15 pF load
10. WCT1001A only supports the maximum bus clock of 50 MHz, and WCT1003A supports 100 MHz maximum bus clock.
2.2 Device Characteristics
Table 6. General Device Characteristics
Power Mode Transition Behavior
Symbol Description Min. Max. Unit Notes
TPOR
After a POR event, the amount of delay
from w hen V DD re ac hes 2.7 V to when the
first instruc tion ex ecutes (over t he
operating tem perat ur e range) .
199 225 µs
TS2R STOP mode to RUN mode 6.79 7.29 µs 1
TLPS2LPR LPS mode to LPRUN mode 240 551 µs 2
TVLPS2VLPR VLPS mode to VLPRUN mode 1424 1500 µs 4
TW2R WAIT mode to RUN mode 0.57 0.62 µs 3
TLPW2LPR LPWAIT mode to LPRUN mode 237.2 554 µs 2
TVLPW2VLPR VLPWAIT mode to VLPRUN mode 1413 1500 µs 4
Power Consumption Operating Behaviors
Mode Conditions Max. Frequency Typical at 3.3 V, 25 °C
Notes
IDD IDDA
RUN1
100 MHz core clock, 50 MHz peripheral
clock, regulators are in full regulation,
relaxation oscillat or on, PLL powered on,
continuous MAC instructions with fetches
from program Fl ash, all peripheral modules
enabled, TMRs and SCIs using 1 ×
peripheral clock, NanoEdge within
eFlexPWM using 2× peripheral clock,
ADC/DAC (only one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparat or pow ered on, all ports
configured as inputs with input low and no
DC loads
100 MHz 35.58 mA/- 9.08 mA/- 5
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8 Freescale Semiconductor
RUN2
50 MHz/100 MHz5 core and peripheral
clock, regulators are in full regulation,
relaxation oscillat or on, PLL powered on,
continuous MAC instructions with fetches
from program Fl ash, all peripheral modules
enabled, TMRs and SCIs using 1 ×
peripheral clock, NanoEdge within
eFlexPWM using 2× peripheral clock,
ADC/DAC (onl y one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparat or pow ered on, all ports
configured as inputs with input low and no
DC loads
50 MHz/100
MHz5 25.62 mA/63.7
mA
9.07
mA/16.7
mA 5
WAIT
50 MHz/100 MHz5 core and peripheral
clock, regulators are in full regulation,
relaxation oscillat or on, PLL powered on,
core in WAIT state, all peripheral modules
enabled, TMRs and SCIs using 1× clock,
NanoEdge within eFlexPWM using 2×
clock, ADC/DAC (one 12-bit DAC, all 6-bit
DACs)/comparator powered off, all ports
configured as inputs with input low and no
DC loads
50 MHz/100
MHz5 22.0 mA/43.5
mA
7.93
mA/13.58
µA 5
STOP
4 MHz core and peripheral clock,
regulators are in full regulation, relaxation
oscillator on, PLL powered off, core in
STOP state, all periph er al mo dule and
core clocks are off, ADC/DAC/Comparator
powered off, all ports configur ed as inputs
with input low and no DC loads
4 MHz 5.58 mA/9.19
mA
1.77
uA/13.20
uA 5
LPRUN
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby , PLL disa ble d,
repeat NOP instructions, all peripheral
modules ena bled, ex cept NanoEdge within
eFlexPWM and cyclic ADCs , one 12-bit
DAC and all 6-bit DACs enabled, simple
loop with running from platform instruction
buffer, all ports configured as inputs with
input low and no DC loads
2 MHz 2.39 mA/1.86
mA
0.82
mA/3.33
mA 5
LPWAIT
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are i n s tandby, PLL disabled, all
peripheral modules enabled, except
NanoEdge within eFlexPWM and cyclic
ADCs, one 12-bit DAC and all 6-bit DACs
enabled, core in WAIT mode, all ports
configured as inputs with input low and no
DC loads
2 MHz 2.37 mA/1.83
mA
0.81
mA/2.67
mA 5
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Freescale Semiconductor 9
LPSTOP
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby , PLL disa ble d,
only PITs and COP enabled, other
peripheral modules disabled and clocks
gated off, core in STOP mode, all ports
configured as inputs with input low and no
DC loads
2 MHz 0.99 mA/1.07
mA
0.97
uA/13.13
uA 5
VLPRUN
32 kHz core and per ipheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby ,
small regulator is disabled, PLL disabled,
repeat NOP instructions, all peripheral
modules, except COP and EWM, disabled
and clocks gated off, simple loop running
from platform ins truc tion buffer, all port s
configured as inputs with input low and no
DC loads
200 kHz 0.48 mA/0.57
mA
0.96
uA/13.04
uA 5
VLPWAIT
32 kHz core and per ipheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regu lator is in s tandby ,
small regulator is disabled, PLL disabled,
all peripheral modules, except COP,
disabled and clocks gated off, core in
WAIT mode, all ports configur ed as inputs
with input low and no DC loads
200 kHz 0.46 mA/0.56
mA
0.95
uA/12.02
uA 5
VLPSTOP
32 kHz core and per ipheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby ,
small regulator is disabled, PLL disabled,
all peripheral modules, except CO P,
disabled and clocks gated off, core in
STOP mode, all ports configured as inputs
with input low and no DC loads
200 kHz 0.43 mA/0.56
mA
0.93
uA/10.58
uA 5
Reset and Interrupt Timing
Symbol Characteristic Min. Max. Unit Notes
tRA Minimum
RESET
Assertion Duration 16 - ns 6
tRDA
RESET
deassertion to First Address Fetch 865 × TOSC + 8 ×
TSYSCLK - ns 7
tIF Delay from Interrupt Assertion to Fetch of
first instruction (exiting STOP mode) 361.3 570.9 ns
PM C Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Symbol Characteristic Min. Typ. Max. Unit
VPOR_A POR Assert Voltage8 - 2.0 - V
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
10 Freescale Semiconductor
VPOR_R POR Release Voltage9 - 2.7 - V
VLVI_2p7 LVI_2p7 Threshold Voltage - 2.73 - V
VLVI_2p2 LVI_2p2 Threshold Voltage - 2.23 - V
JTAG Timing
Symbol Description Min. Max. Unit Notes
fOP TCK frequency of operation DC fSYSCLK/8 (16) MHz 10
tPW TCK clock pulse width 50 - ns
tDS TMS, TDI data set-up time 5 - ns
tDH TMS, TDI data hold time 5 - ns
tDV TCK low to TDO data valid - 30 ns
tTS TCK low to TDO tri-state - 30 ns
Regulator 1.2 V Parameters
Symbol Characteristic Min. Typ. Max. Unit
VCAP Output Voltage11 - 1.22 - V
ISS Short Circuit Current
12
- 600 - mA
TRSC Short Circuit Tolerance (VCAP shorted to
ground) - - 30 Mins
VREF Reference Voltage (after trim) - 1.21 - V
External Clock Timing
Symbol Characteristic Min. Typ. Max. Unit
fOSC Frequency of operatio n (external clock
driver) - - 50 MHz
tPW Clock pulse width13 8 ns
trise External clock input rise time 14 - - 1 ns
tfall External clock inpu t fa ll time 15 - - 1 ns
Vih Input high voltage ov erdriv e by an external
clock 0.85×VDD - - V
Vil Input low voltage ov erdr iv e by an exter nal
clock - - 0.3×VDD V
Phase-Locked Loop (PLL) Timing
Symbol Characteristic Min. Typ. Max. Unit
fRef_PLL PLL input reference frequency16 8 8 16 MHz
fOP_PLL PLL output frequency17 200/240 - 400 MHz
tLock_PLL P LL lock time18 35.5 - 73.2 µs
tDC_PLL Allowed Duty Cycle of input reference 40 50 60 %
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Freescale Semiconductor 11
External Crystal or Resonator Specifications
Symbol Characteristic Min. Typ. Max. Unit
fXOSC Frequency of operation 4 8 16 MHz
Relaxation Oscillator Electrical Specifications
Symbol Characteristic Min. Typ. Max. Unit
fROSC_8M
8 MHz Output Frequency20
RUN Mode
• 0 °C to 105 °C
• -40 °C to 105 °C
Standby Mode (IRC trimmed @ 8 MHz)
• -40 °C to 105 °C
7.84
7.76
266.8
8
8
402
8.16
8.24
554.3
MHz
MHz
kHz
fROSC_8M_Delta
8 MHz Frequency Variation
RUN Mode
Due to temperature
• 0 °C to 105 °C
• -40 °C to 105 °C
-
-
+/-1.5
+/-1.5
+/-2
+/-3
%
%
fROSC_200k/32k19,
20
200 kHz/32 kHz Output Frequency
19,21
RUN Mode
• -40 °C to 105 °C
194/30.1
200/32
206/33.9
kHz
fROSC_200k/32k_D
elta19,20
200 kHz/32 kHz Output Frequency
Variation19,21
RUN Mode
Due to temperature
• 0 °C to 85 °C
• -40 °C to 105 °C22
-
-
+/-1.5
+/-1.5 (2.5)
+/-2
+/-3 (4)
%
%
tStab Stabilization Time
• 8 MHz output23
• 200 kHz/32 kHz output19,24
-
-
0.12
10/14.4
0.4
-/16.2
µs
µs
tDC_ROSC Output Duty Cycle 48 50 52 %
Flash Specifications
Symbol Description Min. Typ. Max. Unit
thvpgm4 Longw ord Progr am high-voltage time - 7.5 18 µs
thversscr Sector Erase high-voltage time25 - 13 113 ms
thversall Erase All high-voltage time25,26 - 52 452 ms
thversblk32k Erase Block high-voltage time for 32
KB25,27 - 52 452 ms
thversblk256k Erase Block high-voltage tim e for 256
KB25,27 - 104 904 ms
trd1sec1k/2k Read 1s Section execution time (flash
sector)28 - - 60 µs
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12 Freescale Semiconductor
trd1blk32k
trd1blk256k
Read 1s Block execution time27
• 32 KB FlexNVM
• 256 KB program Flash
-
-
-
-
0.5
1.7
ms
ms
tpgmchk Program Check execution time28 - - 45 µs
trdrsrc Read Resource execution time28 - - 30 µs
tpgm4 Program Longword execution time - 65 145 µs
tersscr Erase Flash Sector execution time29 - 14 114 ms
tersblk32k
tersblk256k
Erase Flash Block execution time27,29
• 32 KB FlexNVM
• 256 KB p rogr am Flash
-
-
55
122
465
985
ms
ms
tpgmsec512p
tpgmsec512n
tpgmsec1kp
tpgmsec1kn
Program Section execution time
27
• 512 B program Flash
• 512 B FlexNVM
• 1 KB program Flash
• 1 KB FlexNVM
-
-
-
-
2.4
4.7
4.7
9.3
-
-
-
-
ms
ms
ms
ms
trd1all Read 1s All Blocks execution time - - 0.9/1.830 ms
trdonce Read Once execution time28 - - 25 µs
tpgmonce Program Once execution time - 65 - µs
tersall Erase All Blocks execution time29 - 70/17530 575/150030 ms
tvfykey Verify Backdoor Access Key execution
time28 - - 30 µs
tpgmpart32k Program Partition for EEPROM execution
time for 32 KB FlexNVM27 - 70 - ms
tsetramff
tsetram8k
tsetram32k
Set FlexRAM Function execution time
27
• Control Code 0xFF
• 8 KB EEPROM backup
• 32 KB EEPROM backup
-
-
-
50
0.3
0.7
-
0.5
1.0
µs
ms
ms
teewr8bers Byte-write to erased FlexRAM loc ation
execution time27,31 - 175 260 µs
teewr8b8k
teewr8b16k
teewr8b32k
Byte-write to FlexRAM execution time
27
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
-
-
-
340
385
475
1700
1800
2000
µs
µs
µs
teewr16bers Word-write to erased FlexRAM location
execution time27 - 175 260 µs
teewr16b8k
teewr16b16k
teewr16b32k
Word-write to FlexRAM execution time
27
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
-
-
-
340
385
475
1700
1800
2000
µs
µs
µs
teewr32bers Longword-write to erased FlexRAM
location exec ution time27 - 360 540 µs
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Freescale Semiconductor 13
teewr32b8k
teewr32b16k
teewr32b32k
Longword-write to FlexRAM execution
time27
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
-
-
-
545
630
810
1950
2050
2250
µs
µs
µs
tflashret10k Data retention after up to 10 K cycles 5 5032 - years
tflashret1k Data retention after up to 1 K cycles 20 10032 - years
nflashcyc Cycling endur ance 33 10 K 50 K32 - cycles
teeret100 Data retention up to 100% of write
endurance27 5 5032 - years
teeret10 Data retention up to 10% of write
endurance27 20 10032 - years
neewr16
neewr128
neewr512
neewr4k
neewr8k
Write endurance27,34
• EEPROM back up to FlexRAM ratio =
16
• EEPROM backup to FlexRAM ratio =
128
• EEPROM backup to FlexRAM ratio =
512
• EEPROM backup to FlexRAM ratio =
4096
• EEPROM backup to FlexRAM ratio =
8192
35 K
315 K
1.27 M
10 M
20 M
175 K
1.6 M
6.4 M
50 M
100 M
-
-
-
-
-
writes
writes
writes
writes
writes
12-bit Cyclic ADC Electrical Specifications
Symbol Characteristic Min. Typ. Max. Unit
VDDA Supply voltage35 3.0 3.3 3.6 V
VREFHX VREFH supply voltage36 VDDA - 0.6 VDDA V
fADCCLK ADC conversion clock 37 0.1/0.6 - 10/20 MHz
RADC Conversion range38
• Fully differential26
• Single-ended/unipolar
-( VREFH - VREFL)
VREFL
-
-
VREFH -
VREFL
VREFH
V
V
VADCIN Input voltage range (per input)39
• External Reference
• Internal Reference
VREFL
VSSA
-
-
VREFH
VDDA
V
V
tADC Conversion time40 - 8/6 - tADCCLK
tADCPU ADC power-up time (from adc_pdn) - 13 - tADCCLK
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14 Freescale Semiconductor
IADCRUN
ADC RUN current (per ADC block)26
ADC RUN current (per ADC block)27
• at 600 kHz ADC clock, LP mode
• ≤ 8.33 MHz ADC clock, 00 mode
• ≤ 12.5 MHz ADC clock, 01 mode
• ≤ 16.67 MHz ADC clock, 10 mode
• ≤ 20 MHz ADC clock, 11 mode
-
-
-
-
-
-
1.8
1
5.7
10.5
17.7
22.6
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
IADPWRDWN ADC power down current (adc_pdn
enabled)41 - 0.1/0.02 - µA
IVREFH VREFH current (in external mode)42 - 190/0.001 - µA
INLADC Integral non-linearity43 - +/- 1.5 (3) +/- 2.2 (5) LSB44
DNLADC Differential non-linearity43 - +/- 0.5 (0.6) +/- 0.8 (0.9) LSB44
VOFFSET Offset45
• Fully differential26
• Single ended/Unipolar46
-
-
+/- 8
+/- 12 (13.7)
-
-
mV
mV
EGAIN Gain Error -
- 0.996 to 1.004 26
0.994 to 1.00427 0.99 to 1.01 -
-
ENOB Effective number of bits47 - 10.6/9.5 - bits
IINJ Input injection curr e nt48 - - +/-3 mA
CADCI Input sampling capacitance49 - 4.8/1.4 - pF
16-bit SAR ADC Electrical Specifications27
Symbol Characteristic Min. Typ.50 Max. Unit
VDDA Supply voltage 2.7 - 3.6 V
∆ VDDA Supply voltage delta to VDD - 0.1 0 + 0.1 V
∆ VSSA Supply voltage delta to VSS - 0.1 0 + 0.1 V
VREFH ADC reference voltage high VDDA VDDA VDDA V
VREFL ADC reference voltage low VSSA VSSA VSSA V
VADIN Input voltage range VSSA - VDDA V
CADIN Input capacitance
• 16-bit mode
• 8-/10-/12-bit mode
-
-
8
4
10
5
pF
pF
RADIN Input resistance - 2 5 kΩ
fADCK ADC conversion clock frequency51
• 16-bit mode
• 8-/10-/12-bit mode
2
1
-
-
12
18
MHz
MHz
Crate
ADC conversion rate without ADC
hardware averaging
• 16-bit mode
• 8-/10-/12-bit mode
37.037
20.000
-
-
461.467
818.330
ksps
ksps
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Freescale Semiconductor 15
IDDA_ADC Supply current52 - - 1.7 mA
fADACK
ADC asynchronous clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
MHz
MHz
MHz
MHz
INLAD
Integral non-linearity54
• 16-bit mode
• 12-bit mode
• < 12-bit m odes
-
-
-
+/- 7.0
+/- 1.0
+/- 0.5
-
- 2.7 to +
1.9
- 0.7 to +
0.5
LSB53
LSB53
LSB53
DNLAD
Differential non-linearity54
• 16-bit mode
• 12-bit mode
• < 12-bit m odes
-
-
-
- 1.0 to + 4.0
+/- 0.7
+/- 0.2
-
-
- 0.3 to +
0.5
LSB53
LSB53
LSB53
EFS Full-scale error (VADIN = VDDA)54
• 12-bit mode
• < 12-bit m odes
-
-
- 4
- 1.4
- 5.4
- 1.8
LSB53
LSB53
EQ Quantization error
• 16-bit mode
• 12-bit mode
-
-
- 1 to 0
-
-
+/- 0.5
LSB53
LSB53
ENOB
Effective number of bits55
16-bit single-ended mode
• Avg = 32
• Avg = 4
12-bit single-ended mode
• Avg = 32
• Avg = 4
12.2
11.4
-
-
13.9
13.1
10.8
10.2
-
-
-
-
bits
bits
bits
bits
STEMP Temp sensor s lope un der -40 °C to 105 °C - 1.715 - mV/°C
VTEMP25 Temp sensor voltage56 at 25 °C - 722 - mV
12-bit DAC Electrical Specifications
Symbol Characteristic Min. Typ. Max. Unit
tSETTLE Settling time57 under RLD = 3 kΩ, CLD = 400
pF - 1 - µs
tDACPU DAC power-up time (from PWRDWN
release to valid DACOUT) - - 11 µs
INLDAC Integral non-linearity59 - +/- 3 +/- 4 LSB58
DNLDAC Differential non-linearity59 - +/- 0.8 +/- 0.9 LSB58
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16 Freescale Semiconductor
MONDAC Monotonicity (> 6 sigma mono t onic ity, <
3.4 ppm non-monotonicity) Guaranteed -
VOFFSET Offset error59 (5% to 95% of full range) - +/- 25 +/- 43 mV
EGAIN Gain error59 (5% to 95% of full range) - +/- 0.5 +/- 1.5 %
VOUT Output voltage range VSSA + 0.04 - VDDA - 0.04 V
SNR Signal-to-noise ratio - 85 - dB
ENOB Effective number of bits - 11 - bits
Comparator and 6-bit DAC Electrical Specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 2.7 - 3.6 V
IDDHS Supply current, High-speed m ode(E N=1,
PMODE=1)60 - 300/- -/200 µA
IDDLS Supply current, Low-speed mode(EN=1,
PMODE=0)60 - 36/- -/20 µA
VAIN Analog input voltage Vss - 0.3 - VDD V
VAIO Analog input offset voltage - - 20 mV
VH
Analog compar ator hy steresis61
• CR0[HYSTCTR]=00
• CR0[HYSTCTR]=01
• CR0[HYSTCTR]=10
• CR0[HYSTCTR]=11
-
-
-
-
5
25/10
55/20
80/30
13
48
105
148
mV
mV
mV
mV
VCMPOh Output high VDD - 0.5 - - V
VCMPOl Output low - - 0.5 V
tDHS Propagation delay, high-speed
mode(EN=1, PMODE=1)62 - - 50 ns
tDLS Propagation delay, low-speed
mode(EN=1, PMODE=0) 62 - - 200 ns
tDInit Analog comparator initialization delay63 - 40 - µs
IDAC6b 6-bit DAC current adder (enabled) - 7 - µA
RDAC6b 6-bit DAC reference inputs VDDA - VDD V
INLDAC6b 6-bit DAC integral non-linearity -0.5 - 0.5 LSB64
DNLDAC6b 6-bit DAC differential non-linearity -0.3 - 0.3 LSB64
PWM Timing Parameters
Symbol Characteristic Min. Typ. Max. Unit
fPWM PWM clock frequency - 100 - MHz
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Freescale Semiconductor 17
SPWMNEP NanoEdge Placement (NEP) step size65,66 - 312 - ps
tDFLT Delay for fault input activating to PWM
output deactivated 1 - - ns
tPWMPU Power-up time67 - 25 - µs
Quad Timer Timing
Symbol Characteristic Min. Max. Unit Notes
PIN Timer input period 2Ttimer + 6 - ns 68
PINHL Timer input high/low period 1Ttimer + 3 - ns 68
POUT Timer output period 2Ttimer - 2 - ns 68
POUTHL Timer output high/low period 1Ttimer - 2 - ns 68
QSPI Timing
69
Symbol Characteristic Min. Max. Unit
Master Slave Master Slave
tC Cycle time 60/35 60/35 - - ns
tELD Enable lead time - 20/17.5 - - ns
tELG Enable lag time - 20/17.5 - - ns
tCH Clock (SCLK) high time 28/16.6 28/16.6 - - ns
tCL Clock (SCLK) low time 28/16.6 28/16.6 - - ns
tDS Data set-up tim e req uire d for i nput s 20/16.5 1 - - ns
tDH Data hold time required for inputs 1 3 - - ns
tA Acce ss tim e (ti me t o data active from
high-impedan ce sta te) 5 - ns
tD Disable time (hold time to high-impedance
state) 5 - ns
tDV Data valid for outputs - - -/5 -/15 ns
tDI Data invalid 0 0 - - ns
tR Rise time - - 1 1 ns
tF Fall time - - 1 1 ns
QSCI Timing
Symbol Characteristic Min. Max. Unit Notes
BRSCI Baud rate - (fMAX_SCI /16) Mbit/s 70
PWRXD RXD pulse width 0.965/BRSCI 1.04/BRSCI ns
PWTXD TXD pulse width 0.965/BRSCI 1.04/BRSCI ns
LIN Slave Mode
FTOL_UNSYNCH Deviation of slav e node clock f rom nominal
clock rate before synchronization - 14 14 %
FTOL_SYNCH Deviation of slave node cl oc k relativ e to
the master node clock after
synchronization - 2 2 %
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18 Freescale Semiconductor
TBREAK Minimum break character length 13 - Mater node
bit periods
11 - Slave node
bit periods
CAN Timing
Symbol Characteristic Min. Max. Unit Notes
BRCAN Baud rate - 1 Mbit/s
TWAKEUP CAN Wakeup dominant pul se filtered - 1.5/2 µs 71
TWAKEUP CAN Wakeup dominant pul se pas s 5 - µs
IIC Timing
Symbol Characteristic Min. Max. Unit Notes
Min. Max. Min. Max.
fSCL SCL clock frequency 0 100 0 400 kHz
tHD_STA Hold time (repeated) START condition.
After this period , the fi rst clock pulse is
generated. 4 - 0.6 - µs
tSCL_LOW LOW period of the SCL clock 4.7 - 1.3 - µs
tSCL_HIGH HIGH period of the SCL clock 4 - 0.6 - µs
tSU_STA Set-up time for a repeated START
condition 4.7 - 0.6 - µs
tHD_DAT Data hold time for IIC bus devices 072 3.4573 074 0.972 µs
tSU_DAT Data set-up time 25075 - 10076 - ns 73
tr Rise time of SDA and SCL signals - 1000 20 + 0.1Cb 300 ns 77
tf Fall time of SDA and SCL signals - 300 20 + 0.1Cb 300 ns 76
tSU_STOP Set-up time for STOP condition 4 - 0.6 - µs
tBUS_Free Bus free time between STOP and START
condition 4.7 - 1.3 - µs
tSP Pulse width of spikes that must be
suppressed by the input filt er N/A N/A 0 50 ns
1. CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured
from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode.
2. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO.
3. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO.
4. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO.
5. WCT1001A supports maximum 100 MHz CPU clock and 50 MHz peripheral bus clock, maximum 100 MHz CPU and peripheral bus
clock for WCT1003A. In total, WCT1003A has higher power consumption than WCT1001A in the same operating mode. For the
current consumption data, the former is for WCT1001A, and the latter for WCT1003A.
6. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be
greater than 21 ns.
7. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle.
8. During 3.3 V VDD power supply ramp down.
9. During 3.3 V VDD power supply ramp up (gated by LVI_2p7).
10. The maximum TCK operation frequency is fSYSCLK/8 for WCT1001A, fSYSCLK/16 for WCT1003A.
11. Value is after trim.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 19
12. Guaranteed by design.
13. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
14. External clock input rise time is measured from 10% to 90%.
15. External clock input fall time is measured from 90% to 10%.
16. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is
optimized for 8 MHz input.
17. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to
400 MHz. And the minimum PLL output frequency is 200 MHz for WCT1001A, 240 MHz for WCT1003A.
18. This is the time required after the PLL is enabled to ensure reliable operation.
19. 200 kHz internal RC oscillator is on WCT1001A, 32 kHz internal RC oscillator on WCT1003A.
20. Frequency after application of 8 MHz trimmed.
21. Frequency after application of 200 kHz/32 kHz trimmed.
22. Typical +/-1.5%, maximum +/-3% frequency variation for 200 kHz internal RC oscillator, and typical +/-2.5%, maximum +/-4%
frequency variation for 32 kHz internal RC oscillator.
23. Standby to run mode transition.
24. Power down to run mode transition. Typical 10 µs stabilization time for 200 kHz internal RC oscillator, and 14.4 µs stabilization time
for 32 kHz internal RC oscillator.
25. Maximum time based on expectations at cycling end-of-life.
26. The specification is only for WCT1001A.
27. The specification is only for WCT1003A.
28. Assumes 25 MHz flash clock frequency.
29. Maximum times for erase parameters based on expectations at cycling end-of-life.
30. All blocks size is 64 KB on WCT1001A, 256 KB on WCT1003A. Longer all blocks command operation time for WCT1003A.
31. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
32. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use
profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619.
33. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
34. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤ Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM.
35. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed.
36. When the input is at the VREFL level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain
error. When the input is at the VREFH level the output will be all ones (hex FFF), minus any error contribution due to offset and gain
error.
37. ADC clock duty cycle is 45% ~ 55%. WCT1001A only supports the maximum ADC clock of 10 MHz and minimum ADC clock of 0.1 MHz,
and WCT1003A supports 20 MHz maximum ADC clock and 0.6 MHz minimum ADC clock.
38. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
39. In unipolar mode, positive input must be ensured to be always greater than negative input.
40. For WCT1001A, the first conversion takes 10 clock cycles, 8 clock cycles for the subsequent conversion; On WCT1003A, 8.5 clock
cycles for the first conversion, 6 clock cycles for the subsequent conversion.
41. For WCT1001A, the power down current of ADC is 0.1 µA, and 0.02 µA for WCT1003A.
42. For WCT1001A, the VREFH current of ADC is 190 µA, and 0.001 µA for WCT1003A.
43. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. On WCT1001A,
typical value is +/- 1.5 LSB, and maximum value +/- 2.2 LSB for INLADC; typical value is +/- 0.5 LSB, and maximum value +/- 0.8 LSB for
DNLADC. On WCT1003A, typical value is +/- 3 LSB, and maximum value +/- 5 LSB for INLADC; typical value is +/- 0.6 LSB, and maximum
value +/- 1 LSB for DNLADC.
44. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting.
45. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk).
46. Typical +/- 12 mV offset for WCT1001A, +/- 13.7 mV offset for WCT1003A.
47. Typical ENOB is 10.6 bits for WCT1001A, 9.5 bits for WCT1003A.
48. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC.
49. Typical input capacitance is 4.8 pF for WCT1001A, 1.4 pF for WCT1003A.
50. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and
are not tested in production.
51. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
52. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest
power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed.
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20 Freescale Semiconductor
53. 1 LSB = (VREFH - VREFL)/2N.
54. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11).
55. Input data is 100 Hz sine wave; ADC conversion clock < 12 MHz.
56. System clock = 4 MHz, ADC clock = 2 MHz, AVG = Max, Long Sampling = Max.
57. Settling time is swing range from VSSA to VDDA.
58. LSB = 0.806 mV.
59. No guaranteed specification within 5% of VDDA or VSSA.
60. Typical supply current with high-speed mode is 300 µA, typical supply current with low-speed mode is 36 µA on WCT1001A.
Maximum supply current with high-speed mode is 200 µA, maximum supply current with low-speed mode is 20 µA on WCT1003A.
61. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. On WCT1001A, typical 25 mV for CR0[HYSTCTR]
= 01, typical 55 mV for CR0[HYSTCTR] = 10, typical 80 mV for CR0[HYSTCTR] = 11. On WCT1003A, typical 10 mV for CR0[HYSTCTR] =
01, typical 20 mV for CR0[HYSTCTR] = 10, typical 30 mV for CR0[HYSTCTR] = 11.
62. Signal swing is 100 mV.
63. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL,
PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
64. 1 LSB = Vreference/64.
65. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.
66. Temperature and voltage variations do not affect NanoEdge Placement step size.
67. Powerdown to NanoEdge mode transition.
68. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns.
69. For QSPI specifications, all data with xx/xx format, the former is for WCT1001A, the latter is for WCT1003A.
70. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device.
71. WCT1001A supports maximum 1.5 us pulse filtered, and WCT1003A supports maximum 2 us pulse filtered.
72. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this
address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
73. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal.
74. Input signal Slew = 10 ns and Output Load = 50 pF
75. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
76. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT ≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns
(according to the Standard mode IIC bus specification) before the SCL line is released.
77. Cb = total capacitance of the one bus line in pF.
2.3 Thermal Operating Characteristics
Table 7. General Thermal Characteristics
Symbol Description Min Max Unit
TJ Die junction temperature -40 125 °C
TA Ambient temperature -40 105 °C
3 Typical Performance Characteristics
3.1 System Efficiency
The typic al ma ximum system e ff iciency (rece ive r output power vs. tran smitter input powe r) on Freescale
WCT100xA A13 transmitter reference solution is shown in Figure 1, using a test receiver (aka Rx, low
power receiver) under resistive load.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 21
Figure 1. System Efficiency on Fr eescale A13 Reference Board
Note: Power components are the main factor to determine the system efficiency, such as drivers and
MOSFETs.
Figure 2 shows the active charging area of the Freescale WCT100xA A13 transmitter reference solution
— transmitter well charges receiver load at different X/Y offsets. For this test, the low power receiver is
used as the test receiver with constant 700 mA loading and 3 mm Z gap between transmitter surface and
receiver surface.
Figure 2. Active Charging Area on WCT100xA A13 Transmitter Reference Solution
3.2 Standby Power
The purpose of the standby mode of operation is to reduce the power consumption of a wireless power
transfer system when power transfer is not required. There are two ways to enter standby mode. The first is
when the transmitter does not detect the presence of a valid receiver. The second is when the receiver
sends only an End Power Transfer Packet. In standby mode, the transmitter only monitors whether a
receiver is placed on the active charging area of the transmitter or removed from there.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
22 Freescale Semiconductor
It is recommended that the transmitter’s power consumption in standby mode meets the relative regional
regulations especially for “No-load power consumption”.
3.3 Digital Demodulation
In order to optimize system BOM cost, WCT100xA solution employs digital demodulation algorithm to
communicate with receiver. This method can achieve high performance, low cost, and very simple coil
signal sensing circuit with fewer external components.
3.4 Foreign Object Detection
WCT100xA solution employs flexible, intelligent, and easy-to-use FOD algorithm to ensure accurate
foreign metal objects detection. With Freescale FreeMASTER GUI tool, FOD algorithm can be easily
calibrated to get accurate power loss information especially for very sensitive foreign objects.
4 Device Inform ation
4.1 Functional Block Diagram
This functional block diagram just shows the common pin assignment information by all members of the
family. For the detailed pin multiplexing information, refer to Section 4.4 “Pin Function Description”.
Figure 3. WCT1001/3AVLH Function Block Diagra m
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Freescale Semiconductor 23
4.2 Product Features Ove rview
The following table highlights features that differ among members of the family. Features not listed are
shared in common by all members of the family.
Table 8. Feature Comparison Between WCT1001A and WCT1003A
Part WCT1001A WCT1003A
Maximum Core/Bus Clock (MHz) 100/50 100/100
Maximum Fully Run Current Consumption (mA) 35.58 (VDD) + 9.08 (VDDA) 63.7 (VDD) + 16.7 (VDDA)
On-Chip Flash
Memory Size (KB)
Program Flash Memory 64 256
FlexNVM/FlexRAM 0/0 32/2
Total Flash Memory 64 288
On-Chip SRAM Memory Size (KB) 8 32
Memory Resource Protection Yes Yes
Inter-Peripheral Crossbar Switches with AOI Yes Yes
On-Chip Relaxation Oscillator 1 (8 MHz) + 1 (200 kHz) 1 (8 MHz) + 1 (32 kHz)
Computer Operating Properly (Watchdog) 1 (windowed) 1
External Watchdog Monitor 1 1
Cyclic Redundancy Check 1 1
Periodic Interrupt Timer 2 2
Quad Timer 1 x 4 2 x 4
Programmable Delay Block 0 2
12-bit Cyclic ADC Channels 2 x 8 2 x 8
16-bit SAR ADC Channels 0 1 x 8
PWM Channels High-Resolution 8 8
Standard 4 1
12-bit DAC 2 1
Analog Comparator /w 6-bit REF DAC 4 4
DMA Channels 4 4
Queued Seri al Communications Interface 2 2
Queued Serial Peripheral Interface 2 1
Inter-Integrated Circui t 1 2
Controller Area Network 1 (MSCAN) 1 (FlexCAN)
GPIO 54 54
Package 64 LQFP 64 LQFP
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
24 Freescale Semiconductor
4.3 Pinout Diagram
Figure 4. WCT1001/3AVLH Pinout Diagram
4.4 Pin Function Description
By default, each pin is configured for its primary function (listed first). Any alternative functionality,
shown in parentheses, can be programmed through GPIO module peripheral enable registers and SIM
module GPIO peripheral select registers.
Table 9. Pin Signal Descriptions
Signal Name Pin No.
Multiplexing
Signals
Function Description
TCK 1 GPIOD2
test logic an d shift serial da ta to the JTAG /EOnCE port. The pin is connected
internally to a pull-up resi stor. A Schmitt-trigger input is used for noise
immunity.
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
RESET 2 GPIOD4
— This input is a direct hardware reset on the processor. When
is asserted low, the device is ini tialized and placed in the reset stat e .
A Schmitt-trigger in put is used f or noise immun ity. The internal reset signal is
de-asserted sy nchro nous with the intern al clo ck s after a fixed number of
internal clock s.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 25
or output pin. If
functionality is disabled i n th is mode and the c hip c an
be reset only via POR, COP reset, or software reset.
GPIOC0 3 EXTAL/CLKIN0
or output pin.
EXTAL — External Crystal Oscillator Input. This input connects the internal
crystal oscillator input to an external crystal or cerami c resonator.
CLKIN0 — This pin serves as an external clock inp ut 0.
GPIOC1 4 XTAL
or output pin.
XTAL — External Cry stal Oscill ator Output. T his output co nnects the internal
crystal oscillator output to an external crystal or ceramic resonator.
GPIOC2 5 TXD0/XB_OUT
11(TB0)/XB_IN
2/CLKO0
or output pin.
TXD0 — The SCI0 transmit data output or transmit/receive in single wire
operation.
XB_OUT11 — Crossbar module output 11 only on WCT1001A.
TB0 — Quad timer module B channel 0 input/output only on WCT1003A.
XB_IN2 — Crossbar module input 2.
CLKO0 — This is a buffered clock output 0; the clock source is selected by
clock out select (CLKOSEL) bits in the clock output select re gist er
(CLKOUT) of the SIM.
GPIOF8 6 RXD0/XB_OUT
10(TB1)/CMPD
_O/PWM_2X
output pin.
RXD0 — The SCI0 receive data input.
XB_OUT10 — Crossbar module output 10 only on WCT1001A.
TB1 — Quad timer module B channel 1 input/output only on WCT1003A.
CMPD_O — Analog comparator D output.
PWM_2X — NanoEdge eFlexPWM sub-module 2 output X or input capture
X only on WCT1001A.
GPIOC3 7 TA0/CMPA_O/
RXD0/CLKIN1
or output pin.
TA0 — Quad timer module A channel 0 input/output.
CMPA_O — Analog comparator A output.
RXD0 — The SCI0 receive data input.
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26 Freescale Semiconductor
GPIOC4 8 TA1/CMPB_O/X
B_IN6(XB_IN8)/
EWM_OUT
or output pin.
TA1 — Quad timer module A channel 1 input/output.
CMPB_O — Analog comparator B output.
XB_IN6 — Crossbar module input 6 only on WCT1001A.
XB_IN8 — Crossbar module input 8 only on WCT1003A.
— Ex ternal w atchdog mon itor output.
GPIOA7 9 ANA7&CMPD_I
N3(ANC11)
or output pin.
ANA7&CMPD_IN3 — Analog input to channel 7 of ADCA and input 3 of
analog comparator D on ly on WCT1001A. When used as an analog input,
the signal goes to the ANA7 and CMPD_IN3.
ANA7&ANC11 — Analog in put to channel 7 of ADCA and analog input 11 of
ADCC only on WCT1003A. When used as an analog input, the signal goes
to the ANA7 and ANC11.
GPIOA6 10 ANA6&CMPD_I
N2(ANC10)
or output pin.
ANA6&CMPD_IN2 — Analog input to channel 6 of ADCA and input 2 of
analog comparator D only on WCT1001A. W hen used as an analog input,
the signal goes to the ANA6 and CMPD_IN2.
ANA6&ANC10 — Analog input to channel 6 of ADCA and ana log input 1 0 of
ADCC only on WCT1003A. When used as an analog input, the signal goes
to the ANA6 and ANC10.
GPIOA5 11 ANA5&CMPD_I
N1(ANC9)
or output pin.
ANA5&CMPD_IN1 — Analog input to channel 5 of A DCA and input 1 of
analog comparator D only on WCT1001A. W hen used as an analog input,
the signal goes to the ANA5 and CMPD_IN1.
ANA5&ANC9 — Analog input to channel 5 of ADCA and analog input 9 of
ADCC only on WCT1003A. When used as an analog input, the signal goes
to the ANA5 and ANC9.
GPIOA4 12 ANA4&CMPD_I
N0&ANC8
or output pin.
ANA4&CMPD_IN0 — Analog input to channel 4 of ADCA and input 0 of
analog comparator D on ly on WCT1001A. When used as an analog input,
the signal goes to the ANA4 and CMPD_IN0.
ANA4&CMPD_IN0&ANC8 — Analog input to channel 4 of ADCA and input 0
of analog comparator D and analog input to channel 8 of ADCC only on
WCT1003A. When used as an analog input, the signal goes to the ANA4
and CMPD_IN0 and ANC8.
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Freescale Semiconductor 27
GPIOA0 13 ANA0&CMPA_I
N3/CMPC_O
or output pin.
ANA0&CMPA_IN3 — Analog input to channel 0 of ADCA and input 3 of
analog compar at or A. When used as an analog input, the signal go es to t he
ANA0 and CMPA_IN3.
CMPC_O — Analog comparator C output.
GPIOA1 14 ANA1&CMPA_I
N0
or output pin.
ANA1 and CMPA_IN0 — Analog input to channel 1 of ADCA and input 0 of
analog compar at or A. When used as an analog input, the signal goes to the
ANA1 and CMPA_IN0.
GPIOA2 15 ANA2&VREFH
A&CMPA_IN1
or output pin.
ANA2&VREFHA&CMPA_IN1 — Analog input to channel 2 of ADCA and
analog refer enc es h igh o f ADCA and input 1 of analog comp a r ator A . When
used as an analog input, the signal goes to ANA2 and VREFHA and
CMPA_IN1. ADC co ntrol register confi gures t his input as ANA2 or VREFHA.
GPIOA3 16 ANA3&VREFLA
&CMPA_IN2
or output pin.
ANA3&VREFLA&CMPA_IN2 — Analog input to channel 3 of ADCA and
analog references low of ADCA and input 2 of analog comparator A. When
used as an analog input, the signal goes to ANA3 and VREFLA an d
CMPA_IN2. ADC control regist er co nfigures thi s input as ANA3 or VREFLA.
GPIOB7 17 ANB7&CMPB_I
N2&ANC15
or output pin.
ANB7&CMPB_IN2 — Analog input to channel 7 of A DCB and input 2 of
analog comparator B only on WCT1001A. When used as an analog input,
the signal goes to the ANB7 and CMPB_IN2.
ANB7&CMPB_IN2&ANC15 — Analog input to channel 7 of ADCB and i nput
2 of analog comparator B and analog input to channel 15 of ADCC only on
WCT1003A. When used as an analog input, the signal goes to the ANB7
and CMPB_IN2 and ANC15.
GPIOC5 18 DAC_O/XB_IN7
or output pin.
DAC_O — 12-bit Digital-to-Analog Converter output. For WCT 1001A, it’s
DACA output.
XB_IN7 — Crossbar module input 7.
GPIOB6 19
ANB6&CMPB_I
N1&ANC14
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28 Freescale Semiconductor
ANB6&CMPB_IN1 — Analog input to channel 6 of A DCB and input 1 of
analog comparator B only on WCT1001A. When used as an analog input,
the signal goes to the ANB6 and CMPB_IN1.
ANB6&CMPB_IN1&ANC14 — Analog input to channel 6 of ADCB and input
1 of analog comparator B and analog input to channel 14 of ADCC only on
WCT1003A. When used as an analog input, the signal goes to the ANB6
and CMPB_IN1 and ANC14.
GPIOB5 20 ANB5&CMPC_I
N2&ANC13
or output pin.
ANB5&CMPC_IN2 — Analog input to channel 5 of ADCB and input 2 of
analog comparator C only on WCT1001A . When used as an analog input,
the signal goes to the ANB5 and CMPC_IN2.
ANB5&CMPC_IN2&ANC13 — Analog in put to chann el 5 of ADCB and in put
2 of analog comparator C an d analog input to channel 13 of ADCC only on
WCT1003A. When used as an analog input, the signal goes to the ANB5
and CMPC_IN2 and ANC13.
GPIOB4 21 ANB4&CMPC_I
N1&ANC12
or output pin.
ANB4&CMPC_IN1 — Analog input to channel 4 of ADCB and input 1 of
analog comparator C only on WCT1001A. W hen used as an analog input,
the signal goes to the ANB4 and CMPC_IN1.
ANB4&CMPC_IN1&ANC12 — Analog in put to chann el 4 of ADCB and in put
1 of analog comparator C and analog input to channel 12 of ADCC only on
WCT1003A. When used as an analog input, the signal goes to the ANB4
and CMPC_IN1 and ANC12.
VDDA 22 -
VSSA 23 -
GPIOB0 24 ANB0&CMPB_I
N3
or output pin.
ANB0&CMPB_IN3 — Analog input to channel 0 of ADCB and input 3 of
analog comparator B. When used as an analog input, the signal goes to
ANB0 and CMPB_IN3.
GPIOB1 25 ANB1&CMPB_I
N0/DACB_O
or output pin.
ANB1&CMPB_IN0 — Analog input to channel 1 of ADCB and input 0 of
analog comparator B. When used as an analog input, the signal goes to
ANB1 and CMPB_IN0.
DACB_O — 12-bit Digital-to-Analog Converter B output only on WCT1001A.
VCAP1 26 -
stabilize the core voltage regulator output required for proper device
GPIOB2
27
ANB2&VREFH
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Freescale Semiconductor 29
B&CMPC_IN3
ANB2&VREFHB&CMPC_IN3 — Analog input to channel 2 of ADCB and
analog ref eren ce s hi gh o f AD CB and inpu t 3 of analog compar ator C . When
used as an analog input, the signal goes to ANB2 and VREFHB and
CMPC_IN3. ADC control register configur es this input as ANB2 or VREFHB.
GPIOB3 28 ANB3&VREFLB
&CMPC_IN0
or output pin.
ANB3&VREFLB&CMPC_IN0 — Analog input to channel 3 of ADCB and
analog references low of ADCB and input 0 of analog comparator C. When
used as an analog input, the signal goes to ANB3 and VREFLB and
CMPC_IN0. ADC control regi ster configure s this input as ANB3 or VREFLB.
VDD1
29
-
VSS1
30
-
GPIOC6 31 TA2/XB_IN3/C
MP_REF/SS0
or output pin.
TA2 — Quad timer module A channel 2 input/output.
XB_IN3 — Crossbar module input 3.
CMP_REF — Input 5 of analog comparator A and B and C and D.
SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the
current transfer is to be received. This signal is only on WCT1001A.
GPIOC7 32 SS0/TXD0/XB_I
N8
or output pin.
SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the
current transfer is to be received.
TXD0 — SCI0 transmit data output or transmit/receive in single wire
operation.
XB_IN8 — Crossbar module input 8 only on WCT1001A.
GPIOC8 33 MISO0
/RXD0/XB_IN9/
XB_OUT6
or output pin.
MISO0 — Master in/slave out. In master mode, this pin serves as the data
input. In sl ave mode, this pi n serves as the dat a outp ut. The MISO0 line of a
slave device is placed in the high-impedance stat e if the slave device is not
selected.
RXD0 — SCI0 receive data input.
XB_IN9 — Crossbar module input 9.
XB_OUT6 — Crossbar module output 6 only on WCT1001A.
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30 Freescale Semiconductor
GPIOC9 34 SCLK0/XB_IN4/
TXD0/XB_OUT
8
or output pin.
SCLK0 — The SPI0 serial clock. In master mod e, this pin serv es as an
output, clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
XB_IN4 — Crossbar module input 4.
TXD0 — SCI0 transmit data output or transmit/receive in single wire
operation. This signal is only on WCT1001A.
XB_OUT8 — Crossbar module output 8 only on WCT1 001A.
GPIOC10 35 MOSI0
/XB_IN5/MISO0
/XB_OUT9
or output pin.
MOSI0 — Master out/slave in. In master mode, this pin serves as the data
output. In slave mode, this pin serves as the data input.
XB_IN5 — Crossbar module input 5.
MISO0 — Master in/slave out. In master mode, this pin serves as the data
input. In sl ave mode, this pi n serves as the dat a outp ut. The MISO0 line of a
slave device is placed in the high-im ped anc e state if the slave device is not
selected.
XB_OUT9 — Crossbar module output 9 only on WCT1001A.
GPIOF0 36 XB_IN6/TB2/SC
LK1
output pin.
XB_IN6 — Crossbar module input 6.
TB2 — Quad timer module B channel 2 input/output only on WCT1003A.
SCLK1 — The SPI1 serial clock. In master mod e, this pin serv es as an
output, clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
GPIOC11 37 CAN_TX/SCL0(
SCL1)/TXD1
or output pin.
CANTX — CAN transmit data output.
SCL0 — IIC0 serial clo ck only on WCT1001A.
SCL1 — IIC1 seri a l clo ck only on WCT1003A.
TXD1 — SCI1 transmit data output or transmit/receive in single wire
operation.
GPIOC12 38 CAN_RX/SDA0(
SDA1)/RXD1
or output pin.
CANRX — CAN receive data input.
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Freescale Semiconductor 31
RXD1 — SCI1 receive data input.
GPIOF2 39 SCL0(SCL1)/XB
_OUT6/MISO1
output pin.
SCL0 — IIC0 seri a l clo ck only on WCT1001A.
SCL1 — IIC1 seri a l clo ck only on WCT1003A.
XB_OUT6 — Crossbar module output 6.
MISO1 — Master in/slave out. In master mode, this pin serves as the data
input. In sl ave mode, this pi n serves as the dat a outp ut. The MISO1 line of a
slave device is placed in the high-im ped anc e state if the slave device is not
selected. This signal is only on WCT1001A.
GPIOF3 40 SDA0(SDA1)/X
B_OUT7/
MOSI1
output pin.
SDA0 — IIC0 serial data line o nly on WCT1001A .
SDA1 — IIC1 serial data line o nly on WCT1003A .
XB_OUT7 — Crossbar module output 7.
MOSI1 — Master out/slave in. In master mode, this pin serves as the data
output. In sl ave mode, this pin serves as the data input . This signa l is only on
WCT1001A.
GPIOF4 41 TXD1/XB_OUT
8/PWM_0X/PW
M_FAULT6
output pin.
TXD1 — The SCI1 transmit data output or transmit/receive in single wire
operation.
XB_OUT8 — Crossbar module output 8.
PWM_0X — NanoEdge eFlexPWM sub-module 0 output X or input capture
X only on WCT1001A.
PWM_FAULT6 — NanoEdge eFlexPWM fault input 6 only on WCT1001A.
GPIOF5 42 RXD1/XB_OUT
9/PWM_1X/PW
M_FAULT7
output pin.
RXD1 — The SCI1 receive data input.
XB_OUT9 — Crossbar module output 9.
PWM_1X — NanoEdge eFlexPWM sub-module 1 output X or input capture
X only on WCT1001A.
PWM_FAULT7 — NanoEdge eFlexPWM fault input 7 only on WCT1001A.
VSS2
43
-
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32 Freescale Semiconductor
VDD2
44
-
GPIOE0 45 PWM_0B
or output pin .
PWM_0B — NanoEdge eFlexPWM sub-module 0 output B or input capture
B.
GPIOE1 46 PWM_0A
or output pin.
PWM_0A — NanoEdge eFlexPWM sub-module 0 output A or input capture
A.
GPIOE2 47 PWM_1B
or output pin.
PWM_1B — NanoEdge eFlexPWM sub-module 1 output B or input capture
B.
GPIOE3 48 PWM_1A
or output pin.
PWM_1A — NanoEdge eFlexPWM sub-module 1 output A or input capture
A.
GPIOC13 49 TA3/XB_IN6/
EWM_OUT
or output pin.
TA3 — Quad timer module A channel 3 input/output.
XB_IN6 — Crossbar module input 6.
EWM_OUT — Ext ernal wat chdog monitor output.
GPIOF1 50 CLKO1/XB_IN7/
CMPD_O
output pin.
CLKO1 — This is a buffered clock output 1; the clock source is selected by
clock out select (CLKOSEL) bits in the clock output select register
(CLKOUT) of the SIM.
XB_IN7 — Crossbar module input 7.
CMPD_O — Analog comparator D output.
GPIOE4 51 PWM_2B/XB_I
N2
or output pin.
PWM_2B — NanoEdge eFlexPWM sub-module 2 output B or input capture
B.
XB_IN2 — Crossbar module input 2.
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Freescale Semiconductor 33
GPIOE5 52 PWM_2A/XB_I
N3
or output pin.
PWM_2A — NanoEdge eFlexPWM sub-module 2 output A or input capture
A.
XB_IN3 — Crossbar module input 3.
GPIOE6 53 PWM_3B/XB_I
N4
or output pin.
PWM_3B — NanoEdge eFlexPWM sub-module 3 output B or input capture
B.
XB_IN4 — Crossbar module input 4.
GPIOE7 54 PWM_3A/XB_I
N5
or output pin.
PWM_3A — NanoEdge eFlexPWM sub-module 3 output A or input capture
A.
XB_IN5 — Crossbar module input 5.
GPIOC14 55 SDA0/XB_OUT
4/PWM_FAULT
4
or output pin.
SDA0 — IIC0 serial data line.
XB_OUT4 — Crossbar module output 4.
PWM_FAULT4 — NanoEdge eFlexPWM fault input 4 only on WCT1001A.
GPIOC15 56 SCL0/XB_OUT
5/PWM_FAULT
5
or output pin.
SCL0 — IIC0 serial clo ck.
XB_OUT5 — Crossbar module output 5.
PWM_FAULT5 — NanoEdge eFlexPWM fault input 5 only on WCT1001A.
VCAP2 57 -
stabilize the core voltage regulator output required for proper device
GPIOF6 58 TB2/PWM_3X/X
B_IN2
output pin.
TB2 — Quad timer module B channel 2 input/output only on WCT1003A.
PWM_3X — NanoEdge eFlexPWM sub-module 3 output X or input capture
X.
XB_IN2 — Crossbar module input 2.
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34 Freescale Semiconductor
GPIOF7 59 TB3/CMPC_O/
SS1/XB_IN3
output pin.
TB3 — Quad timer module B channel 3 input/output only on WCT1003A.
CMPC_O— Analog comparator C output.
SS1 — SS1 is used in slave mode to indicate to the SPI1 module that the
current transfer is to be received.
XB_IN3 — Crossbar module input 3.
VDD3
60
-
VSS3
61
-
TDO 62 GPIOD1
data stream from the JT AG /E O nCE port. It is driven in the shift-IR and
shift-DR controll er states and changes on the falling edge of TC K.
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
TMS 63 GPIOD3
controller’s state machine. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Port D GPIO — This GPIO pin can be individually programmed as an input
or output pin.
After reset, the defa ult state is TMS.
NOTE: Always tie the TMS pin to VDD through a 2.2 kΩ resistor if need to
TDI 64 GPIOD0
JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an
on-chi p pull-up resistor.
Port D GPIO — This GPIO pin ca n be individually programmed as an input
or output pin.
4.5 Ordering Information
Table 10 lists the pertine nt information needed to place an or der. Consult a Freescale Semiconductor sales
office to determine availability and to order this device.
Table 10. MWCT100xAVLH Ordering Information
Device Supply Voltage Package Type Pin Count Ambient Temp. Order Number
MWCT1001AVLH 3.0 to 3.6V LQFP 64 -40 to +105℃ MWCT1001AVLH
MWCT1003AVLH 3.0 to 3.6V LQFP 64 -40 to +105℃ MWCT1003AVLH
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 35
4.6 Package Outline Drawing
To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document
number of 98ASS23234W.
5 Software Library
The software for WCT100xA is matured and tested for production ready. Freescale provides a Wireless
Charging Transmitter (WCT) software library for speeding user designs. In this library, low level drivers
of HAL (Hardware Abstract Layer), callback functions for library access are open to user. About the
software API and library details, see the WCT1001A/WCT1003A Transmitter Library User’s Guide
(WCT100XALIBUG).
5.1 Memory Map
WCT100xA has large on-chip Flash memory and RAM for user design. Besides wireless charging
transmitter library code, the user can develop private functions and link it to library through predefined
APIs.
Table 11. WCT100xA Memory Footprint (CodeWarrior V10.6, code size optimization level 4)
Part Memory Total Size Library Size FreeMASTER Size EEPROM Size Free Size
WCT1001A Flash 64 Kbytes 22.2 Kbytes 1.5 Kbytes 1 Kbytes 39.3 Kbytes
RAM 8 Kbytes 2.5 Kbytes 0.1 Kbytes 0 Kbytes 5.4 Kbytes
WCT1003A Flash 288 Kbytes 22.2 Kbytes 1.5 Kbytes 1 Kbytes 263.3 Kbytes
RAM 32 Kbytes 1.2 Kbytes 0.1 Kbytes 0 Kbytes 30.7 Kbytes
5.2 Software Library and API Description
For more and detailed information about WCT software library and API definition, see the
WCT1001A/WCT1003A Transmitter Library User’s Guide (WCT100XALIBUG).
6 Design Considerat ions
6.1 Electrical Design Considerations
To ensure correct operations on the device and system, pay attention to the following points:
• The minimum bypass requirement is to place 0.01 - 0.1μF capacitors positioned as near as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum
capacitors tend to provide better tolerances.
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
36 Freescale Semiconductor
• Bypass the VDD and VSS with approximately 10μF, plus the number of 0.1μF ceramic
capacitors.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VDDA and VSSA pins.
• It is recommended to use separate power planes for VDD and VDDA and use separate ground
planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as
near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the
same power supply, you should connect a small inductor or ferrite bead in serial with VDDA trace.
• If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the
range of 4.7 kΩ – 10 kΩ; and the capacitor value should be in the range of 0.1μF – 4.7μF.
• Add a 2.2 kΩ external pull-up on the TMS pin of the JTAG port to keep device in a restate during
normal operation if JTAG converter is not present.
• During reset and afte r reset but bef ore I/O initia lization, all I /O pins are at input mode with internal
weak pull-up.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than 33pF/10 Ω
RC filter.
• To assure chip reliable operation, reserve enough margin for chip electrical design. Figure 6 shows
the relationship between electrical ratings and electrical operating characteristics for correct chip
operation.
Electrical operating characteristics (min.)
Electrical operating characteristics (max.)
Fatal range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Normal operating range
Expected permanent failure
- No permanent failure
- Correct operation
Degraded operating range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Degraded operating range Fatal range
Expected permanent failure
Electrical rating (min.)
Electrical rating (max.)
∞−
∞+
Operating (power on)
Fatal range Handling range
Expected permanent failure
No permanent failure
Fatal range
Expected permanent failure
Handling rating (min.)
Handling rating (max.)
∞−
∞+
Handling (power off)
Figure 5. Relationship between Ratings and Operating Characteristics
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 37
6.2 PCB Layout Considerations
• Provide a low-impedance path from the board power supply to each VDD pin on the device and
from the board ground to each VSS pin.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS pins are as short as possible.
• PCB trace lengths should be minimal for high-frequency signals.
• Physically separate analog components from noisy digital components by ground planes. Do not
place an analog trace in parallel with digital traces. Place an analog ground trace around an analog
signal trace to isolate it from digital traces.
• The decoupling capacitors of 0.1μF must be placed on the VDD pins as close as possible, and
place those ceramic capacitors on the same PCB layer with WCT100xA device. VIA is not
recommend between the VDD pins and decoupling capacitors.
• The WCT100xA bottom EP pad should be soldered to the ground plane, which will make the
system more stable, and VIA matrix method can be used to connect this pad to the ground plane.
• As the wireless charging system functions as a switching-mode power supply, the power
components layout is very important for the whole system power transfer efficiency and EMI
performance. The power routing loop should be as small and short as possible. Especially for the
resonant network, the traces of this circuit should be short and wide, and the current loop should be
optimized smaller for the MOSFETs, resonant capacitor and primary coil. Another important thing
is that the control circuit and power circuit should be separated.
6.3 Thermal Design Conside rations
WCT100xA power consumption is not so critical, so there is not additional part needed for power
dissipation. However, the power inverter needs the additional PCB Cu copper to dissipate the heat, so
good thermal package MOSFET is recommended, such as DFN package, and for the resonant capacitor,
C0G material, and 1206 or 1210 package are recommended to meet the thermal requirement. The worst
thermal case is on the inverter, so the user should make some special actions to dis sipate the heat for good
transmitter system thermal performance.
7 References and Lin ks
7.1 References
• WCT1001A/WCT1003A Automotive A13 Wireless Charging Application User’s Guide
(WCT100XAWCAUG)
• WCT1001A/WCT1003A Transmitter Library User’s Guide (WCT100XALIBUG)
• WCT1001A/WCT1003A Run-Time Debug User’s Guide (WCT100XARTDUG)
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
38 Freescale Semiconductor
• WPC Low Power Wireless Transfer System Description Part 1: Interface Definition Version 1.1
7.2 Useful Links
• freescale.com
• freescale.com\wirelesscharging
• www.wirelesspowerconsortium.com
Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014
Freescale Semiconductor 39
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
informa tio n in this document.
Freescale reserves the right to make changes without further notice to any products herein.
Freescale makes no warranty, representation, or guarantee regarding the suitability of its
products for any particular purpose, nor does Freescale assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters that
may be provided in Freescale data sheets and/or specifications can and do vary in different
applications, and actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by customer’s
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Document Number: WCT100XADS
Rev. 1.0
08/2014
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