Precision Rail-to-Rail
Input and Output Operational Amplifiers
OP184/OP284/OP484
Rev. J
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FEATURES
Single-supply operation
Wide bandwidth: 4 MHz
Low offset voltage: 65 μV
Unity-gain stable
High slew rate: 4.0 V/ μs
Low noise: 3.9 nV/√Hz
APPLICATIONS
Battery-powered instrumentation
Power supply control and protection
Telecommunications
DAC output amplifier
ADC input buffer
GENERAL DESCRIPTION
The OP184/OP284/OP484 are single, dual, and quad single-supply,
4 MHz bandwidth amplifiers featuring rail-to-rail inputs and
outputs. They are guaranteed to operate from 3 V to 36 V (or
±1.5 V to ±18 V).
These amplifiers are superb for single-supply applications requiring
both ac and precision dc performance. The combination of wide
bandwidth, low noise, and precision makes the OP184/OP284/
OP484 useful in a wide variety of applications, including filters
and instrumentation.
Other applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection,
and use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The OP184/OP284/OP484 are specified over the hot extended
industrial temperature range of −40°C to +125°C. The single
OP184 is available in 8-lead SOIC surface mount packages. The
dual OP284 is available in 8-lead PDIP and SOIC surface mount
packages. The quad OP484 is available in 14-lead PDIP and
14-lead, narrow-body SOIC packages.
PIN CONFIGURATIONS
1
2
3
4
OUT A
V+
DNC
NC
DNC
–IN A
+IN A
V–
8
7
6
5
NOTES
1. NC = NO CONNE CT
2. DNC = DO NOT CONNE CT
+
00293-001
TOP VI EW
(No t t o Scale)
OP184
Figure 1. 8-Lead SOIC (S-Suffix)
00293-002
1
2
3
4
8
7
6
5
OUT B
–IN B
+IN B
V+
OUT A
–IN A
+IN A
V–
OP284
TOP VIEW
(Not t o Scal e)
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP484
TOP VI EW
(No t t o Scale)
00293-003
Figure 3. 14-Lead PDIP (P-Suffix)
14-Lead Narrow-Body SOIC (S-Suffix)
Table 1. Low Noise Op Amps
Voltage Noise 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.2 nV 3.8 nV 3.9 nV
Single AD797 AD8597 ADA4004-1 AD8675/ADA4075-2 OP27 AD8671 OP184
Dual AD8599 ADA4004-2 AD8676 OP270 AD8672 OP284
Quad ADA4004-4 OP470 AD8674 OP484
OP184/OP284/OP484
Rev. J | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 14
Functional Description .............................................................. 14
Input Overvoltage Protection ................................................... 14
Output Phase Reversal ............................................................... 15
Designing Low Noise Circuits in Single-Supply Applications
....................................................................................................... 15
Overdrive Recovery ................................................................... 16
Single-Supply, 3 V Instrumentation Amplifier ...................... 16
2.5 V Reference from a 3 V Supply .......................................... 17
5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 17
High-Side Current Monitor ...................................................... 18
Capacitive Load Drive Capability ............................................ 18
Low Dropout Regulator with Current Limiting ..................... 19
3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 23
REVISION HISTORY
4/11—Rev. I to Rev J
Change to Figure 27 ....................................................................... 10
10/10Rev. H to Rev I
Change to Output Characteristics, Output Voltage High
Parameter, Table 2 ............................................................................. 3
Change to Output Characteristics, Output Voltage High
Parameter, Table 3 ............................................................................. 4
7/10Rev. G to Rev. H
Added Table 1 .................................................................................... 1
2/09Rev. F to Rev. G
Change to Large Signal Voltage Gain, Table 3 .............................. 5
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/08Rev. E to Rev. F
Changes to General Description .................................................... 1
Changes to Figure 4 .......................................................................... 6
Changes to Low Dropout Regulator with Current Limiting .... 20
7/08Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
Changes to Figure 12 ........................................................................ 8
Changes to Figure 36 and Figure 37 ............................................. 12
Changes to Designing Low Noise Circuits in Single-Supply
Applications Section ....................................................................... 15
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
4/06Rev. C to Rev. D
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 4
Changes to Table 3 ............................................................................. 5
Deleted Reference to 1993 System Applications Guide .............. 15
3/06Rev. B to Rev. C
Changes to Figure 1 Caption............................................................ 1
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 4
Changes to Table 3 ............................................................................. 5
Changes to Table 4 ............................................................................. 6
Changes to Figure 5 through Figure 9 ............................................ 7
Changes to Functional Description Section ............................... 14
Deleted SPICE Macro Model ........................................................ 21
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/02Rev. A to Rev. B
Changes to Pin Configurations ....................................................... 1
Changes to Specifications, Input Bias Current Maximum .......... 2
Changes to Ordering Guide ............................................................. 5
Updated Outline Dimensions ....................................................... 19
6/02Rev. 0 to Rev. A
10/96Revision 0: Initial Version
OP184/OP284/OP484
Rev. J | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1VOS 65 μV
40°C ≤ TA ≤ +125°C 165 μV
Offset Voltage, OP184/OP284F Grade1 VOS 125 μV
40°C ≤ TA ≤ +125°C 350 μV
Offset Voltage, OP484E Grade1 VOS 75 μV
40°C ≤ TA ≤ +125°C 175 μV
Offset Voltage, OP484F Grade1 VOS 150 μV
40°C ≤ TA ≤ +125°C 450 μV
Input Bias Current IB 60 450 nA
40°C ≤ TA ≤ +125°C 600 nA
Input Offset Current IOS 2 50 nA
40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 60 dB
VCM = 1.0 V to 4.0 V, −40°C ≤ T
A ≤ +125°C 86 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, 1 V ≤ VO 4 V 50 240 V/mV
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 25 V/mV
Bias Current Drift ΔIB/ΔT 150 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1.0 mA 4.80 V
Output Voltage Low VOL IL = 1.0 mA 125 mV
Output Current IOUT ±6.5 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.0 V to 10 V, −40°C TA ≤ +125°C 76 dB
Supply Current/Amplifier ISY VO = 2.5 V, −40°C ≤ TA ≤ +125°C 1.45 mA
Supply Voltage Range VS 3 36 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 k 1.65 2.4 V/µs
Settling Time tS To 0.01%, 1.0 V step 2.5 µs
Gain Bandwidth Product GBP 3.25 MHz
Phase Margin ΦM 45 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.3 μV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
Current Noise Density in 0.4 pA/√Hz
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
OP184/OP284/OP484
Rev. J | Page 4 of 24
VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1 VOS 65 μV
40°C ≤ TA ≤ +125°C 165 μV
Offset Voltage, OP184/OP284F Grade1 VOS 125 μV
40°C ≤ TA ≤ +125°C 350 μV
Offset Voltage, OP484E Grade1 VOS 100 μV
40°C ≤ TA ≤ +125°C 200 μV
Offset Voltage, OP484F Grade1 VOS 150 μV
40°C ≤ TA ≤ +125°C 450 μV
Input Bias Current IB 60 450 nA
40°C ≤ TA ≤ +125°C 600 nA
Input Offset Current IOS 40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 60 dB
VCM = 0 V to 3 V, −40°C ≤ T
A ≤ +125°C 56 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1.0 mA 2.80 V
Output Voltage Low VOL IL = 1.0 mA 125 mV
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±1.25 V to ±1.75 V 76 dB
Supply Current/Amplifier ISY VO = 1.5 V, −40°C ≤ TA +125°C 1.35 mA
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP 3 MHz
NOISE PERFORMANCE
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
OP184/OP284/OP484
Rev. J | Page 5 of 24
VS = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1 VOS 100 μV
40°C ≤ TA ≤ +125°C 200 μV
Offset Voltage, OP184/OP284F Grade1 VOS 175 μV
40°C ≤ TA ≤ +125°C 375 μV
Offset Voltage, OP484E Grade1 VOS 150 μV
40°C ≤ TA ≤ +125°C 300 μV
Offset Voltage, OP484F Grade1 VOS 250 μV
40°C ≤ TA ≤ +125°C 500 μV
Input Bias Current IB 80 450 nA
40°C ≤ TA ≤ +125°C 575 nA
Input Offset Current IOS 40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −15 +15 V
Common-Mode Rejection Ratio CMRR VCM = −14.0 V to +14.0 V, −40°C ≤ TA ≤ +125°C 86 90 dB
VCM = −15.0 V to +15.0 V 80 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, −10 V ≤ VO 10 V 150 1000 V/mV
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 75 V/mV
Offset Voltage Drift E Grade ΔVOS/ΔT 0.2 2.00 μV/°C
Bias Current Drift ΔVB/ΔT 150 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1.0 mA 14.8 V
Output Voltage Low VOL IL = 1.0 mA 14.875 V
Output Current IOUT ±10 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.0 V to ±18 V, 40°C ≤ T
A ≤ +125°C 90 dB
Supply Current/Amplifier ISY VO = 0 V, −40°C ≤ TA ≤ +125°C 2.0 mA
Supply Current/Amplifier ISY VS = ±18 V, −40°C ≤ TA ≤ +125°C 2.25 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 k 2.4 4.0 V/µs
Full-Power Bandwidth BWp 1% distortion, RL = 2 kΩ, VO = 29 V p-p 35 kHz
Settling Time tS To 0.01%, 10 V step 4 µs
Gain Bandwidth Product GBP 4.25 MHz
Phase Margin ΦM 50 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.3 µV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
Current Noise Density in 0.4 pA/√Hz
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
OP184/OP284/OP484
Rev. J | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage ±18 V
Input Voltage ±18 V
Differential Input Voltage1 ±0.6 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range
P-Suffix, S-Suffix Packages −65°C to +150°C
Operating Temperature Range
OP184/OP284/OP484E/OP484F −40°C to +125°C
Junction Temperature Range
P-Suffix, S-Suffix Packages −65°C to +150°C
Lead Temperature
(Soldering 60 sec)
300°C
1 For input voltages greater than 0.6 V, the input current should be limited to
less than 5 mA to prevent degradation or destruction of the input devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device in socket for PDIP. θJA is specified for a
device soldered in the circuit board for SOIC packages.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
8-Lead PDIP (P-Suffix) 103 43 °C/W
8-Lead SOIC (S-Suffix) 158 43 °C/W
14-Lead PDIP (P-Suffix) 83 39 °C/W
14-Lead SOIC (S-Suffix) 92 27 °C/W
ESD CAUTION
R3
Q1
–IN +IN
QL1
QL2
Q4
Q3 Q2
QB5
QB6
RB2 QB3
R1
Q5
R2
QB4
JB2
QB1
N+CB1
P+M
QB2
CC1
Q9
Q7
Q11 Q8
Q6
Q10
Q12
QB7 QB8
QB9
RB1
JB1
TP
R4
R5
R6
RB3
FFC
R7
R8
Q13 Q14
R10
Q15
RB4
QB10 CC2
CO
Q17
Q16
R11
Q18
V
CC
OUT
V
EE
R9
00293-004
Figure 4. Simplified Schematic
OP184/OP284/OP484
Rev. J | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (µV)
QUANTITY
300
0
270
180
90
60
30
240
210
120
150
–100 –75 –50 –25 025 50 75 100
00293-005
V
S
= 3V
T
A
= 25° C
V
CM
= 1.5V
Figure 5. Input Offset Voltage Distribution
00293-006
INPUT OFFSET VOLTAGE (µV)
QUANTITY
300
0
270
180
90
60
30
240
210
120
150
–100 –75 –50 –25 025 50 75 100
V
S
= 5V
T
A
= 25° C
V
CM
= 2.5V
Figure 6. Input Offset Voltage Distribution
00293-007
INPUT OFFSET VOLTAGE (µV)
QUANTITY
200
0
175
100
75
50
25
150
125
–125 –100 –75 –50 –25 025 10050 75 125
VS= ±15V
TA= 25° C
Figure 7. Input Offset Voltage Distribution
300
250
200
150
100
50
000.25 0.50 0.75 1.00 1.25 1.50
QUANTITY
OFFSET VOLTAGE DRIFT, TCV
OS
(µV/°C)
00293-008
V
S
= 5V
–40°C ≤ T
A
≤ +125°C
Figure 8. Input Offset Voltage Drift Distribution
300
250
200
150
100
50
000.25 0.50 0.75 1.00 1.25 1.50
QUANTITY
OFFSET VOLTAGE DRIFT, TCV
OS
(µV/°C)
00293-009
V
S
= ±15V
–40°C ≤ T
A
≤ +125°C
Figure 9. Input Offset Voltage Drift Distribution
–40
–45
–50
–55
–60
–65
–70
–75
–80
–40 25 85 125
VCM = VS/2
VS = +5V
VS = ±15V
INP UT BIAS CURRE NT (n A)
TEMPERATURE (°C)
00293-010
Figure 10. Bias Current vs. Temperature
OP184/OP284/OP484
Rev. J | Page 8 of 24
500
–500
–400
–300
–200
–100
0
100
200
300
400
–15 –10 –5 0 5 10 15
INP UT BIAS CURRE NT (n A)
COMMON-MODE VOLT AGE (V)
00293-011
VS = ±15V
Figure 11. Input Bias Current vs. Common-Mode Voltage
1000
10
100
0.01 0.1 110
OUTPUT VOLTAGE (mV)
LOAD CURRENT ( mA)
00293-012
SOURCE
SINK
VS = ±15V
Figure 12. Output Voltage to Supply Rail vs. Load Current
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
–40 25 85 125
SUPP LY CURRENT /AMPLIFIER ( mA)
TEMPERATURE (°C)
00293-013
VS = ±15V
VS = +5V
VS = +3V
Figure 13. Supply Current vs. Temperature
1.50
1.25
1.00
0.75
0.50
0.25
00±2.5 ±5.0 ±7.5 ±10.0 ±12.5 ±15.0 ±17.5 ±20.0
SUPP LY CURRENT /PER AM P LIFIER ( mA)
SUPPLY VOLT AGE (V)
00293-014
T
A
= 25° C
Figure 14. Supply Current vs. Supply Voltage
50
40
30
20
10
0
–50 –25 025 50 75 100 125
SHO RT-CIRCUIT CURRE NT (mA)
TEMPERATURE (°C)
00293-015
VS = ±15V
+ISC
–ISC
+ISC
–ISC
VS = +5V, VCM = +2. 5V
Figure 15. Short-Circuit Current vs. Temperature
70
60
50
40
30
20
10
0
–10
–20
–30
0
45
90
135
180
225
270
10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE S HIFT ( Degrees)
FRE QUENCY (Hz )
00293-016
VS = 5V
TA = 25° C
NO LOAD
Figure 16. Open-Loop Gain and Phase vs. Frequency (No Load)
OP184/OP284/OP484
Rev. J | Page 9 of 24
70
60
50
40
30
20
10
0
–10
–20
–30
0
45
90
135
180
225
270
10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE S HIFT ( Degrees)
FRE QUENCY (Hz )
00293-017
VS = 3V
TA = 25° C
NO LOAD
Figure 17. Open-Loop Gain and Phase vs. Frequency (No Load)
70
60
50
40
30
20
10
0
–10
–20
–30
0
45
90
135
180
225
270
10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE S HIFT ( Degrees)
FRE QUENCY (Hz )
00293-018
VS = ±15V
TA = 25° C
NO LOAD
Figure 18. Open-Loop Gain and Phase vs. Frequency (No Load)
2500
2000
1500
1000
500
0
–50 1251007550250–25
OPEN-LOO P G AIN (V/mV)
TEMPERATURE (°C)
00293-019
VS = ±15V
–10V < VO < +10V
RL = 2k
VS = +5V
+1V < VO < +10V
RL = 2k
Figure 19. Open-Loop Gain vs. Temperature
60
50
40
30
20
10
0
–10
–20
–40
–30
10 1k 100k 10M100 10k 1M
CLOSED-LOOP GAIN (dB)
FRE QUENCY (Hz )
00293-020
VS = 5V
RL = 2k
TA = 25° C
Figure 20. Closed-Loop Gain vs. Frequency (2 kΩ Load)
60
50
40
30
20
10
0
–10
–20
–40
–30
10 1k 100k 10M100 10k 1M
CLOSED-LOOP GAIN (dB)
FRE QUENCY (Hz )
00293-020
VS = ±15V
RL = 2k
TA = 25° C
Figure 21. Closed-Loop Gain vs. Frequency (2 kΩ Load)
60
50
40
30
20
10
0
–10
–20
–40
–30
10 1k 100k 10M100 10k 1M
CLOSED-LOOP GAIN (dB)
FRE QUENCY (Hz )
00293-020
VS = 3V
RL = 2k
TA = 25° C
Figure 22. Closed-Loop Gain vs. Frequency (2 kΩ Load)
OP184/OP284/OP484
Rev. J | Page 10 of 24
300
270
240
210
180
150
120
90
60
0
30
10 1k 100k 10M100 10k 1M
OUTPUT IMPE DANCE ( Ω)
FRE QUENCY (Hz )
00293-023
VS = 5V
TA = 25° C
AV = +100
AV = +10
AV = +1
Figure 23. Output Impedance vs. Frequency
300
270
240
210
180
150
120
90
60
0
30
10 1k 100k 10M100 10k 1M
OUTPUT IMPE DANCE ( Ω)
FRE QUENCY (Hz )
00293-024
VS = 15V
TA = 25° C
AV = +100 AV = +10
AV = +1
Figure 24. Output Impedance vs. Frequency
300
270
240
210
180
150
120
90
60
0
30
10 1k 100k 10M100 10k 1M
OUTPUT IMPE DANCE ( Ω)
FRE QUENCY (Hz )
00293-025
VS = 3V
TA = 25° C AV = +100
AV = +10
AV = +1
Figure 25. Output Impedance vs. Frequency
5
4
3
2
1
01k 100k 10M10k 1M
MAXIMUM OUTPUT SWING (V p -p )
FRE QUENCY (Hz )
00293-026
V
S
= 5V
V
IN
= 0.5V TO 4.5V
R
L
= 2k
T
A
= 25° C
Figure 26. Maximum Output Swing vs. Frequency
30
25
20
15
10
5
01k 100k 10M10k 1M
VOUT (V)
FRE QUENCY (Hz )
00293-027
V
S
= ±15V
V
IN
= ±14V
R
L
= 2k
T
A
= 25° C
Figure 27. Maximum Output Swing vs. Frequency
180
160
140
120
100
80
60
40
20
0
–2010 100k 10M1k100 10k 1M
CMRR (dB)
FRE QUENCY (Hz )
00293-028
V
S
= ±15V
V
S
= +5V
V
S
= +3V
T
A
= 25° C
Figure 28. CMRR vs. Frequency
OP184/OP284/OP484
Rev. J | Page 11 of 24
160
140
120
100
80
60
40
20
0
–40
–20
10 100k 10M1k100 10k 1M
PSRR ( dB)
FRE QUENCY (Hz )
00293-029
V
S
= ±15V
V
S
= +5V
V
S
= +3V
T
A
= 25° C
Figure 29. PSRR vs. Frequency
80
70
60
50
40
30
20
10
010 1000100
OVERSHOOT (%)
CAPACITIVE LOAD (pF)
00293-030
+OS
–OS
V
S
= ±2. 5V
T
A
= 25° C, A
VCL
= 1
V
IN
= ±50mV
Figure 30. Small Signal Overshoot vs. Capacitive Load
7
6
5
4
3
2
1
0
–50 –25 025 50 75 100 125
SLEW RATE (V/µs)
TEMPERATURE (°C)
00293-031
V
S
= ±15V
R
L
= 2k
V
S
= ±5V
R
L
= 2k
+SL E W RATE
–SL E W RATE
+SL E W RATE
–SL E W RATE
Figure 31. Slew Rate vs. Temperature
30
25
20
15
10
5
0110 100 1000
NOISE DENSITY (nV/ Hz)
FRE QUENCY (Hz )
00293-032
±2.5V ≤ V
S
≤ ±15V
T
A
= 25° C
Figure 32. Voltage Noise Density vs. Frequency
10
8
6
4
2
0110 100 1000
CURRENT NOISE DE NS ITY ( pA/ Hz )
FRE QUENCY (Hz )
00293-033
±2.5V ≤ V
S
≤ ±15V
T
A
= 25° C
Figure 33. Current Noise Density vs. Frequency
5
4
3
2
1
–5
–4
–3
–2
–1
0
0 654321
STEP SIZ E (V)
SETTLING TIME (µs)
00293-034
V
S
= 5V
T
A
= 25° C
0.1% 0.01%
Figure 34. Step Size vs. Settling Time
OP184/OP284/OP484
Rev. J | Page 12 of 24
10
8
6
4
2
–10
–8
–6
–4
–2
0
0 654321
STEP SIZ E (V)
SETTLING TIME (µs)
00293-035
V
S
= ±15V
T
A
= 25° C
0.1% 0.01%
Figure 35. Step Size vs. Settling Time
0.3
0.2
0.1
0
–0.1
–0.2
–0.3–5 –4 –3 –2 –1 0 1 2 3 4 5
TIME
NOISE (µV)
00293-036
V
S
= ±2. 5V
A
V
= 10M
Figure 36. 0.1 Hz to 10 Hz Noise
0.3
0.2
0.1
0
–0.1
–0.2
–0.3–5 –4 –3 –2 –1 0 1 2 3 4 5
TIME
NOISE (µV)
00293-037
V
S
= ±15V
A
V
= 10M
Figure 37. 0.1 Hz to 10 Hz Noise
160
140
120
100
80
–40
–20
0
20
40
60
100 10M1M100k10k1k
CHANNEL S E P ARATIO N ( dB)
FRE QUENCY (Hz )
00293-038
T
A
= 25° C
V
S
= ±15V
V
S
= +3V
Figure 38. Channel Separation vs. Frequency
00293-039
V
S
= 5V
A
V
= +1
R
L
= OPEN
C
L
= 300pF
T
A
= 25° C
1µs
100
90
10
0%
100mV
400mV
0V
Figure 39. Small Signal Transient Response
00293-040
VS = 5V
AV = +1
RL = 2k
CL = 300pF
TA = 25° C
1µs
100
90
10
0%
100mV
400mV
0V
Figure 40. Small Signal Transient Response
OP184/OP284/OP484
Rev. J | Page 13 of 24
00293-041
VS = ±1. 5V
AV = +1
NO LOAD
TA = 25° C
500ns
100
90
10
0%
100mV
+200mV
0V
–200mV
Figure 41. Small Signal Transient Response
00293-042
V
S
= ±0. 75V
A
V
= +1
NO LOAD
T
A
= 25° C
1µs
100
90
10
0%
100mV
+200mV
0V
–200mV
Figure 42. Small Signal Transient Response
0.1
0.0005
0.001
0.01
20 1k 20k100 10k
THD+N ( %)
FRE QUENCY (Hz )
00293-043
VO = ±0. 75V
VO = ±2. 5V
VO = ±1. 5V
AV = +1000
VS = ±2. 5V
RL = 2k
Figure 43. Total Harmonic Distortion + Noise vs. Frequency
OP184/OP284/OP484
Rev. J | Page 14 of 24
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The OP184/OP284/OP484 are precision single-supply, rail-to-rail
operational amplifiers. Intended for the portable instrumentation
marketplace, the OPx84 family of devices combine the attributes
of precision, wide bandwidth, and low noise to make them a superb
choice in single-supply applications that require both ac and
precision dc performance. Other low supply voltage appli-
cations for which the OP284 is well suited are active filters,
audio microphone preamplifiers, power supply control, and
telecommunications. To combine all of these attributes with
rail-to-rail input/output operation, novel circuit design techniques
are used.
D1
D2
Q4
V+
I1
Q3 2Q1Q
I2
V01
V02
–IN x
V–
+IN x
00293-044
R4
3k
R3
3k
R2
4k
R1
4k
Figure 44. OP284 Equivalent Input Circuit
For example, Figure 44 illustrates a simplified equivalent circuit
for the input stage of the OP184/OP284/OP484. It comprises
an NPN differential pair, Q1→Q2, and a PNP differential pair,
Q3→Q4, operating concurrently. Diode Network D1→Diode
Network D2 serves to clamp the applied differential input
voltage to the OP284, thereby protecting the input transistors
against avalanche damage. Input stage voltage gains are kept low
for input rail-to-rail operation. The two pairs of differential
output voltages are connected to the second stage of the OP284,
which is a compound folded cascade gain stage. It is also in the
second gain stage, where the two pairs of differential output
voltages are combined into a single-ended, output signal voltage
used to drive the output stage. A key issue in the input stage is
the behavior of the input bias currents over the input common-
mode voltage range. Input bias currents in the OP284 are the
arithmetic sum of the base currents in Q1→Q3 and in Q2→Q4.
As a result of this design approach, the input bias currents in
the OP284 not only exhibit different amplitudes; they also
exhibit different polarities. This effect is best illustrated by
Figure 10. It is, therefore, of paramount importance that the
effective source impedances connected to the OP284 inputs
be balanced for optimum dc and ac performance.
To achieve rail-to-rail output, the OP284 output stage design
employs a unique topology for both sourcing and sinking current.
This circuit topology is illustrated in Figure 45. The output stage
is voltage-driven from the second gain stage. The signal path
through the output stage is inverting; that is, for positive input
signals, Q1 provides the base current drive to Q6 so that it conducts
(sinks) current. For negative input signals, the signal path via
Q1→Q2→D1→Q4→Q3 provides the base current drive for Q5 to
conduct (source) current. Both amplifiers provide output current
until they are forced into saturation, which occurs at approxi-
mately 20 mV from the negative supply rail and 100 mV from
the positive supply rail.
00293-045
V+
I2
I1
Q1 Q3
Q4
Q2
V–
Q5
VOUT
Q6
R6R3
R2
R1
R4
R5
D1
INPUT FROM
SECOND GAI N
STAGE
Figure 45. OP284 Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the OP284 maximum output voltage swing. Output
short-circuit current limiting is determined by the maximum
signal current into the base of Q1 from the second gain stage.
Under output short-circuit conditions, this input current level
is approximately 100 µA. With transistor current gains around 200,
the short-circuit current limits are typically 20 mA. The output
stage also exhibits voltage gain. This is accomplished by the use
of common-emitter amplifiers, and, as a result, the voltage gain
of the output stage (thus, the open-loop gain of the device)
exhibits a dependence to the total load resistance at the output
of the OP284.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier could be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current. Figure 46 illustrates the
overvoltage I-V characteristic of the OP284. This graph was
generated with the supply pins connected to GND and a curve
tracer’s collector output drive connected to the input.