Rev. 0.2 / Dec. 2008 1
204pin DDR3 SDRAM SODIMMs
** Contents are subject to change without prior notice.
DDR3 SDRAM
Unbuffered SODIMMs
Based on 1Gb A version
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Rev. 0.2 / Dec. 2008 2
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Revision History
Revision No. History Draft Date Remark
0.01 Initial draft Sep. 2007 preliminary
0.02 Added IDD, corrected typos Mar. 2008 preliminary
0.03 Halogen-free added May. 2008 preliminary
0.1 Initial Specification Release May 2008
0.2 Added outline: DIMMs with thermal sensor.
Corrected typo on package ball feature. Dec. 2008
Rev. 0.2 / Dec. 2008 3
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
3.2 1GB, 128Mx64 Module(2Rank of x16)
3.3 2GB, 256Mx64 Module(2Rank of x8)
4. Absolute Maximum Ratings
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Range
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
5.2 DC & AC Logic Input Levels
5.2.1 For Single-ended Signals
5.2.2 For Differential Signals
5.2.3 Differential Input Cross Point
5.3 Slew Rate Definition
5.3.1 For Ended Input Signals
5.3.2 For Differential Input Signals
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
5.4.2 Differential DC & AC Output Levels
5.4.3 Single Ended Output Slew Rate
5.4.4 Differential Ended Output Slew Rate
5.5 Overshoot/Undershoot Specification
5.5.1 Address and Control Overshoot and Undershoot Specifications
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
5.6 Input/Output Capacitance & AC Parametrics
5.7 IDD Specifications & Measurement Conditions
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
6.2 DDR3 Standard speed bins and AC para
7. DIMM Outline Diagram
7.1 512MB, 64Mx64 Module(1Rank of x16)
7.2 1GB, 128Mx64 Module(2Rank of x16)
7.3 2GB, 256Mx64 Module(2Rank of x8)
Rev. 0.2 / Dec. 2008 4
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
1. Description
This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 1Gb A version. DDR3
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM
series based on 1Gb A version provide a high performance 8 byte interface in 67.60mm width form factor of industry
standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• VDDSPD=3.0V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7 , 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1 and CL-2 sup-
ported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8 banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 78ball
FBGA(x4/x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• 8 bit pre-fetch
Rev. 0.2 / Dec. 2008 5
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
1.1.2 Ordering Information
Two types, with integrated thermal sensor and with no thermal sensor, exist in each configuration.
Part Name Density Organization # of
DRAMs # of
ranks Materials
HMT164S6AFP6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 Lead free
HMT164S6AFR6C-S6/S5/G8/G7/ H9/H8 512MB 64Mx64 4 1 Halogen free
HMT112S6AFP6C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 2 Lead free
HMT112S6AFR6C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 2 Halogen free
HMT125S6AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Lead free
HMT125S6AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Halogen free
Rev. 0.2 / Dec. 2008 6
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
1.2 Speed Grade & Key Parameters
1.3 Address Table
MT/S DDR3-800 DDR3-1066 DDR3-1333 Unit
Grade -S6 -S5 -G8 -G7 -H9 -H8
tCK (min) 2.5 1.875 1.5 ns
CAS Latency 658798tCK
tRCD (min) 15 12.5 15 13.125 13.5 12 ns
tRP (min) 15 12.5 15 13.125 13.5 12 ns
tRAS (min) 37.5 37.5 37.5 37.5 36 36 ns
tRC (min) 52.5 50 52.5 50.625 49.5 48 ns
CL-tRCD-tRP 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 tCK
512MB 1GB 2GB
Organization 64M x 64 128M x 64 256M x 64
Refresh Method 8K/64ms 8K/64ms 8K/64ms
Row Address A0-A12 A0-A12 A0-A13
Column Address A0-A9 A0-A9 A0-A9
Bank Address BA0-BA2 BA0-BA2 BA0-BA2
Page Size 2KB 2KB 1KB
# of Rank 12 2
# of Device 48 16
Rev. 0.2 / Dec. 2008 7
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
2. Pin Architecture
2.1 Pin Definition
Pin Name Description Pin Name Description
CK[1:0] Clock Inputs, positive lin e 2 DQ[63:0] Data Input/Output 64
CK[1:0] Clock Inputs, negative line 2 DM[7:0] Data Masks 8
CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8
RAS Row Address Strobe 1 DQS[7:0] Data strobes complement 8
CAS Column Address Strobe 1 RESET Reset pin 1
WE Write Enable 1 TEST Logic Analyzer specific test pin (No
connect on SODIMM) 1
S[1:0] Chip Selects 2 EVENT Temperature event pin 1
A[9:0], A11,
A[15:13] Address Inputs 14 VDD Core and I/O power 18
A10/AP Address Input/Autoprecharge 1 VSS Ground 52
A12/BC Address Input/Burst Stop 1 VREFDQ Input/Output Reference 2
BA[2:0] SDRAM Bank Address 3 VREFCA
ODT[1:0] On-die termination control 2 VDDSPD SPD and Temp sensor power 1
SCL Serial Presence Detect (SPD) Clock
input 1 Vtt Termination voltage 2
SDA SPD Data Input/Output 1 NC Reserved for future use 2
SA[1:0] SPD address 2 Total 204
Rev. 0.2 / Dec. 2008 8
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
2.2 Input/Output Functional Description
Symbol Type Polarity Function
CK0/CK0
CK1/CK1Input Cross point
The system clock inputs. All address and comman d l ines are sampled on the cross
point of the rising edge of CK and f all ing edge of CK . A Dela y Locked Loop (DLL) cir-
cuit is driven from the clock inputs and output timing for read operations is synchro-
nized to the input clock.
CKE[1:0] Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Po wer Down mode or the Self
Refresh mode.
S[1:0] Input Active Low
Enables the associated DDR3 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new com-
mands are ignored but previous operations continue. Rank 0 is selected by S0; Rank
1 is selected by S1.
RAS, CAS, WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, sig-
nals CAS, RAS, and WE define the operation to be executed by the SDRAM.
BA[2:0] Input - Selects which DDR3 SDRAM internal bank of eight is activated.
ODT[1:0] Input Active High Assert s on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR3 SDRAM mode register.
A[9:0], A10/AP,
A11, A12/BC,
A[15:13] Input -
During a Bank Ac tivate command cycle, defines the row address when sampled at
the cross point of the rising edge of CK and falling edge of CK. During a Read or
Write c ommand cycle, def in e s t h e co lumn address when sampled at the cross point
of the rising edge of CK and falli ng edge of CK. In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be
precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to
precharge. If AP is high, all banks will be precharged reg ardless of the state o f BA0-
BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped)
DQ[63:0] In/Out - Data Input/Output pins.
DM[7:0] Input Active High The data write masks, associated wi th one data byte. In Write mode, DM operates
as a byte mask by allowing input d a ta to be written if it is low but blocks the write
operation if it is high. In Read mode, DM lines have no effect.
DQS[7:0],
DQS[7:0] In/Out Cross Point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, th e data str obe is sour ced by t he contr oller an d is cent er ed in the da ta
window . In R ead mode, the data stro be is sourced by the DDR3 SDRAMs and is sent
at the leading edge of the data window . DQS signals are complements, and timing is
relative to the crosspoint of respective DQS and DQS.
Rev. 0.2 / Dec. 2008 9
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
VDD,VDDSPD,
VSS, Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for
the module.
VREFDQ,
VREFCA Supply Reference voltage for SSTL 15 inputs.
SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and
Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the
system planar to act as a pull up.
SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA[1:0] Input Address pins used to select the Serial Presence Detect and Temp sensor base
address.
TEST In/Out The TEST pin is reserved f or bus analys is tools and is not conn ect e d on normal
memory modules (SO-DIMMs).
EVENT Wire OR
Out Active Low The EVENT pin is reserved for use to flag critical module temperature. A resistor
may be connected from EVENT bus line to VDDSPD on the system planar to act as a
pullup.
RESET In Active Low This signal resets the DDR3 SDR A M
Symbol Type Polarity Function
Rev. 0.2 / Dec. 2008 10
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
2.3 Pin Assignment
Pin
#Front
Side Pin
#Back
Side Pin
#Front
Side Pin
#Back
Side Pin
#Front
Side Pin
#Back
Side Pin
#Front
Side Pin
#Back
Side
1VREFDQ 2VSS 53 DQ19 54 VSS 105 VDD 106 VDD 157 DQ42 158 DQ46
3VSS 4
DQ4
55 VSS 56
DQ28
107
A10/AP
108
BA1
159
DQ43
160
DQ47
5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161 VSS 162 VSS
7DQ18VSS 59 DQ25 60 VSS 111 VDD 112 VDD 163 DQ48 164 DQ52
9VSS 10
DQS0
61 VSS 62
DQS3
113
WE
114
S0
165
DQ49
166
DQ53
11 DM0 12 DQS0 63 DM3 64 DQS3 115 CAS 116 ODT0 167 VSS 168 VSS
13 VSS 14 VSS 65 VSS 66 VSS 117 VDD 118 VDD 169
DQS6
170 DM6
15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 A132120 ODT1 171 DQS6 172 VSS
17
DQ3
18
DQ7
69
DQ27
70
DQ31
121
S1
122
NC
173 VSS 174
DQ54
19 VSS 20 VSS 71 VSS 72 VSS 123 VDD 124 VDD 175 DQ50 176 DQ55
21 DQ8 22 DQ12 73 CKE0 74 CKE1 125 TEST 126 VREFCA 177 DQ51 178 VSS
23
DQ9
24
DQ13
75 VDD 76 VDD 127 VSS 128 VSS 179 VSS 180
DQ60
25 VSS 26 VSS 77 NC 78 A152129 DQ32 130 DQ36 181 DQ56 182 DQ61
27
DQS1
28 DM1 79 BA2 80 A142131 DQ33 132 DQ37 183 DQ57 184 VSS
29
DQS1
30
RESET
81 VDD 82 VDD 133 VSS 134 VSS 185 VSS 186
DQS7
31 VSS 32 VSS 83 A12/BC 84 A11 135
DQS4
136 DM4 187 DM7 188 DQS7
33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138 VSS 189 VSS 190 VSS
35
DQ11
36
DQ15
87 VDD 88 VDD 139 VSS 140
DQ38
191
DQ58
192
DQ62
37 VSS 38 VSS 89 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63
39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144 VSS 195 VSS 196 VSS
41
DQ17
42
DQ21
93 VDD 94 VDD 145 VSS 146
DQ44
197
SA0
198
EVENT
43 VSS 44 VSS 95 A3 96 A2 147 DQ40 148 DQ45 199 VDDSPD 200 SDA
45
DQS2
46 DM2 97 A1 98 A0 149 DQ41 150 VSS 201 SA1 202 SCL
47
DQS2
48 VSS 99 VDD 100 VDD 151 VSS 152
DQS5
203
V
TT
204
V
TT
49 VSS 50 DQ22 101 CK0 102 CK1 153 DM5 154 DQS5
51 DQ18 52 DQ23 103 CK0 104 CK1 155 VSS 156 VSS
NC = No Connect; RFU = Reserved Future Use
1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be con-
nected to the termination resistor.
Rev. 0.2 / Dec. 2008 11
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
DQS1
DQS1
DM1
DQ [8:15]
DQS0
DQS0
DM0
DQ [0:7]
LDQS
LDQS
LDM
DQ [0:7]
D0
UDQS
UDQS
UDM
DQ [8:15]
A2
Temp Sensor
SDA
D0–D3
V
DD
SPD
SPD/TS
D0–D3
V
REF
CA
SCL
V
tt
D0–D3
V
DD
EVENT
RAS
CAS
S0
WE
CK0
CK0
CKE0
ODT0
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS3
DQS3
DM3
DQ [24:31]
DQS2
DQS2
DM2
DQ [16:23]
LDQS
LDQS
LDM
DQ [0:7]
D1
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS5
DQS5
DM5
DQ [40:47]
DQS4
DQS4
DM4
DQ [32:39]
LDQS
LDQS
LDM
DQ [0:7]
D2
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS7
DQS7
DM7
DQ [56:63]
DQS6
DQS6
DM6
DQ [48:55]
LDQS
LDQS
LDM
DQ [0:7]
D3
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
Vtt Vtt
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VDD
A1
A0
SCL
SA0
SA1 (with SPD)
EVENT
A2 SDA
SCL
WP
A1
A0
SCL
SA0
SA1 (SPD)
V
tt
V
REF
DQ
V
SS
CK0
CK0
CK1
CK1
ODT1
S1
EVENT
RESET
D0–D3, SPD, Temp sensor
D0–D3
D0–D3
Terminated at near
card edge
NC
NC
Temp Sensor
D0-D3
D0 D1 D2 D3
Vtt
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS relation-
ships are maintained as shown
Address and Control Lines
Rank 0
The SPD may be
integrated with the T emp
Sensor or may be
a separate component
Rev. 0.2 / Dec. 2008 12
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
3.2 1GB, 128Mx64 Module(2Rank of x16)
DQS1
DQS1
DM1
DQ [8:15]
DQS0
DQS0
DM0
DQ [0:7]
LDQS
LDQS
LDM
DQ [0:7]
D0
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
S0
WE
CK0
CK0
CKE0
ODT0
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS3
DQS3
DM3
DQ [24:31]
DQS2
DQS2
DM2
DQ [16:23]
LDQS
LDQS
LDM
DQ [0:7]
D1
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS5
DQS5
DM5
DQ [40:47]
DQS4
DQS4
DM4
DQ [32:39]
LDQS
LDQS
LDM
DQ [0:7]
D2
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
DQS7
DQS7
DM7
DQ [56:63]
DQS6
DQS6
DM6
DQ [48:55]
LDQS
LDQS
LDM
DQ [0:7]
D3
UDQS
UDQS
UDM
DQ [8:15]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm
ZQ +/-1%
Vtt
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VDD
LDQS
LDQS
LDM
DQ [0:7]
D4
UDQS
UDQS
UDM
DQ [8:15]
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D5
UDQS
UDQS
UDM
DQ [8:15]
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D6
UDQS
UDQS
UDM
DQ [8:15]
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D7
UDQS
UDQS
UDM
DQ [8:15]
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
CK1
CK1
CKE1
ODT1
S1
VDD
A2
Temp Sensor
SDA
D0–D7
V
DD
SPD
SPD/TS
D0–D7
V
REF
CA
SCL
V
tt
D0–D7
V
DD
EVENT
A1
A0
SCL
SA0
SA1 (with SPD)
EVENT
A2 SDA
SCL
WP
A1
A0
SCL
SA0
SA1 (SPD)
V
tt
V
REF
DQ
V
SS
CK0
CK0
CK1
CK1
EVENT
RESET
D0–D7, SPD, Temp sensor
D0–D3
D0–D7
Temp Sensor
D0-D7
NOTES
1. DQ wiring may differ from that shown
however, DQ , DM, DQS , and DQS relation-
ships are maintained as shown
Address and Control Lines
Rank 0
The SPD may be
integrated with the T emp
Sensor or may be
a separate component
D0–D3
D0–D7
D0 D1 D2 D3
Vtt
D4 D5 D6 D7
Vtt
V1 V2 V4V3
V1 V2 V4V3
Rank 1
Vtt Vtt
Rev. 0.2 / Dec. 2008 13
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
3.3 2GB, 256Mx64 Module(2Rank of x8)
DQS3
DQS3
DM3
DQ[24:31]
DQS
DQS
DM
DQ [0:7]
D11
RAS
CAS
S1
WE
CK1
CK1
CKE1
ODT1
A[O:N]/BA[O:N]
240ohm
ZQ
+/-1%
Vtt
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D3
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
CK0
CK0
CKE0
ODT0
S0
A2
Temp Sensor
SDA
D0–D15
V
DD
SPD
SPD/TS
D0–D15
V
REF
CA
SCL
V
tt
D0–D15
V
DD
EVENT
A1
A0
SCL
SA0
SA1 (with SPD)
EVENT
A2 SDA
SCL
WP
A1
A0
SCL
SA0
SA1 (SPD)
V
tt
V
REF
DQ
V
SS
CK0
CK0
CK1
CK1
CKE0
CKE1
D0–D15, SPD, Temp sensor
D0–D7
D8–D15
D0-D7
D8-D15
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS
relationships are maintained as shown
Rank 0
D0–D7
D8–D15
Rank 1
DQS1
DQS1
DM1
DQ[8:15]
DQS
DQS
DM
DQ [0:7]
D1
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D9
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS0
DQS0
DM0
DQ[0:7]
DQS
DQS
DM
DQ [0:7]
D0
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D8
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:43]
DQS5
DQS5
DM5
DQ[40:47]
Vtt Vtt
VDD VDD
Cterm Cterm
D12
D4
DQS
DQS
DM
DQ [0:7]
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
D6
D14
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
D7
D15
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
DQS2
DQS2
DM2
DQ[6:23]
DQS
DQS
DM
DQ [0:7]
D2
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D10
240ohm
ZQ +/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
D5
D13
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
S0
ODT0
S1
ODT1
EVENT
RESET
D0–D7
D8–D15
Temp Sens or
D0-D15
D0–D7
D8–D15
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
D0
V1
V9
D1 D11
D2 D13
D4 D14
D15
D9
D8 D10
D3 D12
D5 D7
D6
Vtt
V1V2
V3
V4 V5 V6
V8 V7
V6
V8
V7
V5
V9V1
V4
V3
V2
Rev. 0.2 / Dec. 2008 14
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
4. ABSOLUTE MAXIMUM RATINGS
4.1 Absolute Maximum DC Ratings
4.2 DRAM Component Operating Temperature Range
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VIN, VOUT Volt age on any pin relative to Vss - 0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 ℃℃1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Symbol Parameter Rating Units Notes
TOPER Normal Temperature Range 0 to 85 ℃,2
Extended Temperature Range 85 to 95 ℃1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.
For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating
conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and
95°… case temperature.
Full specifications are guaranteed in this r ange, but the following additiona l conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
(This double refresh requirement may not apply for some devices.) It is also possible to specify a component
with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/
or the DIMM SPD for option avail ability.
b) If Self-Refresh operation is required in the Extended Temperature Range , than it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or
enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 0.2 / Dec. 2008 15
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
5.2 DC & AC Logic Input Levels
5.2.1 DC & AC Logic Input Levels for Single-Ended Signals
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure
6.2.1. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ like-
wise).VRef(DC) is the linear a v er age of VR e f (t) ov er a very long per iod of time (e.g. 1 sec). This av erage has to meet
the min/max requirements in Table 1. Furthermore VRef (t) may tem porarily deviate fr om VRef (DC) by no more than
+/- 1% VDD.
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.500 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD bad VDDQ tied together.
Symbol Parameter DDR3-800, DDR3-1066, DDR3-1333 Unit Notes
Min Max
VIH(DC) DC input logic high Vref + 0.100 - V 1, 2
VIL(DC) DC input logic low Vref - 0.100 V 1, 2
VIH(AC) AC input logic high Vref + 0.175 - V 1, 2
VIL(AC) AC input logic low Vref - 0.175 V 1, 2
VRefDQ (DC) Ref er ence Voltage for
DQ, DM inputs 0.49 * VDD 0.51 * VDD V 3, 4
VRefCA (DC) Reference Voltage for
ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4
VTT Termination v oltage f or
DQ, DQS outputs VDDQ/2 - TBD VDDQ/2 + TBD V
1. For DQ and DM, Vref = VrefDQ. For input only pins except RESET#, Vref = VrefCA.
2. The “t.b.d.” entries might change based on overshoot and undershoot specification.
3. The ac peak noise on VRef may not allow VRef to deviate from VRef (DC) by more than +/-1% VDD
(for reference: approx. +/- 15 mV).
For reference: approx. VDD/2 +/- 15 mV.
Rev. 0.2 / Dec. 2008 16
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
< Figure 6.2.1: Illustration of Vref (DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on
VRef. "VRef" shall be understood as VRef (DC), as defined in Figure 6.2.1
This clarifies, that dc-variations of VRef affect the absolute v oltage a signal has to reach to ach ieve a v alid high or low
level and therefor e the time to which setup and hold is measured. S ystem timing and voltage budgets need to account
for VRef (DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and volta ge associ-
ated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)
are included in DRAM timings and their associated deratings.
5.2.2 DC & AC Logic Input Levels for Differential Signals
Note1:
Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page
Symbol Parameter DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes
Min Max
VIHdiff Differential input logic high + 0.200 - V 1
VILdiff Diff erentia l in put logic lo w - 0.200 V 1
VDD
VSS
VDD/2
VRef(DC)
VRef ac-noise
voltage
time
VRef(DC)max
VRef(DC)min
VRef(t)
Rev. 0.2 / Dec. 2008 17
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.2.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3
The differential input cr oss point voltage VI X is measured fr om the actual cross point of true and complement signal to
the midlevel between of VDD and VSS.
< Figure 5.2.3 Vix Definition >
< Table 5.2.3: Cross point voltage for differential input signals (CK, DQS) >
Symbol Parameter DDR3- 800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes
Min Max
VIX Differential Input Cross Point
Voltage relative to VDD/2 - 150 + 150 mV
VDD
VSS
VDD/2
VIX
VIX
VIX
CK#, DQS#
CK, DQS
Rev. 0.2 / Dec. 2008 18
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.3 Slew Rate Definitions
5.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef
and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VRef and the first crossing of VIL (AC) max.
- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and
the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIH (DC) min and the first crossing of VRef.
< Table 5.3.1: Single-Ended Input Slew Rate Defi nition >
Description Measured Defined by Applicable for
Min Max
Input slew rate for rising edge Vref VIH (AC) min VIH (AC) min-Vref
Delta TRS Setup
(tIS, tDS)
Input slew rate for falling edge Vref VIL (AC) max Vref-VIL (AC) max
Delta TFS
Input slew rate for rising edge VIL (DC) max Vref Vref-VIL (DC) max
Delta TFH Hold
(tIH, tDH)
Input slew rate for falling edge VIH (DC) min Vref VIH (DC) min-Vref
Delta TRH
Delta TFS
Delta TRS
vIH(AC)min
vIH(DC)min
vIL(DC)max
vIL(AC)max
vRefDQ or
vRefCA
Part A: Set up
Single Ended input Voltage(DQ,ADD, CMD)
Rev. 0.2 / Dec. 2008 19
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
< Figure 5.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
5.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured a s shown in below Table
and Figure .
Note:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Description Measured Defined by
Min Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS) VILdiffmax VIHdiffmin VIHdiffmin-VILdiffmax
DeltaTRdiff
Differential inp ut slew r ate f or f alling edge
(CK-CK and DQS-DQS) VIHdiffmin VILdiffmax VIHdiffmin-VILdiffmax
DeltaTFdiff
Part B: Hold
Delta TFH
Delta TRH
vIH(AC)min
vIH(DC)min
vIL(DC)max
vIL(AC)max
vRefDQ or
vRefCA
Single Ended input Voltage(DQ,ADD, CMD)
Rev. 0.2 / Dec. 2008 20
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
< Figure 5.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals.
Symbol Parameter DDR3-800, 1066, 1333 Unit Notes
VOH(DC) DC output high measurement level
(for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level
(for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level
(for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level
(for output SR) VTT + 0.1 x VDDQ V 1
VOL(AC) AC output low measurement level
(for output SR) VTT - 0.1 x VDDQ V 1
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing
with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
Delta
TFdiff
Delta
TRdiff
vIHdiffmin
vILdiffmax
0
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Rev. 0.2 / Dec. 2008 21
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals.
5.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3.
Note:
Output slew rate is verified by design and characterisation, and may not be subject to production test.
< Figure 5.4.3: Single Ended Output Slew Rate Definition >
Symbol Parameter DDR3-800, 1066, 1333 Unit Notes
VOHdiff
(AC) AC differential output high
measurement level (for output SR) + 0.2 x VDDQ V 1
VOLdiff
(AC) AC differential output low
measurement level (for output SR) - 0.2 x VDDQ V 1
1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high
or low swing with a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of
the differential output
Description Measured Defined by
From To
Single ended output slew rate for rising edge VOL(AC) VOH(AC) VOH(AC)-VOL(AC)
DeltaTRse
Single ended output slew rate for falling edge VOH(AC) VOL(AC) VOH(AC)-VOL(AC)
DeltaTFse
Delta TFse
Delta TRse
vOH(AC)
vOL(AC)
V∏
Single Ended Output Voltage(l.e.DQ)
Rev. 0.2 / Dec. 2008 22
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
*** Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
For Ron = RZQ/7 setting
< Table 5.4.3: Output Slew Rate (single-ended) >
5.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and mea-
sured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in below Table and Figure 5.4.4
Note: Output slew rate is verified by design and characterization, and may not be subject to production test..
< Figure 5.4.4: Differential Output Slew Rate Definition >
Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 Units
Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 2.5 5 2.5 5 2.5 5 V/ns
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) VOHdiff (AC)-VOLdiff (AC)
DeltaTRdiff
Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) VOHdiff (AC)-VOLdiff (AC)
DeltaTFdiff
Delta
TFdiff
Delta
TRdiff
vOLdiff(AC)
O
Differential Output Voltage(i.e. DQS-DQS)
vOHdiff(AC)
Rev. 0.2 / Dec. 2008 23
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
***Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting < Table 5.4.4: Differential Output Slew Rate >
5.5 Overshoot and Undershoot Specifications
5.5.1 Address and Control Overshoot and Undershoot Specifications
< Table 5.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins >
< Figure 5.5.1: Address and Control Overshoot and Undershoot Definition >
Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 Units
Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 V/ns
Description Specification
DDR3-800 DDR3-1066 DDR3-1333
Maximum peak amplitude allowed for
overshoot area (see Figure) 0.4V 0.4V 0.4V
Maximum peak amplitude allowed for
undershoot area (see Figure) 0.4V 0.4V 0.4V
Maximum overshoot area above VDD
(See Figure) 0.67 V-ns 0.5 V-ns 0.4 V-ns
Maximum undershoot area below VSS
(See Figure) 0.67 V-ns 0.5 V-ns 0.4 V-ns
Maximum Amplitude
Overshoot Area
VDD
VSS
Volts
(V)
Maximum Amplitude Undershoot Area
Time (ns)
Rev. 0.2 / Dec. 2008 24
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
< Table 5.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >
< Figure 5.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >
Description Specification
DDR3-800 DDR3-1066 DDR3-1333
Maximum peak amplitude allowed for
overshoot area (see Figure) 0.4V 0.4V 0.4V
Maximum peak amplitude allowed for
undershoot area (see Figure) 0.4V 0.4V 0.4V
Maximum overshoot area above VDDQ
(See Figure) 0.25 V-ns 0.19 V-ns 0.15 V-ns
Maximum undershoot area below VSSQ
(See Figure) 0.25 V-ns 0.19 V-ns 0.15 V-ns
Ma x imu m A mp litu d e
O vershoot Area
VDDQ
VSSQ
Maximum Amplitude Undershoot Area
Tim e (ns)
Clock, Data Strobe and M ask Overshoot and U ndershoot D efinition
Volts
(V)
Rev. 0.2 / Dec. 2008 25
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.6 Pin Capacitance
Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 Units Notes
Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS,
TDQS#) CIO TBD TBD TBD TBD TBD TBD pF 1,2,3
Input capacitance, CK and CK# CCK TBD TBD TBD TBD TBD TBD pF 2,3,5
Input capacitance delta
CK and CK# CDCK TBD TBD TBD TBD TBD TBD pF 2,3,4
Input capacitance
(All other input-only pins) CITBD TBD TBD TBD TBD TBD pF 2,3,6
Input capacitance delta, DQS
and DQS# CDDQS TBD TBD TBD TBD TBD TBD pF 2,3,12
Input capacitance delta
(All CTRL input-only pins) CDI_CTRL TBD TBD TBD TBD TBD TBD pF 2,3,7,8
Input capacitance delta
(All ADD/CMD input-only pins) CDI_ADD_C
MD TBD TBD TBD TBD TBD TBD pF 2,3,9,1
0
Input/output capacitance delta
(DQ, DM, DQS, DQS#) CDIO TBD TBD TBD TBD TBD TBD pF 2,3,11
Notes:
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic
characterization of TDQS/TDQS# should be close as much as possible, Cio & Cdio requirement is applied
(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,
the loading matches DQ and DQS.”)
2. This parameter is not subject to production test. It is verified by de sign and characterization. Input capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NET-
WORK
ANALYZER(VNA)”) with VDD, VDDQ , VS S,VSSQ applied an d all other pins floating (ex cept the pin under test, CKE,
RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK#.
5. The minimum CCK will be equal to the minimum CI.
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.
7. CTRL pins defined as ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#))
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#))
12. Absolute value of CIO(DQS) - CIO(DQS#)
Rev. 0.2 / Dec. 2008 26
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.7 IDD Specifications (TCASE: 0 to 95oC)
512MB, 64M x 64 SO-DIMM: HMT164S6AFP6C
1GB, 128M x 64 SO-DIMM: HMT112S6AFP6C
Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note
IDD0 360 420 480 mA
IDD1 480 540 620 mA
IDD2P(F) 100 120 140 mA
IDD2P(S) 40 40 40 mA
IDD2Q 180 240 280 mA
IDD2N 200 240 300 mA
IDD3P 140 180 200 mA
IDD3N 220 280 340 mA
IDD4W 700 880 1060 mA
IDD4R 700 860 1020 mA
IDD5B 740 780 840 mA
IDD6(D) 40 40 40 mA 1
IDD6(S) 24 24 24 mA 1
IDD7 1300 1420 1720 mA
Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note
IDD0 560 660 780 mA
IDD1 680 780 960 mA
IDD2P(F) 200 240 280 mA
IDD2P(S) 80 80 80 mA
IDD2Q 360 480 560 mA
IDD2N 400 480 600 mA
IDD3P 280 360 400 mA
IDD3N 440 560 680 mA
IDD4W 900 1120 1360 mA
IDD4R 900 1100 1320 mA
IDD5B 940 1020 1140 mA
IDD6(D) 80 80 80 mA 1
IDD6(S) 48 48 48 mA 1
IDD7 1500 1660 2020 mA
Rev. 0.2 / Dec. 2008 27
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
2GB, 256M x 64 SO-DIMM: HMT125S6AFP8C
Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note
IDD0 1040 1240 1440 mA
IDD1 1160 1360 1560 mA
IDD2P(F) 400 480 560 mA
IDD2P(S) 160 160 160 mA
IDD2Q 720 960 1120 mA
IDD2N 800 960 1200 mA
IDD3P 560 720 800 mA
IDD3N 880 1120 1360 mA
IDD4W 1520 1920 2160 mA
IDD4R 1440 1800 2280 mA
IDD5B 1880 2040 2320 mA
IDD6(D) 160 160 160 mA 1
IDD6(S) 96 96 96 mA 1
IDD7 2200 2480 3040 mA
Rev. 0.2 / Dec. 2008 28
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
5.7 IDD Measurement Conditions
Within the tables provided further down, an overview about the IDD measurement conditions is
provided as follows:
Within the tables about IDD measurement conditions, the following definitions are used:
- LOW is defined as VIN <= VILAC (max.); HIGH is defined as VIN >= VIH AC (min.).
- STABLE is defined as inputs are stable at a HIGH or LOW level.
- FLOATING is defined as inputs are VREF = VDDQ / 2.
- SWITCHING is defined as described in the following 2 tables.
Table 1 — Overview of Tables providing IDD Measurement Conditions and DRAM Behavior
Table number Measurement Conditions
Table 5 on page 33 IDD0 and IDD1
Table 6 on page 36 IDD2N, IDD2Q, IDD2P(0), IDD2P(1)
Table 7 on page 38 IDD3N and IDD3P
Table 8 on page 39 IDD4R, IDD4W, IDD7
Table 9 on page 42 IDD7 for different Speed Grades and different tRRD, tFAW conditions
Table 10 on page 43 IDD5B
Table 11 on page 44 IDD6, IDD6ET
Table 2 — Definition of SWITCHING for Address and Command Input Signals
SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:
Address
(row, column):
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change
then to the opposite value
(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax .....
please see each IDDx definition for details
Bank address:If not otherwise mentioned the bank addresses should be switched like the row/column
addresses - please see each IDDx definition for details
Command
(CS, RAS, CAS, WE):
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH}
Define Command Background Pattern = D D D D D D D D D D D D...
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background
Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary
command.
See each IDDx definition for details and figures 1,2,3 as examples.
Rev. 0.2 / Dec. 2008 29
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Timing parameters are listed in the following table:
The following conditions apply:
- IDD specifications are tested after the device is properly initialized.
- Input slew rate is specified by AC Parametric test conditions.
- IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12).
Table 3 — Definition of SWITCHING for Data (DQ)
SWITCHING for Data (DQ) is defined as
Data (DQ)
Data DQ is changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals, which means that data DQ is stable during one clock; see each IDDx
definition for exceptions from this rule and for further details.
See figures 1,2,3 as examples.
Data Masking (DM) NO Switching; DM must be driven LOW all the time
Table 4 — For IDD testing the following parameters are utilized.
Parameter
Bin DDR3-800 DDR3-1066 DDR3-1333 Unit
5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9
t
CKmin(IDD) 2.5 1.875 1.5 ns
CL(IDD) 56678789clk
t
RCDmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns
t
RCmin(IDD) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 ns
t
RASmin(IDD) 37.5 37.5 37.5 37.5 37.5 36 36 36 ns
t
RPmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns
t
FAW(IDD) x4/x8 40 40 37.5 37.5 37.5 30 30 30 ns
x165050505050454545ns
t
RRD(IDD) x4/x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 ns
x1610101010107.57.57.5ns
t
RFC(IDD) -
512Mb 90 90 90 90 90 90 90 90 ns
t
RFC(IDD) - 1
Gb 110 110 110 110 110 110 110 110 ns
t
RFC(IDD) - 2
Gb 160 160 160 160 160 160 160 160 ns
t
RFC(IDD) - 4
Gb tbd tbd tbd tbd tbd tbd tbd tbd ns
Rev. 0.2 / Dec. 2008 30
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 5 — IDD Measurement Conditions for IDD0 and IDD1
Current
I
DD0
I
DD1
Name
Operating Current 0
-> One Bank Activate
-> Precharge
Operating Current 1
-> One Bank Activate
-> Read
-> Precharge
Measurement Condition
Timing Diagram Example Figure 1
CKE HIGH HIGH
External Clock on on
t
CK
t
CKmin(IDD)
t
CKmin(IDD)
t
RC
t
RCmin(IDD)
t
RCmin(IDD)
t
RAS
t
RASmin(IDD)
t
RASmin(IDD)
t
RCD n.a.
t
RCDmin(IDD)
t
RRD n.a. n.a.
CL n.a. CL(IDD)
AL n.a. 0
CS HIGH between. Activate and Precharge
Commands
HIGH between Activate, Read and
Precharge
Command Inputs
(CS,RAS, CAS, WE)
SWITCHING as described in Table 2
only exceptions are Activate and
Precharge commands; example of IDD0
pattern:
A0DDDDDDDDDDDDDD P0
(DDR3-800:
t
RAS = 37.5ns between
(A)ctivate and (P)recharge to bank 0;
Definition of D and D: see Table 2
SWITCHING as described in Table 2; only
exceptions are Activate, Read and
Precharge commands; example of IDD1
pattern:
A0DDDDR0DDDDDDDDD P0
(DDR3-800 -555:
t
RCD = 12.5ns between
(A)ctivate and (R)ead to bank 0;
Definition of D and D: see Table 2)
Rev. 0.2 / Dec. 2008 31
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Row, Column Addresses Row addresses SWITCHING as described
in Table 2;
Address Input A10 must be LOW all the
time!
Row addresses SWITCHING a s described
in Table 2;
Address Input A10 must be LOW all the
time!
Bank Addresses bank address is fixed (bank 0) bank address is fixed (bank 0)
Data I/O SWITCHING as described in Table 3 Read Data: output data switches every
clock, which means that Read data is
stable during one clock cycle.
To achieve Iout = 0mA, the output buffer
should be switched off by MR1 Bit A12 set
to “1”.
When there is no read data burst from
DRAM, the DQ I/O should be FLOATING.
Output Buffer DQ,DQS
/ MR1 bit A12
off / 1 off / 1
ODT
/ MR1 bits [A6, A2]
disabled
/ [0,0]
disabled
/ [0,0]
Burst length n.a. 8 fixed / MR0 Bits [A1, A0] = {0,0}
Active banks one
ACT-PRE loop
one
ACT-RD-PRE loop
Idle banks all other all other
Precharge Power Down Mode /
Mode Register Bit 12
n.a. n.a.
Table 5 — IDD Measurement Conditions for IDD0 and IDD1
Current
I
DD0
I
DD1
Name
Operating Current 0
-> One Bank Activate
-> Precharge
Operating Current 1
-> One Bank Activate
-> Read
-> Precharge
Rev. 0.2 / Dec. 2008 32
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
< Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer
should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3
parts.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18
3FF 000 3FF 000 3F000
000
11 00 11 0000
ACT D#DD# RDDD# D# D D D# D# D D D# PRE D D D#
0 0 1 1 0 0 1 1
CK
BA[2:0]
ADDR_a[9:0]
ADDR_b[10]
ADDR_c[12:11]
CS
RAS
CAS
WE
CMD
DQ
DM IDD 1 Measurm ent Loop
Rev. 0.2 / Dec. 2008 33
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 6 — IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q
Current
I
DD2N
I
DD2P(1) a
a.
I
DD2P(0)
I
DD2Q
Name Precharge Standby
Current
Precharge Power
Down Current
Fast Exit -
MRS A12 Bit = 1
Precharge Power
Down Current
Slow Exit -
MRS A12 Bit = 0
Precharge Quiet
Standby Current
Measurement Condition
Timing Diagram
Example Figure 2
CKE HIGH LOW LOW HIGH
External Clockonononon
t
CK
t
CKmin(IDD)
t
CKmin(IDD)
t
CKmin(IDD)
t
CKmin(IDD)
t
RC n.a. n.a. n.a. n.a.
t
RAS n.a. n.a. n.a. n.a.
t
RCD n.a. n.a. n.a. n.a.
t
RRD n.a. n.a. n.a. n.a.
CL n.a. n.a. n.a. n.a.
AL n.a. n.a. n.a. n.a.
CS HIGH STABLE STABLE HIGH
Bank Address, Row
Addr. and Command
Inputs
SWITCHING as
described in
Table 2 STABLE STABLE STABLE
Data inputs SWITCHING FLOATING FLOATING FLOATING
Output Buffer
DQ,DQS
/ MR1 bit A12 off / 1 off / 1 off / 1 off / 1
ODT
/ MR1 bits [A6, A2] disabled
/ [0,0] disabled
/ [0,0] disabled
/ [0,0] disabled
/ [0,0]
Burst length n.a. n.a. n.a. n.a.
Active banks none none none none
Idle banks all all all all
Precharge Power
Down Mode /
Mode Register Bit a n.a. Fast Exit / 1
(any valid command
after tXPb)
b.
Slow Exit / 0
Slow exit (RD and
ODT commands must
satisfy tXPDLL-AL)
n.a.
a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different
Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off
(slow exit, bit 12 = 0).
b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set,
Enter - Self Refresh
Rev. 0.2 / Dec. 2008 34
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
<Figure 2. IDD2N / IDD3N Example > (DDR3-800-555, 512Mb x8)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
7 00
7 00
D# D# D D D# D# D D D# D#
FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
CK
BA[2:0]
ADDR[12:0]
CS
RAS
CAS
WE
CMD
DQ[7:0]
DM
Rev. 0.2 / Dec. 2008 35
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit)
Current
I
DD3N
I
DD3P
Name Active Standby Current Active Power-Down Currenta
Always Fast Exit
a. DDR3 will offer only ONE active power down mode with D LL on (-> f ast exit). MRS bit 12 will not be used for active
power down. Instead bit 12 will be used to switch between two different precharge power down modes.
Measurement Condition
Timing Diagram Example Figure 2
CKE HIGH LOW
External Clock on on
t
CK
t
CKmin(IDD)
t
CKmin(IDD)
t
RC n.a. n.a.
t
RAS n.a. n.a.
t
RCD n.a. n.a.
t
RRD n.a. n.a.
CL n.a. n.a.
AL n.a. n.a.
CS HIGH STABLE
Addr. and cmd Inputs SWITCHING as described in Table 2 STABLE
Data inputs SWITCHING as described in Table 3 FLOATING
Output Buffer DQ,DQS
/ MR1 bit A12 off / 1 off / 1
ODT
/ MR1 bits [A6, A2]
disabled
/ [0,0]
disabled
/ [0,0]
Burst length n.a. n.a.
Active banks all all
Idle banks none none
Precharge Power Down Mode /
Mode Register Bit an.a. n.a. (Active Power Down Mode is always
“Fast Exit” with DLL on
Rev. 0.2 / Dec. 2008 36
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
I
DD4R
I
DD4W
I
DD7
Name Operating Current
Burst Read Operating Current
Burst Write All Bank Interleave Read
Current
Measurement Condition
Timing Diagram
Example Figure 3
CKE HIGH HIGH HIGH
External Clock on on on
t
CK
t
CKmin(IDD)
t
CKmin(IDD)
t
CKmin(IDD)
t
RC n.a. n.a.
t
RCmin(IDD)
t
RAS n.a. n.a.
t
RASmin(IDD)
t
RCD n.a. n.a.
t
RCDmin(IDD)
t
RRD n.a. n.a.
t
RRDmin(IDD)
CL CL(IDD) CL(IDD) CL(IDD)
AL 0 0
t
RCDmin - 1
t
CK
CS HIGH btw. valid cmds HIGH btw. valid cmds HIGH btw. valid cmds
Command Inputs (CS,
RAS, CAS, WE)SWITCHING as described in
Table 2; exceptions are Read
commands => IDD4R
Pattern:
R0DDDR1DDDR2DDDR3.DD
D R4.....
Rx = Read from bank x;
Definition of D and D: see
Table 2
SWITCHING as described in
Table 2; exceptions are Write
commands => IDD4W
Pattern:
W0DDDW1DDDW2DDDW3
DDD W4...
Wx = Write to bank x;
Definition of D and D: see
Table 2
For patterns see Table 9
Rev. 0.2 / Dec. 2008 37
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Row, Column
Addresses
column addresses
SWITCHING as described in
Table 2;
Address Input A10 must be
LOW all the time!
column addresses
SWITCHING as described in
Table 2;
Address Input A10 must be
LOW all the time!
STABLE during DESELECTs
Bank Addresses bank address cycling (0 -> 1 -
> 2 -> 3...)
bank address cycling (0 -> 1 -
> 2 -> 3...)
bank address cycling (0 -> 1 -
> 2 -> 3...), s ee pattern in
Table 9
DQ I/O
Seamless Read Data Burst
(BL8): output data switches
every clock, which means that
Read data is stable during one
clock cycle.
To achieve Iout = 0mA the
output buffer should be
switched off by MR1 Bit A12
set to “1”.
Seamless Write Data Burst
(BL8): input data switches
every clock, which means that
Write data is stable during one
clock cycle.
DM is low all the time.
Read Data (BL8 ): output data
switches every clock, which
means that Read data is
stable during one clock cycle.
To achieve Iout = 0mA the
output buffer should be
switched off by MR1 Bit A12
set to “1”.
Output Buffer
DQ,DQS
/ MR1 bit A12
off / 1 off / 1 off / 1
ODT
/ MR1 bits [A6, A2]
disabled
/ [0,0]
disabled
/ [0,0]
disabled
/ [0,0]
Burst length 8 fixed / MR0 Bits [A1, A0] =
{0,0}
8 fixed / MR0 Bits [A1, A0] =
{0,0}
8 fixed / MR0 Bits [A1, A0] =
{0,0}
Active banks all all all, rotational
Idle banks none none none
Precharge Power
Down Mode /
Mode Register Bit
n.a. n.a. n.a.
Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
I
DD4R
I
DD4W
I
DD7
Name Operating Current
Burst Read Operating Current
Burst Write All Bank Interleave Read
Current
Rev. 0.2 / Dec. 2008 38
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
< Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer
should be switched off (per MR1 Bit A12=”1”) to achieve Iout = 0mA. Address inputs are split into 3
parts.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
001 010 011
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
CK
BA[2:0]
ADDR[12:0]
CS
RAS
CAS
WE
CMD[2:0]
DQ[7:0]
DM
T10 T11 T12
3FF 000 3FF
ADDR_b[10]
11 00 11
ADDR_c[12:11]
000
000
00
RD DD# D# RD DD# D# D# RDD# RD D
-> Start of M easurem ent Loop
Rev. 0.2 / Dec. 2008 39
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 9 — IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions
Speed Bin Org. tFAW tFAW tRRD tRRD IDD7 Patterna
a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect
Mb/s [ns] [CLK] [ns] [CLK] (Note this entire sequence is repeated.)
800
all x4/x8 40 16 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4
RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
all x16 50 20 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
D D D D
1066
all x4/x8 37.5 20 7.5 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
D D D D
all x16 50 27 10 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3
RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D
A6 RA6 D D D D A7 RA7 D D D D D D D
1333
all x4/x8 30 20 6 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
D D D D
all x16 45 30 7.5 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D
D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D
D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D
1600
all x4/x8 30 24 6 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D
D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D
D A7 RA7 D D D D D D D
all x16 40 32 7.5 6
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3
RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5
D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D
D D D
Rev. 0.2 / Dec. 2008 40
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 10 — IDD Measurement Conditions for IDD5B
Current
I
DD5B
Name Burst Refresh Current
Measurement Condition
CKE HIGH
External Clock on
t
CK
t
CKmin(IDD)
t
RC n.a.
t
RAS n.a.
t
RCD n.a.
t
RRD n.a.
t
RFC
t
RFCmin(IDD)
CL n.a.
AL n.a.
CS HIGH btw. valid cmds
Addr. and cmd Inputs SWITCHING
Data inputs SWITCHING
Output Buffer DQ,DQS / MR1 bit A12 off / 1
ODT / MR1 bits [A6, A2] disabled / [0,0]
Burst length n.a.
Active banks Refresh command every tRFC = tRFCmin
Idle banks none
Precharge Power Down Mode / Mode Register Bit n.a.
Rev. 0.2 / Dec. 2008 41
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET
Current
I
DD6
I
DD6ET
Name Self-Refresh Current
Normal Temperature Range
T
CASE = 0.. 85 °C
Self-Refresh Current
Extended Temperature Range a
T
CASE = 0 .. 95 °C
a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM
devices support the following options or requirements referred to in this material.
Measurement Condition
Temperature
T
CASE = 85 °C
T
CASE = 95 °C
Auto Self Refresh (ASR) /
MR2 Bit A6 Disabled / “0” Disabled / “0”
Self Refresh Temperature
Range (SRT) /
MR2 Bit A7 Normal / “0” Extended / “1”
CKE LOW LOW
External Clock OFF; CK and CK at LOW OFF; CK and CK at LOW
t
CK n.a. n.a.
t
RC n.a. n.a.
t
RAS n.a. n.a.
t
RCD n.a. n.a.
t
RRD n.a. n.a.
CL n.a. n.a.
AL n.a. n.a.
CS FLOATING FLOATING
Command Inputs
(RAS, CAS, WE)FLOATING FLOATING
Row, Column Addresses FLOATING FLOATING
Bank Addresses FLOATING FLOATING
Data I/O FLOATING FLOATING
Output Buffer DQ,DQS
/ MR1 bit A12 off / 1 off / 1
ODT
/ MR1 bits [A6, A2] disabled
/ [0,0] disabled
/ [0,0]
Burst length n.a. n.a.
Active banks all during self-refresh actions all during self-refresh actions
Idle banks all btw. Self-Refresh actions all btw. Self-Refresh actions
Precharge Power Down Mode
/ MR0 bit A12 n.a. n.a.
Rev. 0.2 / Dec. 2008 42
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
6.2 DDR3 SDRAM Standard Speed Bins includ e tCK, tRCD, tRP, tRAS and tRC
for each corresponding bin
Parameter Symbol 512Mb 1Gb 2Gb 4Gb 8Gb Units
REF command to
ACT or REF
command time tRFC 90 110 160 300 350 ns
Average periodic
refresh interval tREFI 0 ×C < TCASE < 85 ×C 7.8 7.8 7.8 7.8 7.8 ms
85 ×C < TCASE < 95 ×C 3.9 3.9 3.9 3.9 3.9 ms
DDR3 800 Speed Bin DDR3-800D DDR3-800E
Unit Notes
CL - nRCD - nRP 5-5-5 6-6-6
Parameter Symbol min max min max
Internal read command to first data
t
AA 12.5 20 15 20 ns
ACT to internal read or write delay time
t
RCD 12.5 — 15 — ns
PRE command period
t
RP 12.5 — 15 — ns
ACT to ACT or REF command period
t
RC 50 — 52.5 — ns
ACT to PRE command period
t
RAS 37.5 9 * tREFI 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 2.5 3.3 Reserved ns 1)2)3)4)
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 2.5 3.3 ns 1)2)3)
Supported CL Settings 5, 6 6
n
CK
Supported CWL Settings 55
n
CK
Rev. 0.2 / Dec. 2008 43
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
DDR3 1066 Speed Bin DDR3-1066E DDR3-1066F DDR3-1066G
Unit Note
CL - nRCD - nRP 6-6-6 7-7-7 8-8-8
Parameter Symbol min max min max min max
Internal read command to
first data
t
AA 11.25 20 13.125 20 15 20 ns
ACT to internal read or
write delay time
t
RCD 11.25 — 13.125 — 15 — ns
PRE command period
t
RP 11.25 — 13.125 — 15 — ns
ACT to ACT or REF
command period
t
RC 48.75 — 50.625 — 52.5 — ns
ACT to PRE command
period
t
RAS 37.5 9 * tREFI 37.5 9 * tREFI 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 2.5 3.3 Reserved Reserved ns 1)2)3)4)6)
CWL = 6
t
CK(AVG) Reserved Reserved Reserved ns 4)
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2)3)6)
CWL = 6
t
CK(AVG) 1.875 < 2.5 Reserved Reserved ns 1)2)3)4)
CL = 7 CWL = 5
t
CK(AVG) Reserved Reserved Reserved ns 4)
CWL = 6
t
CK(AVG) 1.875 < 2.5 1.875 < 2.5 Reserved ns 1)2)3)4)
CL = 8 CWL = 5
t
CK(AVG) Reserved Reserved Reserved ns 4)
CWL = 6
t
CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1)2)3)
Supported CL Settings 5, 6, 7, 8 6, 7, 8 6, 8
n
CK
Supported CWL Settings 5, 6 5, 6 5, 6
n
CK
Rev. 0.2 / Dec. 2008 44
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
DDR3 1333 Speed Bin DDR3-1333F
(optional) DDR3-1333G DDR3-1333H DDR3-1333J
(optional)
Unit Note
CL - nRCD - nRP 7-7-7 8-8-8 9-9-9 10-10-10
Parameter Symbol min max min max min max min max
Internal read
command to first
t
AA 10.5 20 12 20 13.5 20 15 20 ns
ACT to internal read
or write delay time
t
RCD 10.5 — 12 — 13.5 — 15 — ns
PRE command period
t
RP 10.5 — 12 — 13.5 — 15 — ns
ACT to ACT or REF
command period
t
RC 46.5 — 48 — 49.5 — 51 — ns
ACT to PRE
command period
t
RAS 36 9 *
tREFI 36 9 *
tREFI 36 9 *
tREFI 36 9 *
tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 2.5 3.3 2.5 3.3 Reserved Reserved ns 1,2,3,4,7
CWL = 6, 7
t
CK(AVG) Reserved Reserved Reserved Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,7
CWL = 6
t
CK(AVG) 1.875 < 2.5 Reserved Reserved Reserved ns 1 ,2,3,4,7
CWL = 7
t
CK(AVG) Reserved Reserved Reserved Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved Reserved Reserved Reserved ns 4
CWL = 6 tCK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 Reserved ns 1,2,3,4,7
(Optional)
Note 9.10
CL = 8 CWL = 5
t
CK(AVG) Reserved Reserved Reserved Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,7
CWL = 7
t
CK(AVG) 1.5 <1.875 1.5 <1.875 Reserved Reserved ns 1,2,3,4
CL = 9 CWL = 5, 6
t
CK(AVG) Reserved Reserved Reserved Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 Reserved ns 1,2,3,4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved Reserved Reserved Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3
(Optional) (Optional) (Optional) ns 5
Supported CL Settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 7, 8, 9 6, 8, 10
n
CK
Supported CWL Settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7
n
CK
Rev. 0.2 / Dec. 2008 45
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
*Speed Bin Table Notes*
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1. The CL setting and CWL se tting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection
of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the
DLL - all possible intermediate freque ncies may not be guaranteed. An application should use the next smaller JEDEC
standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns],
rounding up to the next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK (AVG ) = tAA.MAX / CLSELECTED and round the result ing tCK (AVG) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to
CLSELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory
feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
8. It is not a mandatory bin. Refer to supplier’s data sheet and/or the DIMM SPD information.
9. If it’ s supporte d, the minimum tA A/tRCD/tRP that this dev ice support is 13.125ns. Theref ore, In Module application,
tAA/tRCD/tRP should be programed with minimum supported values. For example, DDR3-1333H supporting down-
shift to DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). DDR3-
1600K supporting down-shift to DDR3-1333H and/or DDR3-1066F should program SPD as 13.125ns for
tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20).
Rev. 0.2 / Dec. 2008 46
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
7. DIMM Outline Diagram
7.1 64Mx64 - HMT164S6AFP(R)6C
Front View
Back View
0.20
2.55
0.60
0.45
Detail of Contacts A
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
SPD
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail- A Detail-B
1.00 m m
3.80mm max
Side
1.65 0.10±
1.80 0.10±2
X
φ
0.10±
0.15±
0.05±
0.08±
Rev. 0.2 / Dec. 2008 47
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
64Mx64 - HMT164S6AFP(R)6C (with temperature sensor)
Front View
Back View
SPD (TS)
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail- A Detail-B
3.80mm max
Side
4.00 0.10±
1.65 0.10±
1.80 0.10±2
X
φ
1.00 mm
0.08±
0.20
2.55
0.60
0.45
Detail of Contacts A
0.10±
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
0.15±
0.05±
Rev. 0.2 / Dec. 2008 48
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
7.2 128Mx64 - HMT112S6AFP(R)6C
Front View
Back View
SPD
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail- A Detail-B
3.80mm max
Side
4.00 0.10±
1.65 0.10±
1.00 m m
0.08±
1.80 0.10±2
X
φ
0.20
2.55
0.60
0.45
Detail of Contacts A
0.10±
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
0.15±
0.05±
Rev. 0.2 / Dec. 2008 49
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
128Mx64 - HMT112S6AFP(R)6C (with temperature sensor)
Front View
Back View
SPD (TS)
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail- A Detail-B
3.80mm max
Side
4.00 0.10±
1.65 0.10±
1.00 m m
0.08±
1.80 0.10±2
X
φ
0.20
2.55
0.60
0.45
Detail of Contacts A
0.10±
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
0.15±
0.05±
Rev. 0.2 / Dec. 2008 50
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
7.3 256Mx64 - HMT125S6AFP(R)8C
Front View
Bacl View
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail-
A
SPD
3.80mm max
Side
Detail-B
4.00 0.10±
1.65 0.10±
1.00 mm
0.08±
0.20
2.55
0.60
0.45
Detail of Contacts A
0.10±
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
0.15±
0.05±
1.80 0.10±2
X
φ
Rev. 0.2 / Dec. 2008 51
HMT164S6AFP(R)6C
HMT112S6AFP(R)6C
HMT125S6AFP(R)8C
256Mx64 - HMT125S6AFP(R)8C (with temperature sensor)
Front View
Back View
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail- A
SPD (TS)
3.80mm max
Side
Detail-B
4.00 0.10±
1.65 0.10±
1.00 mm
0.08±
1.80 0.10±2
X
φ
0.20
2.55
0.60
0.45
Detail of Contacts A
0.10±
2.55
1.00
Detail of Contacts B
0.3
0.3~1.0
3.00
4.00
0.15±
0.05±
