ES_LPC4350/30/20/10 Rev A Errata sheet LPC4350, LPC4330, LPC4320, LPC4310 Rev A Rev. 2.2 -- 8 August 2012 Errata sheet Document information Info Content Keywords LPC4350FET256, LPC4350FET180, LPC4350FBD208, LPC4330FET256, LPC4330FET180, LPC4330FET100, LPC4330FBD144, LPC4320FET100, LPC4320FBD144, LPC4320FBD100, LPC4310FET100, LPC4310FBD144, Rev A errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table. ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A Revision history Rev Date 2.2 20120808 2.1 20120713 2 20120601 1.3 20120401 1.2 20120201 1.1 20120123 1 20120103 Description * * * * * * * * * * Added IBAT.2 and RGU.1. Corrected C_CAN0/C_CAN1 peripheral assignment. Added C_CAN.1. Added ISP.1, ETM.1, IAP.1, PMC.1 and IBAT.1. Updated SPIFI.1. Added SPIFI.2. Removed ADC.1 and USB0.1. Added OTP.1. Added ADC.1. Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 2 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 1. Product identification The LPC4350/30/20/10 devices (hereafter referred to as `LPC43x0') typically have the following top-side marking: LPC43x0xxxxxx xxxxxxxx xxxYYWWxR[x] The last/second to last letter in the last line (field `R') will identify the device revision. This Errata Sheet covers the following revisions of the LPC43x0: Table 1. Device revision table Revision identifier (R) Revision description `A' Initial device revision Field `YY' states the year the device was manufactured. Field `WW' states the week the device was manufactured during that year. 2. Errata overview Table 2. Functional problems Functional problems table Short description Revision identifier Detailed description AES.1 AES decryption is not functional `A' Section 3.1 BOOT.1 USB1 boot is not functional `A' Section 3.2 C_CAN.1 Writes to CAN registers write through to other peripherals `A' Section 3.3 ETM.1 Time stamping is not functional. `A' Section 3.4 IAP.1 In-Application Programming API not present on flashless parts `A' Section 3.5 ISP.1 Part ID format incorrect `A' Section 3.6 MCPWM.1 MCPWM abort pin not functional `A' Section 3.7 OTP.1 OTP ROM driver may not program boot source. `A' Section 3.8 PMC.1 PMC.x power management controller fails to wake up from deep sleep, power down, or deep power down `A' Section 3.9 RGU.1 CORE_RST status bits in the RESET_STATUS0 register do not work. `A' Section 3.10 SPIFI.1 The ROM driver does not properly re-initialize the external flash device `A' Section 3.11 SPIFI.2 The ROM driver does not support 4-byte address mode `A' Section 3.12 ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 3 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A Table 3. AC/DC deviations table AC/DC deviations Short description Product version(s) Detailed description IBAT.1 VBAT supply current higher than expected `A' Section 4.1 IBAT.2 VBAT supply current higher than expected `A' Section 4.2 PWR.1 Deep sleep and Power-down mode consume more current than expected `A' Section 4.3 Table 4. Errata notes table Errata notes Short description Revision identifier Detailed description n/a n/a n/a n/a ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 4 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3. Functional problems detail 3.1 AES.1: AES decryption is non-functional Introduction: The LPC43x0 contains a hardware-based AES security engine programmable through an on-chip API. This engine implements AES decryption with 128 bit keys. Problem: The hardware-based AES security engine is non-functional at this time. Work-around: We can produce parts with functional AES decryption engines for export to a limited number of countries. There is also an LPC43x0-S version product with fully functional AES encryption and decryption. Please contact sales for more information. 3.2 BOOT.1: USB1 boot is not functional Introduction: The internal ROM memory is used to store the boot code of the LPC43x0. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: * ...Boot from USB1.... Problem: Boot from USB1 is not functional. This does not affect use of USB1 after bootup. Work-around: USB0 can be used to boot the part. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 5 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.3 C_CAN.1: Writes to CAN registers write through to other peripherals Introduction: Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. Problem: On the LPC43x0, there is an issue with the CAN controller bus that applies to both CAN controllers. It affects peripherals on the same bus as the CAN controller. Writes to the CAN peripheral can update registers in the ADC, DAC, I2C, and I2S peripherals. Specifically, writes to C_CAN1 can affect I2C0, MCPWM, and I2S. Writes to C_CAN0 can affect I2C1, DAC, ADC0, and ADC1. Write to these other peripherals on the same APB bus can update registers in the CAN controller. Work-around: The safest workaround is to avoid using the CAN peripheral and make sure that it is not routed out using the pin multiplex registers. Since it is still possible to use the CAN controller when ADC, DAC, I2C, MCPWM, and I2S are not used, it may be possible to initialize all of peripherals by careful use of registers. 3.4 ETM.1: Time stamping is not functional Introduction: The Cortex-M4 Embedded Trace Macrocell (ETM-M4) is an optional debug component that enables a debugger to reconstruct program execution. A system implementation may provide a timestamp count which can be used by several trace sources as an aid to correlating the trace streams. Problem: The timestamps are always zero on the LPC43x0 microcontrollers. This means that sleep, deep sleep, and power down durations are not visible to debug tools by using the trace data. It also means that it might be difficult for trace tools to identify that the CPU clock frequency has changed. Work-around: While using the ETM trace feature, avoid using sleep or power-down modes and run at a constant clock frequency. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 6 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.5 IAP.1: In-Application Programming API not present on flashless parts Introduction: The LPC43x0 microcontrollers contain an API for In-Application Programming of flash memory. This API also allows identification of the part. Problem: On the LPC43x0 microcontrollers, the IAP API is not present. The ISP interface is present which allows the part to be identified externally (via the UART) but part identification is not possible internally using the IAP call because it is not implemented. Work-around: To detect whether or not the IAP API is present, check the IAP entry point at 0x10400100. If it is set to 0x12345678, the part does not implement IAP. The first word of the Part ID can be read directly from OTP at 0x40045000. The second word of the Part ID is always '0' on flashless parts. 3.6 ISP.1: Part ID format incorrect Introduction: A reduced set of In-System-Programming (ISP) commands are supported for flashless parts. The ISP 'J' command can be used to query the part identification number. Problem: On the LPC43x0 microcontrollers, the J command returns incorrectly formatted data. Instead of returning two words (plus the return code) as specified in the User's Manual, IAP command 54 and ISP command 'J' only return a single word (plus return code). That single word contains the first word of the part identification number with the first 16 bits swapped with the last 16 bits. For example, an LPC4350FET256 will return 0x0830A000 instead of the correct value, 0xA0000830. Work-around: When using ISP, if only one word of data is returned, swap the two 16-bit segments of the word and assume the second word of data is 0. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 7 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.7 MCPWM.1: MCPWM Abort pin is not functional Introduction: The Motor Control PWM engine is optimized for three-phase AC and DC motor control applications, but can be used in many other applications that need timing, counting, capture, and comparison. The MCPWM contains a global Abort input that can force all of the channels into a passive state and cause an interrupt. Problem: The MCPWM Abort input is not functional. Work-around: The MCPWM Abort function can be emulated in software with the use of a non-maskable interrupt combined with an interrupt handler that shuts down the PWM. This will result in a small delay on the order of 50 main clock cycles or about 1/3 of a microsecond at 150 MHz. Alternatively, the State Configurable Timer (SCT) can be configured to implement MCPWM functionality including an Abort input. The SCT can respond to external inputs in one clock cycle. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 8 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.8 OTP.1: OTP ROM driver may not program boot source Introduction: The LPC43x0 contains OTP memory which can configure the boot source, as well as a set of routines in ROM to program the boot source into OTP memory. Problem: There is a problem in the OTP boot source programming code in ROM which requires registers to be initialized in order to ensure successful boot source OTP programming. Work-around: 1. Add this function to your program. void OTP_fix(volatile unsigned dummy0,volatile unsigned dummy1,volatile unsigned dummy2,volatile unsigned dummy3) { } 2. Call this function before calling otp_ProgBootSrc. rval = otp_Init(); OTP_fix(0,0,0,0); rval = otp_ProgBootSrc(OTP_BOOTSRC_SPIFI); This will be fixed in the next boot ROM revision. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 9 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.9 PMC.1: PMC.x power management controller fails to wake up from Deep Sleep, Power Down, or Deep Power Down Introduction: The PMC implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral. In addition, wake-up from any of the power-down modes based on hardware events is supported. Problem: When the chip is in a transition from active to Deep Sleep, Power Down, or Deep Power Down, wakeup events are not captured and they will block further wakeup events from propagating. The time window for this transition is 6 uS and is not affected by the chip clock speed. After a wakeup event is received during the PMC transition, the chip can only recover by using an external hardware reset or by cycling power. Work-around: Make sure that a wakeup signal is not received during the Deep Sleep, Power Down, or Deep Power Down transition period. An example circuit to work around this could include an external 6 uS one shot which could be triggered via software using a GPIO line when entering Deep Sleep, Power Down, or Deep Power Down mode. The one-shot's output could be used to gate the wakeup signal(s) to prevent receiving a wakeup signal during the PMC transition period. Depending on the system design, it may also be needed to latch the wakeup signal(s) so that they will still be present after the one-shot's 6 uS timeout. Run mode PMC transition period 6 us PMC state Keep-out area Low power mode PMC software trigger Wakeup signal asserted (ok) Fig 1. ES_LPC43X0_A Errata sheet PMC wakeup keep-out area All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 10 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.10 RGU.1: CORE_RST status bits in the RESET_STATUS0 register do not work Introduction: The Reset Generation Unit can independently reset blocks, peripherals, and the core. Status registers in the RGU include bits that correspond to the reset signals that were generated. Two bits in the first of these status registers (RESET_STATUS0) provide an indication of how the core was reset. These bits indicate if the core is coming up from a powered down state, or if the core was reset by the reset signal, or by a write to the RESET_CTRL register in the RGU. Problem: The CORE_RST bits in the RGU's status register do not properly indicate the cause of the core reset. When the core is reset the RGU is also reset and as a result the state of these bits will always read with their default values. As a result, these status bits cannot be used to determine the cause of the core reset. Work-around: 1. Use a flag in internal RAM to determine the cause of a core reset. a. Check the value of a flag at the start of execution. Possible flag values are: i. !=0xaa55ff01 && !=0xaa55ff02 power on reset ii.0xaa55ff01 external reset signal iii.0xaa55ff02 RGU generated core reset b. After checking the flag, write a value of 0xaa55ff01 to this flag. c. Before performing an RGU generated core reset write a value of 0xaa55ff02 to this flag. 2. Use bits in the event router registers to determine the cause of a core reset. a. Check the state of the HILO, EDGE registers, and the RESET_E and RESET_ST bits in the EDGE and STATUS registers i. HILO==0 & EDGE==0 power on reset ii. RESET_E==1 && RESET_ST==1 external reset input (RESET) b. Setup the event router to detect RESET: i. RESET_L = 0 // detect a low level (this is the bit's reset value) ii. RESET_E = 1 // detect a falling edge iii. RESET_CLRST = 1 // clear the previous event ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 11 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.11 SPIFI.1: The ROM driver does not properly re-initialize the external serial flash device Introduction: The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected to the ARM Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. SPIFI provides a memory-mapped area where the contents of the external serial flash memory appear. Problem: The built-in SPIFI ROM driver used for booting does not properly re-initialize the external serial flash device if it is already set up for "no opcode" or "continuous read" mode. This affects use after unplanned resets such as a hardware reset or watchdog timer reset. Booting from SPIFI is affected and may not be successful until after the 60 second boot failure timeout if the external serial flash device is in "no opcode" or "continuous read" mode. Work-around: During a planned reboot, remove the external QSPI flash from no opcode mode before resetting the CPU by using the SPIFI driver library's cancel_mem_mode call. The SPIFI driver library is available from lpcware.com. In the event of an unplanned reset, the driver will initialize the flash device if it is called a second time so an external watchdog could be provided to reset the CPU in case of boot failure from SPIFI. Finally there is a built-in 60-second boot timeout which will result in a successful boot after one minute in the event of a failure. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 12 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 3.12 SPIFI.2: The ROM driver does not support 4-byte address mode Introduction: The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected to the ARM Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. SPIFI provides a memory-mapped area where the contents of the external serial flash memory appear. Problem: The built-in SPIFI ROM driver used for booting does not properly initialize the SPIFI hardware to support serial flash devices using 4-byte address mode, such as Micron devices 32 MB or larger. Work-around: A 16 MB or smaller serial flash device could be used, or a parallel flash memory could be used for booting instead. This problem does not affect the ability to use large serial flash devices after booting using the SPIFI library from lpcware.com. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 13 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 4. AC/DC deviations detail 4.1 IBAT.1: VBAT supply current higher than expected Introduction: The LPC43x0 contain a Real-Time Clock which measures the passage of time. The RTC has an ultra-low power design to support battery powered systems with a dedicated battery supply pin. Problem: On the LPC43x0, high current consumption of about 70 uA may occur on the VBAT power supply pin. Work-around: VBAT current consumption can be lowered significantly by configuring the RTC_ALARM pin as "Inactive" by setting the ALARMCTRL 7:6 field in CREG0 to 0x3. These bits persist through power cycles and reset while VBAT is present. 4.2 IBAT.2: VBAT supply current higher than expected Introduction: The LPC43x0 contain a Real-Time Clock which measures the passage of time. The RTC has an ultra-low power design to support battery powered systems with a dedicated battery supply pin. Problem: On the LPC43x0, high current consumption of about 15 uA may occur on the VBAT power supply pin despite applying the workaround in IBAT.1. Work-around: The problem is caused by a design error and there is currently no work-around. 4.3 PWR.1: Deep sleep and Power-down modes consume more current than expected Introduction: The LPC43x0 contains several low-power modes. The PMC implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral. Problem: A design error results in about 15 A higher current consumption during Deep Sleep and Power Down mode. Work-around: None. ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 14 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 5. Errata notes detail 5.1 n/a ES_LPC43X0_A Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 15 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 6. Legal information 6.1 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ES_LPC43X0_A Errata sheet malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2.2 -- 8 August 2012 (c) NXP B.V. 2012. All rights reserved. 16 of 17 ES_LPC43x0 NXP Semiconductors Errata sheet LPC4350/30/20/10 Rev A 7. Contents 1 2 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Product identification . . . . . . . . . . . . . . . . . . . . 3 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional problems detail . . . . . . . . . . . . . . . . 5 AES.1: AES decryption is non-functional . . . . . 5 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 BOOT.1: USB1 boot is not functional . . . . . . . . 5 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 C_CAN.1: Writes to CAN registers write through to other peripherals. . . . . . . . . . . . . . . . . . . . . . 6 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ETM.1: Time stamping is not functional . . . . . . 6 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 IAP.1: In-Application Programming API not present on flashless parts. . . . . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ISP.1: Part ID format incorrect . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 MCPWM.1: MCPWM Abort pin is not functional 8 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 OTP.1: OTP ROM driver may not program boot source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PMC.1: PMC.x power management controller fails to wake up from Deep Sleep, Power Down, or Deep Power Down . . . . . . . . . . . . . . . . . . . . . 10 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .10 RGU.1: CORE_RST status bits in the RESET_STATUS0 register do not work . . . . . 11 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.11 3.12 4 4.1 4.2 4.3 5 5.1 6 6.1 6.2 6.3 7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPIFI.1: The ROM driver does not properly re-initialize the external serial flash device . . 12 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPIFI.2: The ROM driver does not support 4-byte address mode . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC/DC deviations detail . . . . . . . . . . . . . . . . . 14 IBAT.1: VBAT supply current higher than expected 14 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IBAT.2: VBAT supply current higher than expected 14 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWR.1: Deep sleep and Power-down modes consume more current than expected . . . . . . 14 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Errata notes detail . . . . . . . . . . . . . . . . . . . . . . 15 n/a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 August 2012 Document identifier: ES_LPC43X0_A