AM29F002NBT-70EC - AMD - Datasheet.Directory

This Data Sheet states AMD’s curre nt technic al sp ec ifications reg ar ding the Prod uc ts described here in. T his Data

She et may be revised by subsequent vers ions or m odifications due t o c hanges in tec hnic al spe c ifications. Publication# 21527 Rev: BAmendment/0

Issue Date: Januar y 1999

Am29F002B/Am29F002NB

2 Megabit (256 K x 8-Bit)

CM O S 5 .0 Volt-only Bo ot Secto r Flash Memo r y

DISTINCTIVE CHARACTERISTICS

■Si ngle p owe r supply operation

— 5.0 Volt-onl y operation for read, erase, and

pr ogram opera tions

— Minimizes system level requirements

■Manufactured on 0.32 µm pr ocess technolo g y

— Compatible with 0.5 µm Am29F002 device

■High performance

— Access times as fast as 55 ns

■Low power consumption (typical values at

5 MHz)

— 1 µA standby mode current

— 20 mA read current

— 30 m A program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

t hr ee 64 Kby te sec t or s

— Supports full chip erase

— Sector Protection features:

A ha rdwar e method of lo ckin g a sector to

pr event any program or erase operation s within

that sector

Sectors can be lock ed via programming equipment

Temporary Sector Unprotect feature allows code

chang es in previously locked sectors

■Top or bott om boot b loc k c onfi gurati ons av aila bl e

■Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of design ated sectors

— Embedded Program algorithm automaticall y

writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per

sector

■20-year data retention at 125°C

— Reliable operation for the life of the system

■Package option

— 32-pin PDIP

— 32-pin TSOP

— 32-pin PLCC

■Compatibility with JEDEC standards

— Pinout and software com patib le with

s ingle-p ow er sup pl y Fl a sh

— Superior inadvertent write pr otection

■Dat a# Polling a nd toggle bi ts

— Provides a software method of detecting

pr ogra m or erase operation completion

■Er as e Sus pe nd /E r as e Res um e

— Suspends an erase operation to read data from,

or pr ogram data to, a sector that is not being

erased, then resumes the erase operation

■Hardware reset pin ( R ESET#)

— Hardware method to reset the de vice to reading

array data (not available on Am29F002NB)

2 Am29F002B/Am29F002NB

GENERAL DESCRIPTION

The Am29F002B Family consists of 2 Mbit, 5.0

vo lt-o nl y F lash m em or y de vi ces organi zed as 2 62, 14 4

bytes. The Am29F002B offers the RESET# function,

the Am29F002NB does not. The data appears on

DQ7–DQ0. The device is offered in 32-pin PLCC,

32-pin T SOP , an d 3 2-pin PDIP packa ges . T hi s d evi c e

is designed to be programmed in-system with the stan-

dard system 5.0 volt VCC supply. No VPP is required for

write or erase operations. The device can also be pro-

grammed in standard EPROM programmers.

This device is manufactured using AMD’s 0.32 µm

pr oces s tec hno log y, and off e rs a ll t he f eat ure s an d be n-

efits of the Am29F002, which was manufactured using

0.5 µm process technology.

The sta nd ar d device offers acc ess tim es of 55 , 70, 90,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate b us contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power

supply for both read and write functions. Internally

gene rat ed and re gulate d voltag es are pr ovide d for th e

program and erase operations.

The device is entirely comma nd set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of th e device is similar to reading from other

Fl ash or EPRO M devices .

Devic e p ro gram m ing occ u rs by executin g th e program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an inte rnal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies pro per cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) stat us bi ts . After a pr ogram

or er ase cycle has been completed, the device is ready

to read array data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

er ased when shipped from the factory.

Har d ware dat a pr ot ect ion measur es i nc lude a l o w V CC

detector that automatically inhibits write operations during

power transitions. The hardware sector protection

feature disables both program and erase operations in

any combination of the sectors of memor y. This can be

achi eve d via pr og ra mming equi pm ent.

The Erase Suspend feature enables the user to put

erase on hol d for any pe r iod of tim e to rea d da ta fr om ,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arra y data. The RESET# p in may be tied to the

system reset circ uitr y. A sys tem rese t would thus a ls o

reset the device, enabling the system microprocessor

to r ead the boot-up firmware from the Flash memor y.

(This feature is not available on the Am29F002NB.)

The sy stem ca n pl ace the de vice i nto the standby mode.

Pow er consum pti on is gr eat ly re duced in t his mod e.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest le vels of qual ity, reliability and cost eff ectiv eness.

The device electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The

data is programmed using hot electron injection.

Am29F002B/Am29F002NB 3

PR ODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29F002B/Am29F002NB

Speed Option VCC = 5.0 V ± 5% -55

VCC = 5.0 V ± 10% -70 -90 -120

Max access time, ns (tACC) 55 70 90 120

Max CE# access time, ns (tCE) 55 70 90 120

Max OE# access time, ns (tOE) 30303550

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A17

21527B-1

n/a Am29F002NB

4 Am29F002B/Am29F002NB

CONNECTION DIAGRAMS

A16

DQ0

A15

A12

DQ1

DQ2

VSS

A11

OE#

A10

CE#

DQ7

VCC

WE#

DQ6

A17

A14

A13

DQ5

DQ4

DQ3

A11

A13

A14

A17

WE#

VCC

RESET#

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

131 30

13 17 18 19 2016

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A12

A15

A16

RESET#

VCC

WE#

A17

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

21527B-2

PDIP

Standard TSOP

PLCC

NC on Am29F002NB

RESET#

Am29F002B/Am29F002NB 5

PIN CONFIGURATION

A0– A 17 = 18 addr es se s

DQ0–DQ7 = 8 data inputs/outputs

CE# = Chip enable

OE# = Output enable

WE# = Wr ite en abl e

RESET# = Hardware reset pin, active low

(not available on A m 29F002NB)

VCC = +5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

VSS = Device ground

NC = Pin no t co nnected internally

LOGIC SYMBOL

21527B-3

18 8

DQ0–DQ7

A0–A17

CE#

OE#

WE#

RESET#

N/C on Am29F002NB

6 Am29F002B/Am29F002NB

ORDERING INFORMATION

Standard Product

AM D stan dard p roduc ts are ava ilable in s evera l p ackages an d opera ting r anges. Th e orde r numbe r (Valid Co mbi -

nation) is formed by a combination of the elements below .

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am29F002B/Am29F002NB

2 Megabit (256 K x 8-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

AM29F002B -55 P C

OPTIONAL PROCESSING

Blank = Standard Proces sing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (-40°C to +85°C)

E=Exte nded (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 032)

SPEED OPTION

See Product Selector Guide and

Valid Combinations

BOOT CODE SECTO R ARCHITEC TURE

T = Top sector

B = Bottom sector

Valid Combinations

AM29F002BT-55

AM29F002BB-55

AM29F002NBT-55

AM29F002NBB-55

PC, JC, JI, EC, EI

AM29F002BT-70

AM29F002BB-70

AM29F002NBT-70

AM29F002NBB-70

PC, PI, JC, JI, EC, EI

AM29F002BT-90

AM29F002BB-90

AM29F002NBT-90

AM29F002NBB-90 PC, PI, PE,

JC, JI, JE,

EC, EI, EE

AM29F002BT-120

AM29F002BB-120

AM29F002NBT-120

AM29F002NBB-120

Am29F002B/Am29F002NB 7

DEVI CE BUS OPERATIONS

This section describes the requirements and use of the

device bus ope rations, which are in itiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The cont ents of

the register serve as inputs to the internal state

machine. The state machine o utputs dictate the func -

tion of the device. The appropriate device bus

operations table lists the inputs and control levels

required, and the resulting output. The following sub-

sections describe each of these operations in further

detail.

Table 1. Am29 F002B/A m29F002NB Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, A

= Address In

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. This function requires

the RESET# pin and is therefore not available on the Am29F002NB device.

Requirements for Reading Array Data

To read array data from the outputs, the system must

dr ive the CE# and OE# pins to V IL. CE# is the p ower

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at VIH.

The internal state machine is set for reading array data

upon device pow er-u p, or aft er a har dwar e rese t. Thi s

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standa rd microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

See “Reading Array Data” for more infor mation. Refer

to the AC Read Operations table for timing specifica-

tio ns and to th e Read Op erat ions Ti ming s diagr am for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the sy stem must drive WE# and

CE# to VIL, and OE# to VIH.

An erase operation can e r ase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “ sect or ad dres s” consi sts of t he add res s bit s r equi red

to uniquely select a sector. See the Command Defini-

tions section for details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the “Autoselect Mode” and

Autoselect Command Sequence sections for more

information.

ICC2 in the DC Characteristics table represents the

active current specification for the write mode. The “A C

Characteristics” section contains timing specification

tables and timing diagrams for write ope rations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and ICC

read specifications apply. Refer to “Write Operation

Operation CE# OE# WE# RESET#

(n/a Am29F002NB) A0–A17 DQ0–DQ7

Read L L H H AIN DOUT

Write L H L H AIN DIN

CMOS Standby VCC ± 0.5 V X X H X High-Z

TTL Standby H X X H X High-Z

Output Disable L H H H X High-Z

Reset (n/a on Am29F002NB) X X X L X High-Z

Temporary Sector Unprotect

(See Note) XXX V

ID XX

8 Am29F002B/Am29F002NB

Status” fo r mor e infor mati on, and to each AC Cha rac-

teristics se ction for timing diagrams.

Stand by Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, cur re n t c on sum pt i on i s gr ea tl y r ed uce d, an d t he

outp uts are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when CE#

and RESET# p ins ( CE# onl y on the Am 29F002 NB) are

both held at VCC ± 0.5 V. (Note that this is a more

restricted voltage range than VIH.) The device enters

the TTL standby mode when CE# and RESET# pins

(C E# onl y on th e Am 29F 002NB ) are both held at VIH.

The de vic e re quire s s tanda rd a cces s t ime (t CE) f or read

access when the device is in either of these standby

modes, before it is ready to read data.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, ICC3 represents the

standby current specification.

RESET#: Hardware Reset Pin

Note: The RESET# pin is not available on the

Am29F002NB.

The RESET# pin p ro vides a hardware method of reset-

ting the device to reading array data. When the system

drives the RESET# pin low fo r at least a period of tRP

the device immediately terminates any operation in

progr ess , tr istat es all da ta outp ut pi ns, and ig nore s all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state

machine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to

ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VIL, the device enters

the TTL standby mode; if RESET# is held at VSS ±

0.5 V, the device enters the CMOS standby mode.

The RESET# pin may be tied to the system reset cir-

cuitr y. A syste m reset wo uld thus also rese t the F lash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the AC Characteristics tables for RESET#

parameters and timi ng diagram.

Output Disable Mode

Whe n t h e O E# i n pu t is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29F002B/Am29F002NB Top Boot Block Sector Address Table

Sector A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Rang e

(in hexadecimal)

SA0 0 0 X X X 64 00000h–0FFFFh

SA1 0 1 X X X 64 10000h–1FFFFh

SA2 1 0 X X X 64 20000h–2FFFFh

SA3 1 1 0 X X 32 30000h–37FFFh

SA411100 8 38000h–39FFFh

SA511101 8 3A000h–3BFFFh

SA61111X 16 3C000h–3FFFFh

Am29F002B/Am29F002NB 9

Ta ble 3. Am29F002B/Am29F002NB Bo ttom Boot Block Sector Address Ta ble

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a de vice to be programmed with

its co rresponding programming algorithm. However,

the aut oselec t co des c an also be a cces sed in -sy stem

through the command register.

When using programming equipment, the autoselect

mode re qui res V ID on address pin A9. Address pins A6,

A1, and A0 must be as shown in Autoselect Codes

(High V oltage Method) table. In addition, when verifying

sector protection, the sector address must appear on

the appropriate highest order address bits. Ref er to the

co rresp ondin g Se ctor A ddr ess Ta bles. The Comm and

Definitions table shows the remaining address bits that

are do n’ t car e. W h en all n ec essa ry bit s h ave b ee n se t

as required, the programming equipment may then

read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Comm and Defini-

tions table. This method does not require VID. See

“Command Definitions” for details on using the autose-

lect mode.

Table 4. Am29F002B/Am29F002NB Autoselect Codes (High Voltage Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don’t care.

Sector A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Rang e

(in hexadecimal)

SA00000X 16 00000h–03FFFh

SA100010 8 04000h–05FFFh

SA200011 8 06000h–07FFFh

SA3 0 0 1 X X 32 08000h–0FFFFh

SA4 0 1 X X X 64 10000h–1FFFFh

SA5 1 0 X X X 64 20000h–2FFFFh

SA6 1 1 X X X 64 30000h–3FFFFh

Description CE# OE# WE#

A17

A13

A12

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL 01h

Device ID:

Am29F002B/Am29F002NB

(Top Boot Block)

LLH

XXV

ID XLXLH B0h

LLH

Device ID:

Am29F002B/Am29F002NB

(Bottom Boot Block)

LLH

XXV

ID XLXLH 34h

LLH

Sector Protection Verification L L H SA X VID XLXHL

01h

(protected)

00h

(unprotected)

10 Am29F002B/Am29F002NB

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

progra m and era se operations in previou sly prote cted

sectors.

Sector protection/unprotection must be implemented

using programming equipment. The procedure

requires a high voltage (VID) on addr ess pin A 9 and t he

control pins . Details on this method are pro vided in the

supplements, publication numbers 20819

(Am 29F 002B ) and 21 183 (Am2 9F00 2N B) . Contac t an

AMD representative to obtain a copy of the appropriate

document.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

Note: This feature requires the RESET# pin and is

theref ore not available on the Am29F002NB.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to VID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected

sectors are prote cted a gain. Figure 1 shows the algo -

rithm, and the Temporary Sector Unprotect diagram

shows the timing w a veforms, for this feature.

Figure 1. Temporary Sector Unprotect Opera tion

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect

Completed (Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

21527B-4

Am29F002B/Am29F002NB 11

Hardware Data Pro tection

The command sequence requiremen t of unloc k cycles

for programming or erasing provides data protection

against inadverten t writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

pr otec ti on mea sures pre v ent ac cid enta l er asur e or pr o-

gramming, which might otherwise be caused by

spurious system le vel signals during VCC pow er-up and

power-down transitions, or from system noise.

Low VCC Writ e Inhibit

When VCC is less than VLKO, the device does not

accept any write cycles. This protects data during VCC

power-up and power-down. The command register and

al l int ernal prog ra m/er ase circ uit s are di sa ble d, an d the

de v i ce r es e t s. Sub s eq ue nt wri t es ar e ig n or ed un t i l VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. T he internal state machine is automatically

reset to reading array data on power-up.

12 Am29F002B/Am29F002NB

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. The Command Definitions table defines the

valid re gister command sequences. Writin g incorrect

address and data values or writing them in the

improper s equ en ce resets the device to reading arra y

data.

All addresses are latched on the fall ing edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Character ist ics” section .

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Em be dde d E rase alg or it hm .

After t he de vice accepts an Erase Sus pend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data . A fte r co mpletin g a pr ogra mm ing operation in th e

Erase Suspend mode, the system may once again

read array data with the same exce ption. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The system

must

issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Comma nd” section, next.

See also “Requirements f or Reading Array Data” in the

“D evice Bus Operations” section for mo re information .

The Read Operations table provides the read parame-

ters , and Read Opera tio n Tim ings d iagra m shows th e

timing diagram.

Reset Command

Writing the reset command to the device resets the

device to re ading array data. Address bits are don’t

care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

bef ore erasing begins. This resets the device to reading

array data . Once erasure begins, however, the device

ignores reset commands until the operation is

complete.

The reset command may be written between the

sequence cycles in a program command sequence

before p rogramming begins. Th is rese ts the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, t he d evice igno res reset co mman ds u ntil th e

operation is complete.

The reset command may be written between the

seque nce cycles in an autoselec t comm and sequence.

Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies

to autoselect during Eras e Suspend).

If DQ5 goes hi gh du ring a prog ram or eras e oper ation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manuf acturer and de vices codes,

and determine whether or not a sector is protected.

The Command Definitions t able s hows the address

and data req uir emen ts. Th is method is an alt ernat iv e to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

se quen ce.

A rea d cycle at ad dr ess X X00 h or re trieves the m anu -

facturer code. A read cycle at address XX01h returns

the device code. A read cycle containing a sector

address (SA) and the address 02h in returns 01h if that

se cto r i s pro te c te d, o r 0 0h i f it i s un pr ot ec te d. R efer t o

the Sector Address tables for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

co mman d. T he pr ogram addr ess a nd data are wri tten

next, which in turn initiate the Embedded Program

algorithm. The system is

not

required to provide further

co ntrols or tim ing s. The device au toma tica lly p rovides

in te rnal l y ge ner at e d pr og r a m p u lse s a nd verif y t h e pr o-

grammed cell margin. The Command Definitions take

sh ows the addr ess an d d ata re quire me nts for t he byte

program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

Am29F002B/Am29F002NB 13

DQ7 or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored. On the

Am29F002B only, note that a hardware reset during

the secto r eras e o pe rati o n imm ed iately te r m ina tes th e

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so ma y halt

the op eration and set DQ5 to “ 1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. Ho wever, a succeeding read will show that the

data is still “0 ”. Only era se operat ions ca n convert a “0”

to a “1”.

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 2. Program Ope r ati on

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cyc les, followed by a set- up com mand . Two a ddition al

unlock write cycles are then followed by the chip e rase

command, which in tur n invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

eras e. Th e system is not re qui red to provi de any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip er ase comma nd sequence.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. On the

Am29F002B only, note that a hardware reset during

the secto r era se o pe rat io n imm ed i ate ly te r m i na te s th e

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, or DQ2. See “Write

Opera tio n St atus” for i nform ation on t hese stat us bi ts.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

Figure 3 illustrates the algorithm for the erase opera-

tio n. See th e Era se/Pr ogram O perat ions tabl es in “AC

Characteristics” f or parameters, and to the Chip/Sector

Era se O pe ratio n Ti m ings fo r timi n g wavefor ms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

addit ional unlock writ e cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the

sector era se command sequence.

The device does

not

require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and v erifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors ma y be from one sector to all secto rs. The time

between these add itional cycle s must be le ss than 5 0

µs , ot he r wise th e l a st ad dr es s an d c o mma nd mig ht n ot

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21527B-5

14 Am29F002B/Am29F002NB

in te rru pt s c a n be r e-e na b l e d aft er t h e las t Se c tor E r a se

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addr esses and comman ds.

The sy st em c an mo ni t or DQ 3 to det e rmi ne i f the s ect or

erase timer has timed out. (S ee the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Er a se S us pen d c o mma nd is valid . A l l ot he r c o mma nds

are ignored. On the Am29F002B only , note that a hard-

ware reset during the sector erase operation

immediately terminates the operation. The Sector

Erase command sequence should be reinitiated once

the device has returned to reading array data, to

ensure data integrity.

When the Embedded Erase algorithm i s com ple te, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, or

DQ 2. Refer to “ Writ e O pe ration St atu s” for infor m ati o n

on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

Notes:

1. See the appropriate Command Definitions table f or erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21527B-6

Am29F002B/Am29F002NB 15

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Sus pe nd c om m an d.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The de vice “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is activ ely erasing or is erase-sus-

pended. See “Write Operation Status” for information

on these status bits.

After an erase-suspended program operation is com-

plete, the system can once again read arra y data within

non-suspended sectors. The system can determine

the status of the program operation using th e DQ7 or

DQ 6 s tatus b its , ju st a s in th e s tan da rd pr ogra m op er -

ation. See “Write Operation Status” for more

information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid oper ation. See “Autoselect Co mmand Sequence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to e xit the erase suspend

mode an d c o nti n ue t he s ect or er as e o pe r ati on . Fu rt h er

writes o f the Resume command are ignored. Anot her

Erase Suspend command can be written after the

device has resumed erasing.

16 Am29F002B/Am29F002NB
Table 5. Am29F002B/Am29F002NB Command Definitions
Legend:
X = Don’t care
RA = Address of the memor y loca tion to be read. 
RD = Data read from location RA duri ng read operation.
PA = Address of the memor y location to be programmed. 
Addresses latch on the fal ling edge of the WE# or CE# pulse,  
whichever happens later .
PD = Data to be programmed  at location PA. Data l atches  on the 
rising edge of WE# or CE# pulse, whichever  happens first.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Addr ess bits A17–A13 uniquely select any sector .
Notes:
1. See Tab le 1 for description of bus operat ions.
2. All values are in hexadecima l.
3. Except  w hen reading arr ay or autosel ect  dat a, all bus cycles 
are write operations.
4. Address bi ts A17–A12 are don’t cares for unlock and 
comm and cycl es, except when PA or SA is required.
5. No unlock or command cycle s required when reading array 
data.
6. The Reset comm and is required to return to reading array 
data when dev ice is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
7. The four th cycle of the autoselect  command sequence i s a 
read cycle.
8. The data is 00h for an unprotected sector and 01h for a 
prote cted sector. See “Autoselect Command Sequenc e” for 
more information.
9. The system may read and program in non-erasing sectors, or 
enter  the a utose lect mode, when in the Eras e Suspend 
mode. The Erase Sus pend comm and is valid only  during a 
sect or erase oper ation.
10. The Er ase Resume com mand is vali d only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles ( Notes 2–4)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Not e 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X 00 01
De vice ID, 
Top Boot Block  4 555 AA 2AA 55 555 90 X01 B0
Device ID,
Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 34
Sector Protect Veri fy  
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resum e (Note 10) 1 XXX 30
Cycles

Am29F002B/Am29F002NB 17

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 6 and the following subsections describe

the functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

opera tio n is comple te or in progr ess. Th ese thre e bits

are di scu s se d fi rst .

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

sy ste m w h et he r an E mb ed d ed A lgo ri t hm is in pr og r es s

or completed, or whether the device is i n Eras e Sus -

pend. Data# Polling is valid after the r ising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Em bedde d Pr ogram a lgor ithm i s comp lete, t he devic e

outputs the datum programmed to DQ7. The system

mus t p rovi d e th e p ro gram ad dr es s to r ea d val id statu s

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

appr oxim at el y 2 µs, then the device returns to reading

array da ta.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produc es a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

P olling on DQ7 is active f or appro ximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

When the sys tem detects DQ7 h as changed from the

complement t o true data, it can r ead va lid da ta at DQ7–

DQ0 on the

following

read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data#

Polling Timings (During Embedded Algorithms) figure

in the “AC Cha racterist ics” section illustrates th is.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21527B-7

Figure 4. Data# Polling Algorithm

18 Am29F002B/Am29F002NB
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mod e.  To gg l e Bi t I m ay be re ad  at any add re ss,  an d is
valid aft er the ri sing  edge of the fi n al W E# pulse in th e
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may use either OE#
or CE# to contr ol the read cycles.) When the operation
is comp lete, DQ6 stops toggling.
After an erase command sequence is written, if all
sec tor s se lect ed f o r e ras ing  are  prot ect ed,  DQ6  togg les
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
prot ect ed. 
The sys tem can use DQ6 and DQ2 toge ther to deter -
mine whethe r a sector is actively eras ing or is era se-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are  erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see t he subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggle s for approximately 2 µs after the program
command sequence is written, then returns to reading
array da ta.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
The  Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsect ion  on DQ2: Toggle Bi t II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or w het her  that s ecto r is e ras e-susp ende d. Tog gle  Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is  in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6. 
Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. Se e also the DQ6 : Toggle Bit I sub section.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at lea st twice in  a row to
deter mine whether  a  toggle bit is toggling . Typically,  a
system would note and store the value of the toggle bit
after the first read. After the second read , the system
would compare  the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted  the program o r erase op erat ion. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cyc les, t he system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whet her the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the sys tem mus t wr ite the r eset com man d to retur n to
reading array data. 
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system ma y continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ 5  in dic ate s  wh ether the  pr ogra m  or  e rase  time  ha s
ex cee de d a  spe cifie d inter nal pu lse coun t limit. Under
thes e co ndi tions D Q5  produ ces  a “1 .” Th is is  a failur e
condition  that indicates the  progr am or era se  cycle w as
not successfully completed. 

Am29F002B/Am29F002NB 19

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is pre viously pro-

gr am med to “ 0.” Onl y an erase operation can change

a “0” back to a “ 1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Und er both th ese c ond itio ns , th e s ystem mu st issu e t he

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for er asure, th e entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” The system may ignore DQ3 if the

system can guarantee that the time between additional

sector erase commands will a lwa ys be less than 50 µs.

See also the “Sector Erase Command Sequence”

section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensu re the devic e has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. I f DQ3 is high on the second st atus

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Rechec k toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21527B-8

Figure 5. To ggle Bit Algorithm

(Notes

1, 2)

(Note 1)

20 Am29F002B/Am29F002NB

Table 6. Write Operation Status

Notes:

1. DQ7 and DQ2 require a v alid address when reading status information. Ref er to the appropriate subsection for further details .

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 DQ2

(Note 1)

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle

Embedded Erase Algor ithm 0 Tog gle 0 1 Toggle

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle

Reading within Non-Erase

Suspended Sector Data Data Data Data Data

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

Am29F002B/Am29F002NB 21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V

–2.0 V for periods of up to 20 ns. See . Maximum DC

voltage on input or I/O pins is

+0.5 V. During voltage

transitions, input or I/O pins ma y o vershoot to V

+2.0 V

for periods up to 20 ns. See .

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V

to –2.0 V for periods of up to

20 ns. See . Maximum DC input voltage on pin A9 is +12.5

V which may overshoot to +13.5 V for periods up to 20 ns.

(RESET# is not available on Am29F002NB)

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Tempe ratur e ( TA) . . . . . . . . . . .0°C to +70°C

Industrial (I ) Device s

Ambient Tempe ratur e ( TA) . . . . . . . . .–40°C to +85°C

Extended (E) De vic es

Ambient Tempe ratur e ( TA) . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

VCC for ± 10% devices . . . . . . . . . . . +4.5 V to +5.5 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Figure 1. Figure 2. Maximum P o sitive Overshoot

Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21527B-9

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21527B-10

22 Am29F002B/Am29F002NB
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum I
CC
 specifications are tested with V
CC
 = V
CCmax
.
3. The I
CC
 current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
4. I
CC
 active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET# Input Load Current
(Notes 1, 5) VCC = VCC max; 
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current (Notes 2, 3) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current (Notes 2, 4, 5) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Note 2) CE#, OE# = VIH 0.4 1 mA
ICC4 VCC Reset Current (Notes 1, 2) RESET# = VIL 0.4 1 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC 
+ 0.5 V
VID Voltage for Autoselect and Temporary 
Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

Am29F002B/Am29F002NB 23
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum I
CC
 specifications are tested with V
CC
 = V
CCmax
.
3. The I
CC
 current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
4. I
CC
 active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
6. I
CC3
 and I
CC4
 = 20 µA max at extended temperature (>+85
° 
C).
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET#
Input Load Current (Notes 1, 5) VCC = VCC max; 
A9, OE#, RESET# = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 2, 3) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current 
(Notes 2, 4, 5) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current 
(Notes 2, 6) CE# = VCC ± 0.5 V 1 5 µA
ICC4 VCC Reset Current 
(Notes 1, 2, 6) RESET# = VIL 15µA
V
IL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO L ow VCC Lock-Out Voltage  3.2 4.2 V

24 Am29F002B/Am29F002NB

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHIN G WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

21527B-11

Figure 3. Test Setu p

Note: Diodes are IN3064 or equivalent

Test Condition -55 All

others Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8, 2.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Am29F002B/Am29F002NB 25

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Table 7 and Figure 3 for test specifications.

Parameter

Description

Speed Options

JEDEC Std Test Setup -55 -70 -90 -120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 55 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 15 20 20 30 ns

tGHQZ tDF Output Enable to Output High Z

(Note 1) Max15202030ns

OEH

Output Enable

Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH Output Hold Time From Addresses, CE#

or OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

RESET#

n/a Am29F002NB

tDF

tOH

21527B-12

Figure 4. Read Operations T imin gs

26 Am29F002B/Am29F002NB

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested. RESET# is not available on Am29F002NB.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

RESET#

n/a Am29F002NB tRP

tReady

Reset Timings NOT during Embedded Algorithms

CE#, OE#

tRH

Reset Timings during Embedded Algorithms

RESET#

n/a Am29F002NB tRP

21527B-13

Figure 5. RESET# Timings

Am29F002B/Am29F002NB 27

AC CHARACTERISTICS

Erase/Pr ogram Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description -55 -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 45 45 50 ns

tDVWH tDS Data Setup Time Min 25 30 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min0ns

ELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 30 35 45 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

28 Am29F002B/Am29F002NB

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

tCH

Notes:

1. PA = program address, PD = program data, D

OUT

is the true data at the program address.

21527B-14

Figure 6. Program Operation Timings

Am29F002B/Am29F002NB 29

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

Notes:

1. SA = sector address (for Sector Erase), VA = V alid Address f or reading status data (”see “Write Operation Status”).

21527B-15

Figure 7. Chip/Sector Erase Opera tio n Timings

30 Am29F002B/Am29F002NB

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

DQ7

DQ0–DQ6

Complement True

Addresses VA

OEH

VA VA

Status Data

Complement

Status Data True

Valid Data

ACC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21527B-16

Figure 8. Data# P olling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = Valid address; not required f or DQ6. Illustr ation shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

21527B-17

Figure 9. Toggle Bit Timings (During Embedded Algorithms)

Am29F002B/Am29F002NB 31

AC CHARACTERISTICS

Temporary Sector Unprotect (Am 29F002B only)

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21527B-18

Figure 10. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5 V

21527B-19

Figure 11. Temporary Sector Unprotect Ti ming Diagram (Am29F002B only)

32 Am29F002B/Am29F002NB

AC CHARACTERISTICS

Alter nate CE# Controlled Erase/Pr og ram Operati ons

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std. Description -55 -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 50 ns

tDVEH tDS Data Setup Time Min 25 30 45 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 30 35 45 50 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

Am29F002B/Am29F002NB 33

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

Notes:

1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, D

OUT

= data written to device.

2. Figure indicates the last two bus cycles of the command sequence.

21527B-20

Figure 12. Alternate CE# Controll ed Write Operation Timings

34 Am29F002B/Am29F002NB

ERASE AND PROGRAMMING P E RFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25×C, 5.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V (4.75 V for ±5% devices), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except V

. Test conditions: V

= 5.0 V, one pin at a time. RESET# not available on Am29F002NB.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 7 s

Byte Programming Time 7 300 µs Excludes system level

overhead (Note 5)

Chip Programming Time (Note 3) 1.8 5.4 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Am29F002B/Am29F002NB 35

PLCC AND PDIP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

CIN Input Capacitance VIN = 0 4 6 pF

COUT O utput Capac itance VOUT = 0 8 12 pF

CIN2 Control Pin Capacita nce VPP = 0 8 12 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

36 Am29F002B/Am29F002NB

PHYSICAL DIMENSIONS

PD 032

32-Pin Plastic DIP (measured in inches)

PL 032

32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.680

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .014

.022

SEATING PLANE

.015

.060

16-038-SB_AG

PD 032

DG75

2-28-95 ae

32 17

16 .630

.700

0˚

10˚

.600

.625

.008

.015

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530

Am29F002B/Am29F002NB 37

PHYSICAL DIMENSIONS (co ntinued)

TS 0 3 2

32-Pin Standard Thin Small P ackage (measured in millimeters)

Pin 1 I.D.

18.30

18.50

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TS 032

DA95

3-25-97 lv

19.80

20.20

1.20

MAX

0.50

0.70

0.10

0.21

0˚

5˚

0.08

0.20

38 Am29F002B/Am29F002NB

.REVISION SUMMARY

Revision B

Distinctive Characteristics

Added:

■20-year data retention at 125°C

— Reliable operation for the life of the system

AC Characterisitics—Read Operations Table

EHQZ

, t

GHQZ

: Changed the 55 speed option to 15 ns

from 20 ns

AC Characteristics—Erase/P rogram Operations

WLAX

: Change d the 9 0 spee d option to 45 n s fro m 50 ns .

DVWH

: Cha nged the 5 5 spe ed opt ion to 25 n s fr om 30 ns.

WLWH

: ch anged t he 55 spe ed opti on t o 30 ns fro m 35 ns .

AC Characteristics—Alter nate CE# Controlled

Erase/Program Operations

DVEH

: Changed the 55 speed option to 25 ns from 30 ns.

ELEH

: Ch ang ed th e 5 5 s peed op ti on t o 3 0 n s fr om 3 5 ns.

ELAX

: Change d t he 90 speed opt i on to 45 ns f rom 50 ns.

DC Characteristics— TTL/NMOS Compat ible

CC1

, I

CC2

, I

CC3

CC4

: Added Note 2 “Maximum ICC

sp ecificati o ns are test e d wit h VCC = VCCmax”.

DC Characte ristics—CMOS Compatible

CC1

, I

CC2

, I

CC3

CC4

: Added Note 2 “Maximum ICC

sp ecificati o ns are test e d wit h VCC = VCCmax”.

Trademarks

AMD, the AMD logo, and combinations thereof are regis tered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Mi cro Devices, Inc.

Product names used i n this publication are for identification purposes only and may be trademarks of their respective companies