18 Am29F002B/Am29F002NB
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mod e. To gg l e Bi t I m ay be re ad at any add re ss, an d is
valid aft er the ri sing edge of the fi n al W E# pulse in th e
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may use either OE#
or CE# to contr ol the read cycles.) When the operation
is comp lete, DQ6 stops toggling.
After an erase command sequence is written, if all
sec tor s se lect ed f o r e ras ing are prot ect ed, DQ6 togg les
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
prot ect ed.
The sys tem can use DQ6 and DQ2 toge ther to deter -
mine whethe r a sector is actively eras ing or is era se-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see t he subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggle s for approximately 2 µs after the program
command sequence is written, then returns to reading
array da ta.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsect ion on DQ2: Toggle Bi t II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or w het her that s ecto r is e ras e-susp ende d. Tog gle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. Se e also the DQ6 : Toggle Bit I sub section.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at lea st twice in a row to
deter mine whether a toggle bit is toggling . Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read , the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program o r erase op erat ion. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cyc les, t he system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whet her the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the sys tem mus t wr ite the r eset com man d to retur n to
reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system ma y continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ 5 in dic ate s wh ether the pr ogra m or e rase time ha s
ex cee de d a spe cifie d inter nal pu lse coun t limit. Under
thes e co ndi tions D Q5 produ ces a “1 .” Th is is a failur e
condition that indicates the progr am or era se cycle w as
not successfully completed.