SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008C – MARCH 1984 – REVISED MARCH 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
Low Power Consumption, 80-µA Max ICC
D
Typical tpd = 12 ns
D
±6-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
Inputs Are TTL-Voltage Compatible
D
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive Up
To 15 LSTTL Loads
D
Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
description/ordering information
These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout
with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit
board layout.
The 3-state control gate is a 2-input NOR. If either output-enable (OE1 or OE2) input is high, all eight outputs
are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74HCT540N SN74HCT540N
–40°C to 85°C
SOIC DW
Tube SN74HCT540DW
HCT540
SOIC
–
DW
Tape and reel SN74HCT540DWR
HCT540
–55°C to 125°CCDIP – J Tube SNJ54HCT540J SNJ54HCT540J
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer/driver)
INPUTS OUTPUT
OE1 OE2 AY
L L L H
LLH L
HXX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54HCT540 ...J PACKAGE
SN74HCT540 . . . DW OR N PACKAGE
(TOP VIEW)
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008C – MARCH 1984 – REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
218
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT540 SN74HCT540
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
ttInput transition (rise and fall) time 500 500 ns
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008C – MARCH 1984 – REVISED MARCH 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HCT540 SN74HCT540
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
VI=V
IH or VIL
IOH = –20 µA
45V
4.4 4.499 4.4 4.4
V
V
OH
V
I =
V
IH
or
V
IL IOH = –6 mA
4
.
5
V
3.98 4.3 3.7 3.84
V
VOL
VI=V
IH or VIL
IOL = 20 µA
45V
0.001 0.1 0.1 0.1
V
V
OL
V
I =
V
IH
or
V
IL IOL = 6 mA
4
.
5
V
0.17 0.26 0.4 0.33
V
IIVI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0, VI = VIH or VIL 5.5 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆ICC†One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA
Ci4.5 V
to 5.5 V 3 10 10 10 pF
†This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HCT540 SN74HCT540
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
td
A
Y
4.5 V 13 20 30 25
ns
t
pd
A
Y
5.5 V 12 18 27 23
ns
t
OE
Y
4.5 V 20 30 45 38
ns
t
en
OE
Y
5.5 V 18 27 41 34
ns
tdi
OE
Y
4.5 V 19 30 45 38
ns
t
dis
OE
Y
5.5 V 18 27 41 34
ns
tt
Y
4.5 V 8 12 18 15
ns
t
t
Y
5.5 V 711 16 14
ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HCT540 SN74HCT540
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
td
A
Y
4.5 V 20 30 45 38
ns
t
pd
A
Y
5.5 V 19 27 41 34
ns
t
OE
Y
4.5 V 26 40 60 50
ns
t
en
OE
Y
5.5 V 25 36 54 45
ns
tt
Y
4.5 V 17 42 63 53
ns
t
t
Y
5.5 V 14 38 57 48
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per buffer/driver No load 35 pF
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008C – MARCH 1984 – REVISED MARCH 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
CL
(see Note A)
Test
Point
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V1.3 V 0.3 V0.3 V 2.7 V 2.7 V 3 V
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V 10%10% 90% 90%
3 V
VOH
VOL
0 V
trtf
Input
In-Phase
Output
1.3 V
tPLH tPHL
1.3 V 1.3 V
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
W aveform 1
(See Note B)
1.3 V
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
1.3 V
1.3 V
tPZH tPHZ
Output
W aveform 2
(See Note B)
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
JM38510/65760BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
M38510/65760BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN54HCT540J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN74HCT540DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT540N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74HCT540N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74HCT540NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54HCT540FK OBSOLETE LCCC FK 20 TBD Call TI Call TI
SNJ54HCT540J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT540, SN74HCT540 :
•Catalog: SN74HCT540
•Military: SN54HCT540
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HCT540DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT540DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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