bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 SINGLE-CHIP, LI-ION CHARGE MANAGEMENT IC FOR HANDHELD APPLICATIONS (bqTINYTM) FEATURES 1 DESCRIPTION * Small 3 mm x 3 mm MLP (QFN) Package * Ideal for Low-Dropout Designs for Single-Cell Li-Ion or Li-Pol Packs in Space Limited Applications * Integrated Power FET and Current Sensor for Up to 1-A Charge Applications * Reverse Leakage Protection Prevents Battery Drainage * Integrated Current and Voltage Regulation * 0.5% Voltage Regulation Accuracy * Charge Termination by Minimum Current and Time * Precharge Conditioning With Safety Timer * Status Outputs for LED or System Interface Indicates Charge and Fault Conditions * Battery Insertion and Removal Detection * Works With Regulated and Unregulated Supplies * Short-Circuit Protection * Charge Voltage Options: 4.2 V and 4.36 V 2 The bqTINYTM series are highly integrated Li-Ion and Li-Pol linear charge management devices targeted at space limited portable applications. The bqTINYTM series offer integrated powerFET and current sensor, reverse blocking protection, high accuracy current and voltage regulation, charge status, and charge termination, in a small package. The bqTINYTM charges the battery in three phases: conditioning, constant current, and constant voltage. Charge is terminated based on minimum current. An internal charge timer provides a backup safety feature for charge termination. The bqTINYTM automatically re-starts the charge if the battery voltage falls below an internal threshold. The bqTINYTM automatically enters sleep mode when VCC supply is removed. In addition to the standard features, different versions of the bqTINYTM offer a multitude of additional features. These include temperature sensing input for detecting hot or cold battery packs; power good (PG) output indicating the presence of valid input power; a TTL-level charge-enable input (CE) used to disable or enable the charge process; and a TTL-level timer and termination enable (TTE) input used to disable or enable the fast-charge timer and charge termination. APPLICATIONS * * * * Cellular Phones PDAs, MP3 Players Digital Cameras Internet Appliances bq24012DRC AC ADAPTER 1 IN OUT 10 2 VCC BAT 3 STAT1 CE 8 4 STAT2 PG 7 5 VSS PACK+ BATTERY PACK SYSTEM + 9 PACK SYSTEM INTERFACE SET ISET 6 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. bqTINY is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2008, Texas Instruments Incorporated bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA CHARGE REGULATION VOLTAGE (V) (1) -40C to 125C (1) (2) (3) OPTIONAL FUNCTIONS (1) PART NUMBER (2) (3) MARKINGS 4.2 PG and TS bq24010DRCR AZN 4.2 PG and CE bq24012DRCR AZP 4.2 CE and TTE bq24013DRCR AZQ 4.2 CE and TS 4.36 CE and TTE bq24014DRCR AZR bq24014DRCT bq24018DRCR BZH bq24018DRCT Contact Texas Instruments for other options. The DRC package is available only taped and reeled. Quantities are 3,000 devices per reel (e.g. bq24010DRCR) and 250 devices per mini-reel (e.g. bq24014DRCT). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT -0.3 to 18 V -0.3 to VCC V -0.3 to 7 VDC 0.5 V Supply voltage range, (VCC all with respect to VSS) IN, STAT1, STAT2, TS, PG, CE, TTE Input voltage range (2) BAT, OUT, ISET Voltage difference between VCC and IN inputs VCC - VIN Output sink/source current STAT1, STAT2, PG 15 Output current IN, OUT 1.5 TA Operating free-air temperature range TJ Junction temperature range Tstg Storage temperature (1) (2) -40 to 125 C -65 to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are DC and with respect to VSS. DISSIPATION RATINGS (1) PACKAGE JA TA < 40C POWER RATING DERATING FACTOR ABOVE TA = 40C DRC (1) 47C/W 1.5 W 0.021 W/C1 This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2x3 via matrix. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MAX UNIT VCC Supply voltage (1) (2) MIN 3 16.5 V VIN Input voltage (1) (2) 3 16.5 V TJ Operating junction temperature range -40 125 C (1) (2) 2 NOM Pins VCC and IN must be tied together. If Vin is between UVLO and 4.35V, and above the battery voltage, then the IC is active (can deliver some charge to the battery), but the IC will have limited or degraded performance (some functions may not meet data sheet specifications). The battery may be undercharged (VO(reg) less than in the specification), but will not be overcharged (VO(reg) will not exceed specification). Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS over 0C TJ 125C and recommended supply voltage, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0 3.5 5 mA 5 A 500 nA INPUT CURRENT ICC(VCC) VCC current VCC > VCC(min), STATx pins in OFF state ICC(SLP) Sleep current Sum of currents into OUT and BAT pins, VCC < V(SLP) IIB(BAT) Input bias current on BAT pin IIB(TS) Input current on TS pin IIB(CE) Input current on CE pin 1 IIB(TTE) Input bias current on TTE pin 1 VI(TS) 10 V 1 A VOLTAGE REGULATION VO(REG) + V(DO-MAX) VCC, I(TERM) < IO(OUT) 1 A Output voltage, VO(REG) Voltage regulation accuracy V(DO) Dropout voltage (V(IN) - V(OUT)) bq24010, bq24012, bq24013, bq24014 4.2 bq24018 V 4.36 TA = 25C -0.5% 0.5% -1% VO(REG) + V(DO-MAX)) VCC, IO(OUT) = 1A 1% 650 790 mV CURRENT REGULATION IO(OUT) (1) VCC 4.5 V, VIN 4.5 V, VI(BAT) > V(LOWV), VIN - VI(BAT) > V(DO-MAX) Output current range See note V(SET) Output current set voltage K(SET) Output current ISET factor (2) 100 1000 25 100 mA bq24010, bq24012, bq24013, bq24014 2.45 2.50 2.55 V bq24018 2.548 2.6 2.652 V 50 mA IO(OUT) 1000 mA, V(LOWV) < V(OUT) < V(RCH) 315 335 355 25 mA IO(OUT) < 50 mA, V(LOWV) < V(OUT) < V(RCH) 315 372 10 mA IO(OUT) < 100 mA, V(OUT) < V(LOWV) 350 Voltage on ISET pin, VCC 4.5 V, VIN 4.5 V, VI(BAT) > V(LOWV), VIN - VI(BAT) > V(DO-MAX), VO(REG) = 4.2 V 2.5 mA IO(OUT) < 10 mA, V(OUT) < V(LOWV) 430 1000 450 355 (3) 2.5 mA IO(OUT) < I(PGM), V(OUT) < V(RCH) PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION V(LOWV) Precharge to fast-charge transition threshold Voltage on BAT pin 2.80 2.95 3.10 V V(SC) Precharge to short-charge transition threshold Voltage on BAT pin 1 1.4 1.8 V IO(PRECHG) (4) Precharge range V(SC) < VI(BAT) < V(LOWV), t < t(PRECHG) 100 mV V(PRECHG) Precharge set voltage Voltage on ISET pin, V(SC) < VI(BAT) < V(LOWV) 225 250 280 mV ISC Short circuit current V(SC) > VI(BAT) 660 900 1200 A IO(OUT) = (1) (2) (3) 10 (K(SET) x V(SET) ) R(SET) Specified by design. Not production tested. The ISET pin may be used as a current monitor during voltage regulation by applying the following equation: ae V(ISET ) IO(OUT) = K (ISET ) x c c R(ISET ) + 10 mA e o / / o This equation is also used for calculating the termination point. IO(PRECHG) = (4) (K(SET) x V(PRECHG) ) R(SET) Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 3 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (Continued) over 0C TJ 125C and recommended supply voltage, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 mA CHARGE TAPER AND TERMINATION DETECTION I(TAPER) (1) Charge taper detection range VI(BAT) > V(RCH), t < t(TAPER) V(TAPER) Charge taper detection set voltage Voltage on ISET pin, VI(BAT) > V(RCH), t < t(TAPER), VI(BAT) = VO(REG) 10 V(TERM) Charge termination detection set voltage Voltage on ISET pin, VI(BAT) = VO(REG), VI(BAT) >V(RCH),I(TERM) = K(SET) V(TERM) /R(SET) 225 250 275 mV 5 17.5 50 mV TEMPERATURE COMPARATOR V(TS1) Lower threshold Voltage on TS pin 29 30 31 V(TS2) Upper threshold Voltage on TS pin 60 61 62 Hysteresis %VCC 1 BATTERY RECHARGE THRESHOLD V(RCH) VO(REG) -0.135 Recharge threshold VO(REG) -0.1 VO(REG) -0.075 V 0.5 V STAT1, STAT2, AND PG OUTPUTS VOL Output (low) saturation voltage IO = 10 mA CHARGE ENABLE (CE) AND TIMER AND TERMINATION ENABLE (TTE) INPUTS VIL Low-level input voltage IIL = 1 A 0 VIH High-level input voltage IIL = 1 A 2.0 0.8 V TIMERS t{PRECHG) Precharge time 1, 548 2,065 t(TAPER) Taper time 1, 548 2,065 2,581 2,581 t(CHG) Charge time 15, 480 20,650 25,810 s SLEEP COMPARATOR VSLP Sleep mode entry threshold voltage VCC VI(BAT) + 30 mV VPOR V(IBAT) VO(REG) VCC VI(BAT) + 22 mV Sleep mode exit threshold voltage VPOR V(IBAT) VO(REG) Sleep mode deglitch time VCC decreasing below threshold, 100 ns fall time, 10 mV overdrive 250 V 650 ms BATTERY DETECTION THRESHOLDS I(DETECT) Battery detection current 2 V V(IBAT) V(RCH) -3.1 -4.6 -6.1 mA I(DETECT) battery detection time 2 V V(IBAT) V(RCH) 100 125 150 ms I(FAULT) Fault current V(IBAT) < V(RCH) and/or t > t(PRECHG) 660 900 1200 A 225 2.5 2.75 V POWER-ON RESET AND INPUT VOLTAGE RAMP RATE VPOR (2) Power-on reset threshold voltage IO(TAPER) = (1) (2) 4 (K(SET) x V(TAPER) ) R(SET) Specified by design. Not production tested. Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 DEVICE INFORMATION DRC PACKAGE (TOP VIEW) VSS STAT2 STAT1 VCC 5 4 3 IN 2 1 DRC PACKAGE (TOP VIEW) VSS STAT2 STAT1 VCC 5 bq24010DRC 4 3 2 7 8 9 10 6 7 8 9 ISET PG TS BAT OUT ISET PG CE BAT VSS STAT2 STAT1 VCC 3 10 OUT DRC PACKAGE (TOP VIEW) DRC PACKAGE (TOP VIEW) 4 1 bq24012DRC 6 5 IN IN 2 1 VSS STAT2 STAT1 VCC 5 bq24013DRC and bq24018DRC 4 3 2 IN 1 bq24014DRC 6 7 8 9 10 6 7 8 9 10 ISET CE TTE BAT OUT ISET CE TS BAT OUT Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 5 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL bq24010 bq24012 bq24013 and bq24018 (1) bq24014 BAT 9 9 9 9 I Battery voltage sense input CE - 8 7 7 I Charge enable input (active low) IN 1 1 1 1 I Charge input voltage. This input must be tied to the VCC pin. ISET 6 6 6 6 O Charge current set point OUT 10 10 10 10 O Charge current output PG 7 7 - - O Power good status output (open collector) STAT1 3 3 3 3 O Charge status output 1 (open collector) STAT2 4 4 4 4 O Charge status output 2 (open collector) TTE - - 8 - I Timer and termination enable input (active low) TS 8 - - 8 I Temperature sense input VCC 2 2 2 2 I VCC supply input VSS 5 5 5 5 - Ground input - There is an internal electrical connection between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be connected to the same potential as the Vss pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. NAME Exposed Thermal PAD (1) 6 Pad Pad Pad Pad I/O DESCRIPTION The bq24018 is in product preview status. Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM IN OUT VCC VCC + VI(BAT) VO(REG) ISET CHG ENABLE VCC REFERENCE AND BIAS VCC V(ISET) VSET VO(REG) I(DETECT) ENABLE + I(FAULT) ENABLE CHG ENABLE VI(BAT) V(SLP) DEGLITCH I(FAULT) ENABLE CE I(DETECT) ENABLE TS CHG ENABLE THERMAL SHUTDOWN VSS VI(BAT) CHARGE CONTROL, TIMER, AND DISPLAY LOGIC TTE VO(REG) VI(BAT) V(RCH) DEGLITCH VI(BAT) BAT PG PG RECHARGE PRECHARGE STAT1 VSET V(PRECHG) V(TAPER) VI(SET) VI(SET) V(TERM) DEGLITCH DEGLITCH TAPER STAT2 TERM Dotted lines represent optional features Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 7 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 850 IO(OUT) = 1000 mA 750 Dropout Voltage - mV 650 IO(OUT) = 750 mA 550 450 IO(OUT) = 500 mA 350 250 IO(OUT) = 250 mA 150 50 -50 0 50 150 100 TJ - Junction Temperature - C Figure 1. Regulation Voltage Pre-Conditioning Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase Regulation Current Charge Voltage Minimum Charge Voltage Charge Complete Charge Current Pre-Conditioning and Taper Detect t (PRECHG) t(CHG) t(TAPER) Figure 2. Typical Charging Profile 8 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 FUNCTIONAL DESCRIPTION The bqTINYTM supports a precision Li-Ion, Li-Pol charging system suitable for single-cells. Figure 2 shows a typical charge profile, application circuit and Figure 5 shows an operational flow chart. BATTERY PACK bq24010DRC DC + 1 IN 2 VCC 0.47 mF PACK+ OUT 10 + VCC PACK BAT 9 0.1 mF CHARGE DONE RT1 3 STAT1 TS 8 4 STAT2 PG 7 5 VSS RT2 ISET 6 RSET DCPOWERGOOD Figure 3. Typical Application Circuit USB PORT D+ Dbq24013DRC bq24018DRC 1 VBUS IN OUT 10 2 VCC BAT 9 3 STAT1 TTE 8 4 STAT2 CE 7 PACK+ BATTERY PACK + GND PACK- SYSTEM and USB CONTROLLER 0.47 mF 0.1 mF 2.26 kW 5 VSS ISET 6 SI1032x 100 mA / 500 mA 9.09 kW Figure 4. USB Charger Circuit Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 9 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com POR SLEEP MODE VCC > VI(BAT) checked at all times No Indicate SLEEP MODE Yes Regulate IO(PRECHG) VI(BAT) < V(LOWV) Reset and Start t(PRECHG) timer Yes Indicate Charge-in-Progress No Reset all timers start t(CHG) timers Regulate Current or Voltage Indicate Charge-in-Progress No VI(BAT) < V(LOWV) Suspend charge TJ < t(SHTDWN) Yes No Indicate Charge Suspend Yes t(PRECHG) expired? Yes No TJ < t(SHTDWN) t(CHG) expired? No Yes No Yes Fault Condition Yes VI(BAT) < V(LOWV) Indicate Fault No I(TERM) detection ? VI(BAT) > V(RCH) ? Yes No No No t(TAPER) expired? I(TAPER) detection ? Enable I(FAULT) current? Yes No No Yes Yes VI(BAT) > V(RCH) ? Turn off charge Yes Indicate DONE No Disable I(FAULT) current? VI(BAT) < V(RCH) ? Yes Enter Battery Absent Detection Figure 5. Operational Flow Chart 10 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 TEMPERATURE QUALIFICATION NOTE: The temperature qualifications apply only to versions with temperature sense input (TS) pin option (bq24020 and bq24014). Versions of the bqTINY with the TS pin option, continuously monitor battery temperature by measuring the voltage between the TS and VSS pins. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develops this voltage (see Figure 3). The bqTINY compare this voltage against the internal V(TS1) and V(TS2) thresholds to determine if charging is allowed (see Figure 6). The temperature sensing circuit is immune to any fluctuation in VCC since both the external voltage divider and the internal thresholds are ratiometric to VCC. Once a temperature outside the V(TS1) and V(TS2) thresholds is detected the bqTINY immediately suspend the charge. The bqTINY suspends charge by turning off the power FET and holding the timer value (i.e. timers are NOT reset). Charge is resumed when the temperature returns to the normal range. VCC Charge Suspend V(TS2) Normal Temperature Range V(TS1) Charge Suspend VSS Figure 6. TS Pin Thresholds The resistor values of RT1 and RT2 are calculated by Equation 1 and Equation 2 (for NTC Thermistors). RT1 = RT2 = (5 x RTH x RTC ) (3 x (RTC - RTH )) (1) (5 x RTH x RTC ) (2 x RTC ) - (7 x RTH ) (2) Where RTC is the cold temperature resistance and RTH is the hot temperature resistance of thermistor, as specified by the thermistor manufacturer. RT1 or RT2 can be omitted If only one temperature (hot or cold) setting is required. Applying a constant voltage between the VTS1 and VTS2 thresholds to pin TS disables the temperature-sensing feature. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 11 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com BATTERY PRE-CONDITIONING During a charge cycle if the battery voltage is below the V(LOWV) threshold, the bqTINY applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between the ISET and VSS, RSET, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in the specifications table. IO(PRECHG) = (V(PRECHG) x K(SET) ) R(SET) (3) The bqTINY activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not reached within the timer period, the bqTINY turns off the charger and enunciates FAULT on the STAT1 and STAT2 pins. Refer to Timer Fault Recovery section for additional details. BATTERY CHARGE CURRENT The bqTINY offers on-chip current regulation with programmable set point. The resistor connected between the ISET and VSS, RSET, determines the charge rate. The V(SET) and K(SET) parameters are specified in the specifications table. IO(OUT) = (K(SET) x V(SET) ) R(SET) (4) BATTERY VOLTAGE REGULATION Voltage regulation feedback is accomplished through the BAT pin. This input is tied directly and close to the positive side of the battery pack. The bqTINY monitors the battery-pack voltage between the BAT and VSS pins. When the battery voltage rises to VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper down. As a safety backup, the bqTINY also monitors the charge time in the charge mode. If termination does not occur within this time period, t(CHG), the bqTINY turns off the charger and enunciates FAULT on the STAT1 and STAT1 pins. Refer to the Timer Fault Recovery section for additional details. CHARGE TAPER DETECTION, TERMINATION AND RECHARGE The bqTINY monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER), is detected the bqTINY initiates the taper timer, t(TAPER). Charge is terminated after the timer expires. The resistor connected between the ISET and VSS, RSET, determines the taper detection level. The V(TAPER) and K(SET) parameters are specified in the specifications table. I(TAPER) = (V(TAPER) x K(SET) ) R(SET) (5) The bqTINY resets the taper timer in the event that the charge current returns above the taper threshold, I(TAPER). In addition to the taper current detection, the bqTINY terminates charge in the event that the charge current falls below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition or insertion of a fully charged battery. Note that taper timer is not used for I(TERM) detection. The resistor connected between the ISET and VSS, RSET, determines the taper detection level. The V(TERM) and K(SET) parameters are specified in the specifications table. I(TERM) = 12 (V(TERM) x K(SET) ) R(SET) Submit Documentation Feedback (6) Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 After charge termination, the bqTINY restarts the charge once the voltage on the BAT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. See the Battery Absent Detection section for additional details. SLEEP MODE The bqTINY enters the low-power sleep mode if the VCC is removed from the circuit (PG pin is high impedance). This feature prevents draining the battery during the absence of VCC. The status pins do not function when in sleep mode or when VCC < VPOR and default to the OFF state. CHARGE STATUS OUTPUTS The open-collector STAT1 and STAT2 outputs indicate various charger operations as shown in the following table. These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-collector transistor is turned off. When VCC < VPOR or VCC < VBAT (Sleep Mode - PG OFF) the STAT pins default to their OFF state. Note that this STAT1/STAT2 OFF/OFF state is shared by several operating conditions. Monitoring IN, BAT, PG and TS, it is possible to decode the actual fault condition. Table 1. Status Pins Summary CHARGE STATE Charge-in-progress Charge done Battery absent Charge suspend (temperature) Timer fault Sleep mode (1) STAT1 STAT2 ON OFF OFF (1) OFF ON OFF OFF means the open-collector output transistor on the STAT1 or STAT2 pins is in an off state. PG OUTPUT The open-collector PG (power good) indicates when the ac adapter (i.e., VCC) is present. The PG bipolar transistor turns ON when a valid VCC is detected. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. CE INPUT (CHARGE ENABLE) The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the charge and a high-level signal disables the charge. A high-to-low transition on this pin also resets all timers and fault conditions and starts a new charge cycle. TTE INPUT (TIMER AND TERMINATION ENABLE) The TTE digital input is used to disable or enable the fast-charge timer and charge termination. A low-level signal on this pin enables the fast-charge timer and termination and a high-level signal disables this feature. A high-to-low transition on this pin also resets all timers. THERMAL SHUTDOWN AND PROTECTION The bqTINY monitors the junction temperature, TJ, of the die and suspends charging if TJ exceeds 155C. Charging resumes when TJ falls below approximately 130C. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 13 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com BATTERY ABSENT DETECTION For applications with removable battery packs, bqTINY provides a battery absent detection scheme to reliably detect insertion and/or removal of battery packs. The voltage at the BAT pin is held above the battery recharge threshold, V(RCH), by the charged battery following fast charging. When the voltage at the BAT pin falls to the recharge threshold, either by a load on the battery or due to battery removal, the bqTINY begins a battery absent detection test. This test involves enabling a detection current, I(DETECT), for a period of t(DETECT) and checking to see if the battery voltage is below the pre-charge threshold, V(LOWV). Following this, the precharge current, IO(PRECHG) is applied for a period of t(DETECT) and the battery voltage checked again to be above the recharge threshold. The purpose is to attempt to close a battery pack with an open protector, if one is connected to the bqTINY. Passing both of the discharge and charging tests indicates a battery absent fault at the STAT pins. Failure of either test starts a new charge cycle. For the absent battery condition the voltage on the BAT pin rises and falls between the V(LOWV) and VO(REG) thresholds indefinitely. See Figure 7. Charge Done or Timer Fault No VI(BAT) < V(RCH) Yes Enable I(DETECT) for t(DETECT) VI(BAT) < V(LOWV) No BATTERY PRESENT Begin Charge No BATTERY PRESENT Begin Charge Yes Apply IO(PRECHG) for t(DETECT) VI(BAT) > V(RCH) Yes BATTERY ABSENT Figure 7. Battery Absent Detection 14 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 TIMER FAULT RECOVERY As shown in Figure 5, bqTINY provides a recovery method to deal with timer fault conditions. The following conditions summarize this method. Condition #1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs Recovery method: bqTINY waits for the battery voltage to fall below the recharge threshold. This could happen as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the recharge threshold, the bqTINY clears the fault and enters the battery absent detection routine. A POR or CE toggle also clears the fault. Condition #2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs. Recovery method: Under this scenario, the bqTINY applies the I(FAULT) current. This small current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, then the bqTINY disables the I(FAULT) current and executes the recovery method described for condition #1. Once the battery falls below the recharge threshold, the bqTINY clears the fault and enters the battery absent detection routine. A POR or CE toggle also clears the fault. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 15 bq24010, bq24012 bq24013, bq24014, bq24018 SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 ...................................................................................................................................... www.ti.com APPLICATION INFORMATION SELECTING INPUT CAPACITOR In most applications, all that is needed is a high-frequency decoupling capacitor. A 0.47-F ceramic, placed in close proximity to VCC and VSS pins, works well. The bqTINY is designed to work with both regulated and unregulated external dc supplies. If a non-regulated supply is chosen, the supply unit should have enough capacitance to hold up the supply voltage to the minimum required input voltage at maximum load. If not, more capacitance has to be added to the input of the charger. SELECTING OUTPUT CAPACITOR The bqTINY requires only a small output capacitor for loop stability. A 0.1-F ceramic capacitor placed between the BAT and ISET pins is typically sufficient for embedded applications (i.e., non-removable battery packs). For application with removable battery packs a 1-F ceramic capacitor ensure proper operation of the battery detection circuitry. Note that the output capacitor can also be placed between BAT and VSS pins. THERMAL CONSIDERATIONS The bqTINY is packaged in a thermally enhanced MLP (also referred to as QFN) package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled, QFN/SON PCB Attachment application note (SLUA271). The most common measure of package thermal performance is thermal impedance (JA) measured (or modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical expression for JA is: T x TA qJA = J P (7) Where: TJ = device junction temperature TA = ambient temperature P = device power dissipation Factors that can greatly influence the measurement and calculation of JA include: * whether or not the device is board mounted * trace size, composition, thickness, and geometry * orientation of the device (horizontal or vertical) * volume of the ambient air surrounding the device under test and airflown * whether other surfaces are in close proximity to the device being tested The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET. It can be calculated from the following equation: P = VIN - VI(BAT) x IO(OUT) (8) Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 2. 16 Submit Documentation Feedback Copyright (c) 2002-2008, Texas Instruments Incorporated Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 bq24010, bq24012 bq24013, bq24014, bq24018 www.ti.com ...................................................................................................................................... SLUS530J - SEPTEMBER 2002 - REVISED DECEMBER 2008 PCB LAYOUT CONSIDERATIONS It is important to pay special attention to the PCB layout. The following provides some guidelines: * To obtain optimal performance, the decoupling capacitor from VCC to VSS and the output filter capacitors from BAT to ISET should be placed as close as possible to the bqTINY, with short trace runs to both signal and VSS pins. * All low-current VSS connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small signal ground path and the power ground path. * The BAT pin is the voltage feedback to the device and should be connected with its trace as close to the battery pack as possible. * The high current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. * The bqTINY is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application Note (SLUA271). * There is an internal electrical connection between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. Copyright (c) 2002-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): bq24010, bq24012 bq24013, bq24014, bq24018 17 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ24010DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24010DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24012DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24012DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24013DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24013DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24014DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24014DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24018DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24018DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24018DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24018DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24010DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24012DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24013DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24014DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24018DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24018DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24010DRCR SON DRC 10 3000 367.0 367.0 35.0 BQ24012DRCR SON DRC 10 3000 367.0 367.0 35.0 BQ24013DRCR SON DRC 10 3000 367.0 367.0 35.0 BQ24014DRCR SON DRC 10 3000 367.0 367.0 35.0 BQ24018DRCR SON DRC 10 3000 367.0 367.0 35.0 BQ24018DRCT SON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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