ICS9FG104
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DATASHEET
1
Description
The ICS9FG104 is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-
output skew of less than 35 ps. The ICS9FG104 also provides a copy
of the reference clock. Frequency selection can be accomplished via
strap pins or SMBus control.
Key Specifications
• Output cycle-to-cycle jitter < 50 ps
• Output to output skew < 35 ps
• +/-300 ppm frequency accuracy on output clocks
• +/- 150 ppm frequency accuracy @ 100 MHz outputs
• 28-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Features/Benefits
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
• 4 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
• M/N Programming
Funtional Block Diagram
STOP
LOGIC
XIN/CLKIN
X2
DIF(3:0)
CONTROL
LOGIC
SPREAD
FS(2:0)
S D ATA
SCLK
SEL14M_25M#
DIF_STOP#
PROGRAMMABLE
SPREAD PLL
4
IREF
2
OSC
REFOUT
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
2
Pin Configuration
VDD GND
34
9,21 10,20
28 27 IREF, Analog VDD, GND for PLL Core
Description
Pin Number
REFOUT, Digital Inputs
DIF Outputs
Functionality Table
SEL14M_25M#
(
FS3
)
FS2 FS1 FS0 OUTPUT(MHz)
0 0 0 0 100.00
0 0 0 1 125.00
0 0 1 0 133.33
0 0 1 1 166.67
0 1 0 0 200.00
0 1 0 1 266.00
0 1 1 0 333.00
0 1 1 1 400.00
1 0 0 0 100.00
1 0 0 1 125.00
1 0 1 0 133.33
1 0 1 1 166.67
1 1 0 0 200.00
1 1 0 1 266.00
1 1 1 0 333.00
1 1 1 1 400.00
28-pin SSOP/TSSOP
Power Groups
XIN/CLKIN 1 28 VDDA
X2 2 27 GNDA
VDD 3 26 IREF
GND 4 25 **FS0
REFOUT 5 24 **FS1
**FS2 6 23 DIF_0
DIF_3 7 22 DIF_0#
DIF_3# 8 21 VDD
VDD 9 20 GND
GND 10 19 DIF_1
DIF_2 11 18 DIF_1#
DIF_2# 12 17 *SEL14M_25M#
SDATA 13 16 **SPREAD
SCLK 14 15 DIF_STOP#
ICS9FG104
* Pin has internal 120K pull up
** Pin has internal 120K pull down
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 XIN/CLKIN IN Crystal input or Reference Clock input
2 X2 OUT Crystal output, Nominally 14.318MHz
3 VDD PWR Power supply, nominal 3.3V
4 GND PWR Ground pin.
5 REFOUT OUT Reference Clock output
6 **FS2 IN Frequency select pin.
7 DIF_3 OUT 0.7V differential true clock output
8 DIF_3# OUT 0.7V differential Complementary clock output
9 VDD PWR Power supply, nominal 3.3V
10 GND PWR Ground pin.
11 DIF_2 OUT 0.7V differential true clock output
12 DIF_2# OUT 0.7V differential Complementary clock output
13 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
14 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
15 DIF_STOP# IN Active low input to stop differential output clocks.
16 **SPREAD IN Asynchronous, active high input to enable spread spectrum functionality.
17 *SEL14M_25M# IN Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
18 DIF_1# OUT 0.7V differential Complementary clock output
19 DIF_1 OUT 0.7V differential true clock output
20 GND PWR Ground pin.
21 VDD PWR Power supply, nominal 3.3V
22 DIF_0# OUT 0.7V differential Complementary clock output
23 DIF_0 OUT 0.7V differential true clock output
24 **FS1 I/O Frequency select pin.
25 **FS0 IN Frequency select pin.
26 IREF OUT
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
27 GNDA PWR Ground pin for the PLL core.
28 VDDA PWR 3.3V power for the PLL core.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
General SMBus serial interface information for the ICS9FG104
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address DC (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (h)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Sla ve /Re ce iver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Bl o ck Write Operat ion
Slave Address DC(h)
Beginning Byte = N
WRite
starT bit
Co n tr o ller (Ho st)
TstarT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address DD(h)
Index B lock Read Operati o n
Slave Address DC(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Sla ve/Re cei ve r)
Control ler (Host)
X Byte
ACK
ACK
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
5
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function Type 0 1 PWD
Bit 7 RW Pin 17
Bit 6 RW Pin 6
Bit 5 RW Pin 24
Bit 4 RW Pin 25
Bit 3 RW Off On Pin 16
Bit 2 RW Hardware Select Software Select 0
Bit 1 RW Driven Hi-Z 0
Bit 0 RW Down Center 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 1
Bit 6 DIF_3 EN Output Enable RW Disable Enable 1
Bit 5 DIF_2 EN Output Enable RW Disable Enable 1
Bit 4 1
Bit 3 1
Bit 2 DIF_1 EN Output Enable RW Disable Enable 1
Bit 1 DIF_0 EN Output Enable RW Disable Enable 1
Bit 0 1
SMBus Table: Output Stop Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 0
Bit 6 DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 5 DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 4 0
Bit 3 0
Bit 2 DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 1 DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 0 0
Reserved
Reserved
Reserved
See Frequency Selection Table,
Page 1
FS31
FS21
FS11
FS01
-
-
-
-
-
-
-
Byte 2
-
-
-
-
-
-
Byte 1
-
-
-
DIF_STOP# drive mode
SPREAD TYPE
16 Spread Enable1
-Enable Software Control of Frequency, Spread Enable
(Spread Type always Software Control)
24
25
Byte 0
17
6
Reserved
Reserved
Reserved
Reserved
Reserved
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
6
SMBus Table: Frequency Select Readback Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 SEL14M_25M#1
(FS3) State of pin 17 R Pin 17
Bit 6 FS21State of pin 6 R Pin 6
Bit 5 FS11State of pin 24 R Pin 24
Bit 4 FS01State of pin 25 R Pin 25
Bit 3 SPREAD1State of pin 26 R Off On Pin 16
Bit 2 0
Bit 1 0
Bit 0 0
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 RID3 R - - X
Bit 6 RID2 R - - X
Bit 5 RID1 R - - X
Bit 4 RID0 R - - X
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function Type 0 1 PWD
Bit 7 DID7 RW - - 0
Bit 6 DID6 RW - - 0
Bit 5 DID5 RW - - 0
Bit 4 DID4 RW - - 0
Bit 3 DID3 RW - - 1
Bit 2 DID2 RW - - 0
Bit 1 DID1 RW - - 0
Bit 0 DID0 RW - - 0
SMBus Table: Byte Count Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 BC7 RW - - 0
Bit 6 BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4 BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 RW - - 1
Bit 0 BC0 RW - - 1
Reserved
Reserved
Reserved
Device ID = 08 hex
Byte 3
6
27
45
44
See Frequency Selection Table,
Page 1
-
16
VENDOR ID
-
-
-
-
Byte 4
-
REVISION ID
-
-
-
-
-
-
-
Byte 5
-
-
-
-
-
-
Byte 6
Writing to this register will
configure how many bytes will
be read back, default is 07 = 7
bytes.
-
-
-
-
-
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
SMBus Table: Reserved Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
SMBus Table: Reserved Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
SMBus Table: M/N Programming Enable
Pin # Name Control Function Type 0 1 PWD
Bit 7 M/N_Enable M/N Prog. Enable RW Disable Enable 0
Bit 6 1
Bit 5 REFOUT_En REFOUT Enable RW Disable Enable 1
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 PLL N Div8 N Divider Prog bit 8 RW X
Bit 6 PLL N Div9 N Divider Prog bit 9 RW X
Bit 5 PLL M Div5 RW X
Bit 4 PLL M Div4 RW X
Bit 3 PLL M Div3 RW X
Bit 2 PLL M Div2 RW X
Bit 1 PLL M Div1 RW X
Bit 0 PLL M Div0 RW X
-
Byte 10
-
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-Reserved
Reserved
Reserved
Reserved
-Reserved
-
-
-
5
-Reserved
Reserved
Byte 9
-
-
Reserved
Reserved
Reserved
Reserved
Byte 8
-
-
-
-
-
-
-
Byte 7
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
8
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 PLL N Div7 RW X
Bit 6 PLL N Div6 RW X
Bit 5 PLL N Div5 RW X
Bit 4 PLL N Div4 RW X
Bit 3 PLL N Div3 RW X
Bit 2 PLL N Div2 RW X
Bit 1 PLL N Div1 RW X
Bit 0 PLL N Div0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 PLL SSP7 RW X
Bit 6 PLL SSP6 RW X
Bit 5 PLL SSP5 RW X
Bit 4 PLL SSP4 RW X
Bit 3 PLL SSP3 RW X
Bit 2 PLL SSP2 RW X
Bit 1 PLL SSP1 RW X
Bit 0 PLL SSP0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 0
Bit 6 PLL SSP14 RW X
Bit 5 PLL SSP13 RW X
Bit 4 PLL SSP12 RW X
Bit 3 PLL SSP11 RW X
Bit 2 PLL SSP10 RW X
Bit 1 PLL SSP9 RW X
Bit 0 PLL SSP8 RW X
SMBus Table: Reserved Test Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 1
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
-
-
Reserved Test Register. Do not write to this register, erratic device operation may occur.
-
-
-
-
Byte 14
-
-
-
Spread Spectrum
Programming bit(14:8)
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
-
-
-
-
-
-
-
Byte 13
-Reserved
Byte 12
-
Spread Spectrum
Programming bit(7:0)
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
-
-
-
-
-
-
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
-
-
-
-
-
Byte 11
-
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
9
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# - Assertion (transition from '1' to '0')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_STOP# - De-assertion (transition from '0' to '1')
DIF_STOP#
DIF
DIF#
DIF_Stop#
Tdrive_DIF_Stop, 15nS >200mV
DIF
DIF#
DIF Internal
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
10
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage VDD + 0.5V V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V
Ts Storage Temperature -65 150 °C
Tambient Ambient Operating Temp 0 85 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V1
Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1
Input High Current IIH VIN
= VDD -5 5 uA 1
IIL1
VIN = 0 V; Inputs with no pull-
up resistors -5 uA 1
IIL2
VIN = 0 V; Inputs with pull-up
resistors -200 uA 1
Full Active, CL = Full load;
f = 400 MHz 125 150 mA 1
Full Active, CL = Full load;
f = 100 MHz 110 125 mA 1
All outputs stopped driven 106 120 mA 1
All outputs stopped Hi-Z 48 60 mA 1
Input Frequency3FiVDD = 3.3 V 14 25 MHz 3
Pin Inductance1L
p
in 7nH1
CIN Logic Inputs 1.5 5 pF 1
COUT Output pin capacitance 6 pF 1
Clk Stabilization1,2 TSTAB
From VDD Power-Up and after
input clock stabilization to 1st
clock
1.8 ms 1,2
Modulation Frequency fMOD Triangular Modulation 30 33 kHz 1
DIF output enable tDI FOE
DIF output enable after
DIF_Stop# de-assertion 15 ns 1
Input Rise and Fall times tR/tF20% to 80% of VDD 5 ns 1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to
meet
Input/Output
Capacitance1
Input Low Current
IDD3. 3 STOP
IDD3. 3 OP
Operating Supply Current
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
11
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 85°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Output Impedance Zo
1
V
O
= V
x
3000 Ω1
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross Crossing variation over all edges 140 mV 1
Lon
g
Accurac
y
pp
msee T
eriod min-max values -300 300
pp
m1,2,5
400MHz nominal 2.4993 2.5008 ns 2
400MHz s
p
read 2.4993 2.5133 ns 2,3
333.33MHz nominal 2.9991 3.0009 ns 2
333.33MHz s
p
read 2.9991 3.016 ns 2,3
266.66MHz nominal 3.7489 3.7511 ns 2
266.66MHz s
p
read 3.7489 3.77 ns 2,3
200MHz nominal 4.9985 5.0015 ns 2
200MHz s
p
read 4.9985 5.0266 ns 2,3
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz s
p
read 5.9982 6.0320 ns 2,3
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz s
p
read 7.4978 5.4000 ns 2,3
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz s
p
read 9.9970 10.0533 ns 2,3
400MHz nominal/s
p
read 2.4143 ns 1,2
333.33MHz nominal/s
p
read 2.9141 ns 1,2
266.66MHz nominal/s
p
read 3.6639 ns 1,2
200MHz nominal/s
p
read 4.8735 ns 1,2
166.66MHz nominal/s
p
read 5.8732 ns 1,2
133.33MHz nominal/s
p
read 7.3728 ns 1,2
100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fall Time Variation d-t
f
125 ps 1
Duty Cycle d
t3
Measured Differentially 45 55 % 1
Skew, output to output t
sk3
V
T
= 50% 35 ps 4
Jitter, PCI-e SRC phase t
jPCI-ephase14
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock 42 ps 4
Jitter, PCI-e SRC phase t
jPCI-ephase25
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock 39 ps 4
Jitter, Cycle to cycle t
jcyc-cyc
Measured Differentially 50 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
Fi
g
ures are for down s
p
read.
Statistical measurement on single
ended signal using oscilloscope
math function.
5
+/- 150
pp
m for 100 MHz out
p
uts
4
This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
or 25 MHz
mV
Measurement on single ended
signal using absolute value. mV
T
absmin
Average period Tperiod
Absolute min period
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
12
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 85°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Lon
g
Accurac
y
ppm see Tperiod min-max values -300 0 300 ppm 1
14.318MHz output nominal 69.8270 69.8413 69.8550 ns 1
25.000MHz output nominal 39.9880 40.0000 40.0120 ns 1
Output High Voltage VOH IOH = -1 mA 2.4 V 1
Output Low Voltage VOL IOL = 1 mA 0.4 V 1
Output High Current IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V -29 -23 mA 1
Output Low Current IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V 29 27 mA 1
Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 1.6 2 ns 1
Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 1.6 2 ns 1,2
Duty Cycle dt1 VT = 1.5 V 45 52.5 55 % 1,2
Jitter tjcyc-cyc VT = 1.5 V 150 200 ps 1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
Clock period Tperiod
Electrical Characteristics - Phase Jitter (Applies to: Revision D Devices, Revision ID = 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
PCIe Gen 1 specs
(1.5 - 22 MHz) 40 108 ps 1,2
FBD specs
(11-33 MHz) 3ps rms1
PCIe Gen 2 specs
(5-16 MHz, 8-16 MHz) 2.23 3.1 ps rms 1
Notes on Phase Jitter:
2 Specification applies to revision C devices and later.
1 Applicable to all DIF outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not
tested in production.
Jitter, Phase tjphasePLL
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
13
DIF Reference Clock
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch 1
L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1
L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing Dimension or Value Unit Figure
L4 length, Route as couple d microstrip 100 ohm differential trace. 2 min to 16 max inch 1
L4 length, Route as couple d stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector Dimension or Value Unit Figure
L4 length, Route as couple d microstrip 100 ohm differential trace. 0.25 to 14 max inch 2
L4 length, Route as couple d stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2
Figure 1 D own device ro uting.
Rs
Rs
Rt Rt
HSCL Output
Buffer PCI Ex Board
Down Device
REF_CLK Input
L1 L2
L3’
L4
L1’ L2
L3
L4’
Figure 1
Figure 2 PCI Expre ss Connector Routing.
Rs
Rs
Rt Rt
HSCL Output
Buffer PCI Ex
Add In Board
REF_CLK Input
L1 L2
L3’
L4
L1’ L2’
L3
L4’
Figure 2
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
14
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45 v 0.22v 1.08 33 150 100 100
0.58 0.28
0.3
0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 1.2 33 174 140 100 Standard LVDS
R1a = R1 b = R1
R2a = R2 b = R2
Cable connected AC coupled application, figure 4
Component Value Note
R5a,R5b 5%
R6a,R6b
Cc 0.1
0.350
Vcm volts
Figure_3.
R1b
R1a
R2a R2b
HSCL Output
Buffer Down Device
REF_CLK Input
L1 L2
L3’
L4
L1’ L2’
L3
L4’
R3 R4
Figure_4.
PCIe De v i ce
REF_CLK Input
L4
L4’
R6b
R5b
R6a
R5a
3.3 Volts
Cc
Cc
8.2K
5%
uF
1K
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
15
Ordering Information
9FG104yFLFT
Example:
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
XXXX y F LF T
MIN MAX MIN MAX
A -- 2.00 -- .079
A1 0.05 -- .002 --
A2 1.65 1.85 .065 .073
b 0.22 0.38 .009 .015
c 0.09 0.25 .0035 .010
D
E 7.40 8.20 .291 .323
E1 5.00 5.60 .197 .220
e
L 0.55 0.95 .022 .037
N
α0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.90 10.50 .390 .413
10-0033
Reference Doc.: JEDEC Publication 95, MO-150
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
209 mil SSOP
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
16
Ordering Information
9FG104yGLFT
Example:
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G= TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
XXXX y G LF T
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
28 9.60 9.80 .378 .386
10-0035
4.40 mm. Body, 0.65 mm. Pitch TSSOP
6.40 BASIC 0.252 BASIC
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
(173 mil) (25.6 mil)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
INDEX
AREA
12
N
D
E1 E
SEATING
PLANE
A1
A
A2
e
-C-
--
b
c
L
aaa C
α
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
17
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Jap an
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev. Issue Date Description Page #
D 6/2/2005
1. Updated SMBus Byte 3 bit 7, 5, 4 and 3.
2. Updated LF Orderin
g
Information to RoHS Compliant. 9, 13-14
E 1/13/2006 Corrected Pin-Type for Pins 5 and 7. 2
F 4/13/2006 Addded +/- 150 ppm accuracy spec for 100 MHz outputs. 1, 5
G 6/5/2006 Updated SSOP Comon Dimensions Table. 13
H 12/12/2006 Updated pinout to reflect internal pull up and pull down resistors. 1
I 1/2/2007 Fixed Typos on Pin Description. 2
J 4/2/2007 Added Phase Jitter Table. 12
K 4/12/2007 Added TSSOP Ordering Information. 16
L 11/5/2007 Updated to extended temperature range -
M 2/21/2008 Updated Pin Description. 3
N 8/11/2008 Updated pull up pull down in pin name to clarify pin descriptions 1, 2
O 12/3/2008 Removed ICS prefix from ordering Information. 15-16