DisplayPort VIP Input Board Evaluation Board User Guide FPGA-EB-02014-1.0 March 2018 DisplayPort VIP Input Board Evaluation Board User Guide Contents Acronyms in This Document .................................................................................................................................................3 1. Introduction ..................................................................................................................................................................4 1.1. Further Information ................................................................................................................................................ 5 2. Functional Description ..................................................................................................................................................6 2.1. Switches .................................................................................................................................................................. 6 2.2. DisplayPort Interface .............................................................................................................................................. 6 2.3. LVDS Translator ...................................................................................................................................................... 6 2.4. Clock Interface ........................................................................................................................................................ 6 3. High-Speed Headers .....................................................................................................................................................7 4. Power Supply ................................................................................................................................................................9 5. User LEDs and Headers ...............................................................................................................................................10 6. Ordering Information ..................................................................................................................................................11 References ..........................................................................................................................................................................12 Technical Support Assistance .............................................................................................................................................12 Appendix A. DisplayPort VIP Input Board Schematics ........................................................................................................13 Appendix B. DisplayPort VIP Input Board Bill of Materials .................................................................................................17 Revision History ...................................................................................................................................................................20 Figures Figure 1.1. Top View of DisplayPort VIP Input Board ...........................................................................................................4 Figure 1.2. Bottom View of DisplayPort VIP Input Board .....................................................................................................5 Figure 2.1 Functional Block Diagram ....................................................................................................................................6 Figure 4.1 Power Supply .......................................................................................................................................................9 Figure A.1. Block Diagram ...................................................................................................................................................13 Figure A.2. DP Redriver and Connector I/F .........................................................................................................................14 Figure A.3. Power, Debug LED, Header I/F .........................................................................................................................15 Figure A.4. Clock Synthesizer ..............................................................................................................................................16 Tables Table 3.1. Connector J1 ........................................................................................................................................................7 Table 3.2. Connector J2 ........................................................................................................................................................8 Table 5.1 User LEDs.............................................................................................................................................................10 Table 8.1. Reference Part Number .....................................................................................................................................11 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide Acronyms in This Document A list of acronyms used in this document. Acronym DP Definition DisplayPort I2C LDO Inter-Integrated Circuit Low Dropout LED LVDS mDP Light-emitting Diode Low-Voltage Differential Signaling Mini DisplayPort SPI VIP Serial Peripheral Interface Video Interface Platform (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 3 DisplayPort VIP Input Board Evaluation Board User Guide 1. Introduction This document describes the Lattice Semiconductor DisplayPort(R) VIP Input Board. This board is designed to work with the Lattice Video Interface Platform (VIP) board interconnect system. This user guide includes descriptions of board components, schematics, and bill of materials. Key features of the DisplayPort VIP Input Board include: Integrated Texas Instruments SN75DP130 DisplayPort 1:1 Redriver Mini DisplayPort (mDP) connector Two 60-pin Rugged High-Speed Headers Figure 1.1 shows the top view of the DisplayPort VIP Input Board and its key components. Figure 1.2 shows the bottom view of the board. 3.3 V Power to mDP (Not populated) SI5342B Clock Synthesizer (Not Populated) Mini DisplayPort Connector User Headers User LEDs System Reset SN65MLVD200 SN75DP130 Figure 1.1. Top View of DisplayPort VIP Input Board (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide Upstream Connector (J1) Upstream Connector (J2) Figure 1.2. Bottom View of DisplayPort VIP Input Board 1.1. Further Information The following references provide detailed information on the DisplayPort VIP Input Board: Appendix A. DisplayPort VIP Input Board Schematics Appendix B. DisplayPort VIP Input Board Bill of Materials For more information on boards and kits available for the VIP (Video Interface Platform) system visit www.latticesemi.com/boards For details on the Texas Instruments SN75DP130, visit the Texas Instruments website at www.ti.com (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 5 DisplayPort VIP Input Board Evaluation Board User Guide 2. Functional Description The DisplayPort VIP Input Board receives up to 4-lanes of DisplayPort video from the Mini DisplayPort Connector. The DisplayPort Main Link, Control and Aux Channel are sent through the TI DisplayPort redriver, which regenerates the DisplayPort high-speed digital link to connector J1. DisplayPort Main Link (4 lanes) mDP Connector CN1 HPD/CAD/Control Aux Channel DisplayPort Main Link (4 lanes) SN75DP130 U1 HPD/CAD/Control J1 Aux Channel Figure 2.1 Functional Block Diagram 2.1. Switches The push button switch, SW1, controls the reset signal RESET. Pressing SW1 provides logic 0 to the SN75DP130 RSTN pin. RESET is connected to GSRN on connecter J1, allowing SW1 to control the reset signal for other connected boards. 2.2. DisplayPort Interface The mini DisplayPort connector, CN1, connects the DisplayPort VIP Input Board to a DisplayPort sink. If PWR Out is required on Pin 20, the user must populate the 3.3 V Low Dropout (LDO) regulator, U4, and short jumper J4. 2.3. LVDS Translator The SN65MLV200 LVDS (Low-Voltage Differential Signaling) Driver/Receiver, U2, can be used to translate the LVDS AUX Channel to single ended I/O. This can be used if the downstream processor board is unable to receive LVDS. The single ended I/O are routed to connector J2. 2.4. Clock Interface The DisplayPort VIP Input Board provides the ability to add advanced clock circuitry, allowing the user to provide a fine tunable reference clock to the downstream board. This is done by populating U17 with a Silicon Labs Si5342B, High Performance Jitter Attenuator Clock Multiplier. The device can be programmed from the downstream connector using an I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface) interface. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide 3. High-Speed Headers The two 60-pin high-speed headers, connectors J1 and J2, are used to connect to a downstream host processor board. Table 3.1. Connector J1 J1 Connector Pin 1 Signal Name 3.3V SN75DP130 pin -- Description -- 2 3 5V 3.3V -- -- -- -- 4 5 6 5V GND 5V -- -- -- -- -- -- 7 8 LVDS_P GND -- -- LVDS Reference Clock from Si5342 -- 9 11 13 LVDS_N GND AUX_P -- -- AUX_SRCp LVDS Reference Clock from Si5342 -- DisplayPort Auxiliary Data Channel 14 15 17 GND AUX_N GND -- AUX_SRCn -- -- DisplayPort Auxiliary Data Channel -- 20 22 GND 2.5V -- -- -- -- 23 24 25 GND 2.5V GND -- -- -- -- -- -- 26 28 GND RESET -- RSTN 30 32 34 HPD_SINK CAD_SINK GND 36 38 40 RXP0_D1CH0 RXN0_D1CH0 GND OUT2p OUT2n -- DisplayPort Main Link Lane 0 DisplayPort Main Link Lane 0 -- 41 42 SCL_CTL RXP0_D1CH1 SCL_CTL OUT3p I2C Interface to SN75DP130 DisplayPort Main Link Lane 1 43 44 46 SDA_CTL RXN0_D1CH1 GND SDA_CTL OUT3n -- I2C Interface to SN75DP130 DisplayPort Main Link Lane 1 -- 48 50 RXP0_D0CH0 RXN0_D0CH0 OUT0p OUT0n DisplayPort Main Link Lane 0 DisplayPort Main Link Lane 0 52 54 55 GND RXP0_D0CH1 GND -- OUT1p -- -- DisplayPort Main Link Lane 1 -- 56 57 58 RXN0_D0CH1 GND GND OUT1n -- -- DisplayPort Main Link Lane 1 -- -- 59 10, 12, 60, 16, 18, 19, 21, 27, 29, 31, 33, 35, 37, 39, 45, 47, 49, 51, 53 GND Not Connected HPD_SINK CAD_SINK -- -- -- -- Global System Reset Hot Plug Detect DP Cable Adapter Detect -- -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 7 DisplayPort VIP Input Board Evaluation Board User Guide Table 3.2. Connector J2 J1 Connector Pin 1 2 3 4 7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 35 36 38 39 40 41 43 45 47 51 53 54 55 56 57 58 59 60 5, 6, 15, 16, 28, 34, 37, 42, 44, 46, 48, 49, 50, 52 Signal Name 3.3V 3.3V 3.3V 3.3V AUX_EN LED1 AUX_OUT LED2 AUX_IN LED3 EN LED4 GND GND GND GND SPI_CSN GND SPI_CLK RX_SENSEP SPI_MOSI RX_SENSEN SPI_MISO INT_N SDA_DDC OE_N SCL-DDC GND GND GND GND HEADER1 GND HEADER2 HEADER3 HEADER4 HEADER5 CMOS_CLK GND GND GND GND 2.5V 2.5V 2.5V 2.5V Not Connected SN75DP130 pin -- -- -- -- -- -- -- -- -- -- EN -- -- -- -- -- -- -- -- -- -- -- -- -- SDA_DDC -- SCL_DDC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description -- -- -- -- Aux Channel Translator Enable User LED Aux Channel single ended Out User LED Aux Channel single ended In User LED SN75DP130 Enable User LED -- -- -- -- Si5342 I2C/SPI Interface -- Si5342 I2C/SPI Interface -- Si5342 I2C/SPI Interface -- Si5342 I2C/SPI Interface Si5342 Interrupt I2C Display Data Channel Si5342 Output Enable I2C Display Data Channel -- -- -- -- User I/O Header J3 -- User I/O Header J3 User I/O Header J3 User I/O Header J3 User I/O Header J3 Reference Clock from Si5342 -- -- -- -- -- -- -- -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide 4. Power Supply Board power is supplied through connectors J1 and J2. Figure 4.1 shows the power distribution scheme. To provide power to the mini DisplayPort connector, install a 5.0 V to 3.3 V LDO at U4 and add shunt to jumper J4. 2.5 V from J1/J2 Status LED D5 3.3 V from J1/J2 Status LED D7 5 V from J1 Status LED D6 LDO U19 LDO* U4 1.8 V, 500 mA Status LED D13 3.3 V, 500 mA mDP Connector CN1 * Not Installed J4 Status LED D12 Figure 4.1 Power Supply (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 9 DisplayPort VIP Input Board Evaluation Board User Guide 5. User LEDs and Headers Four discrete LEDs (light-emitting diodes) are available to the user. These are driven by the downstream processor board through connector J2. Table 5.1 User LEDs Signal LED1 LED # D1 Connector J2 Pin 8 Color Green LED2 LED3 LED4 D2 D3 D4 10 12 14 Green Green Green Two 8-pin 100-mil headers, J3 and J10, are included on the board. Header J3 provides five user connections which are routed to the downstream connector J2. Header J10 provides an external interface to the Si5342, U17 (not installed), but can also be used to provide user interface to the downstream connector J2. Table 5.2 Header J3 Signal 3V3 Header J3 Pin 1 Connector J2 Pin -- HEADER1 HEADER2 2 3 39 41 HEADER3 HEADER4 HEADER5 4 5 6 48 45 47 RESET GND 7 8 -- -- Signal 3V3 SPI_CSN Header J10 Pin 1 2 Connector J2 Pin -- 21 SPI_MISO SPI_MOSI 3 4 23 25 SPI_CLK INT_N OE_N 5 6 7 27 29 31 GND 8 -- Table 5.3 Header J10 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide 6. Ordering Information Please visit www.latticesemi.com/boards for the latest ordering information. Table 6.1. Reference Part Number Description DisplayPort VIP Input Board Ordering Part Number DP-VIP-I-EVN (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 11 DisplayPort VIP Input Board Evaluation Board User Guide References For more information, refer to Lattice Embedded Vision Development Kit User Guide (FPGA-UG-02015) ECP5 VIP Processing Board (FPGA-EB-02001) Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide Appendix A. DisplayPort VIP Input Board Schematics 5 4 D 3 2 1 D DisplayPort VIP Input Board 5V,3V3,2V5 OnBoard LDO (pg4) I2C C GPIO I/F DP AUX I/F (pg3&4) Downstream Connector 1&2 C SN75DP130 (pg3) LED & Header I/F (pg4) X4 DP Data Control GPIO X4 DP Data Mini DP Connector B B (pg3) Clock Synthesizer (pg5) A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Title Title & Index Size B Date: 5 4 3 Project DisplayPort VIP Input Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 2 of 5 A 1 Figure A.1. Block Diagram (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 13 DisplayPort VIP Input Board Evaluation Board User Guide 5 4 3 2 1 3V3_RX 1 6 12 25 32 36 3V3 SDA_DDC SCL_DDC SDA_DDC {4} SCL_DDC {4} RXP0_D0CH0 RXN0_D0CH0 C1 RXP0_D0CH1 RXN0_D0CH1 C10 RXP0_D1CH0 RXN0_D1CH0 C11 100nF RXP0_D1CH1 RXN0_D1CH1 C13 100nF C3 100nF 23 22 C4 100nF 20 19 C6 100nF 17 16 100nF 14 13 100nF 100nF SDA_CTL SCL_CTL R40 C15 1M DNI 3V3 AUX_P C18 R17 2.49K SDA_DDC 0 SCL_DDC 0 R6 R8 34 33 CAD_SINK 0 HPD_SINK 0 R10 R12 10 11 28 27 0.1uF R18 51E 7 15 21 46 43 40 37 C C20 R22 1.5K 10uF C21 R42 100K DNI R23 51E 0.1uF IN0p IN0n OUT1p OUT1n IN1p IN1n OUT2p OUT2n IN2p IN2n OUT3p OUT3n SDA_DDC SCL_DDC CAD_SINK HPD_SINK AUX_SINKp AUX_SINKn NC1 NC2 NC3 NC4 NC5 NC6 NC7 C25 IN3p IN3n RSTn EN SCL_CTL SDA_CTL CAD_SRC HPD_SRC AUX_SRCp AUX_SRCn 38 39 C2 41 42 C8 44 45 C12 100nF 47 48 C14 100nF C7 100nF 12 10 C5 100nF 17 15 C9 100nF 11 9 100nF 5 3 100nF 100nF C16 0 R39 RESET VDDD_DREG 0 R5 4 5 0 0 R7 R9 SCL_CTL SDA_CTL 8 9 30 29 0 0 0 0 R11 R13 R15 R19 CAD_SRC HPD_SRC EN 16 18 {4} HPD_SRC CAD_SRC R20 100K DNI 1M 1M 2 C23 C24 100nF 100nF 1uF R24 10K R25 10K RX_SENSEN {4} RX_SENSEP {4} AUX_P AUX_N SCL_CTL SDA_CTL A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 {4} AUX_OUT D 1 R AUX_IN ML_LANE3P ML_LANE3N AUX_CHP AUX_CHN HPD DPPOWER CONFIG1 CONFIG2 GND1 GND2 GND3 GND4 GND5 GND6 C R21 1M {4} DE 3 A {4} RE# LVDS_P LVDS_N 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 {5} {5} L1 2 1 60ohms 2.3A 5 GND 3V3 B 4 VCC 8 AUX_EN U2 5V J1 ML_LANE2P ML_LANE2N C19 1uF C26 D ML_LANE1P ML_LANE1N Mini-DP 3V3 3V3_EXT 4 6 13 14 19 7 8 1 R41 100K 3 C22 2 20 R14 R16 DP_3V3 0.1uF 0.1uF ML_LANE0P ML_LANE0N {3,4,5} C17 1uF RST_N 35 26 3V3 ADDR_EQ SN75DP130SS AUX_N CN1 OUT0p OUT0n SHLD4 SHLD3 SHLD2 SHLD1 R4 4.7k 24 23 22 21 R1 4.7k E-PAD(GND) R3 4.7k GND GND GND EP R2 4.7k 24 18 31 49 D VCC VCC VCC VCC VCC VCC U1 B 6 AUX_P 7 AUX_N B SN65MLVD200 2V5_EXT RESET HPD_SINK CAD_SINK RXP0_D1CH0 RXN0_D1CH0 {3,4,5} 3V3 3V3_RX L4 RXP0_D1CH1 RXN0_D1CH1 RXP0_D0CH0 RXN0_D0CH0 2 1 60ohms 2.3A C28 C29 C30 C31 C32 C33 C34 C35 10uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF A RXP0_D0CH1 RXN0_D0CH1 Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Title DP Redriver & Connector I/F PLACE DE-CAPS CLOSE TO THEIR POWER PINS ERF5-030-07.0-L-DV-K-TR Size B Date: 5 4 3 Project DisplayPort VIP Input Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 3 of 5 A 1 Figure A.2. DP Redriver and Connector I/F (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide 5 4 3 2 1 NOTE : PLACE SWITCH IN THE TOP SIDE 5V REG_3V3 U4 DP_3V3 700mA traces L2 2 1 60ohms 500mA XC6222B331MR-G 500mA traces 1 0.1uF 10uF Vin Vout 5 R30 D CE NC 4.7k 1 0.1uF 2 1 2 2 3V3 EXTERNAL RESET J3 R29 FUSE 4 1 2 3 4 5 6 7 8 Jumper C39 C38 2 C36 Vss 10uF 3 C37 1 3V3 J4 U16 Q2 DNI 4.7k SW1 SYS_RST 2 4 1 3 RESET RESET {3,5} HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 RESET D C40 D1213A-01WS-7 3V3 1V8 5V 3V3 3V3 3V3 8 HEADER 0.1uF R31 R32 R33 R34 330E 330E 330E 330E NCP1117ST18T3G D4 Green 1V8 2V5 LED1 C REG_3V3 3V3 5V 1 5V 1 D3 Green 1 D2 Green 1 0.1uF D1 Green 1 22uF 1 1 C112 2 2 1 600ohm 500mA C113 1 L7 GND 10uF 1 0 2 4 2 C114 R192 OUT TAB 1 IN 2 3 2 500mA traces U19 3V3 C LED2 REG_3V3 LED3 2V5 LED4 1V8 REG_3V3 5V 3V3 R37 {5} 2V5 CMOS_CLK 2V5_EXT L3 2 1 60ohms 2.3A 1 1K SDA_DDC SCL_DDC {3} {3} D7 Green 2V5 Q1 MMBT2222A 1 R38 Q3 MMBT2222A 10K B 1V8 32 D6 Green 1 R483 10K 2 RX_SENSEP RX_SENSEN 1 1 1 D12 Green D13 Green {3} {3} 2V5_EXT TH1 A ERF5-030-07.0-L-DV-K-TR TH2 TH3 ThruHole TH4 ThruHole A ThruHole GND2 GND1 1 ThruHole Lattice Semiconductor Applications Email: techsupport@Latticesemi.com 1 HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 1K D5 Green 2 SPI_CSN SPI_CLK SPI_MOSI SPI_MISO INT_N OE_N 330E 2 {5} {5} {5} {5} {5} {5} 330E LED1 LED2 LED3 LED4 2 B {3} AUX_EN {3} AUX_OUT {3} AUX_IN {3} EN R482 R36 R35 1K 1 R481 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 5V 32 J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 5V 3V3_EXT 2 3V3_EXT Title Power,Debug LED,Header I/F Size B Date: 5 4 3 Project DisplayPort VIP Input Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 4 of 5 A 1 Figure A.3. Power, Debug LED, Header I/F (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 15 DisplayPort VIP Input Board Evaluation Board User Guide 5 4 3 2 1 3 2 1 J6 CON3 3V3 2V5 Place 1uF capacitor closer to each power pin 3V3 1V8 D 3V3 C119 C50 C49 C120 C47 C46 1uF 100nF 1uF 100nF 1uF 1uF D J5 U18 100nF IN0 IN0b X1 54Mhz 26 29 34 OUT1 OUT1b X1 XA XB X2 LOS1b LOS0b E-PAD IN3/FB_IN IN3b/FB_INb SI5342B-B-GM C51 1uF 100nF 1uF 20 19 0 0 R196 R195 25 24 0 R468 CMOS_CLK 3V3 B SPI_CSN SPI_MISO SPI_MOSI SPI_CLK INT_N OE_N 2 Green 330E 1 D9 2 Green 1K 330E 1 D10 2 Green J7 1 2 3 R475 4.7k R476 4.7k CON3 1K SPI_CSN SPI_MISO SPI_CSN {4} SPI_MISO {4} 3V3 CON3 1 2 3 4 5 6 7 8 1 D11 3V3 R469 1 2 3 J10 330E C R478 22 NC {4} R477 27 28 LOLb LOS_XAXBb R484 3V3 {3} {3} 36 35 R470 J8 LVDS_P LVDS_N R480 1K C41 18pF DNI 1uF 31 30 LOS3b LOS2b IN2 IN2B 41 42 3V3 18 23 IN1 IN1B EPAD 2 1 1 G2 G1 4 Place C42,C41 such a that it doesnt create stub when its DNI 10 11 3 C 4 5 6 7 18pF 3 C42 DNI OUT0 OUT0b C123 C122 C52 45 1 2 I2C_SEL 43 44 VDDS1 VDDS2 VDDS3 3 DSC1103CE2-135.0000 38 2 0.1uF VDDO0 VDDO1 U17 C116 100nF SDA/SDIO SCLK A1/SDO A0/CSB GND 5 2V5 13 14 15 16 NC 1uF 8 9 OUT_N 1uF VDDA1 VDDA2 EN 1uF OEb INTRb RSTb 1 C44 1uF R467 100E 12 33 17 4.7k 4 40 39 21 32 R44 OUT_P VDD1 VDD2 VDD3 VDD4 C43 CON3 3V3 C121 C118 C117 C45 C115 100nF VDD IN_SEL0 IN_SEL1 6 3 37 1 2 3 SPI_CLK SPI_MOSI R471 SPI_CLK {4} SPI_MOSI B {4} 3V3 1K J9 R473 1 2 3 8 HEADER 1K CON3 RESET {3,4} INT_N OE_N INT_N {4} OE_N {4} R479 4.7k A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Title CLOCK SYNTHESIZER Size B Date: 5 4 3 Project DisplayPort VIP Output Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 5 of 5 A 1 Figure A.4. Clock Synthesizer (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide Appendix B. DisplayPort VIP Input Board Bill of Materials Item Reference Qty Value Comments Part Number Manufacturer Description 1 CN1 1 Mini-DP -- 2129320-3 TE Connectivity MINI DISPLAYPORT REVERSE OFFSET 2 C1,C2,C3,C4,C5,C6,C7,C8, C9,C10,C11,C12,C13,C14, C15,C16,C115,C116 18 100 nF -- 885012205018 Wurth CAP CER 0.1UF 10V X7R 0402 3 C17,C19,C24,C29,C45,C47, C50,C52,C117,C118,C119, C120,C121,C122,C123 15 1 uF -- GRM155R61A105KE15D Murata CAP CER 1UF 10V 10% X5R 0402 4 C18,C21,C25,C26,C43 5 0.1 uF -- GRM155R61A104KA01D Murata CAP CER 0.1UF 10V X5R 0402 5 C20,C28 2 10 uF -- GRM21BR61A106KE19L Murata CAP CER 10UF 10V 10% X5R 0805 6 C22,C23,C30,C31,C32,C33, C34,C35,C44,C46,C49,C51 12 100 nF -- GRM155R61A104KA01D Murata CAP CER 0.1UF 10V X5R 0402 7 C36,C38 2 10 uF -- CL10X106MP8NRNC Samsung CAP CER 10UF 10V 20% X6S 0603 8 C37,C39 2 0.1 uF -- CL05A104MP5NNNC Samsung CAP CER 0.1UF 10V X5R 0402 9 C40 1 0.1 uF -- 885012205037 Wurth CAP CER 0.1UF 16V X7R 0402 10 C41,C42 2 18 pF DNL C0402C180K3GACTU Kemet CAP CER 18PF 25V C0G 0402 11 C112 1 0.1 uF -- C0402C104K4RACTU Kemet CAP CER 0.1UF 16V X7R 0402 12 C113 1 22 uF -- LMK212BJ226MG-T Taiyo Yuden CAP CER 22UF 10V X5R 0805 13 C114 1 10 uF -- LMK107BJ106MALTD Taiyo Yuden CAP CER 10UF 10V X5R 0603 14 D1,D2,D3,D4,D5,D6,D7,D9, D10,D11,D12,D13 12 Green -- LTST-C190KGKT LITE-On Inc LED GREEN CLEAR 0603 SMD 15 GND1,GND2,5V,1V8,2V5, REG_3V3,3V3 7 TP DNL -- -- -- 16 J1,J2 2 -- -- ERF5-030-07.0-L-DV-KTR Samtec Inc Conn High Speed Edge Rate Terminal Strip HDR 60 POS 0.5 mm Solder ST SMD T/R - (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 17 DisplayPort VIP Input Board Evaluation Board User Guide Item Reference Qty Value Comments Part Number Manufacturer Description 17 J3,J10 2 8 HEADER -- -- -- -- 18 J4 1 Jumper -- -- -- -- 19 J5,J6,J7,J8,J9 5 CON3 -- -- -- -- 20 L1,L3,L4 3 60 2.3 A -- MPZ1608Y600B TDK FERRITE BEAD 60 OHM 0603 1LN 21 L2 1 60 500 mA -- MMZ1608Y600B TDK FERRITE BEAD 60 OHM 0603 1LN 22 L7 1 600 500 mA -- BLM18AG601SN1D Murata FERRITE BEAD 600 OHM 0603 1LN 23 Q1,Q3 2 MMBT2222A -- MMBT2222A,215 NXP USA Inc. TRANS NPN 40V 0.6A SOT23 24 Q2 1 D1213A-01WS-7 -- D1213A-01WS-7 Diodes Incorporated TVS DIODE 3.3VWM 10VC SOD323 25 R1,R2,R3,R4,R29,R30,R44, R475,R476,R479 10 4.7 k -- CRCW06034K70FKEA Vishay RES SMD 4.7K OHM 1% 1/10W 0603 26 R5,R6,R7,R8,R9,R10,R11,R 12,R13,R15,R19,R39,R192, R195,R196,R468 16 0 -- RC0603JR-070RL Yageo RES SMD 0.0OHM JUMPER 1/10W 0603 27 R14,R16,R21 3 1M -- ERJ-2GEJ105X Panasonic RES SMD 1M OHM 5% 1/10W 0402 28 R17 1 2.49 K -- ERA-2AEB2491X Panasonic RES SMD 2.49KOHM 0.1% 1/16W 0402 29 R18,R23 2 51E -- ERJ-2GEJ510X Panasonic RES SMD 51 OHM 5% 1/10W 0402 30 R20,R42 2 100 K DNL ERA-2AEB104X Panasonic RES SMD 100K OHM 0.1% 1/16W 0402 31 R22 1 1.5 K -- ERJ-2RKF1501X Panasonic RES SMD 1.5K OHM 1% 1/10W 0402 32 R24,R25 2 10 K -- RMCF0402JT10K0 Stackpole Electronics Inc RES SMD 10K OHM 5% 1/16W 0402 33 R31,R32,R33,R34,R36,R47 7,R478,R480,R481 9 330E -- CRCW0402330RFKED Vishay Dale RES SMD 330 OHM 1% 1/16W 0402 34 R35 1 1K -- RC0603FR-071KL Yageo RES SMD 1K OHM 1% 1/10W 0603 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-EB-02014-1.0 DisplayPort VIP Input Board Evaluation Board User Guide Item Reference Qty Value Comments Part Number Manufacturer Description 35 R37,R469,R470,R471,R473, R482,R484 7 1K -- RMCF0402JT1K00 Stackpole Electronics Inc RES SMD 1K OHM 5% 1/16W 0402 36 R38,R483 2 10 K -- ERJ-3EKF1002V Panasonic RES SMD 10K OHM 1% 1/10W 0603 37 R40 1 1M DNL ERJ-2GEJ105X Panasonic RES SMD 1M OHM 5% 1/10W 0402 38 R41 1 100 K -- ERA-2AEB104X Panasonic RES SMD 100K OHM 0.1% 1/16W 0402 39 R467 1 100E -- TNPW0402100RBEED Vishay RES SMD 100 OHM 0.1% 1/16W 0402 40 SW1 1 SYS_RST -- 434153017835 Wurth SWITCH TACTILE SPST-NO 0.05A 12V 41 TH1,TH2,TH3,TH4 4 ThruHole DNL -- -- -- 42 U1 1 SN75DP130SS -- SN75DP130SSRGZR Texas Instruments IC DISPLYPRT 1:1 REDRIVR 48VQFN 43 U2 1 SN65MLVD200 -- SN65MLVD200AD Texas Instruments IC LVDS LINE DVR/RCVR 8-SOIC 44 U4 1 XC6222B331MR-G DNL XC6222B331MR-G Torex Semiconductor Ltd IC REG LDO 3.3V 0.7A SOT25 45 U16 1 FUSE -- 0154004.DRT Littelfuse FUSE BRD MNT 4A 125VAC/VDC 2SMD 46 U17 1 SI5342B-B-GM DNL SI5342B-B-GM IC CLK BUFFER PLL 44QFN 47 U18 1 DSC1103CE2135.0000 DNL DSC1103CE2-135.0000 Silicon Laboratories Microchip Technology Inc 48 U19 1 NCP1117ST18T3G -- NCP1117ST18T3G On Semi IC REG LDO 1.8V 1A SOT223 49 X1 1 54 MHz -- CX3225SB54000D0WPT C1 AVX Corp/Kyocera Corp CRYSTAL 54MHZ 8PF SMD 50 DISPLAYPORT-VIP-INPUT BOARD REV1 PCB 1 -- -- 305-PD-16-0949 PACTRON OSC MEMS 135.000MHZ LVDS SMD (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02014-1.0 19 DisplayPort VIP Input Board Evaluation Board User Guide Revision History Date Version March 2018 1.0 Change Summary Initial release. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-EB-02014-1.0 7th Floor, 111 SW 5th Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com