LMP7701,LMP7702,LMP7704 LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers Literature Number: SNOSAI9G LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers General Description Features The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and a wide supply voltage range. The LMP7701/LMP7702/LMP7704 are part of the LMP(R) precision amplifier family and are ideal for sensor interface and other instrumentation applications. The guaranteed low offset voltage of less than 200 V along with the guaranteed low input bias current of less than 1 pA make the LMP7701 ideal for precision applications. The LMP7701/LMP7702/LMP7704 are built utilizing VIP50 technology, which allows the combination of a CMOS input stage and a 12V common mode and supply voltage range. This makes the LMP7701/LMP7702/LMP7704 great choices in many applications where conventional CMOS parts cannot operate under the desired voltage conditions. The LMP7701/LMP7702/LMP7704 each have a rail-to-rail input stage that significantly reduces the CMRR glitch commonly associated with rail-to-rail input amplifiers. This is achieved by trimming both sides of the complimentary input stage, thereby reducing the difference between the NMOS and PMOS offsets. The output of the LMP7701/LMP7702/ LMP7704 swings within 40 mV of either rail to maximize the signal dynamic range in applications requiring low supply voltage. The LMP7701 is offered in the space saving 5-Pin SOT23 and 8-Pin SOIC package. The LMP7702 is offered in the 8-Pin SOIC and 8-Pin MSOP package. The quad LMP7704 is offered in the 14-Pin SOIC and 14-Pin TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable electronics. Unless otherwise noted, typical values at VS = 5V 200 V (max) Input offset voltage (LMP7701) Input offset voltage (LMP7702/LMP7704) 220 V (max) 200 fA Input bias current 9 nV/Hz Input voltage noise 130 dB CMRR 130 dB Open loop gain -40C to 125C Temperature range 2.5 MHz Unity gain bandwidth 715 A Supply current (LMP7701) 1.5 mA Supply current (LMP7702) 2.9 mA Supply current (LMP7704) 2.7V to 12V Supply voltage range Rail-to-rail input and output Applications High impedance sensor interface Battery powered instrumentation High gain amplifiers DAC buffer Instrumentation amplifier Active filters Typical Application 20127305 Precision Current Source LMP(R) is a registered trademark of National Semiconductor Corporation. (c) 2008 National Semiconductor Corporation 201273 www.national.com LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers June 23, 2008 LMP7701/LMP7702/LMP7704 Soldering Information Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model 260C (Note 1) Temperature Range (Note 3) Supply Voltage (VS = V+ - V-) 200V 1000V 300 mV 13.2V V++ 0.3V, V- - 0.3V 10 mA -65C to +150C +150C 3V Electrical Characteristics 235C Wave Soldering Lead Temp. (10 sec) Operating Ratings 2000V Machine Model Charge-Device Model VIN Differential Supply Voltage (VS = V+ - V-) Voltage at Input/Output Pins Input Current Storage Temperature Range Junction Temperature (Note 3) Infrared or Convection (20 sec) -40C to +125C 2.7V to 12V Package Thermal Resistance (JA (Note 3)) 5-Pin SOT23 8-Pin SOIC 8-Pin MSOP 14-Pin SOIC 14-Pin TSSOP 265C/W 190C/W 235C/W 145C/W 122C/W (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 3V, V- = 0V, VCM = V+/2, and RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Input Offset Voltage Conditions Typ (Note 5) Max (Note 6) LMP7701 37 200 500 LMP7702/LMP7704 56 220 520 1 5 0.2 1 50 0.2 1 400 TCVOS Input Offset Voltage Temperature Drift (Note 7) IB Input Bias Current (Notes 7, 8) Min (Note 6) -40C TA 85C (Notes 7, 8) -40C TA 125C IOS Input Offset Current CMRR Common Mode Rejection Ratio 40 0V VCM 3V LMP7701 86 80 130 0V VCM 3V LMP7702/LMP7704 84 78 130 86 82 98 PSRR Power Supply Rejection Ratio 2.7V V+ 12V, Vo = V+/2 CMVR Common Mode Voltage Range CMRR 80 dB -0.2 -0.2 RL = 2 k (LMP7701) VO = 0.3V to 2.7V 100 96 114 RL = 2 k (LMP7702/LMP7704) VO = 0.3V to 2.7V 100 94 114 RL = 10 k VO = 0.2V to 2.8V 100 96 124 CMRR 77 dB AVOL Open Loop Voltage Gain www.national.com 2 Units V V/C pA fA dB dB 3.2 3.2 V dB VOUT Parameter Output Voltage Swing High Output Voltage Swing Low IOUT Output Current (Notes 3, 9) Conditions Typ (Note 5) Max (Note 6) RL = 2 k to V+/2 LMP7701 40 80 120 RL = 2 k to V+/2 LMP7702/LMP7704 40 80 150 RL = 10 k to V+/2 LMP7701 30 40 60 RL = 10 k to V+/2 LMP7702/LMP7704 35 50 100 RL = 2 k to V+/2 LMP7701 40 60 80 RL = 2 k to V+/2 LMP7702/LMP7704 45 100 170 RL = 10 k to V+/2 LMP7701 20 40 50 RL = 10 k to V+/2 LMP7702/LMP7704 20 50 90 Sourcing VO = V+/2 VIN = 100 mV 25 15 42 Sinking VO = V+/2 VIN = -100 mV (LMP7701) 25 20 42 25 15 42 V+/2 Sinking VO = VIN = -100 mV (LMP7702/ LMP7704) IS Supply Current Min (Note 6) Units mV from V+ mV mA LMP7701 0.670 1.0 1.2 LMP7702 1.4 1.8 2.1 LMP7704 2.9 3.5 4.5 AV = +1, VO = 2 VPP 10% to 90% 0.9 V/s 2.5 MHz 0.02 % mA SR Slew Rate (Note 10) GBW Gain Bandwidth THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, R.L = 10 k en Input Referred Voltage Noise Density f = 1 kHz 9 nV/ in Input Referred Current Noise Density f = 100 kHz 1 fA/ 5V Electrical Characteristics (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, and RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Input Offset Voltage Conditions Typ (Note 5) Max (Note 6) LMP7701 37 200 500 LMP7702/LMP7704 32 220 520 1 5 0.2 1 50 0.2 1 400 TCVOS Input Offset Voltage Temperature Drift (Note 7) IB Input Bias Current (Notes 7, 8) Min (Note 6) -40C TA 85C (Notes 7, 8) -40C TA 125C 3 Units V V/C pA www.national.com LMP7701/LMP7702/LMP7704 Symbol LMP7701/LMP7702/LMP7704 Symbol Parameter IOS Input Offset Current CMRR Common Mode Rejection Ratio Conditions Min (Note 6) Typ (Note 5) 0V VCM 5V LMP7701 88 83 130 0V VCM 5V LMP7702/LMP7704 86 81 130 86 82 100 40 PSRR Power Supply Rejection Ratio 2.7V V+ 12V, VO = V+/2 CMVR Common Mode Voltage Range CMRR 80 dB -0.2 -0.2 RL = 2 k (LMP7701) VO = 0.3V to 4.7V 100 96 119 RL = 2 k (LMP7702/LMP7704) VO = 0.3V to 4.7V 100 94 119 RL = 10 k VO = 0.2V to 4.8V 100 96 130 CMRR 78 dB AVOL VOUT Open Loop Voltage Gain Output Voltage Swing High IOUT IS Output Current (Notes 3, 9) Supply Current dB dB 5.2 5.2 110 130 RL = 2 k to V+/2 LMP7702/LMP7704 60 120 200 40 50 70 RL = 10 k to V+/2 LMP7702/LMP7704 40 60 120 RL = 2 k to V+/2 LMP7701 50 80 90 RL = 2 k to V+/2 LMP7702/LMP7704 50 120 190 RL = 10 k to V+/2 LMP7701 30 40 50 RL = 10 k to V+/2 LMP7702/LMP7704 30 50 100 Sourcing VO = V+/2 VIN = 100 mV (LMP7701) 40 28 66 Sourcing VO = V+/2 VIN = 100 mV (LMP7702/LMP7704) 38 25 66 Sinking VO = V+/2 VIN = -100 mV (LMP7701) 40 28 76 Sinking VO = V+/2 VIN = -100 mV (LMP7702/LMP7704) 40 23 76 V dB 60 V+/2 Units fA RL = 2 k to V+/2 LMP7701 RL = 10 k to LMP7701 Output Voltage Swing Low Max (Note 6) mV from V+ mV mA LMP7701 0.715 1.0 1.2 LMP7702 1.5 1.9 2.2 LMP7704 2.9 3.7 4.6 AV = +1, VO = 4 VPP 10% to 90% 1.0 f = 1 kHz, AV = 1, RL = 10 k mA SR Slew Rate (Note 10) GBW Gain Bandwidth 2.5 MHz THD+N Total Harmonic Distortion + Noise 0.02 % www.national.com 4 V/s Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units en Input Referred Voltage Noise Density f = 1 kHz 9 nV/ in Input Referred Current Noise Density f = 100 kHz 1 fA/ 5V Electrical Characteristics (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 5V, V- = -5V, VCM = 0V, and RL > 10 k to 0V. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Input Offset Voltage Conditions Typ (Note 5) Max (Note 6) LMP7701 37 200 500 LMP7702/LMP7704 37 220 520 TCVOS Input Offset Voltage Temperature Drift (Note 7) IB Input Bias Current (Notes 7, 8) Min (Note 6) (Notes 7, 8) 5 1 50 0.2 1 400 -40C TA 125C IOS Input Offset Current CMRR Common Mode Rejection Ratio 40 -5V VCM 5V LMP7701 92 88 138 -5V VCM 5V LMP7702/LMP7704 90 86 138 86 82 98 PSRR Power Supply Rejection Ratio 2.7V V+ 12V, VO = 0V CMVR Common Mode Voltage Range CMRR 80 dB -5.2 -5.2 RL = 2 k (LMP7701) VO = -4.7V to 4.7V 100 98 121 RL = 2 k (LMP7702/LMP7704) VO = -4.7V to 4.7V 100 94 121 RL = 10 k (LMP7701) VO = -4.8V to 4.8V 100 98 134 RL = 10 k (LMP7702/LMP7704) VO = -4.8V to 4.8V 100 97 134 CMRR 78 dB AVOL Open Loop Voltage Gain 5 V V/C 1 0.2 -40C TA 85C Units pA fA dB dB 5.2 5.2 V dB www.national.com LMP7701/LMP7702/LMP7704 Symbol LMP7701/LMP7702/LMP7704 Symbol VOUT Parameter Output Voltage Swing High Output Voltage Swing Low IOUT IS Output Current (Notes 3, 9) Supply Current Conditions Min (Note 6) Typ (Note 5) Max (Note 6) RL = 2 k to 0V LMP7701 90 150 170 RL = 2 k to 0V LMP7702/LMP7704 90 180 290 RL = 10 k to 0V LMP7701 40 80 100 RL = 10 k to 0V LMP7702/LMP7704 40 80 150 RL = 2 k to 0V LMP7701 90 130 150 RL = 2 k to 0V LMP7702/LMP7704 90 180 290 RL = 10 k to 0V LMP7701 40 50 60 RL = 10 k to 0V LMP7702/LMP7704 40 60 110 Sourcing VO = 0V VIN = 100 mV (LMP7701) 50 35 86 Sourcing VO = 0V VIN = 100 mV (LMP7702/LMP7704) 48 33 86 Sinking VO = 0V VIN = -100 mV 50 35 84 Units mV from V+ mV from V- mA LMP7701 0.790 1.1 1.3 LMP7702 1.7 2.1 2.5 LMP7704 3.2 4.2 5.0 AV = +1, VO = 9 VPP 10% to 90% 1.1 V/s mA SR Slew Rate (Note 10) GBW Gain Bandwidth 2.5 MHz THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RL = 10 k 0.02 % en Input Referred Voltage Noise Density f = 1 kHz 9 nV/ in Input Referred Current Noise Density f = 100 kHz 1 fA/ Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) FieldInduced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality Control (SQC) method. Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 8: Positive current corresponds to current flowing into the device. Note 9: The short circuit test is a momentary test. Note 10: The number specified is the slower of positive and negative slew rates. www.national.com 6 LMP7701/LMP7702/LMP7704 Connection Diagrams 5-Pin SOT23 (LMP7701) 8-Pin SOIC (LMP7701) 20127302 Top View 20127364 Top View 8-Pin SOIC/MSOP (LMP7702) 14-Pin SOIC/TSSOP (LMP7704) 20127303 20127304 Top View Top View Ordering Information Package 5-Pin SOT23 8-Pin SOIC 8-Pin SOIC 8-Pin MSOP 14-Pin SOIC 14-Pin TSSOP Part Number LMP7701MF LMP7701MFX LMP7701MA LMP7701MAX LMP7702MA LMP7702MAX LMP7702MM LMP7702MMX LMP7704MA LMP7704MAX LMP7704MT LMP7704MTX Package Marking Transport Media 1k Units Tape and Reel AC2A 3k Units Tape and Reel LMP7701MA LMP7702MA 95 Units/Rail 2.5k Units Tape and Reel 95 Units/Rail 2.5k Units Tape and Reel 1k Units Tape and Reel AA3A 3.5k Units Tape and Reel LMP7704MA LMP7704MT 7 55 Units/Rail 2.5k Units Tape and Reel 94 Units/Rail 2.5k Units Tape and Reel NSC Drawing MF05A M08A M08A MUA08A M14A MTC14 www.national.com LMP7701/LMP7702/LMP7704 Typical Performance Characteristics Unless otherwise noted: TA = 25C, VCM = VS/2, RL > 10 k. Offset Voltage Distribution TCVOS Distribution 20127336 20127341 Offset Voltage Distribution TCVOS Distribution 20127337 20127342 Offset Voltage Distribution TCVOS Distribution 20127338 www.national.com 20127343 8 LMP7701/LMP7702/LMP7704 Offset Voltage vs. Temperature CMRR vs. Frequency 20127306 20127350 Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM 20127307 20127310 Offset Voltage vs. VCM Offset Voltage vs. VCM 20127308 20127309 9 www.national.com LMP7701/LMP7702/LMP7704 Input Bias Current vs. VCM Input Bias Current vs. VCM 20127330 20127346 Input Bias Current vs. VCM Input Bias Current vs. VCM 20127331 20127347 Input Bias Current vs. VCM Input Bias Current vs. VCM 20127348 www.national.com 20127349 10 Supply Current vs. Supply Voltage (Per Channel) 20127345 20127311 Sinking Current vs. Supply Voltage Sourcing Current vs. Supply Voltage 20127313 20127312 Output Voltage vs. Output Current Slew Rate vs. Supply Voltage 20127316 20127317 11 www.national.com LMP7701/LMP7702/LMP7704 PSRR vs. Frequency LMP7701/LMP7702/LMP7704 Open Loop Frequency Response Open Loop Frequency Response 20127315 20127314 Large Signal Step Response Small Signal Step Response 20127318 20127320 Large Signal Step Response Small Signal Step Response 20127326 20127319 www.national.com 12 Open Loop Gain vs. Output Voltage Swing 20127327 20127352 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 20127333 20127335 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 20127332 20127334 13 www.national.com LMP7701/LMP7702/LMP7704 Input Voltage Noise vs. Frequency LMP7701/LMP7702/LMP7704 THD+N vs. Frequency THD+N vs. Output Voltage 20127328 20127329 Crosstalk Rejection Ratio vs. Frequency (LMP7702/ LMP7704) 20127353 www.national.com 14 LMP7701/LMP7702/LMP7704 The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP7701/LMP7702/LMP7704 have a very low input bias current of only 200 fA at room temperature. The wide supply voltage range of 2.7V to 12V over the extensive temperature range of -40C to 125C makes the LMP7701/LMP7702/LMP7704 excellent choices for low voltage precision applications with extensive temperature requirements. The LMP7701/LMP7702/LMP7704 have only 37 V of typical input referred offset voltage and this offset is guaranteed to be less than 500 V for the single and 520 V for the dual and quad, over temperature. This minimal offset voltage allows more accurate signal detection and amplification in precision applications. The low input bias current of only 200 fA along with the low gives the LMP7701/ input referred voltage noise of 9 nV/ LMP7702/LMP7704 superiority for use in sensor applications. Lower levels of noise from the LMP7701/LMP7702/LMP7704 mean of better signal fidelity and a higher signal-to-noise ratio. National Semiconductor is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. The LMP7701 is offered in the space saving 5-Pin SOT23 and 8-Pin SOIC package. The LMP7702 comes in the 8-Pin SOIC and 8-Pin MSOP package. The LMP7704 is offered in the 14Pin SOIC and 14-Pin TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable electronics. 20127321 FIGURE 1. Isolating Capacitive Load INPUT CAPACITANCE CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP7701/LMP7702/ LMP7704 enhance this performance by having the low input bias current of only 200 fA, as well as, a very low input referred voltage noise of 9 nV/ . In order to achieve this a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7701/LMP7702/ LMP7704. The typical value of this input capacitance, CIN, for the LMP7701/LMP7702/LMP7704 is 25 pF. The input capacitance will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The DC gain of the circuit shown in Figure 2 is simply -R2/ R1. CAPACITIVE LOAD The LMP7701/LMP7702/LMP7704 can each be connected as a non-inverting unity gain follower. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the amplifier's output impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be either underdamped or it will oscillate. In order to drive heavier capacitive loads, an isolation resistor, RISO, in Figure 1 should be used. By using this isolation resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output voltage will be. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. 20127344 FIGURE 2. Compensating for Input Capacitance For the time being, ignore CF. The AC gain of the circuit in Figure 2 can be calculated as follows: 15 www.national.com LMP7701/LMP7702/LMP7704 Application Information LMP7701/LMP7702/LMP7704 nates the gain peaking that can be caused by having a larger feedback resistor. Figure 4 shows how CF reduces gain peaking. This equation is rearranged to find the location of the two poles: (1) As shown in Equation 1, as values of R1 and R2 are increased, the magnitude of the poles is reduced, which in turn decreases the bandwidth of the amplifier. Whenever possible, it is best to choose smaller feedback resistors. Figure 3 shows the effect of the feedback resistor on the bandwidth of the LMP7701/LMP7702/LMP7704. 20127355 FIGURE 4. Closed Loop Gain vs. Frequency with Compensation DIODES BETWEEN THE INPUTS The LMP7701/LMP7702/LMP7704 have a set of anti-parallel diodes between the input pins, as shown in Figure 5. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to 300 mV or the input current needs to be limited to 10 mA. 20127354 FIGURE 3. Closed Loop Gain vs. Frequency Equation 1 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. In order to eliminate this effect, the poles should be placed in Butterworth position, since poles in Butterworth position do not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 1 should be set to equal -1. Using this fact and the relation between R1 and R2, R2 = -AV R1, the optimum value for R1 can be found. This is shown in Equation 2. If R1 is chosen to be larger than this optimum value, gain peaking will occur. 20127325 (2) FIGURE 5. Input of LMP7701 In Figure 2, CF is added to compensate for input capacitance and to increase stability. Additionally, CF reduces or elimi- www.national.com 16 Figure 7 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are: RG = 10, RF = 1 k, and RO = 1 k. 20127305 FIGURE 6. Precision Current Source The equation for output current can be derived as follows: Solving for the current I results in the following equation: LOW INPUT VOLTAGE NOISE The LMP7701/LMP7702/LMP7704 have the very low input . This input voltage noise can be voltage noise of 9 nV/ further reduced by placing N amplifiers in parallel as shown in Figure 7. The total voltage noise on the output of this circuit 20127356 FIGURE 7. Noise Reduction Circuit 17 www.national.com LMP7701/LMP7702/LMP7704 is divided by the square root of the number of amplifiers used in this parallel combination. This is because each individual amplifier acts as an independent noise source, and the average noise of independent sources is the quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers, this means: PRECISION CURRENT SOURCE The LMP7701/LMP7702/LMP7704 can each be used as a precision current source in many different applications. Figure 6 shows a typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal. Amplifier A2 is a buffer that eliminates the error current from the load side of the RS resistor that would flow in the feedback resistor if it were connected to the load side of the RS resistor. In general, the circuit is stable as long as the closed loop bandwidth of amplifier A2 is greater then the closed loop bandwidth of amplifier A1. Note that if A1 and A2 are the same type of amplifiers, then the feedback around A1 will reduce its bandwidth compared to A2. LMP7701/LMP7702/LMP7704 HIGH IMPEDANCE SENSOR INTERFACE Many sensors have high source impedances that may range up to 10 M. The output signal of sensors often needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier can load the sensor's output and cause a voltage drop across the source resistance as shown in Figure 9, where VIN+ = VS - IBIAS*RS The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep the error contribution by IBIAS*RS less than the input voltage noise of the amplifier, so that it will not become the dominant noise factor. TOTAL NOISE CONTRIBUTION The LMP7701/LMP7702/LMP7704 have very low input bias current, very low input current noise, and very low input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor applications. Figure 8 shows the typical input noise of the LMP7701/ LMP7702/LMP7704 as a function of source resistance where: en denotes the input referred voltage noise ei is the voltage drop across source resistance due to input referred current noise or ei = RS * in et shows the thermal noise of the source resistance eni shows the total noise on the input. Where: The input current noise of the LMP7701/LMP7702/LMP7704 is so low that it will not become the dominant factor in the total noise unless source resistance exceeds 300 M, which is an unrealistically high value. As is evident in Figure 8, at lower RS values, total noise is dominated by the amplifier's input voltage noise. Once RS is larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As mentioned before, the current noise will not be the dominant noise factor for any practical application. 20127359 FIGURE 9. Noise Due to IBIAS pH electrodes are very high impedance sensors. As their name indicates, they are used to measure the pH of a solution. They usually do this by generating an output voltage which is proportional to the pH of the solution. pH electrodes are calibrated so that they have zero output for a neutral solution, pH = 7, and positive and negative voltages for acidic or alkaline solutions. This means that the output of a pH electrode is bipolar and has to be level shifted to be used in a single supply system. The rate of change of this voltage is usually shown in mV/pH and is different for different pH sensors. Temperature is also an important factor in a pH electrode reading. The output voltage of the senor will change with temperature. Figure 10 shows a typical output voltage spectrum of a pH electrode. Note that the exact values of output voltage will be different for different sensors. In this example, the pH electrode has an output voltage of 59.15 mV/pH at 25C. 20127358 FIGURE 8. Total Input Noise 20127360 FIGURE 10. Output Voltage of a pH Electrode The temperature dependence of a typical pH electrode is shown in Figure 11. As is evident, the output voltage changes with changes in temperature. www.national.com 18 20127361 FIGURE 11. Temperature Dependence of a pH Electrode The schematic shown in Figure 12 is a typical circuit which can be used for pH measurement. The LM35 is a precision integrated circuit temperature sensor. This sensor is differentiated from similar products because it has an output voltage linearly proportional to Celcius measurement, without the need to convert the temperature to Kelvin. The LM35 is used to measure the temperature of the solution and feeds this reading to the Analog to Digital Converter, ADC. This infor- 20127362 FIGURE 12. pH Measurement Circuit 19 www.national.com LMP7701/LMP7702/LMP7704 mation is used by the ADC to calculate the temperature effects on the pH readings. The LM35 needs to have a resistor, RT in Figure 12, to -V+ in order to be able to read temperatures below 0C. RT is not needed if temperatures are not expected to go below zero. The output of pH electrodes is usually large enough that it does not require much amplification; however, due to the very high impedance, the output of a pH electrode needs to be buffered before it can go to an ADC. Since most ADCs are operated on single supply, the output of the pH electrode also needs to be level shifted. Amplifier A1 buffers the output of the pH electrode with a moderate gain of +2, while A2 provides the level shifting. VOUT at the output of A2 is given by: VOUT = -2VpH + 1.024V. The LM4140A is a precision, low noise, voltage reference used to provide the level shift needed. The ADC used in this application is the ADC12032 which is a 12-bit, 2 channel converter with multiplexers on the inputs and a serial output. The 12-bit ADC enables users to measure pH with an accuracy of 0.003 of a pH unit. Adequate power supply bypassing and grounding is extremely important for ADCs. Recommended bypass capacitors are shown in Figure 12. It is common to share power supplies between different components in a circuit. To minimize the effects of power supply ripples caused by other components, the op amps need to have bypass capacitors on the supply pins. Using the same value capacitors as those used with the ADC are ideal. The combination of these three values of capacitors ensures that AC noise present on the power supply line is grounded and does not interfere with the amplifiers' signal. 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