SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Compatible With IEEE Std 1194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
D
Open-Collector B-Port Outputs Sink
100 mA
D
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal
D
High-Impedance State During Power Up
and Power Down
D
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
D
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
AI2
AO1
AI1
CLKAB/LEAB
IMODE1
IMODE0
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
AI8
AO8
GND
CLKBA/LEBA
OMODE0
OMODE1
OEB
GND
B8
AO7
BG GND
B1
V
GND
CC
VCC
RC PACKAGE
(TOP VIEW)
VCC
OEA
BIAS VCC
OEB CC
BG V
GND
AO2
AI3
AO3
AI4
AO4
LOOPBACK
AI5
AO5
AI6
AO6
AI7
GND
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
description
The SN74FB2033A is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port.
The common-I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels.
The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for
B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured
in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock
inputs serve as active-high transparent latch enables.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when VCC is less than 2.5 V, the
AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
The B port is controlled by OEB and OEB. If OEB is low, OEB is high, or VCC is less than 2.5 V, the B port is
inactive. If OEB is high and OEB is low, the B port is active.
BG VCC and BG GND are the bias-generator reference inputs.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO port) or inactive (B port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing
effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V .
Both clamps are active only during ac switching and do not affect the BTL outputs during
steady-state conditions.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
0°C to 70°C QFP – RC Tube SN74FB2033ARC FB2033A
†Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
FUNCTION/MODE
INPUTS
FUNCTION/MODE
OEA OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK
FUNCTION/MODE
L L X X X X X X
Isolation
LXH X X X X X
Isolation
X H L L L X X X AI to B, buffer mode
X H L L H X X X AI to B, flip-flop mode
X H L H X X X X AI to B, latch mode
H L X X X L L L
BtAObff d
HXH X X L L L
B
t
o
AO
,
b
u
ff
er mo
d
e
H L X X X L H L
B t AO fli fl d
HXH X X L H L
B
t
o
AO
,
fli
p-
fl
op mo
d
e
H L X X X H X L
BtAOlth d
HXH X X H X L
B
t
o
AO
,
l
a
t
c
h
mo
d
e
H L X X X L L H
AI to AO buffer mode
HXH X X L L H
AI
to
AO
,
buffer
mode
H L X X X L H H
AI to AO fli
p
flo
p
mode
HXH X X L H H
AI
to
AO
,
flip
-
flop
mode
H L X X X H X H
AI to AO latch mode
HXH X X H X H
AI
to
AO
,
latch
mode
H H L X X X X L AI to B, B to AO
ENABLE/DISABLE
INPUTS OUTPUTS
OEA OEB OEB AO B
L X X Hi Z
H X X Active
XLL Inactive (H)
XLH Inactive (H)
XHL Active
X H H Inactive (H)
BUFFER
INPUT OUTPUT
L H
H L
LATCH
INPUTS
OUTPUT
CLK/LE DATA
OUTPUT
H L H
HHL
L X Q0
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
LOOPBACK
LOOPBACK Q†
L B port
HPoint P‡
†Q is the input to the B-to-A
logic element.
‡P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS SELECTED LOGIC
MODE1 MODE0 ELEMENT
L L Buffer
L H Flip-flop
H X Latch
FLIP-FLOP
INPUTS
OUTPUT
CLK/LE DATA
OUTPUT
L X Q0
↑LH
↑H L
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
CLKBA/LEBA
OEB
OEB
OMODE1
OMODE0
CLKAB/LEAB
AI1
IMODE1
IMODE0
B1
AO1
OEA
LOOPBACK
23
24
21
20
47
50
46
45
19
51
43
7
40
One of Eight Channels
Transceiver
1D
C1
1D
C1
1D
C1
1D
C1
P
Q
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current range, VI: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any B output in the disabled or power-off state, VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO: A port –0.5 V to VCC
. . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current applied to any single output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1) 44°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
VCC,
BG VCC Supply voltage 4.75 5 5.25 V
BIAS VCC Supply voltage 4.5 5 5.5 V
VIH
High level in
p
ut voltage
B port 1.62 2.3
V
V
IH
High
-
level
input
voltage
Except B port 2
V
VIL
Low level in
p
ut voltage
B port 0.75 1.47
V
V
IL
Low
-
level
input
voltage
Except B port 0.8
V
IOH High-level output current AO port –3 mA
IOL
Low level out
p
ut current
AO port 24
mA
I
OL
Low
-
level
output
current
B port 100
mA
∆t/∆vInput transition rise or fall rate Except B port 10 ns/V
TAOperating free-air temperature 0 70 °C
NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to VCC(5 V) or GND, and
B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V to 5.25 V, IOH = –10 µA VCC–1.1
VOH AO port
VCC = 4 75 V
IOH = –3 mA 2.5 2.85 3.4 V
V
CC =
4
.
75
V
IOH = –32 mA 2
AO
p
ort
VCC = 4 75 V
IOL = 20 mA 0.33 0.5
VOL
AO
port
V
CC =
4
.
75
V
IOL = 55 mA 0.8
V
V
OL
B t
VCC = 4 75 V
IOL = 100 mA 0.75 1.1
V
B
por
t
V
CC =
4
.
75
V
IOL = 4 mA 0.5
IIExcept B port VCC = 0, VI = 5.25 V 100 µA
IIH
Except B port VCC = 5.25 V, VI = 2.7 V 50
µA
I
IH B port‡VCC = 0 to 5.25 V, VI = 2.1 V 100 µ
A
IIL
Except B port
VCC = 5 25 V
VI = 0.5 V –50
µA
I
IL B port‡
V
CC =
5
.
25
V
VI = 0.75 V –100 µ
A
IOH B port VCC = 0 to 5.25 V, VO = 2.1 V 100 µA
IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA
IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
IOZH AO port VCC = 5.25 V, VO = 2.7 V 50 µA
IOZL AO port VCC = 5.25 V, VO = 0.5 V –50 µA
IOS§AO port VCC = 5.25 V, VO = 0 –40 –80 –150 mA
ICC All outputs on VCC = 5.25 V, IO = 0 45 70 mA
CiAI port and control inputs VI = 0.5 V or 2.5 V 5 pF
CoAO port VO = 0.5 V or 2.5 V 5 pF
C
B port VCC = 0 to 4.75 V 6p
F
C
io
B
ort
per IEEE Std 1194.1-1991 VCC = 4.75 V to 5.25 V 6
pF
†All typical values are at VCC = 5 V.
‡For I/O ports, the parameters IIH and IIL include the off-state output current.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
live-insertion characteristics over recommended operating free-air temperature range (see Note 3)
PARAMETER TEST CONDITIONS MIN MAX UNIT
ICC (BIAS VCC)
VCC = 0 to 4.5 V
VB=0to2V
Vl(BIAS VCC)=45Vto55V
10
µA
I
CC
(BIAS
V
CC
)
VCC = 4.5 V to 5.5 V
V
B =
0
to
2
V
,
V
l
(BIAS
V
CC
)
=
4
.
5
V
to
5
.
5
V
10 µ
A
VOB port VCC = 0, VI (BIAS VCC) = 4.5 V to 5.5 V 1.62 2.1 V
VCC = 0, VB = 1 V, Vl (BIAS VCC) = 4.5 V to 5.5 V –1
IOB port VCC = 0 to 5.5 V, OEB = 0 to 0.8 V 100 µA
VCC = 0 to 2.2 V, OEB = 0 to 5 V 100
NOTE 3: The power-up sequence is GND, BIAS VCC, VCC.
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 150 150 MHz
twPulse duration CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns
tsu Setup time Data before CLKAB/LEAB or CLKBA/LEBA↑2.7 2.7 ns
thHold time Data after CLKAB/LEAB or CLKBA/LEBA↑0.7 0.7 ns
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CMIN MAX UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX
fmax 150 150 MHz
tPLH AI
B
2.3 3.6 4.6 2.3 5.6
ns
tPHL (through mode)
B
1.9 3 4.2 1.9 4.5
ns
tPLH B
AO
2.5 4.2 5.5 2.5 6.1
ns
tPHL
B
(through mode)
AO
3 4.2 5.6 3 5.7
ns
tPLH AI
B
2.3 3.6 4.6 2.3 5.6
ns
tPHL (transparent)
B
1.9 3 4.1 1.9 4.5
ns
tPLH B
AO
2.5 4.2 5.5 2.5 6.1
ns
tPHL
B
(transparent)
AO
3 4.2 5.6 3 5.7
ns
tPLH
OEB
B
2.4 3.7 4.7 2.4 5.8
ns
tPHL
OEB
B
1.8 3 4.1 1.8 4.4
ns
tPLH
OEB
B
2 3.4 4.3 2 5.2
ns
tPHL
OEB
B
2 3.3 4.4 2 4.8
ns
tPZH
OEA
AO
2 3.5 4.6 2 5.1
ns
tPZL
OEA
AO
2.7 4.2 5.1 2.7 5.4
ns
tPHZ
OEA
AO
2.1 4 5 2.1 5.5
ns
tPLZ
OEA
AO
1.6 2.8 3.9 1.6 4.3
ns
tPLH
CLKAB/LEAB
B
3 4.7 5.8 3 6.9
ns
tPHL
CLKAB/LEAB
B
2.8 4.3 5.6 2.8 6.1
ns
tPLH
CLKBA/LEBA
AO
2 3.6 4.9 2 5.4
ns
tPHL
CLKBA/LEBA
AO
2.2 3.5 4.7 2.2 5.1
ns
tPLH
OMODE
B
2.4 5 6.1 2.4 7.2
ns
tPHL
OMODE
B
2.4 4.5 6 2.4 6.7
ns
tPLH
IMODE
AO
1.8 4 5.3 1.8 5.9
ns
tPHL
IMODE
AO
2.3 4.1 5.2 2.3 5.4
ns
tPLH
LOOPBACK
AO
2.4 5 7 2.4 8
ns
tPHL
LOOPBACK
AO
3.1 4.6 5.7 3.1 5.9
ns
tPLH
AI
AO
1.9 3.7 5.5 1.9 6.1
ns
tPHL
AI
AO
2.6 4.2 5.6 2.6 5.8
ns
trRise time,1.3 V to 1.8 V, B port 0.5 1.2 2.1 0.5 3
ns
tfFall time, 1.8 V to 1.3 V, B port 0.5 1.4 2.3 0.5 3
ns
trRise time, 10% to 90%, AO 2 3.3 4.2 2 5
ns
tfFall time, 90% to 10%, AO 1 2.5 3.4 1 5
ns
B-port input pulse rejection 1 ns
output-voltage characteristics
PARAMETER TEST
CONDITIONS MIN MAX UNIT
VOHP Peak output voltage during turnoff of 100 mA into 40 nH B port See Figure 1 4.5 V
VOHV Minimum output voltage during turnoff of 100 mA into 40 nH B port See Figure 1 1.62 V
VOLV Minimum output voltage during high-to-low switch B port IOL = –50 mA 0.3 V
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
9 Ω
2.1 V
40 nH
30 pF
Figure 1. Load Circuit for VOHP and VOHV
SN74FB2033A
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
500 Ω
500 Ω From Output
Under Test
LOAD CIRCUIT FOR B OUTPUTS
2.1 V
9 Ω
CL = 30 pF
(see Note A)
Test
Point
th
tsu
tPHL tPLH
Output
3 V
0 V
VOH
VOL
Data Input
Timing Input 3 V
0 V
0 V
tPHL tPLH
2.1 V
1 V
VOH
VOL
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES (B TO A)
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES (A TO B)
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPLZ
tPZH
tPZL
tPHZ
3.5 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
3 V
tw
VOLTAGE W AVEFORMS
PULSE DURATION
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES (A PORT)
VOLTAGE W AVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
7 V
Open
1.5 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 VInput
Input 1.5 V 1.5 V
1.55 V1.55 V
Output
Input
1.5 V 1.5 V
1.55 V1.55 V
1.5 V 1.5 V
1.5 V
1.5 V
3 V
2.1 V
1 V
VOHV
VOHP
VOLV
Figure 2. Load Circuits and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty . T esting and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Mailing Address:
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Post Office Box 655303
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Copyright 2001, Texas Instruments Incorporated
