Specifications GAL22LV10Z
GAL22LV10ZD
1
228
NC
I/CLK
I
I
I/DPP
I
I
I
I
I
NC NC
NC
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q I/O/Q
426
25
19
18
21
23
161412
11
9
7
5
• 3.3V LOW VOLTAGE, ZERO POWER OPERATION
— Interfaces with Standard 5V TTL Devices
—50
µA Typical Standby Current (100 µA Max.)
— 40mA Typical Active Current (55mA Max.)
— Input T ransition Detection on GAL22LV10Z
— Dedicated Power-down Pin on GAL22LV10ZD
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 15 ns Maximum Propagation Delay
— Fmax = 71.4MHz
— UltraMOS® Advanced CMOS Technology
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
•E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% T ested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Y ear Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
FUNCTIONAL BLOCK DIAGRAMFEATURES
PACKAGE DIAGRAMS
GAL22LV10Z
GAL22LV10ZD
Low Voltage, Zero Power E2CMOS PLD
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
*GAL22LV10ZD Only
I
I/CLK
I
I
I/DPP*
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
The GAL22L V10Z and GAL22LV10ZD, at 15ns maximum propa-
gation delay time and 100µA standby current, combine 3.3V
CMOS process technology with Electrically Erasable (E2) floating
gate technology to provide the best PLD solution to support
today's new 3.3V systems. E2 technology offers high speed
(<100ms) erase times, providing the ability to reprogram or re-
configure the device quickly and efficiently.
The generic 22V10 architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The GAL22LV10Z uses Input Transition
Detection (ITD) to put the device into standby mode and is fully
function/fuse map/parametric compatible with standard bipolar
and CMOS 22V10 devices. The GAL22LV10ZD utilizes a Dedi-
cated Power-down Pin (DPP) to put the device into standby mode.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor is able to deliver 100% field programma-
bility and functionality of all GAL® products. In addition,100 erase/
rewrite cycles and data retention in excess of 20 years are speci-
fied.
DESCRIPTION
PLCC
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
GAL22LV10Z
GAL22LV10ZD
Top V iew
22lv10zd_02
Specifications GAL22LV10Z
GAL22LV10ZD
2
GAL22LV10Z AND GAL22LV10ZD ORDERING INFORMATION
GAL22LV10Z: Commercial Grade Specifications
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51010155001JQ51-Z01VL22LAGCCLPdaeL-82
52515155001JQ52-Z01VL22LAGCCLPdaeL-82
GAL22LV10ZD: Commercial Grade Specifications
)sn(dpT usT1 )sn( )sn(ocT)Am(ccI(bsIµ)A#gniredrOegakcaP
51010155001JQ51-DZ01VL22LAGCCLPdaeL-82
52515155001JQ52-DZ01VL22LAGCCLPdaeL-82
PART NUMBER DESCRIPTION
Blank = Commercial
Grade
Package
Active Power
Q = Quarter Power
XXXXXXXX XX X X X
Device Name
_
J = PLCC
GAL22LV10Z (Zero Power ITD)
GAL22LV10ZD (Zero Power DPP)
Speed (ns)
Specifications GAL22LV10Z
GAL22LV10ZD
3
OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
GAL22LV10Z AND GAL22LV10ZD OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL22LV10Z and GAL22LV10ZD
have two primary functional I/O modes: registered, and combi-
natorial. The modes and the output polarity are set by two bits (SO
and S1), which are normally controlled by the logic compiler.
Each of these two primary modes, and the bit settings required
to enable them, are described below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be de-
fined by a logic equation. The D flip-flop’ s Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “product-
term driven” (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer . Both polarities (true and
inverted) of the pin are fed back into the AND array.
The GAL22L V10Z and GAL22LV10ZD have a variable number
of product terms per OLMC. Of the ten available OLMCs, two
OLMCs have access to eight product terms (pins 17 and 27), two
have ten product terms (pins 18 and 26), two have twelve product
terms (pins 19 and 25), two have fourteen product terms (pins 20
and 24), and two OLMCs have sixteen product terms (pins 21 and
23). In addition to the product terms available for logic, each OLMC
has an additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low .
The GAL22LV10Z and GAL22LV10ZD have a product term for
Asynchronous Reset (AR) and a product term for Synchronous
Preset (SP). These two product terms are common to all regis-
tered OLMCs. The Asynchronous Reset sets all registers to zero
any time this dedicated product term is asserted. The Synchro-
nous Preset sets all registers to a logic one on the rising edge of
the next clock pulse after this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
AR
SP
D
Q
QCLK
4 TO 1
MUX
2 TO 1
MUX
Specifications GAL22LV10Z
GAL22LV10ZD
4
REGISTERED MODE
ACTIVE HIGHACTIVE LOW
COMBINATORIAL MODE
ACTIVE HIGHACTIVE LOW
S0 = 1
S1 = 1
S0 = 0
S1 = 1
S0 = 0
S1 = 0 S0 = 1
S1 = 0
AR
SP
D
Q
Q
CLK
AR
SP
D
Q
Q
CLK
Specifications GAL22LV10Z
GAL22LV10ZD
5
* Note: Input not available on GAL22LV10ZD
GAL22LV10Z AND GAL22LV10ZD LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC Package
*
2
26
OLMC
S0
5810
S1
5811
0440
.
.
.
.
0880
3
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0 4 8 1216202428323640
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
12
0000
5764
0044
.
.
.
0396 27
S0
5808
S1
5809
25
OLMC
S0
5812
S1
5813
0924
.
.
.
.
.
1452
4
5
6
24
OLMC
S0
5814
S1
5815
1496
.
.
.
.
.
.
2112
23
OLMC
S0
5816
S1
5817
2156
.
.
.
.
.
.
.
2860
21
OLMC
S0
5818
S1
5819
2904
.
.
.
.
.
.
.
3608
20
OLMC
S0
5820
S1
5821
3652
.
.
.
.
.
.
4268
OLMC
S0
5822
S1
5823
4312
.
.
.
.
.
4840
10
19
18
OLMC
S0
5824
S1
5825
4884
.
.
.
.
5324
11
5368
.
.
.
5720 17
OLMC
S0
5826
S1
5827
9
7
13 16
8
10
14
16
12
12
16
14
10
8OLMC
Electronic Signature 5828, 5829 ... ... 5890, 5891
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
Specifications GAL22LV10Z
GAL22LV10ZD
6
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (TA) .............................0 to +75°C
Supply voltage (VCC)
with Respect to Ground ......................... +3.0 to +3.6V
Supply voltage VCC ..................................... -0.5 to +5.6V
Input voltage applied ................................. -0.5 to +5.6V
Off-state output voltage applied................. -0.5 to +5.6V
Storage Temperature..................................-65 to 150°C
Ambient Temperature with
Power Applied .........................................-55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
VIL Input Low V oltage Vss – 0.5 — 0.8 V
VIH Input High V oltage 2.0 — 5.25 V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA
IIH Input or I/O High Leakage Current (VCC − 0.2)V ≤ VIN ≤ VCC ——10µA
VCC ≤ VIN ≤ 5.25V—— 1mA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V
VO H Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V
IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V
IOL Low Level Output Current — — 8 mA
IOH High Level Output Current — — -8 mA
IOS1Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA = 25°C -30 — -130 mA
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS
COMMERCIAL
ISB Stand-by Power VIL = GND VIH = Vcc Outputs Open Z -15/-25 — 50 100 µA
Supply Current ZD -15/-25
ICC Operating Power VIL = GND VIH = 3.0V Z -15/-25 — 40 55 mA
Supply Current ftoggle = 5 MHz Outputs Open ZD -15/-25
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 3.3V and TA = 25 °C
Specifications GAL22LV10Z
GAL22LV10ZD
7
Specifications GAL22LV10Z
tpd A Input or I/O to Combinatorial Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns
tcf2— Clock to Feedback Delay — 10 — 10 ns
tsu1 — Setup T ime, Input or Fdbk before Clk↑10 — 15 — ns
tsu2 — Setup Time, SP before Clk↑14 — 20 — ns
th — Hold Time, Input or Fdbk after Clk↑0—0—ns
A Maximum Clock Frequency with 50 — 33.3 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 50 — 40 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 71.4 — 50 — MHz
No Feedback
twh — Clock Pulse Duration, High 6 — 10 — ns
twl — Clock Pulse Duration, Low 6 — 10 — ns
ten B Input or I/O to Output Enabled 3 15 3 25 ns
tdis C Input or I/O to Output Disabled 3 15 3 25 ns
tar A Input or I/O to Asynch. Reset of Reg. 3 20 3 25 ns
tarw — Asynch. Reset Pulse Duration 15 — 25 — ns
tarr — Asynch. Reset to Clk↑ Recovery T ime 10 — 25 — ns
tspr — Synch. Preset to Clk↑ Recovery T ime 10 — 15 — ns
tas A Last Active Input to Standby 100 250 100 250 ns
tsa4A Standby to Active Output — 15 — 20 ns
-25
MIN. MAX.
-15
MIN. MAX. UNITS
PARAM TEST
COND.1DESCRIPTION
COM
COM
AC SWITCHING CHARACTERISTICS
ST ANDBY POWER TIMING W AVEFORMS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Add tsa to tpd, tsu, tar, ten and tdis when the device is transitioning from standby state to active state.
Over Recommended Operating Conditions
POWER
INPUT or
I/O FEEDBACK
CLK
OUTPUT
t
as
t
pd,
t
en,
t
dis
Icc
Isb
t
sa
t
su
t
co
Specifications GAL22LV10Z
GAL22LV10ZD
8
Specifications GAL22LV10ZD
tpd A Input or I/O to Combinatorial Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns
tcf2— Clock to Feedback Delay — 10 — 10 ns
tsu1 — Setup T ime, Input or Fdbk before Clk↑10 — 15 — ns
tsu2 — Setup T ime, SP before Clk↑14 — 20 — ns
th — Hold Time, Input or Fdbk after Clk ↑0—0—ns
A Maximum Clock Frequency with 50 — 33.3 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 50 — 40 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 71.4 — 50 — MHz
No Feedback
twh — Clock Pulse Duration, High 6 — 10 — ns
twl — Clock Pulse Duration, Low 6 — 10 — ns
ten B Input or I/O to Output Enabled 3 15 3 25 ns
tdis C Input or I/O to Output Disabled 3 15 3 25 ns
tar A Input or I/O to Asynch. Reset of Reg. 3 20 3 25 ns
tarw — Asynch. Reset Pulse Duration 15 — 25 — ns
tarr — Asynch. Reset to Clk↑ Recovery Time 10 — 25 — ns
tspr — Synch. Preset to Clk↑ Recovery T ime 10 — 15 — ns
-25
MIN. MAX.
-15
MIN. MAX.
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
UNITS
PARAM TEST
COND.1DESCRIPTION
COM
COM
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Specifications GAL22LV10Z
GAL22LV10ZD
9
Specifications GAL22LV10ZD
twhd — DPP Pulse Duration High 40 — 40 — ns
twld — DPP Pulse Duration Low 30 — 40 — ns
tivdh — V alid Input before DPP High 0 — 0 — ns
tcvdh — Valid Clock Before DPP High 0 — 0 — ns
tdhix — Input Don't Care after DPP High — 15 — 25 ns
tdhcx — Clock Don't Care after DPP High — 15 — 25 ns
tixdl — Input Don't Care before DPP Low — 0 — 0 ns
tcxdl — Clock Don't Care before DPP Low — 0 — 0 ns
tdliv — DPP Low to Valid Input or I/O 20 — 25 — ns
tdlcv — DPP Low to Valid Clock 30 — 35 — ns
tdlov A DPP Low to Valid Output 5 35 5 45 ns
DEDICATED POWER-DOWN PIN SPECIFICATIONS
Over Recommended Operating Conditions
PARAMETER UNITS
-25
MIN. MAX.
TEST
COND1.DESCRIPTION -15
MIN. MAX.
ACTIVE TO STANDBY
COM COM
ST ANDBY TO ACTIVE
1) Refer to Switching Test Conditions section.
DEDICATED POWER-DOWN PIN (DPP) TIMING W AVEFORMS
t
dhcx
DPP
INPUT or
I/O FEEDBACK
CLK
OUTPUT
t
cvdh
t
ivdh
t
dhix
t
pd,
t
en,
t
dis
t
co
t
dliv
t
dlcv
t
dlov
t
ixdl
t
cxdl
Specifications GAL22LV10Z
GAL22LV10ZD
10
SWITCHING WAVEFORMS
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/
f
max
Input or I/O to Output Enable/Disable
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
wh
t
wl
1/
f
max
REGISTERED
OUTPUT
CLK
t
arw
t
ar
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
fmax with Feedback
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
Synchronous Preset
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIInput Capacitance 8 pF VCC = 3.3V, VI = 0V
CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
Asynchronous Reset
Clock Width
Registered Output
Combinatorial Output
Specifications GAL22LV10Z
GAL22LV10ZD
11
fmax DESCRIPTIONS
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
SWITCHING TEST CONDITIONS
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Input Pulse Levels GND to 3.0V
Input Rise and Fall T imes 2ns 10% – 90%
Input T iming Reference Levels 1.5V
Output T iming Reference Levels 1.5V
Output Load See Figure
All 3-state levels are measured at (V oh - 0.5) V
and (V ol + 0.5) V.
Output Load Conditions (see figure)
Test Condition R1R2CL
A 270Ω220Ω35pF
B Active High 270Ω220Ω35pF
Active Low 270Ω220Ω35pF
C Active High 270Ω220Ω5pF
Active Low 270Ω220Ω5pF
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+3.3V
*CL
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R 2
R 1
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
Specifications GAL22LV10Z
GAL22LV10ZD
12
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer , available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user , and is done automati-
cally as part of the programming cycle.
SECURITY CELL
A security cell is provided in every GAL22LV10Z and
GAL22LV10ZD device to prevent unauthorized copying of the
array patterns. Once programmed, this cell prevents further read
access to the functional bits in the device. This cell can only be
erased by re-programming the device, so the original configuration
can never be examined once this cell is programmed. The Elec-
tronic Signature is always available to the user , regardless of the
state of this control cell.
An electronic signature (ES) is provided in every GAL22LV10Z and
GAL22L V10ZD device. It contains 64 bits of reprogrammable
memory that can contain user-defined data. Some uses include
user ID codes, revision numbers, or inventory control. The
signature data is always available to the user independent of the
state of the security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22L V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22LV10 and a GAL22LV10-UES (UES = User Electronic
Signature). This allows users to maintain compatibility with ex-
isting 22V10 designs, while still having the option to use the GAL
device's extra feature.
The JEDEC map for the GAL22LV10Z and GAL22L V10ZD con-
tains the 64 extra fuses for the electronic signature, for a total of
5892 fuses. However , GAL22L V10Z and GAL22LV10ZD devices
can still be programmed with a standard 22V10 JEDEC map
(5828 fuses) with any qualified device programmer.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
GAL22L V10Z and GAL22LV10ZD devices include circuitry that
allows each registered output to be synchronously set either high
or low . Thus, any present state condition can be forced for test
sequencing. If necessary , approved GAL programmers capable
of executing test vectors perform output register preload automati-
cally.
GAL22L V10Z and GAL22L V10ZD devices are designed with TTL
level compatible input buffers. These buffers have a character-
istically high impedance, and present a much lighter load to the
driving logic than bipolar TTL devices.
INPUT BUFFERS
INPUT TRANSITION DETECTION (ITD)
The GAL22L V10Z relies on its internal input transition detection
circuitry to put the device into power down mode. If there is no
input transition for the specified period of time, the device will go
into the power down state. T ransition detection on any input or
I/O will put the device back into the active state. Any input pulse
widths greater than 5ns at an input transition voltage level of 1.5V
will be detected as an input transition. The device will not detect
input pulse widths less than 1ns measured at an input transition
voltage level of 1.5V as an input transition.
The GAL22LV10ZD uses pin 5 as the dedicated power-down
signal to put the device into the standby state. DPP is an active
high signal. A logic high driven onto this signal puts the device into
the standby state. Input pin 5 cannot be used as a logic function
input on this device.
DEDICATED POWER-DOWN PIN (DPP)
Specifications GAL22LV10Z
GAL22LV10ZD
13
POWER-UP RESET
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
power-up, some conditions must be met to provide a valid power-
up reset of the device. First, the VCC rise must be monotonic. Sec-
ond, the clock input must be at a static TTL level as shown in the
diagram during power up. The registers will reset within a maxi-
mum of tpr time. As in normal system operation, avoid clocking
the device until all input and feedback path setup times have been
met. The clock must also meet the minimum pulse width require-
ments.
Circuitry within the GAL22LV10Z and GAL22LV10ZD provides
a reset signal to all registers during power-up. All internal registers
will have their Q outputs set low after a specified time (tpr , 10µs
MAX). As a result, the state on the registered output pins (if they
are enabled) will be either high or low on power-up, depending
on the programmed polarity of the output pins. This feature can
greatly simplify state machine design by providing a known state
on power-up. Because of the asynchronous nature of system
Typical OutputTypical Input
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Vcc
PIN
Tri-State
Control
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
PIN
Vcc
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Specifications GAL22LV10Z
GAL22LV10ZD
14
GAL22LV10Z/ZD: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.6
0.8
1
1.2
1.4
1.6
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.6
0.8
1
1.2
1.4
1.6
-55 -25 0 25 50 75 100 125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.6
0.8
1
1.2
1.4
1.6
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-0.8
-0.6
-0.4
-0.2
0
12345678910
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-0.8
-0.6
-0.4
-0.2
0
12345678910
RISE
FALL
Delta Tpd vs Output
Loading
Output Loading (pF)
Delta Tpd (ns)
-4
-2
0
2
4
6
8
10
12
14
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-4
-2
0
2
4
6
8
10
12
14
0 50 100 150 200 250 300
RISE
FALL
Specifications GAL22LV10Z
GAL22LV10ZD
15
GAL22LV10Z/ZD: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol (V)
0
0.2
0.4
0.6
0.8
0.00 10.00 20.00 30.00 40.00
Voh vs Ioh
Ioh (mA)
Voh (V)
0
0.5
1
1.5
2
2.5
3
0.00 10.00 20.00 30.00 40.00
Voh vs Ioh
Ioh (mA)
Voh (V)
2.85
2.88
2.91
2.94
2.97
3.00
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.8
0.9
1
1.1
1.2
3 3.15 3.3 3.45 3.6
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.6
1.0
1.4
1.8
2.2
0 20406080100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
1
2
3
4
0 0.5 1 1.5 2 2.5 3 3.5
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
40
80
120
160
200
-1.20 -1.00 -0.80 -0.60 -0.40 -0.20 0.00
Normalized Icc vs Freq.
(ITD)
Frequency (KHz)
Normalized Icc
0
0.2
0.4
0.6
0.8
1
1 10 100 1000 10000
