18-Mbit Burst of 2 Pipelined SRAM with
Q
DR™ Ar
c
hi
tectu
r
e
CY7C1306BV25
CY7C1303BV25
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05627 Rev. *A Revised April 3, 2006
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for hi gh bandwidth
— 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output dat a (C and C ) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supp ly wit h HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
• Variable Impedance HSTL
Configurations
CY7C1303BV25 – 1M x 18
CY7C1306BV25 – 512K x 36
Functional Description
The CY7C1303BV25 and CY7C1306BV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR™ archi-
tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K clock.
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303BV25/
CY7C1306BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing perfor-
mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7 C1303BV25) or two
36-bit words (CY7C1306BV25) that bu rst sequentially into or
out of the device.
Depth expansion is accomplished with a Port Select input fo r
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 2 of 19
512Kx18
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
18
36
Write
18
BWS0
Vref
Write Add. Decode
Data Reg
Write
Data Reg
Memory
Array
512Kx18
Memory
Array
18
18
A(18:0)
19
18
C
C
BWS1
Logic Block Diagram (CY7C1303BV25)
256Kx36
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
36
72
Write
36
BWS0
Vref
Write Add. Decode
Data Reg
Write
Data Reg
Memory
Array
256Kx36
Memory
Array
36
36
A(17:0)
18
36
C
C
BWS1
BWS2
BWS3
Logic Block Diagram (CY7C1306BV25)
Selection Guide
CY7C1303BV25-167
CY7C1306BV25-167 Unit
Maximum Operating Frequency 167 MHz
Maximum Operating Current 500 mA
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 3 of 19
Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1303BV25 (1M x 18 )
1 2 34567891011
ANC Gnd/ 144M NC/ 36M WPS BWS1KNC RPS A Gnd/ 72M NC
BNC Q9 D9 A NC K BWS0ANCNCQ8
CNC NC D10 VSS A A A VSS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS A A A VSS NC NC D1
PNC NC Q17 A A C A A NC D0 Q0
RTDO TCK A A A C AAATMSTDI
CY7C1306BV25 (512K x 36)
1 2 34567891011
ANC Gnd/ 288M NC/72M WPS BWS2KBWS1RPS NC/36M Gnd/ 144M NC
BQ27 Q18 D18 A BWS3KBWS
0AD17Q17Q8
CD27 Q28 D19 VSS A A A VSS D16 Q7 D8
DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
ND34 D26 Q25 VSS A A A VSS Q10 D9 D1
PQ35 D35 Q26 A A C A A Q9 D0 Q0
RTDO TCK A A A C AAATMSTDI
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 4 of 19
Pin Definitions
Name I/O Description
D[x:0] Input-
Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write opera-
tions.
CY7C1303BV25 – D[17:0]
CY7C1306BV25 – D[35:0]
WPS Input-
Synchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[x:0] to be ignored.
BWS0, BWS1,
BWS2, BWS3Input-
Synchronous Byte Write Select 0, 1, 2 and 3 - active LOW . Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations.
CY7C1303BV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1306BV25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corresponding
byte of data to be ignored and not written into the device.
A Input-
Synchronous Address Inputs. Sampled on the rising edge of the K clock during active Read operations and
on the rising edge of K for Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally , the device is organized as 1M x 18 (2 arrays each of 512K x 18)
for CY7C1303BV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306BV25. Therefore,
only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and
18 address inputs for CY7C1306BV25. These inputs are ignored when the appropriate port is
deselected.
Q[x:0] Outputs-
Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
three-stated.
CY7C1303BV25 - Q[17:0]
CY7C1306BV25 - Q[35:0]
RPS Input-
Synchronous Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the K clock. Each read acce ss consists of a burst
of two sequential 18-bit or 36-bit transfers.
C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
CInput-Clock Negative Input Clock for Output Data. C is used in conjun ction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K Input-Clock Positive Input Clock Input. T he rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
KInput-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive
out data through Q[x:0] when in single clock mode.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. Thi s pin cannot be connected directly to GND or left
unconnected.
TDO Output TDO pin for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 5 of 19
Introduction
Functional Overview
The CY7C1303BV25/CY7C1306BV25 are synchronous
pipelined Burst SRAM equ ipped with both a Read port an d a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, this architecture completely
eliminates the need to “turn-around” the data bus and avoid s
any possible data contention, thereby simplifying system
design. 38-05627Each access consists of two 18-bit data
transfers in the case of CY7C1303BV25, and two 36-bit data
transfers in the case of CY7C1306BV25, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timings are referenced to rising edge of output clocks
(C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
The following descriptions take CY7C1303BV25 as an
example. The same basic descriptions apply to
CY7C1306BV25.
Read Operations
The CY7C1303BV25 is organized internally as 2 arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched o n the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q [17:0] using C as
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q[17:0]. The
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
250-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the Write Data register
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified
location.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1 303BV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS0 and BWS1 which are sampled wi th each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow th e data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1303BV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to any
voltage level on CY7C1303BV25/CY7C1306BV25.
GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25.
NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25.
GND/144M Input Address expansion for 144M. This pin has to be tied to GND on
CY7C1303BV25/CY7C1306BV25.
GND/288M Input Address expansion for 288M. This pin has to be tied to GND on CY7C1306BV25.
NC N/A Not connected to the die. Can be tied to any voltage level.
VREF Input-
Reference Reference V oltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Name I/O Description
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 6 of 19
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same i n thi s mo de . To use this mode of ope r a ti on ,
the user must tie C and C HIGH at power-up.This function is
a strap option and not alterable during device operation.
Concurrent T ransactions
The Read and Write ports on the CY7C1303BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be st arted
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1303BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ=1.5V. The output impedance is adjusted every 1024
cycles to account for drifts in supply voltage and temperature.
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7]
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K clock; input write
data on K and K rising edges.
L-H X L D(A+0) at
K(t) ↑D(A+1) at
K(t) ↑
Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
L-H L X Q(A+0) at
C(t+1)↑Q(A+1) at
C(t+1) ↑
NOP: No Operation L-H H H D = X
Q = High-Z D = X
Q = High-Z
Standby: Clock S topped Stopped X X Previous
State Previous
State
Notes:
1. The above application shows 4 QDR-I being used.
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address locat i on latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in sing le clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restar t by overcoming transmission line charging
symmetrically.
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 7 of 19
Write Descriptions (CY7C1303BV25)[2, 8]
BWS0BWS1KK Comments
L L L-H - During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L L - L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
L H - L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
H L L-H - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
H L - L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
H H L-H - No data is written into the device during this portion of a write operation.
H H - L-H No data is written into the device during this portion of a write operation.
Write Descriptions (CY7C1306BV25)[2, 8]
BWS0BWS1BWS2BWS3KK Comments
LLLLL-H-During the Data portion of a Write sequence, all four bytes (D
[35:0]) are
written into the device.
LLLL-L-HDuring the Data portion of a Write sequence, all four bytes (D
[35:0]) are
written into the device.
L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0])
is written into the device. D[35:9] will remain unaltered.
L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D[8:0])
is written into the device. D[35:9] will remain unaltered.
H L H H L-H - During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
H L H H - L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
H H L H L-H - During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H H L H - L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H H H L L-H - During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H H H L - L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
HHHHL-H-No data is written into the device during this portion of a Write operation.
HHHH-L-HNo data is written into the device during this portion of a Write operation.
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, in the case of CY7C1303BV25 and also BWS2 and BWS3
in the case of CY7C1306BV25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. 38-05627
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A Page 8 of 19
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected i f the TAP is n ot used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loa ded into th e TAP instruction register. Fo r
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internall y pulled up and can
be unconnected if the TAP is unused in an a pplic ation. TDI i s
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected betwe en the TDI and TD O pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one registe r can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Da ta is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loa ded when it is placed between the
TDI and TDO pins as shown in T AP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level seri al test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is mo ved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
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Document #: 38-05627 Rev. *A Page 9 of 19
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the T AP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the T AP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during th e Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee th at the boundary scan register wi ll capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's ca pture set-up plus
hold times (tCS and tCH). The SRAM clock input migh t not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still p ossible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register .
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-state
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desire d bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST i nstruction is en tered, thi s bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
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Document #: 38-05627 Rev. *A Page 10 of 19
TAP Controller State Diagram[9]
Note:
9. The 0/1 next to each state re presents the value at TMS at the rising edge of TCK.
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
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Document #: 38-05627 Rev. *A Page 11 of 19
TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range [10, 14, 17]
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH = −2.0 mA 1.7 V
VOH2 Output HIGH Voltage IOH = −100 µA2.1V
VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V
VOL2 Output LOW Voltage IOL = 100 µA0.2V
VIH Input HIGH Voltage 1.7 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.7 V
IXInput and Output Load Current GND ≤ VI ≤ VDDQ −55µA
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter Description Min. Max. Unit
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH 20 ns
tTL TCK Clock LOW 20 ns
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise 10 ns
tTDIS TDI Set-up to TCK clock Rise 10 ns
tCS Capture Set-up to TCK Rise 10 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 10 ns
tTDIH TDI Hold after Clock Rise 10 ns
tCH Capture Hold after Clock Rise 10 ns
Notes:
10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12.Test conditions are specified using the load in TAP AC test condit i ons. tR/tF = 1 ns.
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.106
012
Instruction Register
Bypass Register
Selection
Circuitry Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
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Document #: 38-05627 Rev. *A Page 12 of 19
Output Times
tTDOV TCK Clock LOW to TDO Valid 20 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
TAP Timing and Test Conditions[12]
TAP AC Switching Characteristics Over the Operating Range[11, 12] (continued)
Parameter Description Min. Max. Unit
(a)
TDO
CL= 20 pF
Z0= 50Ω
GND
1.25V
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX tTDOV
50Ω
2.5V
0V
ALL INPUT PULSES
1.25V
Identification Register Definitions
Instruction Field Value DescriptionCY7C1303BV25 CY7C1306BV25
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 01011010010010101 01011010010100 101 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.
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Document #: 38-05627 Rev. *A Page 13 of 19
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 107
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYP ASS 1 11 Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
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Document #: 38-05627 Rev. *A Page 14 of 19
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
06R 27 11H 54 7B 81 3G
16P 28 10G 55 6B 82 2G
26N 29 9G 56 6A 83 1J
37P 30 11F 57 5B 84 2J
47N 31 11G 58 5A 85 3K
57R 32 9F 59 4A 86 3J
68R 33 10F 60 5C 87 2K
78P 34 11E 61 4B 88 1K
89R 35 10E 62 3A 89 2L
911P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F
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Document #: 38-05627 Rev. *A Page 15 of 19
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage on VDD Relative to GND.......–0.5V to + 3.6V
Supply Voltage on VDDQ Relative to GND.....–0.5V to + VDD
DC Applied to Outputs in
High-Z State........................................ –0.5V to VDDQ + 0.5V
DC Input Voltage[17]................... ... .........–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current............... ... ... ............................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)V
DD[13] VDDQ[13]
Com’l 0°C to + 70°C 2.5 ± 0.1V 1.4V to 1.9V
Ind’l –40°C to + 85°C
Electrical Characteristics Over the Operating Range[14]
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditio ns Min. Typ. Max. Unit
VDD Power Supply Voltage 2.4 2.5 2.6 V
VDDQ I/O Supply Voltage 1.4 1.5 1.9 V
VOH Output HIGH Voltage Note 15 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOL Output LOW Voltage Note 16 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V
VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VSS 0.2 V
VIH Input HIGH Voltage[17] VREF + 0.1 VDDQ + 0.3 V
VIL Input LOW Voltage[17, 18] –0.3 VREF – 0.1 V
VREF Input Reference V oltage[19] Ty pical value = 0.75V 0.68 0.75 0.95 V
IXInput Leakage Current GND ≤ VI ≤ VDDQ –5 5 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA
IDD VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 500 mA
ISB1 Automatic
Power-Down
Current
Max. VDD, Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL f = fMAX =1/tCYC,
Inputs Static
240 mA
AC Input Requirements Over the Operating Range
Parameter Description Test Conditio ns Min. Typ. Max. Unit
VIH Input HIGH Voltage VREF + 0.2 – – V
VIL Input LOW Voltage – – VREF – 0. 2 V
Thermal Resistance[20]
Parameter Description Test Conditions 165 FBGA Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51.
16.7 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6.5 °C/W
Notes:
13.Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14.All Voltage refe renced to Ground.
15.Output are impedance contr olled. IOH = –VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
16.Output are impedance contr olled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
17.Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
18.This spec is for all input s except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
19.VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
20.Tested initially and after any design or process change that may affect these p arameters.
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Document #: 38-05627 Rev. *A Page 16 of 19
Capacitance[23]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 6 pF
COOutput Capacitance 7 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range [21]
Cypress
Parameter Consortium
Parameter Description
167 MHz
UnitMin. Max.
tPower[22] VCC (typical) to the First Access Read or Write 10 µs
Cycle Time
tCYC tKHKH K Clock and C Clock Cycle Time 6.0 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 ns
tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 ns
tKHKHtKHKHK/K Clock Rise to K/K Clock Rise and C/C to C/C Rise
(rising edge to rising edge) 2.7 3.3 ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns
Set-up Times
tSA tSA Address Set-up to Clock (K and K) Rise 0.7 ns
tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
tSD tSD D[x:0] Set-up to Clock (K and K) Rise 0.7 ns
Hold Times
tHA tHA Address Hold after Clock (K and K) Rise 0.7 n s
tHC tHC Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
tHD tHD D[x:0] Hold after Clock (K and K) Rise 0.7 n s
Output Times
tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns
tDOH tCHQX Data Output Hold after Output C /C Clock Rise (Active to Active) 1.2 ns
tCHZ tCHZ Clock (C and C) rise to High-Z (Active to High-Z)[23, 24] 2.5 ns
tCLZ tCLZ Clock (C and C) rise to Low-Z[23, 24] 1.2 ns
Notes:
21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing ref erence levels of 0.75V,Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
22.Thi s part has a volt age regulat or that step s down the volt age internally; tPower is t he time power needs to be supp lied above VDD minimum initiall y before a read
or write operation can be initiated.
23.At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
1.25V
0.25V
R = 50Ω
5pF
ALL INPUT PULSES
Device RL= 50Ω
Z0= 50Ω
VREF = 0.75V
VREF = 0.75V
[21]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
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Document #: 38-05627 Rev. *A Page 17 of 19
Switching Waveforms[25, 26, 27]
Notes:
24.tCHZ, tCLZ, are sp ecified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
25.Q00 refers to output from address A0. Q01 ref ers to output from the next internal burst address following A0, i.e., A0+1.
26.Outputs are disabled (High-Z) one clock cycle after a NOP.
27.In this example, if address A2 = A1 then data Q2 0= D10 and Q21 = D1 1. Write data is forwarded immediately as read results.This note applies to the whole diagram.
READ READ WRITE WRITEWRITE NOPREAD WRITE NOP
K
12345 8 1
0
67
K
RPS
W
PS
A
Q
D
C
C
A1
A0
D10
tKH tKHKH
tKHCH tCO
tKL tCYC
tHC
tSA tHA
tHD
tKHCH
DON’T CARE UNDEFINE
D
tCLZ tCHZ
tSC
tKH tKL
A2 A3 A4 A5 A6
tHA
D11 D30 D31 D50 D51 D60 D61
tSD tHD
Q00 Q21Q01 Q20 Q40 Q41
tCO
tDOH tDOH
tKHKH tCYC
9
tSA
tSD
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Document #: 38-05627 Rev. *A Page 18 of 19
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Quad Data Rate™ SRAM and QDR™ SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered”.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
167 CY7C1303BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1306BV25-167BZC
CY7C1303BV25-167BZXC 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1306BV25-167BZXC
CY7C1303BV25-167BZI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1306BV25-167BZI
CY7C1303BV25-167BZXI 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free
CY7C1306BV25-167BZXI
Package Diagram
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25MCAB
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN1CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
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Document #: 38-05627 Rev. *A Page 19 of 19
Document History Page
Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05627
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 253010 See ECN SYT New Data Sheet
*A 43686 4 See ECN NXR Converted from Preliminary to Final.
Removed 133 MHz & 100 MHz from product offering.
Included the Industrial Operating Range.
Changed C/C Description in the Features Section & Pin Description Table.
Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz
and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching
Characteristics table
Modified the ZQ pin definition as follo ws:
Alternately, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.
Modified the Description of IX from Input Load current to Input Leakage
Current on page # 15.
Modified test condition in note# 13 from VDDQ < VDD to VDDQ ≤ VDD
Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram.
