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MPC823ELE/D
Revision 1
MPC823 AC Electrical Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC823.
This device contains circuitry protecting against damage from high-static voltage or electrical
fields. However, it is advised that precautions be taken to avoid application of any voltages
higher than the maximum-rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or V
CC
).
Note:
Visit our website at www.motorola.com if you are using a frequency other than
25, 40, or 50MHz. Our website contains a spreadsheet that you can use to
calculate the timing for your specific system frequency.
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MPC823 ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (GND = 0V)
THERMAL CHARACTERISTICS
RATING SYMBOL VALUE UNIT
Supply Voltage VDDH -0.3 to 4.0 V
VDD -0.3 to 4.0 V
KAPWR -0.3 to 4.0 V
VDDSYN -0.3 to 4.0 V
Input Voltage (JTAG and GPIO) VIN -0.3 to 5.8 V
Input Voltage (All other pins) VIN -0.3 to 3.3 V
Operating Temperature T
A
0 to 70û
or
-40û to 85û
ûC
Storage Temperature Range T
STG
-55 to +150 ûC
NOTES:
1. Functional operating conditions are given in
DC Electrical Characteristics (VCC
= 3.0 - 3.6
V)
. Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause
permanent damage to the device.
2.
CAUTION
: The JTAG and GPIO input voltages cannot be more than 2.5 V greater than
supply voltage, this restriction applies also on Òpower-onÓ as well as on normal operation.
3. 5 Volt friendly inputs are inputs that tolerate 5 volts for JTAG and GPIO pins.
4. If you are using Mask Revision Base #F98S (Revision 0), all pins except EXTAL and CLK4IN
are 5V tolerant inputs.
CHARACTERISTIC SYMBOL VALUE UNIT
Thermal Resistance for BGA
q
Jc
~30
°
C/W
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MPC823 ELECTRICAL SPECIFICATIONS
3
POWER CONSIDERATIONS
The average chip-junction temperature
,
T
J
,
in
°
C can be obtained from
T
J
= T
A
+ (P
D
¥
q
JA
) (1)
where
T
A
= Ambient Temperature
,
¥
C
q
JA
= Package Thermal Resistance
,
Junction to Ambient
,
¥
C/W
P
D
=P
INT
+ P
I/O
P
INT
=I
DD
x V
DD
,
WattsÑChip Internal Power
P
I/O
= Power Dissipation on Input and Output PinsÑUser Determined
For most applications P
I/O
< 0.3
¥
P
INT
and can be neglected. If P
I/O
is neglected
,
an approximate
relationship between P
D
and T
J
is:
P
D
=K
Õ
(T
J
+ 273
¥
C) (2)
Solving equations (1) and (2) for K gives
K = P
D
¥
(T
A
+ 273
¥
C) + q
JA
¥ P
D
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K
,
the values of P
D
and T
J
can be obtained by solving equations (1) and (2) iteratively for any value of T
A
.
Layout Practices
Each V
CC
pin on the MPC823 should be provided with a low-impedance path to the boardÕs
supply. Each GND pin should be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
CC
power supply should be bypassed to
ground using at least four 0.1
m
F bypass capacitors located as close as possible to the four
sides of the package. The capacitor leads and associated printed circuit traces connecting to
chip V
CC
and GND should be kept to less than half an inch per capacitor lead. A four-layer
board that employs two inner layers as V
CC
and GND planes should be used.
All output pins on the MPC823 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections
caused by these fast output switching times. This recommendation particularly applies to the
address and data busses. Maximum PC trace lengths of six inches are recommended.
Capacitance calculations should consider all device loads as well as parasitic capacitances
due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents
in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
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MPC823 ELECTRICAL SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0 - 3.6 V)
CHARACTERISTIC SYMBOL MIN MAX UNIT
Input High Voltage (for JTAG and GPIO) V
IH
2.0 5.5 V
Input High Voltage (all other pins) V
IH
2.0 3.6 V
Input Low Voltage V
IL
GND 0.8 V
EXTAL and EXTCLK Input High Voltage V
IHC
0.7*(V
CC
)V
CC
+0.3 V
Input Leakage Current, V
IN
= 5.5 V I
IN
Ñ ±10 µA
Hi-z (Off State) Leakage Current, V
IN
= 3.5V I
OZ
Ñ ±10 µA
Signal Low Input Current, V
IL
= 0.8 V I
L
±10 µA
Signal High Input Current, V
IH
= 2.0 V I
H
±10 µA
Output High Voltage, I
OH
= Ð2.0 mA
,
V
DDH
= 3.0V
Except XTAL, XFC, and Open-Drain Pins
V
OH
2.4 Ñ V
Output Low Voltage
IOL = 2.0 mA CLKOUT
IOL = 3.2 mAA[6:31], TSIZ0/REG, TSIZ1, D(0:31), DP[0:3]/IRQ[3:6],
RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/
IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/
VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, USBRXD/PA15, RXD2/
PA13, SMRXD2/L1TXDA/PA9, SMTXD2/L1RXDA/PA8, IRQ4/KR/
SPKROUT, TIN1/L1RCLKA/BRGO1/CLK1/PA7, TIN3/TOUT1/
CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TIN4/TOUT2/CLK4/
PA4, LCD_A/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29,
BRGO3/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/
PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23,
SMSYN2/SDACK2/PB22, LCD_B/L1ST1/PB19, L1ST2/RTS2/
PB18, LCD_C/L1ST3/PB17, L1ST4/L1RQA/PB16, L1ST5/DREQ1/
PC15, L1ST6/RTS2/DREQ2/PC14, L1ST7/PC13, L1ST8/L1RQA/
PC12, USBRXP/PC11, USBRXN/TGATE1/PC10, CTS2/PC9,
TGATE1/CD2/PC8, USBTXP/PC7, USBTXN/PC6, SDACK1/
L1TSYNCA/PC5, L1RSYNCA/PC4, LD8/VD7/PD15, LD7/VD6/
PD14, LD6/VD5/PD13, LD5/VD4/PD12, LD4/VD3/PD11, LD3/VD2/
PD10, LD2/VD1/PD9, LD1/VD0/PD8, FRAME/VSYNC/PD5,
LCD_AC/LOE/BLANK/PD6, LD0/FIELD/PD7, LOAD/HSYNC/PD4,
SHIFT/CLK/PD3
V
OL
Ñ 0.5 V
IOL = 5.3 mABDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/
CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,
WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/
GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/
GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,
OP2/MODCK1/STS, OP3/MODCK2/DSDO
IOL = 7.0 mA USBOE/PA14, TXD2/PA12
IOL = 8.9 mATS, TA, TEA, BI, BB, HRESET, SRESET
NOTE: Input pin voltage specifications are V
CC
= +4 V or 5.8 V, whichever is less.
AC timings are based on a 50 p
¦
load.
If you are using Mask Revision Base #F98S, all pins except EXTAL and CLK4IN are 5V tolerant inputs.
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MPC823 ELECTRICAL SPECIFICATIONS
5
AC ELECTRICAL CHARACTERISTICS
CLKOUT
OUTPUTS
INPUTS
INPUTS
2.0V
0.8V
2.0V
2.0V
0.8V 0.8V
2.0V
2.0V
0.8V 0.8V
2.0V
2.0V
0.8V 0.8V
2.0V
OUTPUTS
2.0V
0.8V 0.8V
2.0V
0.8V
CD
A
B
C D
A
B
A = MAXIMUM OUTPUT DELAY SPECIFICATION
B = MINIMUM OUTPUT HOLD TIME
C = MINIMUM INPUT SETUP TIME SPECIFICATION
D = MINIMUM INPUT HOLD TIME SPECIFICATION
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MPC823 ELECTRICAL SPECIFICATIONS
EXTERNAL BUS ELECTRICAL CHARACTERISTICS
Table 1. Bus Operation Timing
NUM CHARACTERISTIC
25MHz 40MHz 50MHz
UNIT
MIN MAX MIN MAX MIN MAX
B1 CLKOUT Period 40 Ñ 25 Ñ 20 Ñ ns
B1a EXTCLK to CLKOUT Phase Skew (EXTCLK>15MHz and
MF
£
2) -0.9 0.9 -0.9 0.9 -0.9 0.9 ns
B1b EXTCLK to CLKOUT Phase Skew (EXTCLK>10MHz and
MF
£ 10) -2.3 2.3 -2.3 2.3 -2.3 2.3 ns
B1c CLKOUT Phase Jitter (EXTCLK>15MHz and MF£2) -0.6 0.6 -0.6 0.6 -0.6 0.6 ns
B1d CLKOUT Phase Jitter (EXTCLK>10MHz and MF£10) -22-22-22ns
B1e CLKOUT Frequency Jitter (MF<10) Ñ 0.5 Ñ 0.5 Ñ 0.5 %
B1f CLKOUT Frequency Jitter (10<MF<500) Ñ2Ñ2Ñ2 %
B1g CLKOUT Frequency Jitter (MF>500) Ñ3Ñ3Ñ3 %
B1h Frequency Jitter on EXTCLK Ñ 0.5 Ñ 0.5 Ñ 0.5 %
B2 Clock Pulse Width Low 16 Ñ 10 Ñ 8 Ñ ns
B3 Clock Pulse Width High 16 Ñ 10 Ñ 8 Ñ ns
B4 CLKOUT Rise Time Ñ4Ñ4Ñ4 ns
B5 CLKOUT Fall Time Ñ4Ñ4Ñ4 ns
B6 N/A (Used on Interactive Spreadsheet)
B7 CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3)
Invalid 10Ñ5Ñ5Ñns
B7a CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3),BDIP, PTR Invalid 10 Ñ5Ñ5Ñns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2),
LWP(0:1), STS Invalid 10Ñ5Ñ5Ñns
B8 CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3) Valid 10 19 5 13 5 12 ns
B8a CLKOUT to TSIZ(0:1),REG, RSV, AT(0:3), BDIP, PTR Valid 10 19 5 13 5 12 ns
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ,
LWP(0:1), STS Valid 1019513512ns
B9 CLKOUT to A(6:31), RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1),REG, RSV, AT(0:3), PTR Hi Z 1019513512ns
B10 N/A
B11 CLKOUT to TS, BB Assertion 10 19 5 12.25 5 12.25 ns
B11a CLKOUT to TA, BI Assertion (when driven by the
Memory Controller or PCMCIA Interface) 2.5 11 2.5 9.25 2.5 9.25 ns
B12 CLKOUT to TS, BB Negation 10 19 5 13 5 12 ns
B12a CLKOUT to TA, BI Negation (when driven by the
Memory Controller or PCMCIA Interface) 2.5 11 2.5 11 2.5 11 ns
B13 CLKOUT to TS, BB Hi Z 1024521519ns
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MPC823 ELECTRICAL SPECIFICATIONS 7
B13a CLKOUT to TA, BI Hi Z (When Driven by the Memory
Controller or PCMCIA Interface) 2.5 15 2.5 15 2.5 16 ns
B14 CLKOUT to TEA Assertion 2.5 11 2.5 11 2.5 10 ns
B15 CLKOUT to TEA Hi Z 2.5 15 2.5 15 2.5 15 ns
B16 TA, BI Valid to CLKOUT (Setup Time) 9.75 Ñ 9.75 Ñ 9.75 Ñ ns
B16a TEA, KR, RETRY Valid to CLKOUT (Setup Time) 11 Ñ 10 Ñ 10 Ñ ns
B16b BB, BG, BR Valid to CLKOUT (Setup Time) 8.5 Ñ 8.5 Ñ 8.5 Ñ ns
B17 CLKOUT to TA, TEA, BI , BB, BG, BR Valid (Hold Time) 1Ñ1Ñ1Ñns
B17a CLKOUT to KR, RETRY Valid (Hold Time) 2Ñ2Ñ2Ñns
B18 D(0:31), DP(0:3) Valid to CLKOUT Rising Edge (Setup Time) 6Ñ6Ñ6Ñns
B19 CLKOUT Rising Edge to D(0:31), DP(0:3) Valid (Hold Time) 2Ñ2Ñ2Ñns
B20 D(0:31), DP(0:3) Valid to CLKOUT Falling Edge (Setup Time) 4Ñ4Ñ4Ñns
B21 CLKOUT Falling Edge to D(0:31), DP(0:3) Valid (Hold Time) 2Ñ2Ñ2Ñns
B22 CLKOUT Rising Edge to CS Asserted -GPCM- ACS = 00 10 20 5 13 5 13 ns
B22a CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 10,
TRLX = 0 Ñ10Ñ8Ñ8 ns
B22b CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11,
TRLX = 0, EBDF = 0 1020513513ns
B22c CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11,
TRLX = 0, EBDF = 1 1425716716ns
B23 CLKOUT Rising Edge to CS Negated -GPCM-Read Access -
GPCM-Write Access, ACS=00, TRLX=0, CSNT=0 3102828ns
B24 A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 0 8Ñ3Ñ3Ñns
B24a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 0 18 Ñ8Ñ8Ñns
B25 CLKOUT Rising Edge to OE, WE(0:3) Asserted Ñ 11 Ñ9Ñ9 ns
B26 CLKOUT Rising Edge to OE Negated 3 11 2929ns
B27 A(6:31) to CS Asserted -GPCM- ACS = 10, TRLX = 1 48 Ñ 23 Ñ 23 Ñ ns
B27a A(6:31) to CS Asserted -GPCM- ACS = 11, TRLX = 1 58 Ñ 28 Ñ 28 Ñ ns
B28 CLKOUT Rising Edge to WE(0:3) Negated -GPCM-Write
Access CSNT = Ô0Ô Ñ11Ñ9Ñ9 ns
B28a CLKOUT Falling Edge to WE(0:3) Negated -GPCM-Write
Access TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF=0 1020513513ns
B28b CLKOUT Falling Edge to CS Negated -GPCM-Write Access
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0 Ñ20Ñ13Ñ13 ns
Table 1. Bus Operation Timing (Continued)
NUM CHARACTERISTIC
25MHz 40MHz 50MHz
UNIT
MIN MAX MIN MAX MIN MAX
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MPC823 ELECTRICAL SPECIFICATIONS
B28c CLKOUT Falling Edge to WE(0:3) Negated -GPCM-Write
Access TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF=1 1425716716ns
B28d CLKOUT Falling Edge to CS Negated -GPCM-Write Access
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 1 Ñ25Ñ16Ñ16 ns
B29 WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, CSNT = Ô0Õ 8Ñ3Ñ3Ñns
B29a WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF = 0 18Ñ8Ñ8Ñns
B29b CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
ACS = Ô00Õ, TRLX = Ô0Õ & CSNT = Ô0Õ 8Ñ3Ñ3Ñns
B29c CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0 18Ñ8Ñ8Ñns
B29d WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, TRLX = Ô1Õ, CSNT = Ô1Õ, EBDF = 0 58Ñ28Ñ28Ñ ns
B29e CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô1Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 0 58Ñ28Ñ28Ñ ns
B29f WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, TRLX = Ô0Õ, CSNT = Ô1Õ, EBDF = 1 12Ñ5Ñ5Ñns
B29g CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô0Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF = 1 12Ñ5Ñ5Ñns
B29h WE(0:3) Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write
Access, TRLX = Ô1Õ, CSNT = Ô1Õ, EBDF = 1 52Ñ24Ñ24Ñ ns
B29i CS Negated to D(0:31), DP(0:3) Hi Z -GPCM- Write Access,
TRLX = Ô1Õ, CSNT = Ô1Õ, ACS = Ô10Õ or ACS=Õ11Õ, EBDF =1 52Ñ24Ñ24Ñ ns
B30 CS, WE(0:3) Negated to A(6:31) invalid -GPCM- Write
Access. 8Ñ3Ñ3Ñ
B30a
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
TRLX=Õ0Õ, CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCM-
Write Access, TRLX=Õ0Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 0
18Ñ8Ñ8Ñns
B30b
WE(0:3) Negated to A(6:31)Invalid -GPCM- Write Access,
TRLX=Õ1Õ, CSNT = '1Õ. CS Negated to A(6:31)Invalid -GPCM-
Write Access, TRLX=Õ1Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 0
58Ñ28Ñ28Ñ ns
B30c
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
TRLX=Õ0Õ, CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCM-
Write Access, TRLX=Õ0Õ, CSNT = '1Õ, ACS = 10 ,ACS = =Õ11Õ,
EBDF = 1
12Ñ4Ñ4Ñns
B30d
WE(0:3) Negated to A(6:31) Invalid -GPCM- Write Access,
TRLX=Õ1Õ, CSNT = '1Õ. CS Negated to A(6:31) Invalid -GPCM-
Write Access, TRLX=Õ1Õ, CSNT = '1Õ, ACS = 10,ACS = =Õ11Õ,
EBDF = 1
52Ñ24Ñ24Ñ ns
B31 CLKOUT Falling Edge to CS valid as requested by CST4 in
the corresponding word of the UPM 1.5 10 1.5 8 1.5 8 ns
Table 1. Bus Operation Timing (Continued)
NUM CHARACTERISTIC
25MHz 40MHz 50MHz
UNIT
MIN MAX MIN MAX MIN MAX
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MPC823 ELECTRICAL SPECIFICATIONS 9
B31a CLKOUT Falling Edge to CS valid as requested by CST1 in
the corresponding word of the UPM, EBDF = 0 1020513513ns
B31b CLKOUT Rising Edge to CS valid as requested by CST2 in
the corresponding word of the UPM 1.5 10 1.5 8 1.5 8 ns
B31c CLKOUT Rising Edge to CS valid as requested by CST3 in
the corresponding word of the UPM 1020513513ns
B31d CLKOUT Falling Edge to CS valid as requested by CST1 in
the corresponding word of the UPM, EBDF = 1 1025516516ns
B32 CLKOUT Falling Edge to BS valid as requested by BST4 in
the corresponding word of the UPM 1.5 10 1.5 8 1.5 8 ns
B32a CLKOUT Falling Edge to BS valid as requested by BST1 in
the corresponding word of the UPM, EBDF = 0 1020513513ns
B32b CLKOUT Rising Edge to BS valid as requested by BST2 in the
corresponding word of the UPM 1.5 10 1.5 8 1.5 8 ns
B32c CLKOUT Rising Edge to BS valid as requested by BST3 in the
corresponding word of the UPM 1020513513ns
B32d CLKOUT Falling Edge to BS valid as requested by BST1 in
the corresponding word of the UPM, EBDF = 1 1025516516ns
B33 CLKOUT Falling Edge to GPL valid as requested by GxT4 in
the corresponding word of the UPM 1.5 10 1.5 8 1.5 8 ns
B33a CLKOUT Rising Edge to GPL valid as requested by GxT3 in
the corresponding word of the UPM 1020513513ns
B34 A(6:31) and D(0:31) to CS valid as requested by CST4 in the
corresponding word of the UPM 8Ñ3Ñ3Ñns
B34a A(6:31) and D(0:31) to CS valid as requested by CST1 in the
corresponding word of the UPM 18Ñ8Ñ8Ñns
B34b A(6:31) and D(0:31) to CS valid as requested by CST2 in the
corresponding word of the UPM 28Ñ13Ñ13Ñ ns
B35 A(6:31) and D(0:31) to BS valid as requested by BST4 in the
corresponding word of the UPM 8Ñ3Ñ3Ñns
B35a A(6:31) and D(0:31) to BS valid as requested by BST1 in the
corresponding word of the UPM 18Ñ8Ñ8Ñns
B35b A(6:31) and D(0:31) to BS valid as requested by BST2 in the
corresponding word of the UPM 28Ñ13Ñ13Ñ ns
B36 A(6:31) and D(0:31) to GPL valid as requested by GxT4 in the
corresponding word of the UPM 8Ñ3Ñ3Ñns
B37 UPWAIT Valid to CLKOUT Falling Edge 6Ñ6Ñ6Ñns
B38 CLKOUT Falling Edge to UPWAIT Valid 1Ñ1Ñ1Ñns
B39 AS Valid to CLKOUT Rising Edge 9Ñ7Ñ7Ñns
Table 1. Bus Operation Timing (Continued)
NUM CHARACTERISTIC
25MHz 40MHz 50MHz
UNIT
MIN MAX MIN MAX MIN MAX
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MPC823 ELECTRICAL SPECIFICATIONS
B40 A(6:31), TSIZ(0:1), RD/WR, BURST, Valid to CLKOUT Rising
Edge 9Ñ7Ñ7Ñns
B41 TS Valid to CLKOUT Rising Edge (Setup Time) 9Ñ7Ñ7Ñns
B42 CLKOUT Rising Edge to TS Valid (Hold Time) 2Ñ2Ñ2Ñns
B43 AS Negation to Memory Controller Signals Negation Ñ 13 Ñ 13 Ñ 13 ns
NOTES:
1. The timing for BR output is relevant when the MPC823 is selected to work with the external bus arbiter.
The timing for BG output is relevant when the MPC823 is selected to work with the internal bus arbiter.
2. The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device
(and not when the memory controller or the PCMCIA interface drive them).
3. The timing required for BR input is relevant when the MPC823 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC823 is selected to work with the external bus arbiter.
4. The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the T
A
input signal is asserted.
5. The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is
valid only under control of the UPM in the memory controller.
6. The timing B30 refers to CS when ACS = Ô00Õ and to WE(0:3) when CSNT = Ô0Õ.
7. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings
speciÞed in B37 and B38 are speciÞed to enable the freeze of the UPM output signals.
8. The AS signal is considered asynchronous to the CLKOUT signal.
Figure 1. External Clock Timing Diagram
Table 1. Bus Operation Timing (Continued)
NUM CHARACTERISTIC
25MHz 40MHz 50MHz
UNIT
MIN MAX MIN MAX MIN MAX
CLKOUT
B1
B1
B4 B5
B3
B2
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Figure 2. Synchronous Output Signals Timing Diagram
CLKOUT
OUTPUT
SIGNALS
OUTPUT
SIGNALS
OUTPUT
SIGNALS
B8
B9
B9
B8a
B7a
B7
B7b
B8b
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Figure 3. Synchronous Active Pull-Up and Open-Drain
Outputs Signals Timing Diagram
CLKOUT
TS, BB
TEA
TA, BI
B11
B13
B13a
B12
B12a
B11a
B14
B15
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MPC823 ELECTRICAL SPECIFICATIONS 13
Figure 4. Synchronous Input Signals Timing Diagram
CLKOUT
TA, BI, TEA
TEA, RETRY, KR
BB, BG, BR
B16
B16a
B16b
B17
B17a
B17
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Figure 5. Input Data In Normal Case Timing Diagram
Figure 6. Input Data When Controlled by the UPM Timing Diagram
CLKOUT
TA
D(0:31),
DP(0:3)
B16
B18
B19
B17
TA
D(0:31),
DP(0:3)
CLKOUT
B20
B21
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Figure 7. External Bus Read Timing Diagram (GPCM ControlledÐACS = Ô00Õ)
Figure 8. External Bus Read Timing Diagram (GPCM ControlledÐTRLX = Ô0Õ, ACS = Ô10Õ)
CLKOUT
B11
TS
CSx
OE
WE(0:3)
D(0:31),
DP(0:3)
A(6:31)
B8
B22a
B28
B26
B18
B12
B23
B19
B25
CLKOUT
TS
A(6:31)
B11
CSx
OE
D(0:31),
DP(0:3)
B8
B12
B19
B25
B23
B22b
B18
B24a B26
B22c
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Figure 9. External Bus Read Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, ACS = Ô11Õ)
CLKOUT
TS
A(6:31)
B11
CSx
OE
D(0:31),
DP(0:3)
B12
B26
B19
B25
B23
B22b
B18
B24a
B22c
B8
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Figure 10. External Bus Read Timing Diagram
(GPCM ControlledÐTRLX = Ô1Õ, ACS = Ô10Õ, ACS = Ô11Õ)
CLKOUT
TS
A(6:31)
CSx
OE
D(0:31),
DP(0:3)
B22a
B18
B19
B27
B27a
B22b
B12
B26
B23
B11
B8
B22c
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Figure 11. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, CSNT = Ô0Õ)
CLKOUT
TS
A(6:31)
CSx
WE(0:3)
D(0:31),
DP(0:3)
B8
OE
B12
B8
B11
B22
B28
B30
B23
B29b
B26
B29
B9
B25
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MPC823 ELECTRICAL SPECIFICATIONS 19
Figure 12. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô0Õ, CSNT = Ô1Õ)
CLKOUT
TS
A(6:31)
CSx
WE(0:3)
D(0:31),
DP(0:3)
OE
B22
B11 B12
B30
B28c
B9
B30a
B28d
B25
B8
B23
B28b
B29gB29c
B29f
B29a
B28a
B8
B26
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Figure 13. External Bus Write Timing Diagram
(GPCM ControlledÐTRLX = Ô1Õ, CSNT = Ô1Õ)
CLKOUT
TS
A(6:31)
CSx
WE(0:3)
D(0:31),
DP(0:3)
OE
B22
B11
B8
B12
B30d B30b
B23
B28d
B29e
B29h B29d
B29b
B28c
B28a
B9
B8
B26
B25
B28b
B29f
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Figure 14. External Bus Timing Diagram (UPM-Controlled Signals)
CLKOUT
A(6:31)
GPLA(0:5),
GPLB(0:5)
CSx
BS_AB(0:3)
B8
B31
B31d
B31a
B31b
B31c
B32c
B32b
B33a
B36
B33
B35b
B35a
B35
B32
B32a
B32d
B34b
B34a
B34
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Figure 15. Asynchronous UPWAIT Asserted Detection in UPM
Handled Cycles Timing Diagram
CLKOUT
UPWAIT
CSx
BS_AB(0:3)
GPLA(0:5),
GPLB(0:5)
B37
B38
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Figure 16. Asynchronous UPWAIT Negated Detection in UPM
Handled Cycles Timing Diagram
Figure 17. Synchronous External Master Access Timing Diagram
(GPCM HandledÐACS = Ô00Õ)
CLKOUT
UPWAIT
CSx
BS_AB(0:3)
GPLA(0:5),
GPLB(0:5)
B37
B38
CLKOUT
TS
A(6:31), TSIZ(0:1),
CSx
RD/WR, BURST
B40
B41
B42
B22
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Figure 18. Asynchronous External Master Memory Access Timing Diagram
(GPCM ControlledÐACS = Õ00Õ)
Figure 19. Asynchronous External Master Timing Diagram
(Control Signals Negation Time)
CLKOUT
AS
A(6:31),
CSx
TSIZ(0:1),
RD/WR
B40
B39
B22
AS
CSx,
WE(0:3),
OE, GPLx,
BS(0:3),
B43
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MPC823 ELECTRICAL SPECIFICATIONS 25
Table 2. Interrupt Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
I39 IRQx valid to CLKOUT rising edge (setup time) 6 Ñ 6/6 Ñ 6/6 Ñ ns
I40 IRQx hold time after CLKOUT 2 Ñ 2/2 Ñ 2/2 Ñ ns
I41 IRQx pulse width low 3 Ñ 3/3 Ñ 3/3 Ñ ns
I42 IRQx pulse width high 3 Ñ 3/3 Ñ 3/3 Ñ ns
I43 IRQx edge to edge time 160 Ñ 80/80 Ñ 80/80 Ñ ns
NOTES:
1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with
reference to the CLKOUT.
2. The timings I41 and I42 are speciÞed to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC823 can support.
Figure 20. Interrupt Detection Timing Diagram
for External Level-Sensitive Lines
CLKOUT
IRQx
I39
I40
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Figure 21. Interrupt Detection Timing Diagram
for External Edge-Sensitive Lines
CLKOUT
IRQx
I39
I43
I42
I41
I43
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MPC823 ELECTRICAL SPECIFICATIONS 27
Table 3. PCMCIA Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
P44 A(6:31), REG valid to PCMCIA strobe asserted 28 Ñ 13 Ñ 13 Ñ ns
P45 A(6:31), REG valid to ALE negation 38 Ñ 18 Ñ 18 Ñ ns
P46 CLKOUT to REG valid 10 19 5 13 5 13 ns
P47 CLKOUT to REG invalid 11 Ñ6Ñ6Ñns
P48 CLKOUT to CE1, CE2 asserted 10 19 5 13 5 13 ns
P49 CLKOUT to CE1, CE2 negated 10 19 5 13 5 13 ns
P50 CLKOUT to PCOE, IORD, PCWE, IOWR assert
time Ñ12Ñ11Ñ11ns
P51 CLKOUT to PCOE, IORD, PCWE, IOWR negate
time 312211211ns
P52 CLKOUT to ALE assert time 10 19 5 13 5 13 ns
P53 CLKOUT to ALE negate time Ñ 19 Ñ 13 Ñ 13 ns
P54 PCWE, IOWR negated to D(0:31) invalid 8Ñ3Ñ3Ñns
P55 WAIT_B valid to CLKOUT rising edge 8Ñ8Ñ8Ñns
P56 CLKOUT rising edge to WAIT_B invalid 2Ñ2Ñ2Ñns
NOTES:
1. PSST = 1. Otherwise, add PSST times cycle time.
2. PSHT = 0. Otherwise, add PSHT times cycle time.
3. These synchronous timings deÞne when the WAIT_B signal is detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAIT_B assertion will be effective only if it is detected two cycles before the PSL
timer expiration.
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Figure 22. PCMCIA Access Cycles Timing Diagram (External Bus Read)
CLKOUT
TS
A(0:31)
REG
CE[1:2]
PCOE,
IORD
ALE
D(0:31)
PCOE,
P44
P45
P46
P48
P52
P50
P53
B18
P47
P49
P51
P52
B19
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MPC823 ELECTRICAL SPECIFICATIONS 29
Figure 23. PCMCIA Access Cycles Timing Diagram (External Bus Write)
CLKOUT
TS
A[0:31]
REG
CE[1:2]
PCOE,
IORD
ALE
D[0:31]
P44
P45
P46
P50
P53
P52
P48
B8 B9
P54
P52
P51
P49
P47
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Figure 24. PCMCIA Wait Signals Detection Timing Diagram
Figure 25. PCMCIA Wait Signals Detection Timing Diagram
CLKOUT
WAITx
P55
P56
CLKOUT
WAITx
P55
P56
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MPC823 ELECTRICAL SPECIFICATIONS 31
Table 4. PCMCIA Port Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
P57 CLKOUT to OPx Valid Ñ 25 Ñ 19 Ñ 19 ns
P58 HRESET negated to OPx drive 30 Ñ 18 Ñ 18 Ñ ns
P59 IP_Bx valid to CLKOUT Rising Edge 6Ñ5Ñ5Ñns
P60 CLKOUT Rising Edge to IP_Bx invalid 2Ñ1Ñ1Ñns
NOTE: *OP2 and OP3 only.
Figure 26. PCMCIA Output Port Timing Diagram
Figure 27. PCMCIA Input Port Timing Diagram
CLKOUT
OUTPUT
SIGNALS
HRESET
OP2, OP3
P58
P57
INPUT
SIGNALS
CLKOUT
P59
P60
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Table 5. Debug Port Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
D61 DSCK cycle time 120 Ñ 60 Ñ 60 Ñ ns
D62 DSCK clock pulse width 50 Ñ 25 Ñ 25 Ñ ns
D63 DSCK rise and fall times 030303ns
D64 DSDI input data setup time 8Ñ8Ñ8Ñns
D65 DSDI data hold time 5Ñ5Ñ5Ñns
D66 DSCK low to DSDO data valid 0 15 0 15 0 15 ns
D67 DSCK low to DSDO invalid 020202ns
Figure 28. Debug Port Clock Input Timing Diagram
CLKOUT
D61
D61
D63 D63
D62
D62
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MPC823 ELECTRICAL SPECIFICATIONS 33
Figure 29. Debug Port Timing Diagram
DSCK
DSDI
DSDO
D64
D65
D66
D67
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Table 6. Reset Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
R68 CLKOUT to HRESET high impedance Ñ 20 Ñ 20 Ñ 20 ns
R69 CLKOUT to SRESET high impedance Ñ 20 Ñ 20 Ñ 20 ns
R70 RSTCONF pulse width 680 Ñ 425 Ñ 340 Ñ ns
R71 N/A
R72 Configuration data to HRESET rising edge setup
time 650 Ñ 425 Ñ 350 Ñ ns
R73 Configuration data to RSTCONF rising edge setup
time 650 Ñ 425 Ñ 350 Ñ ns
R74 Configuration data hold time after RSTCONF
negation 0Ñ0Ñ0Ñns
R75 Configuration data hold time after HRESET negation 0Ñ0Ñ0Ñns
R76 HRESET and RSTCONF asserted to data out drive Ñ 25 Ñ 25 Ñ 25 ns
R77 RSTCONF negated to data out high impedance Ñ 25 Ñ 25 Ñ 25 ns
R78 CLKOUT of last rising edge before chip three-states
HRESET to data out high impedance Ñ25Ñ25Ñ25 ns
R79 DSDI and DSCK setup 120 Ñ 75 Ñ 60 Ñ ns
R80 DSDI and DSCK hold time 0Ñ0Ñ0Ñns
R81 SRESET negated to CLKOUT rising edge for DSDI
and DSCK sample 320 Ñ 200 Ñ 160 Ñ ns
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MPC823 ELECTRICAL SPECIFICATIONS 35
Figure 30. Reset Timing Diagram (Configuration from Data Bus)
Figure 31. Reset Timing DiagramÐMPC823 Data Bus Weak Drive During Configuration
HRESET
RSTCONF
D(0:31) (IN)
R75
R74
R73
R76
R71
CLKOUT
HRESET
D(0:31) (OUT)
RSTCONF
(WEAK)
R77
R78
R79
R69
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Figure 32. Reset Timing DiagramÐDebug Port Configuration
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80
R81
R81
R80
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MPC823 ELECTRICAL SPECIFICATIONS 37
Table 7. JTAG Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
J82 TCK cycle time 100 Ñ 100 Ñ 100 Ñ ns
J83 TCK clock pulse width measured at 1.5V 40 Ñ 40 Ñ 40 Ñ ns
J84 TCK rise and fall times 0 10 0 10 0 10 ns
J85 TMS, TDI data setup time 5Ñ5Ñ5Ñns
J86 TMS, TDI data hold time 25 Ñ 25 Ñ 25 Ñ ns
J87 TCK low to TDO data valid Ñ 27 Ñ 27 Ñ 27 ns
J88 TCK low to TDO data invalid 0Ñ0Ñ0Ñns
J89 TCK low to TDO high impedance Ñ 20 Ñ 20 Ñ 20 ns
J90 TRST assert time 100 Ñ 100 Ñ 100 Ñ ns
J91 TRST setup time to TCK low 40 Ñ 40 Ñ 40 Ñ ns
J92 TCK falling edge to output valid Ñ 50 Ñ 50 Ñ 50 ns
J93 TCK falling edge to ouput valid out of high impedance Ñ 50 Ñ 50 Ñ 50 ns
J94 TCK falling edge to output high impedance Ñ 50 Ñ 50 Ñ 50 ns
J95 Boundary scan input valid to TCK rising edge 50 Ñ 50 Ñ 50 Ñ ns
J96 TCK rising edge to boundary scan input invalid 50 Ñ 50 Ñ 50 Ñ ns
Figure 33. JTAG Test Clock Input Timing Diagram
TCK
J84
J83J82
J82
J84
J83
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Figure 34. JTAGÐTest Access Port Timing Diagram
Figure 35. JTAGÐTRST Timing Diagram
TCK
TMS, TDI
TDO
J85
J86
J88
J87
J89
TCK
TRST
J91
J90
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MPC823 ELECTRICAL SPECIFICATIONS 39
Figure 36. Boundary Scan (JTAG) Timing Diagram
TCK
OUTPUT
SIGNALS
OUTPUT
SIGNALS
OUTPUT
SIGNALS
J92
J94
J93
J96
J95
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COMMUNICATION ELECTRICAL CHARACTERISTICS
Table 8. Parallel Input/Output Port Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
29 Data-in setup time to clock high 20 Ñ 15 Ñ 15 Ñ ns
30 Data-in hold time from clock high 10 Ñ 7.5 Ñ 7.5 Ñ ns
31 Clock high to data-out valid (CPU writes
data, control, or direction) Ñ25Ñ25Ñ25ns
Figure 37. Parallel Input/Output Data-In/Data-Out Timing Diagram
CLKOUT
DATA IN
DATA OUT
29
31
30
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MPC823 ELECTRICAL SPECIFICATIONS 41
Table 9. IDMA Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
40 DREQ setup time to clock high 12 Ñ7Ñ7Ñnsec
41 DREQ hold time from clock high 5Ñ3Ñ3Ñnsec
42 SDACK assertion delay from clock high Ñ 20 Ñ 12 Ñ 12 nsec
43 SDACK negation delay from clock low Ñ 20 Ñ 12 Ñ 12 nsec
44 SDACK negation delay from TA low Ñ 25 Ñ 20 Ñ 20 nsec
45 SDACK negation delay from clock high Ñ 20 Ñ 15 Ñ 15 nsec
46 TA assertion to falling edge of the clock
setup time 12Ñ7Ñ7Ñnsec
NOTE: Applies to external TA.
Figure 38. IDMA External Requests Timing Diagram
CLKOUT
DREQ
(INPUT)
(OUTPUT)
41
40
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Figure 39. SDACK Timing DiagramÐPeripheral Write, TA Sampled Low
at the Falling Edge of the Clock
SDACK
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
DATA
TA
(OUTPUT)
42
46
43
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MPC823 ELECTRICAL SPECIFICATIONS 43
Figure 40. SDACK Timing DiagramÐPeripheral Write, TA Sampled High
at the Falling Edge of the Clock
SDACK
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
DATA
TA
(OUTPUT)
42 44
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Figure 41. SDACK Timing DiagramÐPeripheral Read
SDACK
CLKOUT
(OUTPUT)
TS
(OUTPUT)
RD / WR
(OUTPUT)
DATA
TA
(OUTPUT)
42 45
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Table 10. Baud Rate Generator Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ UNIT
MIN MAX MIN MAX MIN MAX
50 BRGO rise and fall times Ñ 10 Ñ 10 Ñ 10 ns
51 BRGO duty cycle 40 60 40 60 40 60 %
52 BRGO cycle 40 Ñ 40 Ñ 40 Ñ ns
Figure 42. Baud Rate Generator Timing Diagram
BRGOx
50 50
51
51
52
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Table 11. General-Purpose Timers Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
61 TIN/TGATE rise and fall times 12 10 7 10 7 10 ns
62 TIN/TGATE low time 513131clk
63 TIN/TGATE high time Ñ 20 Ñ 12 Ñ 12 clk
64 TIN/TGATE cycle time Ñ 20 Ñ 12 Ñ 12 clk
65 CLKO low to TOUT valid Ñ 25 Ñ 20 Ñ 20 ns
Figure 43. General-Purpose Timers Timing Diagram
CLKOUT
TIN / TGATE
(INPUT)
TOUT
(OUTPUT)
61
60
63 62
64
61
65
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MPC823 ELECTRICAL SPECIFICATIONS 47
Table 12. Serial Interface Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
70 L1RCLK and L1TCLK frequency (DSC=0)1,3 Ñ10Ñ10Ñ10MHz
71 L1RCLK and L1TCLK width low (DSC=0)3P+10 Ñ P+10 Ñ P+10 Ñ ns
71a L1RCLK and L1TCLK width high (DSC=0)2P+10 Ñ P+10 Ñ P+10 Ñ ns
72 L1TXD, L1ST(1Ð8), L1RQ, L1CLKO rise and fall
times Ñ15Ñ15Ñ15 ns
73 L1RSYNC, L1TSYNC valid to L1CLK edge
(SYNC setup time) 20Ñ20Ñ20Ñ ns
74 L1CLK edge to L1RSYNC and L1TSYNC invalid
(SYNC hold time) 35Ñ35Ñ35Ñ ns
75 L1RSYNC and L1TSYNC rise and fall times Ñ 15 Ñ 15 Ñ 15 ns
76 L1RXD valid to L1CLK edge (L1RXD setup time) 42 Ñ 42 Ñ 42 Ñ ns
77 L1CLK edge to L1RXD invalid (L1RXD hold time) 35 Ñ 35 Ñ 35 Ñ ns
78 L1CLK edge to L1ST(1Ð8) valid 10 45 10 45 10 45 ns
78a L1SYNC valid to L1ST(1Ð8) valid410 45 10 45 10 45 ns
79 L1CLK edge to L1ST(1Ð8) invalid 10 45 10 45 10 45 ns
80 L1CLK edge to L1TXD valid 10 65 10 65 10 65 ns
80a L1TSYNC valid to L1TXD valid410 65 10 65 10 65 ns
81 L1CLK edge to L1TXD high impedance 0 42 0 42 0 42 ns
82 L1RCLK and L1TCLK frequency (DSC=1) Ñ 12.5 Ñ 16 Ñ 16 MHz
83 L1RCLK and L1TCLK width low (DSC=1) P+10 Ñ P+10 Ñ P+10 Ñ ns
83a L1RCLK and L1TCLK width high (DSC=1)2P+10 Ñ P+10 Ñ P+10 Ñ ns
84 L1CLK edge to L1CLKO valid (DSC=1) Ñ 30 Ñ 30 Ñ 30 ns
85 L1RQ valid before falling edge of L1TSYNC31Ñ1Ñ1ÑL1TCLK
86 L1GR setup time342Ñ42Ñ42Ñ ns
87 L1GR hold time342Ñ42Ñ42Ñ ns
88 L1CLK edge to L1SYNC valid
(FSD = 00, CNT = 0000, BYT = 0, DSC=0) Ñ0Ñ0Ñ0 ns
NOTES:
1. The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2. Where P=1/CLKO1. For a 25MHz CLKO1 rate, P=40ns.
3. These electrical speciÞcations are only valid for IDL mode.
4. The strobes and TXD2 on the Þrst bit of the frame becomes valid after L1CLK edge or L1SYNC, whichever
is later.
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Figure 44. Serial Interface Receive Timing Diagram With Normal Clocking (DSC =0)
BIT0
RFCD=1
L1RCLK
(FE=0, CE=0)
(INPUT)
L1RCLK
(FE=1, CE=1)
(INPUT)
L1RSYNC
(INPUT)
L1RXD
(INPUT)
L1ST(1-4)
(OUTPUT)
71 70
72
75
73
74
77
76
78 79
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MPC823 ELECTRICAL SPECIFICATIONS 49
Figure 45. Serial Interface Transmit Timing Diagram
TFCD=0
L1TCLK
(FE=0, CE=0)
(INPUT)
L1TCLK
(FE=1, CE=1)
(INPUT)
L1TSYNC
(INPUT)
L1TXD
(OUTPUT)
L1ST(1-4)
(OUTPUT)
BIT0
71
70
72
73
75
74
80a
80
78a
78
79
81
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Table 13. Serial Communication Controller in NMSI External Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
100 RCLK1 and TCLK1 width high1CLKOUT
FÑ CLKOUT
FÑ CLKOUT
FÑ MHz
101 RCLK1 and TCLK1 width low CLKOUT
+5ns Ñ CLKOUT
+5ns Ñ CLKOUT
+5ns Ñns
102 RCLK1 and TCLK1 rise and fall times Ñ 15 Ñ 15 Ñ 15 ns
103 TXD2 active delay (from TCLK1 falling
edge) 050050050ns
104 RTS1 active/inactive delay (from TCLK1
falling edge) 050050050ns
105 CTS1 setup time to TCLK1 rising edge 5Ñ5Ñ5Ñns
106 RXD2 setup time to RCLK1 rising edge 5Ñ5Ñ5Ñns
107 RXD2 hold time from RCLK1 rising
edge25Ñ5Ñ5Ñns
108 CD1 setup time to RCLK1 rising edge 5Ñ5Ñ5Ñns
NOTES:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2. Applies to CD and CTS hold time when they are used as external sync signals.
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Table 14. Serial Communication Controller in NMSI Internal Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
100 RCLK1 and TCLK1 frequency10 8.3 0 13 0 16 MHz
102 RCLK1 and TCLK1 rise and all times ÑÑÑÑÑÑns
103 TXD2 active delay (from TCLK1 falling
edge) 030030030ns
104 RTS1 active/inactive delay (from TCLK1
falling edge) 030030030ns
105 CTS1 setup time to TCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns
106 RXD2 setup time to RCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns
107 RXD2 hold time from RCLK1 rising edge20Ñ0Ñ0Ñns
108 CD1 setup time to RCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns
NOTES:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1.
2. Applies to CD and CTS hold time when they are used as external sync signals.
Figure 46. SCC NMSI Receive Timing Diagram
RCLK1
RXD2
(INPUT)
CD1
(INPUT)
CD1
(SYNC
INPUT)
102 102 101
100
107
106
108
107
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Figure 47. SCC NMSI Transmit Timing Diagram
TCLK1
TXD2
(OUTPUT)
RTS1
(OUTPUT)
CTS1
(INPUT)
CTS1
(SYNC
INPUT)
102
102
101
100
103
104
105
104
107
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MPC823 ELECTRICAL SPECIFICATIONS 53
Figure 48. HDLC Bus Timing Diagram
TCLK1
TXD2
(OUTPUT)
RTS1
(OUTPUT)
CTS1
(ECHO
INPUT)
102 101
100
103
104
105
107
104
102
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Table 15. Ethernet Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
120 CLSN (CTS2) width high 40 Ñ 40 Ñ 40 Ñ ns
121 RCLK1 rise and fall times Ñ 15 Ñ 15 Ñ 15 ns
122 RCLK1 width low 40 Ñ 40 Ñ 40 Ñ ns
123 RCLK1 clock period180 120 80 120 80 120 ns
124 RXD2 setup time 20 Ñ 20 Ñ 20 Ñ ns
125 RXD2 hold time 5Ñ5Ñ5Ñns
126 RENA (CD2) active delay (from RCLK1
rising edge of the last data bit) 10Ñ10Ñ10Ñns
127 RENA (CD2) width low 100 Ñ 100 Ñ 100 Ñ ns
128 TCLK1 rise and fall times Ñ 15 Ñ 15 Ñ 15 ns
129 TCLK1 width low 40 Ñ 40 Ñ 40 Ñ ns
130 TCLK1 clock period199 101 99 101 99 101 ns
131 TXD2 active delay (from TCLK1 rising edge) 10 50 10 50 10 50 ns
132 TXD2 inactive delay (from TCLK1 rising
edge) 10 50 10 50 10 50 ns
133 TENA (RTS2) active delay (from TCLK1
rising edge) 10 50 10 50 10 50 ns
134 TENA (RTS2) inactive delay (from TCLK1
rising edge) 10 50 10 50 10 50 ns
135 N/A
136 N/A
137 N/A
138 CLKx low to SDACK asserted2Ñ20Ñ20Ñ20ns
139 CLKx low to SDACK negated3Ñ20Ñ20Ñ20ns
NOTES:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2. SDACK is asserted when the SDMA writes the incoming frame DA into memory.
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MPC823 ELECTRICAL SPECIFICATIONS 55
Figure 49. Ethernet Collision Timing Diagram
Figure 50. Ethernet Receive Timing Diagram
CLSN (CTS1)
(INPUT)
120
RCLK1
RXD2
RENA (CD1)
(INPUT)
(INPUT) LAST BIT
121 121
123
127
126
125
124
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Figure 51. Ethernet Transmit Timing Diagram
TCLK1
TXD2
RENA (CD1)
(INPUT)
(OUTPUT)
TENA (RTS1)
(INPUT)
(NOTE 2)
NOTES:
1.
TRANSMIT CLOCK INVERT (TCI) BIT IN THE GSMR IS SET.
2.
IF RENA IS DEASSERTED BEFORE TENA, OR RENA IS NOT ASSERTED AT ALL DURING
TRANSMIT, THEN THE CSL BIT IS SET IN THE BUFFER DESCRIPTOR AT THE END OF FRAME TRANSMISSION.
128 128
132
121
131
133
129
134
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Table 16. Serial Peripheral Interface Master Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
160
Master cycle time 4 1,024 4 1,024 4 1,024 tcyc
161
Master clock (SCK) high or low time 2 512 2 512 2 512 tcyc
162
Master data setup time (inputs) 50 Ñ 50 Ñ 50 Ñ ns
163
Master data hold time (inputs) 0Ñ0Ñ0Ñns
164
Master data valid (after SCK edge) Ñ 20 Ñ 20 Ñ 20 ns
165
Master data hold time (outputs) 0Ñ0Ñ0Ñns
166
Rise time output Ñ 15 Ñ 15 Ñ 15 ns
167
Fall time output Ñ 15 Ñ 15 Ñ 15 ns
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
Figure 52. SPI Master (CP=0) Timing Diagram
SPICLK
CI=0
(OUTPUT)
SPICLK
CI=1
(OUTPUT)
SPIMISO
(INPUT)
SPIMOSI
(OUTPUT)
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB OUT
161
161
160
166
167
166
167
163
162
165
164
166
167
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Figure 53. SPI Master (CP=1) Timing Diagram
SPICLK
CI=0
(OUTPUT)
SPICLK
CI=1
(OUTPUT)
SPIMISO
(INPUT)
SPIMOSI
(OUTPUT)
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB OUT
161
161
167
160
166
167
166
163
162
165
164
166
167
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Table 17. Serial Peripheral Interface Slave Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
170
Slave cycle time 2Ñ2Ñ2Ñtcyc
171
Slave enable lead time 15 Ñ 15 Ñ 15 Ñ ns
172
Slave enable lag time 15 Ñ 15 Ñ 15 Ñ ns
173
Slave clock (SPICLK) high or low time 1Ñ1Ñ1Ñtcyc
174
Slave sequential transfer delay (does not
require deselect) 1Ñ1Ñ1Ñtcyc
175
Slave data setup time (inputs) 20 Ñ 20 Ñ 20 Ñ ns
176
Slave data hold time (inputs) 20 Ñ 20 Ñ 20 Ñ ns
177
Slave access time Ñ 50 Ñ 50 Ñ 50 ns
178
Slave SPI MISO disable time Ñ 50 Ñ 50 Ñ 50 ns
179
Slave data valid (after SPICLK edge) Ñ 50 Ñ 50 Ñ 50 ns
180
Slave data hold time (outputs) 0Ñ0Ñ0Ñns
181
Rise time (input) Ñ 15 Ñ 15 Ñ 15 ns
182
Fall time (input) Ñ 15 Ñ 15 Ñ 15 ns
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Figure 54. SPI Slave (CP=0) Timing Diagram
SPICLK
CI=0
(INPUT)
SPICLK
CI=1
(INPUT)
SPIMISO
(OUTPUT)
SPIMOSI
(INPUT)
MSB OUT DATA LSB OUT MSB OUT
MSB IN DATA LSB IN MSB IN
SPISEL
(INPUT)
UNDEF
173
173
182
170 181 174
172 171
178
182
181
179
181
182
176
175
177
180
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Figure 55. SPI Slave (CP=1) Timing Diagram
SPICLK
CI=0
(INPUT)
SPICLK
CI=1
(INPUT)
SPIMISO
(OUTPUT)
SPIMOSI
(INPUT)
SPISEL
(INPUT)
UNDEF DATA LSB OUT MSB OUT
MSB IN DATA LSB IN MSB IN
MSB OUT
171
173
173 170
182
172
174
178
180
182
181
181
179
176
175
182 181
177
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Table 18. I
2
C TimingÑSCL < 100 kHz
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
200
SCL clock frequency (slave) 0 100 0 100 0 100 kHz
200
SCL clock frequency (master) 1.5 100 1.5 100 1.5 100 kHz
202
Bus free time between transmissions 4.7 Ñ 4.7 Ñ 4.7 Ñ
m
s
203
Low period of SCL 4.7 Ñ 4.7 Ñ 4.7 Ñ
m
s
204
High period of SCL 4.0 Ñ 4.0 Ñ 4.0 Ñ
m
s
205
Start condition setup time 4.7 Ñ 4.7 Ñ 4.7 Ñ
m
s
206
Start condition hold time 4.0 Ñ 4.0 Ñ 4.0 Ñ
m
s
207
Data hold time 0Ñ0Ñ0Ñ
m
s
208
Data setup time 250 Ñ 250 Ñ 250 Ñ ns
209
SDL/SCL rise time Ñ1Ñ1Ñ1
m
s
210
SDL/SCL fall time Ñ 300 Ñ 300 Ñ 300 ns
211
STOP condition setup time 4.7 Ñ 4.7 Ñ 4.7 Ñ
m
s
NOTE: SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) * pre_scaler * 2 ).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
Table 19. I
2
C TimingÑSCL > 100 kHz
NUM CHARACTERISTIC MINIMUM MAXIMUM UNIT
200
SCL clock frequency (slave) 0 BRGCLK/48 Hz
200
SCL clock frequency (master) BRGCLK/16512 BRGCLK/48 Hz
202
Bus free time between transmissions 1/(2.2 * fSCL) Ñ sec
203
Low period of SCL 1/(2.2 * fSCL) Ñ sec
204
High period of SCL 1/(2.2 * fSCL) Ñ sec
205
Start condition setup time 1/(2.2 * fSCL) Ñ sec
206
Start condition hold time 1/(2.2 * fSCL) Ñ sec
207
Data hold time 0 Ñ sec
208
Data setup time 1/(40 * fSCL) Ñ sec
209
SDL/SCL rise time Ñ 1/(10 * fSCL) sec
210
SDL/SCL fall time Ñ 1/(33 * fSCL) sec
211
Stop condition setup time 1/(2.2 * fSCL) Ñ sec
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Figure 56. I
2
C Bus Timing Diagram
SDA
SCL
202
205
203
207
204
208
210
209
206
211
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Table 20. Serial Management Controller Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
150
CLK1 clock period 100 Ñ 100 Ñ 100 Ñ ns
151
CLK1 width low 50 Ñ 50 Ñ 50 Ñ ns
151A
CLK1 width high 50 Ñ 50 Ñ 50 Ñ ns
152
CLK1 rise and fall times Ñ 15 Ñ 15 Ñ 15 ns
153
SMTXDx active delay (from CLK1 falling
edge)
10 50 10 50 10 50 ns
154
SMRXDx/SYNC1 setup time 20 Ñ 20 Ñ 20 Ñ ns
155
SMRXDx/SYNC1 hold time 5Ñ5Ñ5Ñns
NOTE: The ratio SyncCLK/SMCLK must be greater than or equal to 2/1.
Figure 57. SMC Transparent Timing Diagram
150
NOTE:
* THIS DELAY IS EQUAL TO AN INTEGER NUMBER OF ÒCHARACTER LENGTHÓ CLOCKS.
SMCLK
SMTXDX
(OUTPUT)
SYNC1
SMRXDX
(INPUT)
*
152
152
151 161a
153
155
154
154
155
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Tcyc is the cycle time of the LCD clock (shift clock). Tdelay is a circuit delay that is specified in
the AC electrical specifications. 1Ð16 lines is a time period that can vary between one scan line
and 16, depending on how the LCD controller is programmed in the VPW field of the LCVCR.
0Ð1,023 lines is a time period that can vary between 0 and 1,023 scan lines in the WBF field of
the LCVCR.
Table 21. LCD Controller Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
220
Shift clock cycle time 40 Ñ 40 Ñ 40 Ñ nsec
221
Shift clock high time 20 Ñ 20 Ñ 20 Ñ nsec
223
CLOCK/HSYNC/VSYNC/OE rise and fall
times Ñ 10 Ñ 10 Ñ 10 nsec
224
Data valid delay from shift clock high Ñ 15 Ñ 15 Ñ 15 nsec
225
VSYNC to HSYNC setup time
1
5Ñ5Ñ5ÑT
226
VSYNC hold time 1Ñ1Ñ1ÑT
227
HSYNC pulse width 4Ñ4Ñ4ÑT
228
Time from clock falling edge to HSYNC
rising edge 4.5 Ñ 4.5 Ñ 4.5 Ñ T
229
Time from HSYNC falling edge to clock
rising edge
2
4Ñ4Ñ4ÑT
230
AC active delay Ñ 25 Ñ 25 Ñ 25 nsec
231
VSYNC pulse width (TFT) 1 16 1 16 1 16 Line
232
HSYNC to OE delay
3
4Ñ4Ñ4ÑT
233
OE to HSYNC delay 4Ñ4Ñ4ÑT
234
VSYNC to OE delay (TFT) 0 1,023 0 1,023 0 1,023 T
235
VSYNC/HSYNC/OE active delay (TFT) Ñ 15 Ñ 15 Ñ 15 nsec
236
Wait between frames
4
WBF Ñ WBF Ñ WBF Ñ Line
NOTES:
1. T = shift clock cycle (220).
2. This number is given for wbl(wait between lines)
£
2. For wbl=n {n
>
2} the timing will be (n+2)T.
3. This number is given for wbl(wait between lines)
£
2. For wbl=n {n
>
2} the timing will be (n+2)T.
4. Wait Between Frames (WBF) is a programmable parameter.
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Figure 58. Passive Panel Timing Diagram
SHIFT CLOCK
DATA
SHIFT CLOCK
HSYNC
VSYNC
LCD_AC
VSYNC
HSYNC
SHIFT CLOCK
NTH LINE FIRST LINE SECOND LINE
224
223
223 220
221
228 227 229
226
225
230
236
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Figure 59. TFT Panel Timing Diagram
SHIFT
DATA
OE
VSYNC
HSYNC
OE
FIRST LINE
NTH LINE
HSYNC
VSYNC
OE
227
235 224
233
235
234
231
232
225
235
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Table 22. Video Controller Timing
NUM CHARACTERISTIC
25MHZ 40MHZ 50MHZ
UNIT
MIN MAX MIN MAX MIN MAX
240
Clock cycle time 32 Ñ 32 Ñ 32 Ñ nsec
241
Clock high time 13 Ñ 13 Ñ 13 Ñ nsec
242
CLK/HSYNC/VSYNC/BLANK/FIELD
rise and fall times Ñ 10 Ñ 10 Ñ 10 nsec
243
Clock high to data valid 10 25 10 25 10 25 nsec
Figure 60. Video Controller Timing
CLK
DATA
HSYNC
VSYNC
FIELD
BLANK
243
242
242 240
241
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