LTC4300-1IMS8#TRPBF - Linear Technology Corporation

LTC4300-1/LTC4300-2

sn430012 430012fs

The LTC

4300 series hot swappable 2-wire bus buffers

allow I/O card insertion into a live backplane without cor-

ruption of the data and clock busses. When the connection

is made, the LTC4300-1/LTC4300-2 provide bidirectional

buffering, keeping the backplane and card capacitances

isolated. Rise-time accelerator circuitry* allows the use of

weaker DC pull-up currents while still meeting rise-time

requirements. During insertion, the SDA and SCL lines are

precharged to 1V to minimize bus disturbances.

The LTC4300-1 incorporates a CMOS threshold digital

ENABLE input pin, which forces the part into a low current

mode when driven to ground and sets normal operation when

driven to V

. It also includes an open drain READY output

pin, which indicates that the backplane and card sides are

connected together. The LTC4300-2 replaces the ENABLE

pin with a dedicated supply voltage pin, V

CC2

, for the card

side, providing level shifting between 3.3V and 5V systems.

Both the backplane and card may be powered with supply

voltages ranging from 2.7V to 5.5V, with no contraints on

which supply voltage is higher. The LTC4300-2 also replaces

the READY pin with a digital CMOS input pin, ACC, which

enables and disables the rise-time accelerator currents.

The LTC4300 is available in a small 8-pin MSOP package.

■

Hot Board Insertion

■

Servers

■

Capacitance Buffer/Bus Extender

■

Desktop Computer

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Bidirectional Buffer for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

■

Isolates Input SDA and SCL Lines from Output

■

Compatible with I

, I

C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

■

Small MSOP 8-Pin Package

■

Low I

Chip Disable: <1µA (LTC4300-1)

■

READY Open Drain Output (LTC4300-1)

■

1V Precharge on all SDA and SCL Lines

■

Supports Clock Stretching, Arbitration and

Synchronization

■

5V to 3.3V Level Translation (LTC4300-2)

■

High Impedance SDA, SCL Pins for V

= 0V

Hot Swappable

2-Wire Bus Buffers

C is a trademark of Philips Electronics N. V.

*U.S. Patent No. 6,650,174

24k

3.3V

24k

ENABLE

SCLIN SCLOUT

SDAIN SDAOUT

GND

LTC4300-1READY

0.01µF

C2* C4*

C5*

C3*

4300-1/2 TA01

24k R4

24k

*CAPACITORS NOT REQUIRED

IF BUS IS SUFFICIENTLY LOADED

APPLICATIO S

FEATURES

TYPICAL APPLICATIO

DESCRIPTIO

Input–Output Connection tPLH

OUTPUT

SIDE

50pF

INPUT

SIDE

150pF

LTC4300-1/LTC4300-2

sn430012 430012fs

to GND .................................................... –0.5 to 7V

CC2

to GND (LTC4300-2) .............................–0.5 to 7V

SDAIN, SCLIN, SDAOUT, SCLOUT.................–0.5 to 7V

READY, ENABLE (LTC4300-1)....................... –0.5 to 7V

ACC (LTC4300-2) ..........................................–0.5 to 7V

Operating Temperature Range

LTC4300-1C/LTC4300-2C ....................... 0°C to 70°C

LTC4300-1I/LTC4300-2I .................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)..................300°C

ORDER PART

NUMBER

MS8

PART MARKING

JMAX

= 125°C, θ

= 200°C/W

Consult LTC marketing for parts specified with wider operating temperature ranges.

LTUB

LTUC

LTVJ

LTVK

LTC4300-1CMS8

LTC4300-1IMS8

LTC4300-2CMS8

LTC4300-2IMS8

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

(Note 1)

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.

ENABLE/V

CC2

SCLOUT

SCLIN

GND

SDAOUT

SDAIN

READY/ACC*

TOP VIEW

MS8 PACKAGE

8-LEAD PLASTIC MSOP

*LTC4300-2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

Positive Supply Voltage ●2.7 5.5 V

Supply Current V

= 5.5V, V

SDAIN

= V

SCLIN

= 0V, LTC4300-1 ●2.8 6 mA

Supply Current in Shutdown Mode V

ENABLE

= 0V, LTC4300-1 0.1 µA

CC2

Card Side Supply Voltage LTC4300-2 ●2.7 5.5 V

VCC1

Supply Current V

SDAIN

= V

SCLIN

= 0V, V

CC1

= V

CC2

= 5.5V, 1.8 3.6 mA

LTC4300-2

VCC2

CC2

Supply Current V

SDAOUT

= V

SCLOUT

= 0V, V

CC1

= V

CC2

= 5.5V, 1.2 2.4 mA

LTC4300-2

Start-Up Circuitry

PRE

Precharge Voltage SDA, SCL Floating ●0.8 1.0 1.2 V

IDLE

Bus Idle Time ●50 95 150 µs

ENABLE Threshold Voltage LTC4300-1 0.5 • V

0.9 • V

DIS

Disable Threshold Voltage LTC4300-1, ENABLE Pin 0.1 • V

0.5 • V

ENABLE Input Current ENABLE from 0V to V

, LTC4300-1 ±0.1 ±1µA

PHL

ENABLE Delay, On-Off LTC4300-1 100 ns

READY Delay, Off-On LTC4300-1 10 ns

PLH

ENABLE Delay, Off-On LTC4300-1 80 µs

READY Delay, On-Off LTC4300-1 10 µs

OFF

READY OFF State Leakage Current LTC4300-1 ±0.1 µA

READY Output Low Voltage I

PULLUP

= 3mA, LTC4300-1 ●0.4 V

LTC4300-1/LTC4300-2

sn430012 430012fs

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired

Note 2: I

PULLUPAC

varies with temperature and V

voltage, as shown in

the Typical Performance Characteristics section.

Note 3: The connection circuitry always regulates its output to a higher

voltage than its input. The magnitude of this offset voltage as a function of

the pullup resistor and V

voltage is shown in the Typical Performance

Characteristics section.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Rise-Time Accelerators

PULLUPAC

Transient Boosted Pull-Up Current Positive Transition on SDA,SCL, V

= 2.7V, 1 2 mA

Slew Rate = 1.25V/µs (Note 2),

LTC4300-2, ACC = 0.7 • V

CC2

, V

CC2

= 2.7V

ACCDIS

Accelerator Disable Threshold LTC4300-2 0.3 • V

CC2

0.5 • V

CC2

ACCEN

Accelerator Enable Threshold LTC4300-2 0.5 • V

CC2

0.7 • V

CC2

VACC

ACC Input Current LTC4300-2 ±0.1 ±1µA

PDOFF

ACC Delay, On/Off LTC4300-2 5 ns

Input-Output Connection

Input-Output Offset Voltage 10k to V

on SDA, SCL, V

= 3.3V (Note 3), ●0 75 150 mV

LTC4300-2, V

CC2

= 3.3V, V

= 0.2V

SCL, SDA

Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz

Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF

Output Low Voltage, Input = 0V SDA, SCL Pins, I

SINK

= 3mA, V

= 2.7V, ●0 0.4 V

CC2

= 2.7V, LTC4300-2

LEAK

Input Leakage Current SDA, SCL Pins = V

= 5.5V, ±5µA

LTC4300-2, V

CC2

= 5.5V

Timing Characteristics

I2C

C Operating Frequency (Note 4) 0 400 kHz

BUF

Bus Free Time Between Stop (Note 4) 1.3 µs

and Start Condition

hD,STA

Hold Time After (Repeated) (Note 4) 0.6 µs

Start Condition

su,STA

Repeated Start Condition Setup Time (Note 4) 0.6 µs

su,STO

Stop Condition Setup Time (Note 4) 0.6 µs

hD, DAT

Data Hold Time (Note 4) 300 ns

su, DAT

Data Setup Time (Note 4) 100 ns

LOW

Clock Low Period (Note 4) 1.3 µs

HIGH

Clock High Period (Note 4) 0.6 µs

Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • C

300 ns

Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • C

300 ns

Note 4: Guaranteed by design, not subject to test.

Note 5: C

= total capacitance of one bus line in pF.

LTC4300-1/LTC4300-2

sn430012 430012fs

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

IPULLUPAC (mA)

4300-1/2 G03

VCC = 2.7V

VCC = 5V

VCC = 3V

PULLUP

(Ω)

010,000 20,000 30,000 40,000

OUT

– V

(mV)

4300-1/2 G04

300

250

200

150

100

= 3.3V

= 5V

= 25°C

= 0V

IPULLUPAC vs Temperature Connection Circuitry VOUT – VIN

TYPICAL PERFOR A CE CHARACTERISTICS

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

PHL

(ns)

4300-1/2 G02

100

= 2.7V

= 3.3V

= 5.5V

= C

OUT

= 100pF

PULLUPIN

= R

PULLUPOUT

= 10k

Input – Output t

PHL

vs Temperature

(LTC4300-1)

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

(mA)

4300-1/2 G01

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

= 5.5V

= 2.7V

ICC vs Temperature (LTC4300-1)

LTC4300-1/LTC4300-2

sn430012 430012fs

ENABLE/V

CC2

(Pin 1): Chip Enable Pin/Card Supply Volt-

age. For the LTC4300-1, this is a digital CMOS threshold

input pin. Grounding this pin puts the part in a low current

(<1µA) mode. It also disables the rise-time accelerators,

disables the bus precharge circuitry, drives READY low,

isolates SDAIN from SDAOUT and isolates SCLIN from

SCLOUT. Drive ENABLE all the way to V

for normal

operation. Connect ENABLE to V

if this feature is not

being used. For the LTC4300-2, this is the supply voltage

for the devices on the card I

C busses. Connect pull-up

resistors from SDAOUT and SCLOUT to this pin. Place a

bypass capacitor of at least 0.01µF close to this pin for best

results.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card. See Figures 3 and 4 for bus pull-

up resistance and capacitance requirements.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to the

SCL bus on the backplane. See Figures 3 and 4 for bus pull-

up resistance and capacitance requirements.

GND (Pin 4): Ground. Connect this pin to a ground plane

for best results.

READY/ACC (Pin 5): Connection Flag/Rise-Time Accel-

erator Control. For the LTC4300-1, this is an open-drain

NMOS output which pulls low when either ENABLE is low

or the start-up sequence described in the Operation sec-

tion has not been completed. READY goes high when

ENABLE is high and start-up is complete. Connect a 10k

resistor from this pin to V

to provide the pull up. For the

LTC4300-2, this is a CMOS threshold digital input pin that

enables and disables the rise-time accelerators on all four

SDA and SCL pins. Drive ACC all the way to the V

CC2

supply

voltage to enable all four accelerators; drive ACC to ground

to turn them off.

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane. See Figures 3 and 4 for bus

pull-up resistance and capacitance requirements.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card. See Figures 3 and 4 for bus pull-

up resistance and capacitance requirements.

(Pin 8): Main Input Power Supply from Backplane.

This is the supply voltage for the devices on the backplane

C busses. Connect pull-up resistors from SDAIN and

SCLIN to this pin. Place a bypass capacitor of at least

0.01µF close to this pin for best results.

PI FU CTIO S

UUU

LTC4300-1/LTC4300-2

sn430012 430012fs

100k

RCH1 100k

RCH3

–

0.5pF

READY

1ENABLE

UVLO

3SCLIN

4300-1 BD

CONNECT

STOP BIT AND BUS IDLE

GND

CONNECT

20pF

SQB

0.5µA

0.55V

0.45V

–

0.55V

0.45V

2mA

95µs

DELAY

BACKPLANE-TO-CARD

CONNECTION

CONNECTCONNECT

2SCLOUT

6SDAIN BACKPLANE-TO-CARD

CONNECTION

CONNECT CONNECT

7SDAOUT

PRECHARGE

100k

RCH2 100k

RCH4

SLEW RATE

DECTECTOR

2mA

SLEW RATE

DECTECTOR

2mA

SLEW RATE

DECTECTOR

2mA

SLEW RATE

DECTECTOR

CONNECT

ENABLE

2-Wire Bus Buffer and Hot Swap

Controller

BLOCK DIAGRA

Hot Swap is a trademark of Linear Technology Corporation.

(LTC4300-1)

LTC4300-1/LTC4300-2

sn430012 430012fs

BLOCK DIAGRA

(LTC4300-2)

100k

RCH1 100k

RCH3

–

0.5pF

UVLO

3SCLIN

4300-2 BD

CONNECT CONNECT

STOP BIT AND BUS IDLE

GND

20pF

SQB

0.5µA

0.55V

0.45V

–

0.55V

CC2

0.45V

CC2

2mA

95µs

DELAY

BACKPLANE-TO-CARD

CONNECTION

CONNECTCONNECT

2SCLOUT

6SDAIN

BACKPLANE-TO-CARD

CONNECTION

CONNECT CONNECT

7SDAOUT

CC2

5ACC

PRECHARGE

100k

RCH2 100k

RCH4

CONNECT

SLEW RATE

DECTECTOR

2mA

SLEW RATE

DECTECTOR

2mA

SLEW RATE

DECTECTOR

ACC

2mA

SLEW RATE

DECTECTOR

2-Wire Bus Buffer and Hot Swap Controller

LTC4300-1/LTC4300-2

sn430012 430012fs

OPERATIO

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms, as

described here.

Input to Output Offset Voltage

When a logic low voltage, V

LOW1

, is driven on any of the

LTC4300’s data or clock pins, the LTC4300 regulates the

voltage on the other side of the chip (call it V

LOW2

) to a

slightly higher voltage, as directed by the following

equation:

LOW2

= V

LOW1

+ 50mV + (V

/R) • 100

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV and if

= 3.3V and the pull-up resistor R on SDAIN is 10k, then

the voltage on SDAIN = 10mV + 50mV + (3.3/10000) • 100

= 93mV. See the Typical Performance Characteristics

section for curves showing the offset voltage as a function

of V

and R.

Propagation Delays

During a rising edge, the rise-time on each side is deter-

mined by the combined pull-up current of the LTC4300

boost current and the bus resistor and the equivalent

capacitance on the line. If the pull-up currents are the

same, a difference in rise-time occurs which is directly

proportional to the difference in capacitance between the

two sides. This effect is displayed in Figure 1 for V

= 3.3V

and a 10k pull-up resistor on each side (50pF on one side

and 150pF on the other). Since the output side has less

capacitance than the input, it rises faster and the effective

PLH

is negative.

There is a finite propagation delay, t

PHL

, through the

connection circuitry for falling waveforms. Figure 2 shows

the falling edge waveforms for the same V

, pull-up

resistors and equivalent capacitance conditions as used in

Figure 1. An external NMOS device pulls down the voltage

on the side with 150pF capacitance; the LTC4300 pulls

down the voltage on the opposite side, with a delay of

55ns. This delay is always positive and is a function of

supply voltage, temperature and the pull-up resistors and

equivalent bus capacitances on both sides of the bus. The

Typical Performance Characteristics section shows t

PHL

Start-Up

When the LTC4300 first receives power on its V

pin,

either during power-up or during hot swapping, it starts in

an undervoltage lockout (UVLO) state, ignoring any activ-

ity on the SDA and SCL pins until V

rises above 2.5V. For

the LTC4300-2, the part also waits for V

CC2

to rise above

2V. This ensures that the part does not try to function until

it has enough voltage to do so.

During this time, the 1V precharge circuitry is also active

and forces 1V through 100k nominal resistors to the SDA

and SCL pins. Because the I/O card is being plugged into

a live backplane, the voltage on the backplane SDA and SCL

busses may be anywhere between 0V and V

. Precharging

the SCL and SDA pins to 1V minimizes the worst-case

voltage differential these pins will see at the moment of con-

nection, therefore minimizing the amount of disturbance

caused by the I/O card.

Once the LTC4300 comes out of UVLO, it assumes that

SDAIN and SCLIN have been hot swapped into a live

system and that SDAOUT and SCLOUT are being powered

up at the same time as itself. Therefore, it looks for either

a stop bit or bus idle condition on the backplane side to

indicate the completion of a data transaction. When either

one occurs, the part also verifies that both the SDAOUT

and SCLOUT voltages are high. When all of these condi-

tions are met, the input-to-output connection circuitry is

activated, joining the SDA and SCL busses on the I/O card

with those on the backplane.

Connection Circuitry

Once the connection circuitry is activated, the functional-

ity of the SDAIN and SDAOUT pins is identical. A low forced

on either pin at any time results in both pin voltages being

low. SDAIN and SDAOUT enter a logic high state only when

all devices on both SDAIN and SDAOUT force a high. The

same is true for SCLIN and SCLOUT. This important fea-

ture ensures that clock stretching, clock arbitration and the

acknowledge protocol always work, regardless of how the

devices in the system are tied to the LTC4300.

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

LTC4300-1/LTC4300-2

sn430012 430012fs

as a function of temperature and voltage for 10k pull-up

resistors and 100pF equivalent capacitance on both sides

of the part. By comparison with Figure 2, the V

= 3.3V

curve shows that increasing the capacitance from 50pF to

150pF results in a t

PHL

increase from 55ns to 75ns. Larger

output capacitances translate to longer delays (up to

150ns). Users must quantify the difference in propagation

times for a rising edge vs a falling edge in their systems

and adjust setup and hold times accordingly.

Rise-Time Accelerators

Once connection has been established, rise-time accelera-

tor circuits on all four SDA and SCL pins are activated.

These allow the user to choose weaker DC pull-up currents

on the bus, reducing power consumption while still meet-

ing system rise-time requirements. During positive bus

transitions, the LTC4300 switches in 2mA of current to

quickly slew the SDA and SCL lines once their DC voltages

exceed 0.6V. Using a general rule of 20pF of capacitance

for every device on the bus (10pF for the device and 10pF

for interconnect), choose a pull-up current so that the bus

will rise on its own at a rate of at least 1.25V/µs to

guarantee activation of the accelerators.

For example, assume an SMBus system with V

= 3V, a

10k pull-up resistor and equivalent bus capacitance of

200pF. The rise-time of an SMBus system is calculated

from (V

IL(MAX)

– 0.15V) to (V

IH(MIN)

+ 0.15V), or 0.65V to

2.25V. It takes an RC circuit 0.92 time constants to

traverse this voltage for a 3V supply; in this case, 0.92 •

(10k • 200pF) = 1.85µs. Thus, the system exceeds the

maximum allowed rise-time of 1µs by 85%. However,

using the rise-time accelerators, which are activated at a

DC threshold of below 0.65V, the worst-case rise-time is:

(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the

1µs rise-time requirement.

READY Digital Output (LTC4300-1)

This pin provides a digital flag which is low when either

ENABLE is low or the start-up sequence described earlier

in this section has not been completed. READY goes high

when ENABLE is high and start-up is complete. The pin is

driven by an open drain pull-down capable of sinking 3mA

while holding 0.4V on the pin. Connect a resistor of 10k to

to provide the pull-up. This feature is available for the

LTC4300-1 only.

ENABLE Low Current Disable (LTC4300-1)

Grounding the ENABLE pin disconnects the backplane

side from the card side, disables the rise-time accelera-

tors, drives READY low, disables the bus precharge cir-

cuitry and puts the part in a near-zero current state. When

the pin voltage is driven all the way to V

, the part waits

for data transactions on both the backplane and card sides

to be complete (as described in the Start-Up section)

before reconnecting the two sides. This feature is available

for the LTC4300-1 only.

ACC Boost Current Enable (LTC4300-2)

Users having lightly loaded systems may wish to disable

the rise-time accelerators. Driving this pin to ground turns

off the rise-time accelerators on all four SDA and SCL pins.

Driving this pin to the V

CC2

voltage enables normal opera-

tion of the rise-time accelerators, as described in the Rise-

Time Accelerators section above. This feature is available

for the LTC4300-2 only.

OPERATIO

Figure 1. Input–Output Connection tPLH Figure 2. Input–Output Connection tPHL

OUTPUT

SIDE

50pF

INPUT

SIDE

150pF

INPUT

SIDE

150pF

OUTPUT

SIDE

50pF

LTC4300-1/LTC4300-2

sn430012 430012fs

Resistor Pull-Up Value Selection

The system pull-up resistors must be strong enough to

provide a positive slew rate of 1.25V/µs on the SDA and

SCL pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value R

using the formula:

R ≤ (V

CC(MIN)

– 0.6) (800,000) / C

where R is the pull-up resistor value in ohms, V

CC(MIN)

the minimum V

voltage and C is the equivalent bus

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always

choose R ≤ 16k for V

= 5.5V maximum, R ≤ 24k for

␣ =␣ 3.6V maximum. The start-up circuitry requires logic

high voltages on SDAOUT and SCLOUT to connect the

backplane to the card, and these pull-up values are needed

to overcome the precharge voltage. See the curves in

Figures 3 and 4 for guidance in resistor pull-up selection.

Minimum SDA and SCL Capacitance Requirements

The LTC4300 I/O connection circuitry requires a minimum

capacitance loading on the SDA and SCL pins in order to

function properly. The value of this capacitance is a

function of V

and the bus pull-up resistance. Estimate

the bus capacitance on both the backplane and the card

data and clock busses, and refer to Figures 3 and 4 to

choose appropriate pull-up resistor values. Note from the

APPLICATIO S I FOR ATIO

WUUU

figures that 5V systems must have at least 47pF capaci-

tance on their busses and 3.3V systems must have at least

22pF capacitance for proper operation of the LTC4300. For

applications with less capacitance, add a capacitor to

ground to ensure these minimum capacitance conditions.

Hot Swapping and Capacitance Buffering Application

Figures 5 through 8 illustrate the usage of the LTC4300 in

applications that take advantage of both its hot swapping

and capacitance buffering features. In all of these applica-

tions, note that if the I/O cards were plugged directly into

the backplane, all of the backplane and card capacitances

would add directly together, making rise- and fall-time

requirements difficult to meet. Placing a LTC4300 on the

edge of each card, however, isolates the card capacitance

from the backplane. For a given I/O card, the LTC4300 drives

the capacitance of everything on the card and the backplane

must drive only the capacitance of the LTC4300, which is

less than 10pF.

Figure 5 shows the LTC4300-1 in a CompactPCI

con-

figuration. Connect VCC to the output of one of the

CompactPCI power supply hot swap circuits and connect

ENABLE to the short “board enable” pin. VCC is monitored

by a filtered UVLO circuit. With the VCC voltage powering

up after all other pins have established connection, the

UVLO circuit ensures that the backplane and card data and

clock busses are not connected until the transients asso-

Figure 3. Bus Requirements for 3.3V Systems Figure 4. Bus Requirements for 5V Systems

CBUS (pF)

RPULLUP (kΩ)

4300-1/2 F03

0100 200 300 400

RMAX = 24k

RISE-TIME > 300ns

RECOMMENDED

PULL-UP

CBUS (pF)

RPULLUP (kΩ)

4300-1/2 F04

100 200 300 400

RISE-TIME

> 300ns

RECOMMENDED

PULL-UP

RMAX = 16k

CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.

LTC4300-1/LTC4300-2

sn430012 430012fs

APPLICATIO S I FOR ATIO

WUUU

ciated with hot swapping have settled. Owing to their small

capacitance, the SDAIN and SCLIN pins cause minimal dis-

turbance on the backplane busses when they make con-

tact with the connector.

Figure 6 shows the LTC4300-2 in a CompactPCI configu-

ration. The LTC4300-2 receives its V

voltage from one

of the long “early power” pins. Because this power is not

switched, add a 5Ω to 10Ω resistor between the V

pins

of the connector and the LTC4300-2, as shown in the

figure. In addition, make sure that the V

bypassing on

the backplane is large compared to the 0.01µF bypass

capacitor on the card. Establishing early power V

en-

sures that the 1V precharge voltage is present at the

SDAIN and SCLIN pins before they make contact. Connect

CC2

to the output of one of the CompactPCI power supply

hot swap circuits. V

CC2

is monitored by a filtered UVLO

circuit. With the V

CC2

voltage powering up after all other

pins have established connection, the UVLO circuit en-

sures that the backplane and card data and clock busses

are not connected until the transients associated with hot

swapping have settled.

Figure 7 shows the LTC4300-1 in a PCI application, where

all of the pins have the same length. In this case, connect

an RC series circuit on the I/O card between V

and

ENABLE. An RC product of 10ms provides a filter to

prevent the LTC4300-1 from becoming activated until the

transients associated with hot swapping have settled.

Figure 8 shows the LTC4300-2 in an application where the

user has a custom connector with pins of three different

lengths available. Making V

CC2

the shortest pin ensures

that all other pins are firmly connected before V

CC2

receives any voltage. A filtered UVLO circuit on V

CC2

ensures that the V

CC2

pin is firmly connected before the

LTC4300-2 connects the backplane to the card.

Repeater/Bus Extender Application

Users who wish to connect two 2-wire systems separated

by a distance can do so by connecting two LTC4300-1s

back-to-back, as shown in Figure 9. The I

C specification

allows for 400pF maximum bus capacitance, severely

limiting the length of the bus. The SMBus specification

places no restriction on bus capacitance, but the limited

impedances of devices connected to the bus require

systems to remain small if rise- and fall-time specifica-

tions are to be met. The strong pull-up and pull-down

impedances of the LTC4300-1 are capable of meeting rise-

and fall-time specifications for one nanofarad of capaci-

tance, thus allowing much more interconnect distance. In

this situation, the differential ground voltage between the

two systems may limit the allowed distance, because a

valid logic low voltage with respect to the ground at one

end of the system may violate the allowed V

specifica-

tion with respect to the ground at the other end. In

addition, the connection circuitry offset voltages of the

back-to-back LTC4300-1s add together, directly contrib-

uting to the same problem.

Systems with Disparate Supply Voltages (LTC4300-1)

In large 2-wire systems, the V

voltages seen by devices

at various points in the system can differ by a few hundred

millivolts or more. This situation is well modelled by a

series resistor in the V

line, as shown in Figure 10. For

proper operation of the LTC4300-1, make sure that

CC(BUS)

≥ V

CC(LTC4300)

– 0.5V.

5V to 3.3V Level Translator and Power Supply

Redundancy (LTC4300-2)

Systems requiring different supply voltages for the

backplane side and the card side can use the LTC4300-2,

as shown in Figure 11. The pull-up resistors on the card

side connect from SDAOUT to SCLOUT to V

CC2

, and those

on the backplane side connect from SDAIN and SCLIN to

. The LTC4300-2 functions for voltages ranging from

2.7V to 5.5V on both V

and V

CC2

. There is no constraint

on the voltage magnitudes of V

and V

CC2

with respect to

each other.

This application also provides power supply redundancy.

If either the V

or V

CC2

voltage falls below its UVLO

threshold, the LTC4300-2 disconnects the backplane from

the card, so that the side that is still powered can continue

to function.

LTC4300-1/LTC4300-2

sn430012 430012fs

Figure 5. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a CompactPCI System

STAGGERED CONNECTOR

R13

10k

R12

10k R14

10k

I/O PERIPHERAL CARD N

ENABLE

SDAIN

SCLIN

LTC4300-1

GND

CARDN_SCL

CARDN_SDA

SDAOUT

SCLOUT

READY

ENABLE

SDAIN

SCLIN

GND

SDAOUT

SCLOUT

READY

ENABLE

SDAIN

SCLIN

GND

SDAOUT

SCLOUT

READY

4300-1/2 F05

• • •

10k

10k R10

10k

I/O PERIPHERAL CARD 2

LTC4300-1

U2 CARD2_SCL

CARD2_SDA

STAGGERED CONNECTORSTAGGERED CONNECTOR

10k

10k R6

10k

I/O PERIPHERAL CARD 1

LTC4300-1

U1 CARD_SCL

CARD_SDA

10k

BACKPLANE

CONNECTOR

SDA

BD_SEL

SCL

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

0.01µF

POWER SUPPLY

HOT SWAP

POWER SUPPLY

HOT SWAP

POWER SUPPLY

HOT SWAP

APPLICATIO S I FOR ATIO

WUUU

LTC4300-1/LTC4300-2

sn430012 430012fs

APPLICATIO S I FOR ATIO

WUUU

Figure 6. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 in a CompactPCI System

0.01µF

0.01µFR13

10k

R12

10k R14

10k

I/O PERIPHERAL CARD N

SDAIN

SCLIN

LTC4300-2

CC2

GND

CARDN_SCL

CARDN_SDA

SDAOUT

SCLOUT

ACC

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ACC

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ACC

4300-1/2 F06

• • •

10k

10k R10

10k

I/O PERIPHERAL CARD 2

LTC4300-2

U2 CARD2_SCL

CARD2_SDA

10k

10k R6

10k

I/O PERIPHERAL CARD 1

LTC4300-2

C2 0.01µF

5.1Ω

CARD_SCL

CARD_SDA

CC2

BACKPLANE

CONNECTOR

SDA

SCL

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

BD_SEL

STAGGERED CONNECTORSTAGGERED CONNECTORSTAGGERED CONNECTOR

POWER SUPPLY

HOT SWAP

C4 0.01µF

5.1Ω

POWER SUPPLY

HOT SWAP

C6 0.01µF

5.1Ω

POWER SUPPLY

HOT SWAP

10k R2

10k

LTC4300-1/LTC4300-2

sn430012 430012fs

APPLICATIO S I FOR ATIO

WUUU

Figure 7. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-1 in a PCI System

100k

ENABLE

SDAIN

SCLIN

GND

SDAOUT

SCLOUT

READY

ENABLE

SDAIN

SCLIN

GND

SDAOUT

SCLOUT

READY

4300-1/2 F07

10k

10k R10

10k

I/O PERIPHERAL CARD 2

LTC4300-1

U2 CARD2_SCL

CARD2_SDA

10k

I/O PERIPHERAL CARD 1

LTC4300-1

C2 0.1µF

100k

C4 0.1µF

CARD_SCL

CARD_SDA

10k

BACKPLANE

CONNECTOR

SDA

SCL

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

0.01µF

10k

Figure 8. Hot Swapping Multiple I/O Cards into a Backplane Using the LTC4300-2 with a Custom Connector

STAGGERED CONNECTOR

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ACC

SDAIN

SCLIN

CC2

GND

SDAOUT

SCLOUT

ACC

4300-1/2 F08

10k

I/O PERIPHERAL CARD 2

LTC4300-2

U2 CARD2_SCL

CARD2_SDA

STAGGERED CONNECTOR

10k

I/O PERIPHERAL CARD 1

LTC4300-2

C2 0.01µF

C4 0.01µF

CARD_SCL

CARD_SDA

10k R2

10k

CC2

BACKPLANE

CONNECTOR

SDA

SCL

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

0.01µF

0.01µFR10

10k

LTC4300-1/LTC4300-2

sn430012 430012fs

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

APPLICATIO S I FOR ATIO

WUUU

10k

5.1k

10k R2

5.1k

= 5V

10k R7

10k R8

10k

2-WIRE SYSTEM 1

ENABLE

SDAIN

SCLIN

LTC4300-1

GND

0.01µF

SDAOUT

SCLOUT

READY

SCL1

TO OTHER

SYSTEM 1

DEVICES

SDA1

0.01µF

10k

2-WIRE SYSTEM 2

LTC4300-1

ENABLE

SDAIN

SCLIN

4300-1/2 F07

SDAOUT

SCLOUT

READY

LONG

DISTANCE

BUS

SCL1

SDA1

TO OTHER

SYSTEM 2

DEVICES

GND

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURE 4

Figure 9. Repeater/Bus Extender Application

PACKAGE DESCRIPTION

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

MSOP (MS8) 1001

0.53 ± 0.015

(.021 ± .006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18

(.077)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015) 0.13 ± 0.05

(.005 ± .002)

0.86

(.034)

REF

0.65

(.0256)

BCS

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

4.88 ± 0.1

(.192 ± .004)

8765

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

NOTE 4

0.52

(.206)

REF

5.23

(.206)

MIN

3.2 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.04

(.0165 ± .0015)

TYP

0.65

(.0256)

BSC

LTC4300-1/LTC4300-2

sn430012 430012fs

 LINEAR TECHNOLOGY CORPORATION 2001

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

LT/TP 0602 2K • PRINTED IN USA

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog Low R

: 35Ω Single-Ended/70Ω Differential,

Mux with SMBus Interface Expandable to 32 Single or 16 Differential Channels

LTC1427-50 Micropower, 10-Bit Current Output DAC Precision 50µA ± 2.5% Tolerance Over Temperature,

with SMBus Interface 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale

LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability

LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package

LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I

C Rise-Time,

Ensures Data Integrity with Multiple SMBus/I

C Devices

LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Configurations

LTC1695 SMBus/I

C Fan Speed Controller in ThinSOTTM 0.75Ω PMOS 180mA Regulator, 6-Bit DAC

LTC1840 Dual I

C Fan Speed Controller Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0

ThinSOT is a trademark of Linear Technology Corporation.

Figure 10. System with Disparate VCC Voltages

10k

DROP

CC_LOW

SDA

SCL

4300-1/2 F08

10k R5

10k

SDAIN

ENABLE

SCLIN

LTC4300-1

GND

SCL2

SDA2

SDAOUT

SCLOUT

READY

0.01µF

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

Figure 11. 5V to 3.3V Level Translator

CC2

GND

SDAOUT

SCLOUT

SDAIN

SCLIN

ACC

10k

CARD_V

, 3V

CARD_SCL

CARD_SDA

0.01µFC1

0.01µF

10k

5V R4

10k

LTC4300-2

SCL

4300-1/2 F09

NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4

TYPICAL APPLICATIO S