Channel 1
LI_0 SOA_0
SOB_0
SIA_0
SIB_0
MUX_S0
Channel 0
LO_0
ENL_0
ENA_0
ENB_0
Mux Buffer
Switch
Fabric A
Switch
Fabric B
FPGA
or
ASIC
Backplane or Cable
LVDS
LVDS
DS08MB200
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SNLS197D –MAY 2006–REVISED MARCH 2013
DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer
Check for Samples: DS08MB200
1FEATURES DESCRIPTION
The DS08MB200 is a dual-port 1 to 2 repeater/buffer
2• Up to 800 Mbps Data Rate per Channel and 2 to 1 multiplexer. High-speed data paths and
• LVDS/BLVDS/CML/LVPECL Compatible Inputs, flow-through pinout minimize internal device jitter and
LVDS Compatible Outputs simplify board layout. The differential inputs and
• Low Output Skew and Jitter outputs interface to LVDS or Bus LVDS signals such
as those on TI's 10-, 16-, and 18- bit Bus LVDS
• On-Chip 100ΩInput Termination SerDes, or to CML or LVPECL signals.
• 15 kV ESD Protection on LVDS Inputs/Outputs The 3.3V supply, CMOS process, and robust I/O
• Hot Plug Protection ensure high performance at low power over the entire
• Single 3.3V Supply industrial -40 to +85°C temperature range.
• Industrial -40 to +85°C Temperature Range
• 48-pin WQFN Package
Typical Application
Block Diagram
Figure 1. DS08MB200 Block Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS08MB200
SNLS197D –MAY 2006–REVISED MARCH 2013
www.ti.com
PIN DESCRIPTIONS
Pin WQFN Pin I/O, Type Description
Name Number
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+ 30 I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
SIA_0−29 LVPECL compatible.
SIA_1+ 19 I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
SIA_1−20 LVPECL compatible.
SIB_0+ 28 I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
SIB_0−27 LVPECL compatible.
SIB_1+ 21 I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
SIB_1−22 LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+ 40 I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_0−39 LVPECL compatible.
LI_1+ 9 I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_1−10 LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+ 34 O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
SOA_0−33
SOA_1+ 15 O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
SOA_1−16
SOB_0+ 32 O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
SOB_0−31
SOB_1+ 17 O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
SOB_1−18
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+ 42 O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
LO_0−41
LO_1+ 7 O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible(1)(2).
LO_1−8
DIGITAL CONTROL INTERFACE
MUX_S0 38 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through
MUX_S1 11 to the Line-side.
ENA_0 36 I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and B-
ENA_1 13 side has a separate enable pin.
ENB_0 35
ENB_1 14
ENL_0 45 I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate
ENL_1 4 enable pin.
POWER
VDD 6, 12, 37, I, Power VDD = 3.3V ±0.3V.
43, 48
GND 2, 3, 46, I, Power Ground reference for LVDS and CMOS circuitry.
47(3) For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is
the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the
ground plane with at least 4 vias for optimal AC and thermal performance.
N/C 1, 5, 23, 24, No Connect
25, 26, 44
(1) For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the APPLICATIONS section of this datasheet.
(2) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have
been optimized for point-to-point backplane and cable applications.
(3) Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN
package.
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Product Folder Links: DS08MB200
VDD
GND
GND
ENL_0
N/C
VDD
LO_0+
LO_0-
LI_0+
LI_0-
MUX_S0
VDD
48
47
46
45
44
43
42
41
40
39
38
37
ENA_1
ENB_1
SOA_1+
SOA_1-
SOB_1+
SOB_1-
SIA_1+
SIA_1-
SIB_1+
SIB_1-
N/C
N/C
13
14
15
16
17
18
19
20
21
22
23
24
VDD
MUX_S1
LI_1-
LI_1+
LO_1-
LO-1+
VDD
N/C
ENL_1
GND
GND
N/C
12 11 10 9 8 7 6 5 4 3 2 1
N/C
N/C
SIB_0-
SIB_0+
SIA_0-
SIA_0+
SOB_0-
SOB_0+
SOA_0-
SOA_0+
ENB_0
ENA_0
25 26 27 28 29 30 31 32 33 34 35 36
DAP
(GND)
VDD
GND
GND
ENL_0
N/C
VDD
LO_0+
LO_0-
LI_0+
LI_0-
MUX_S0
VDD
ENA_1
ENB_1
SOA_1+
SOA_1-
SOB_1+
SOB_1-
SIA_1+
SIA_1-
SIB_1+
SIB_1-
N/C
N/C
VDD
MUX_S1
LI_1-
LI_1+
LO_1-
LO-1+
VDD
N/C
ENL_1
GND
GND
N/C
N/C
N/C
SIB_0-
SIB_0+
SIA_0-
SIA_0+
SOB_0-
SOB_0+
SOA_0-
SOA_0+
ENB_0
ENA_0
Channel 0
Channel 1
DS08MB200
www.ti.com
SNLS197D –MAY 2006–REVISED MARCH 2013
Connection Diagrams
Top View Top View
Figure 2. WQFN Package Figure 3. Directional Signal Paths
See Package Number RHS0048A (Refer to pin names for signal polarity)
DAP = GND
TRI-STATE and Powerdown Modes
The DS08MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows
each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is
useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active
while some are in TRI-STATE.
When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a
Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is
essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators.
When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the
outputs because of the ramp to power up the internal bandgap reference generators.
Any single output enable that remains active will hold the device in active mode even if the other five outputs are
in TRI-STATE.
When in Powerdown mode, any output enable that becomes active will wake up the device back into active
mode, even if the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩto 15kΩrange to minimize loading and waveform distortion to the driver. Please refer to
application note SNLA051B AN-1194, “Failsafe Biasing of LVDS Interfaces” for more information.
Output Characteristics
The output characteristics of the DS08MB200 have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop signaling.
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MULTIPLEXER TRUTH TABLE(1)(2)
Data Inputs Control Inputs Output
SIA_0 SIB_0 MUX_S0 ENL_0 LO_0
X valid 0 1 SIB_0
valid X 1 1 SIA_0
X X X 0 (3) Z
(1) Same functionality for channel 1
(2) X = Don't Care
Z = High Impedance (TRI-STATE)
(3) When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the TRI-STATE and Powerdown
Modes section. REPEATER/BUFFER TRUTH TABLE(1)(2)
Data Input Control Inputs Outputs
LI_0 ENA_0 ENB_0 SOA_0 SOB_0
X 0 0 Z (3) Z(3)
valid 0 1 Z LI_0
valid 1 0 LI_0 Z
valid 1 1 LI_0 LI_0
(1) Same functionality for channel 1
(2) X = Don't Care
Z = High Impedance (TRI-STATE)
(3) When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the TRI-STATE and Powerdown
Modes section.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage (VDD)−0.3V to +4.0V
CMOS Input Voltage -0.3V to (VDD+0.3V)
LVDS Receiver Input Voltage(2) -0.3V to (VDD+0.3V)
LVDS Driver Output Voltage -0.3V to (VDD+0.3V)
LVDS Output Short Circuit Current +40 mA
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Solder, 4sec) 260°C
Max Pkg Power Capacity @ 25°C 5.2W
Thermal Resistance (θJA) 24°C/W
Package Derating above +25°C 41.7mW/°C
ESD Last Passing Voltage HBM, 1.5kΩ, 100pF 8kV
LVDS pins to GND only 15kV
EIAJ, 0Ω, 200pF 250V
CDM 1000V
(1) Absolute maximum ratings are those values beyond which damage to the device may occur. Texas Instruments does not recommend
operation of products outside of recommended operation conditions.
(2) VID max < 2.4V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC) 3.0V to 3.6V
Input Voltage (VI)(1) 0V to VCC
Output Voltage (VO) 0V to VCC
Operating Temperature (TA) Industrial −40°C to +85°C
(1) VID max < 2.4V
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SNLS197D –MAY 2006–REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ(1) Max Units
LVTTL DC SPECIFICATIONS (MUX_Sn, ENA_n, ENB_n, ENL_n)
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA
IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA
CIN1 Input Capacitance Any Digital Input Pin to VSS 3.5 pF
COUT1 Output Capacitance Any Digital Output Pin to VSS 5.5 pF
VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.8 V
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
VTH Differential Input High Threshold(2) VCM = 0.8V or 1.2V or 3.55V, 0 100 mV
VDD = 3.6V
VTL Differential Input Low Threshold(2) VCM = 0.8V or 1.2V or 3.55V, −100 0 mV
VDD = 3.6V
VID Differential Input Voltage VCM = 0.8V to 3.55V, VDD = 3.6V 100 2400 mV
VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.6V 0.05 3.55 V
CIN2 Input Capacitance IN+ or IN−to VSS 3.5 pF
IIN Input Current VIN = 3.6V, VDD = VDDMAX −15 +15 µA
VIN = 0V, VDD = VDDMAX −15 +15 µA
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
VOD Differential Output Voltage(2) RLis the internal 100Ωbetween OUT+ 250 360 500 mV
and OUT−
ΔVOD Change in VOD between -35 35 mV
Complementary States
VOS Offset Voltage(3) 1.05 1.22 1.475 V
ΔVOS Change in VOS between -35 35 mV
Complementary States
IOS Output Short Circuit Current OUT+ or OUT−Short to GND −21 -40 mA
COUT2 Output Capacitance OUT+ or OUT−to GND when TRI- 5.5 pF
STATE
SUPPLY CURRENT (Static)
ICC Supply Current All inputs and outputs enabled and
active, terminated with differential load of 225 275 mA
100Ωbetween OUT+ and OUT-.
ICCZ Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 = 0.6 4.0 mA
ENB_1 = ENL_1 = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT Differential Low to High Transition Use an alternating 1 and 0 pattern at 200 170 250 ps
Time Mb/s, measure between 20% and 80% of
VOD.(4)
tHLT Differential High to Low Transition 170 250 ps
Time
tPLHD Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200 1.0 2.5 ns
Delay Mb/s, measure at 50% VOD between
input to output.
tPHLD Differential High to Low Propagation 1.0 2.5 ns
Delay
tSKD1 Pulse Skew |tPLHD–tPHLD|(4) 25 75 ps
tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or 50 115 ps
tPHLD) among all output channels.(4)
(1) Typical parameters are measured at VDD = 3.3V, TA= 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
(3) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ(1) Max Units
tJIT Jitter(5) RJ - Alternating 1 and 0 at 400 MHz(6) 1.3 1.5 psrms
DJ - K28.5 Pattern, 800 Mbps(7) 15 34 psp-p
TJ - PRBS 27-1 Pattern, 800 Mbps(8) 16 34 psp-p
tON LVDS Output Enable Time Time from ENA_n, ENB_n, or ENL_n to 0.5 1.5 µs
OUT± change from TRI-STATE to active.
tON2 LVDS Output Enable time from Time from ENA_n, ENB_n, or ENL_n to 10 20 µs
powerdown mode OUT± change from Powerdown to active
tOFF LVDS Output Disable Time Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE 12 ns
or powerdown.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 400 MHz, tr= tf= 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been
subtracted. The input voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr= tf= 50ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted.
The input voltage = VID = 500mV, 27-1 PRBS pattern at 800 Mbps, tr= tf= 50ps (20% to 80%).
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POWER SUPPLY CURRENT (mA)
350
0
BIT DATA RATE (Mbps)
0 800
50
100
150
200
200 400 600
250
300
DS08MB200
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SNLS197D –MAY 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current vs. Bit Data Rate Total Jitter vs. Temperature
Total Jitter measured at 0V differential while running a PRBS 27-1
Dynamic power supply current was measured with all channels active pattern with one channel active, all other channels are disabled. VDD =
and toggling at the bit data rate. Data pattern has no effect on the 3.3V, VID = 0.5V, VCM = 1.2V, 800 Mbps data rate. Stimulus and
power consumption. VDD = 3.3V, TA= +25°C, VID = 0.5V, VCM = 1.2V. fixture jitter has been subtracted.
Figure 4. Figure 5.
Total Jitter vs. Bit Data Rate
Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with one channel active, all other channels are disabled.
VDD = 3.3V, TA= +25°C, VID = 0.5V. Stimulus and fixture jitter has been subtracted.
Figure 6.
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LVPECL
R2
150:
R1
150:
50:
50:
15MB200
0.1 PF
0.1 PF
LVPECL
R2
150:
R1
150:
50:
50:
15MB200
DS08MB200
SNLS197D –MAY 2006–REVISED MARCH 2013
www.ti.com
APPLICATIONS
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.
This drives a pair of emitter-followers that require a 50 ohm to VCC-2.0 load. A modern LVPECL driver will
typically include the termination scheme within the device for the emitter follower. If the driver does not include
the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB,
therefore, a load scheme without a unique power supply requirement may be used.
Figure 7. DC Coupled LVPECL to LVDS Interface
Figure 7 is a separated πtermination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for
the driver emitter followers, and may be included as part of the driver device. The DS08MB200 includes a 100
ohm input termination for the transmission line. The common mode voltage will be at the normal LVPECL
levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage,
VCM, range. Most Texas Instruments LVDS receivers have wide VCM range. The exceptions are noted in devices’
respective datasheets. Those LVDS devices that do have a wide VCM range do not vary in performance
significantly when receiving a signal with a common mode other than standard LVDS VCM of 1.2 V.
Figure 8. AC Coupled LVPECL to LVDS Interface
An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This
is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 8 illustrates an AC
coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device,
provide DC load for the emitter followers and may range between 140-220 ohms for most LVPECL devices for
this particular configuration. The DS08MB200 includes an internal 100 ohm resistor to terminate the transmission
line for minimal reflections. The signal after ac coupling capacitors will swing around a level set by internal
biasing resistors (i.e. fail-safe) which is either VDD/2 or 0 V depending on the actual failsafe implementation. If
internal biasing is not implemented, the signal common mode voltage will slowly wander to GND level.
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15MB200
R4
130:
R3
130:
50:
50:
LVPECL
VDD
R1
83:
R2
83:
0.1PF
0.1PF
15MB200
R2
50:
R1
50:
50:
50:
LVPECL
VT
DS08MB200
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SNLS197D –MAY 2006–REVISED MARCH 2013
Interfacing LVDS to LVPECL
An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a
differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should
be selected to match transmission line characteristic differential impedance so that the line is properly
terminated. The termination resistor should be placed as close to the receiver inputs as possible. When
interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within
the common mode range of the receiver. This may be done by using separate biasing voltage which demands
another power supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB).
Figure 9. DC Coupled LVDS to LVPECL Interface
Figure 9 illustrates interface between an LVDS driver and a LVPECL with a VTpin available. R1 and R2, if not
present in the receiver, provide proper resistive load for the driver and termination for the transmission line, and
VTsets desired bias for the receiver.
Figure 10. AC Coupled LVDS to LVPECL Interface
Figure 10 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VTpin
available. The resistors R1, R2, R3, and R4, if not present in the receiver, provide a load for the driver, terminate
the transmission line, and bias the signal for the receiver.
The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver
device. The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility between
the driver and receiver terminations and common mode operating ranges.
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS08MB200TSQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
DS08MB200TSQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS08MB200TSQ/NOPB WQFN RHS 48 250 210.0 185.0 35.0
DS08MB200TSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
48X 0.30
0.18
5.1 0.1
48X 0.5
0.3
0.8
0.7
(A) TYP
0.05
0.00
44X 0.5
2X
5.5
2X 5.5
A7.15
6.85 B
7.15
6.85
0.30
0.18
0.5
0.3
(0.2)
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
DIM A
OPT 1 OPT 2
(0.1) (0.2)
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
12 25
36
13 24
48 37
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
49 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 1.800
DETAIL
OPTIONAL TERMINAL
TYPICAL
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
48X (0.25)
48X (0.6)
( 0.2) TYP
VIA
44X (0.5)
(6.8)
(6.8)
(1.25) TYP
( 5.1)
(R0.05)
TYP
(1.25)
TYP
(1.05) TYP
(1.05)
TYP
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
SYMM
1
12
13 24
25
36
37
48
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
49
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
48X (0.6)
48X (0.25)
44X (0.5)
(6.8)
(6.8)
16X
( 1.05)
(0.625) TYP
(R0.05) TYP
(1.25)
TYP
(1.25)
TYP
(0.625) TYP
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
49
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
SYMM
1
12
13 24
25
36
37
48
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