MIEGE 10.000 LOGIC DIAGRAMS Numbers in parenthesis dencte pin numbers for F package (Case 650). FUNCTIONS AND CHARACTERISTICS (continued) Type 0) Propagation Power Dissipation Delay mW Function -30 to +85C | -55 to +125C ns typ typ/pkg* Case Universal Decade Counter MC10137 MC10537 f= 150 MHz 625 620,650 Bi-Quinary Counter MC10138 _ f= 150 MHz 370 620 64-Bit Random Access Memory (90 2) MCM10140 - taccess = 15 (max) 420 620,690 Four-Bit Universal Shift Register MC10141 MC 10541 # = 200 MHz 425 620,648 650 64 Bit Random Access Memory (50 $2) MCM10142 ~ taAccess = 10 (max) 420 620 8 x 2 Muitiport Register File (RAM} MCM10143 - taccess = 10 610 623 256-Bit Random Access Memory MCM10144 - taccess = 30 (max) 420 620,690 64-Bit Register File (RAM) MCM10145 - taccess = 10 625 620 128-Bit Random Access Memory MCM10147 - taccess = 12 (max) 420 620 64-Bit Random Access Memory (50 92) MCM10148 _ taccess = 15 (max) 420 620 1024-Bit Programmable Read Only Memory MCM10150 _ taccess = 20 = 690 Quad Latch MC10153 _ 4.0 310 620 12-Bit Parity Generator-Checker MC10160 MC10560 5.0 320 620,648 650 Binary to 1-8 Decoder (Low) MC10161 Mc10561 4.0 315 620,648,650 Binary to 1-8 Decoder (High) MC 10162 MC10562 4.0 315 620,648 ,650 Error Detection-Correction Circuit MC10163 _ 5.0 520 620 8-Line Multiplexer MC10164 MC 10564 3.0 310 620,648,650 8-Input Priority Encoder MC10165 _ 7.0 545 620,648 5-Bit Magnitude Comparator MC10166 - 6.0 440 620 Quad Latch MC 10168 - 3.0 310 620 Oual Binary To t-4 Decoder (Low) MC10171 Mc10571 4.0 32S 620,648,650 Dual Binary To 1-4 Decoder (High) MC10172 MC10572 4.0 325 620,648,650 Quad 2-Input Multiplexer/Latch MC10173 - 2.5 278 620,648 Dual 4 To 1 Multiplexer MC10174 McC 10574 3.5 305 620,650 Quint Latch MC10175 MC10575 2.5 400 620 Hex D" Master-Slave Flip-Flop mMC10176 - f = 250 MHz 460 620 Triple MECL to NMOS Translator MC10177 _ - 1.0W 620 Binary Counter MC 10178 _ f = 150 MHz 370 620 Look-Ahead Carry Block MC10179 Mc 10579 3,0 (Cn,P} 4.0 (G) 300 620,648,650 Dua! High Speed Adder/Subtractor MC 70180 Mc 10580 4.5 360 620,648,650 4-Bit Arithmetic Logic Unit/Function Generator MC10181 McC10581 See Logic Diag. 600 623,649,652 2-Bit Arithmetic Logic Unit/Function Generator MC10182 - See Logic Diag. 575 620 Error Detection-Correction Circuit MC10193 _ 7.5 520 620 Hex inverter/Buffer MC10195 - 2.0 200 620 Hex AND Gate MC10197 - 2.8 200 620 High Speed Dual 3-Input 3-Output OR Gate MC10210 _ 1.5 160 620 High Speed Oual 3-input 3-Output NOR Gate MC10211 =_ 1.5 160 620 High Speed Dual 3-Input 3-Output OR/NOR Gate MCc10212 _ 1.5 160 620 High Speed Tripie Line Receiver MC 10216 Mc 10616 1.8 100 620,648,650 High Speed Dual Type D Master-Slave Flip-Flop Mc10231 mMc10631 f = 225 MHz 270 620,648,650 High Speed 2 x 1 Bit Array Multiplier Block MC 10287 - ~ 400 620 q@ L suffix denotes Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package {i.e., MC101001. = Ceramic Dual In-Line Package, MC10100P = Plastic Dual !n-Line Package and MC 10S500F = Ceramic Flat Package.) *Load Power not includedLOGIC DIAGRAMS (continued) --DECODERS MC10161 MC 10162 MC10561 MC 10562 Binary To 1-8 Decoder Binary To 1-8 Decoder (Low) _ (High) E 6 ao E 5 Qi 4 a2 3 a3 A 13 a4 12 a5 8 11 a6 10 Q7 TRUTH TABLE TRUTH TABLE ENABLE INPUTS] INPUTS OUTPUTS _/NPUTS OUTPUTS 1[o|c|B]a| ao0[a1| a2]a3] 0405] a6] a7 Eo) et) ] 6] A | 00/01) a2] a3) a4] a5) 06) a7 efefelcefe. ec favo] alatatata LPePeP ep eye pepe yepepeyeye CPetcie[RAP aA PoP Ry apap a aa LPR PL] CPHL PaPePePeE PR Pe ye L L JUJHEL] H H L H H al H H cee ul H/o L]L IH cyte Lye L Lt LILJH]H] # H H L H H H H bie L HI H LIe Ju H u Lye uL CPUYHieye) Hy HP HP HPL YP A) Hy LCeePHP ePuPeJyePuePuyHtepede Lu tc Jealalal a Hu H HM H H H L L L H H L bye L bye LIW L HI @lelole)H]H} a} HpHyHt Aye Cpe PAP APH yep e Pepe pupa a GTHIololeo|/ HLH] H] HP HI] Hi HI RH H/o} Oo) oe} eo] ete; eFPULELPTeEPETe d= Don't Care PlH{ >? >] O]ueTEFePFuePeEYPueye TC + Don't Care Po = 315 mW typ/pkg (No Load) Pp = 315 mW typ/pkg (No Load) tog = 4.0 ns typ tog = 4.0 nstyp MC10171 MC10172 Dual Binary To 1-4 Decoder Dual Binary To 1-4 Decoder (Low) (High) E014 10 00 3 014 10 a0 3 11 QO 2 11Q0 2 12 00 1 12.00 1 Aas Ag 13 40 0 13,00 0 3.01 3 3013 B7 4 ai 2 B7 4 a1 2 E 15 65 a1 1 _ 6a10 F4. Sard E11 2 #12 6 aro TRUTH TABLE TRUTH TABLE ENABLE INPUTS | INPUTS OUTPUTS | 1] Eo] a | Bf{ato}ars} a1 2) 013] a00/G01{ a02/a03 = | o | @ {| a | B { aro| a11 | a12] asa | aoo | a01 | G02 | a03 Tlatnutotlials Turcliels fete L bb L & t L H H H L H H rn ct H H L H L H L L Ll H L L L L L lL H H L H 4 Ha L Hn H L H H H Lt L L n L Lt L H L t L L H L H H Ll H H H tb H L H Hw H H bt L ia H Lt Ll L H L bb lL H 4 H H H L H H H lL l L H iS L L L Lt L H L L Lt L tL H L L 4 H H 4 iS H H H L H L L LY] Hu L L Ll L L uc L tL Hw L L L iS H 4 H H cd H H H o o o L L L L lL L Ll t 4 % @ % e H H H fl H H 4 H @= Dont Care $= Don't Core Pp = 325 mW typ/pkg(No Load) PD = 325 mW typ/pkg (No Load) tod 4.0 nstyp tog = 4.0 ns typMECL 10,000 series DUAL BINARY TO 1-4-DECODER (HIGH) MC10172 The MC10172 is a binary-coded 2 line to dual 4 line decoder with selected outputs high. With either EO or E1 low, the corresponding selected 4 outputs are low. The common en- able E, when high, forces all outputs low. All propagation delay times are equal. High 10 a0 3 impedance 50 k ohm resistors on all inputs eliminate the need to tie unused inputs to VEE. POSITIVE LOGIC E014 1t 00 2 12 Q0 1 13 00 0 3.013 Pp = 325 mW typ/pkg (No Load) toa = 4.0 ns typ B?7 49012 65 a1 1 = 6a10 E12 Voo1= Pint Vec2 =Pin 16 Vee =Pin& TRUTH TABLE E E1 |] Eo] a BjQ10]Q11] at 2/013] Q00]Q01|] A02/ A003 L H H L L H L Ll L H Ll L ul L H H L H t H L cu t H L L L H H H L L L H t L tL H L L H H H H ul & L H L L L H L Ll H Ll L L rs L L H t L L Ll H L L L H L L bt Lb L cl L H o oo] te L L L L L L L $= Don't Care See General information section for packaging and maximum ratings. 3-161Z9L- ELECTRICAL CHARACTERISTICS Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equi- librium has been established. The circuit is in @ test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown only for selected inputs and outputs. Other inputs and outputs are tested in a simitar manner. E614 B mi a ~~ 10 G0 3 11002 12 Q0 7 13 Q0 0 3a13 4a12 sar1 [J De-e or 0 L SUFFIX CERAMIC PACKAGE CASE 620 TEST VOLTAGE VALUES He (Volts) @ Test Temperature Vittmax | Vitmin {| VIHAmin | ViLAmax_| VEE -30C -0.890 -1.890 1.205 ~1.500 5.2 +25C -0.810 -1.850 -1.105 -1.475 ~.2 +85C -0.700 ~1.825 1.035 -1.440 5.2 Pin MC10172L Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW: Under 30C +25C +85C {Vec) Characteristic Symbol | Test Min Max Min Typ Max Min Max Unit Vilmax Vitmin Vitamin | Vitamax VEE Gnd Power Supply Drain Current fe 8 - = - 62 77 - _ mAdc _ _ - - 8 1,16 Input Current linH 14 - - - - 220 - - uAdc 14 - - - 8 1,16 link 14 - - 0s - - - - nAde - 14 - ~ 8 1,16 Logic 1 VOH 6 1,060 | -0.890 | -0.960 = -0.810 ] -0.890 | -0.700 } Vdc 2 = = = 8 7.16 Output Voltage 13 | -1.060 | -0.890 | -0.960 = -0.810 | -0.890 | -0.700 | Vdc 14 ~ ~ - 8 1,16 Logic "0" Output Voltage VoL 13 | -1.890 | -1.675 | -1.850 = -1,650 | -1.825 | -1.615 | Vide 18 2,7,9,14 = 8 1,16 Logic 1 VOHA 6 -1,080 - ~0.980 - - 0.910 ~ Vde - _ 2 = 8 1,16 Threshold Voltage 13 | -1.080 - -0.980 ~ - -0.910 - Vde - - 14 - 8 1,16 Logic 0 VoLA 6 = 1.655 = - 1.630 = -1.595 | Vdc - 29,14 = 7 8 1.16 Threshold Voltage 13 - 1.655 - - 1.630 ' | 1595 | Vde - 27,14 - 9 8 1,16 Switching Times {50 2 Load) +1.11V +0.31V Pulse In Pulse Out {| -3.2V | +2.0V Propagation Delay 1746- 6 15 6.2 15 4.0 6.0 15 64 ns 2 9,14 7 6 8 1,16 17-6+ 6 2 9,14 6 t7413- 13 | | 14 29 13 t7-13+ 13 14 29 13 te+ 6 1.0 3.3 1.1 2.0 3.3 11 3.4 2 9,14 6 Rise Time (20% to 80%) t13+ 13 14 29 13 tg 6 | | | | 2 9,14 6 Fall Time (20% to 80%) 43- 13 14 29 13 (panutjuos) ZLLOLIOWE9L- ELECTRICAL CHARACTERISTICS Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equi- tibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown only for selected inputs and outputs. Other inputs and outputs are tested in a similar manner. 10 a0 3 11:a0 2 12:QG 1 13, a0 0 3a13 4ai2 sai 1 6010 P SUFFIX PLASTIC PACKAGE CASE 648 TEST VOLTAGE VALUES {Volts} @ Test Temperature Vitmax Vitmin | ViHAmin | VitAmax | VEE -30C -0.890 -1.890 -1.205 -1.500 -5.2 +25C -0.810 -1,850 ~1.105 -1.475 -5.2 +85C -0.700 -1.825 1.035 -1.440 5.2 Pin MC10172P Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW: Under -30C +25C +85C Vcc) Characteristic Symbol | Test Min Max Min Typ Max Min Max Unit Vitimax Vitmin Vintamin | VitAmax VEE Gnd Power Supply Drain Current le 8 - _ - 62 77 - mAdc - - ~ - 8 1,16 Input Current lin 14 - - - _ 220 - - uAde 14 - - ~ 8 1,16 lint 14 - - 0s - - - - BAde ~ 14 - - 8 1,16 Logic 1 Vou 6 -1.060 | ~0.890 | -0.960 - -0.810 | -0.890 | -0.700 | Vac 2 = = = 8 7.16 Output Voltage 13 -1.060 | -0.890 | -0.960 = -0.810 | -0.890 | -0.700 | Vdc 14 - - - 8 1,16 Logic 0 Output Voltage VoL 13 -1.890 | -1.675 | -1.850 - -1.650 | -1.825 | -1.615 | Vdc 15 2,7,9,14 = - 8 116 Logic 1 VOHA 6 -1.080 - -0.980 - - -0.910 = Vde = - 2 = 8 1,16 Threshold Voltage 13 -1,080 - -0.980 - - -0.910 = Vde - - 14 - 8 1,16 Logic "0" VoLA 6 - -1.655 - = 1.630 - -1.595 | Vde = 2,9,14 = 7 8 1,16 Threshold Voltage 13 - ~1.655 - - -1,630 _ -1.595 | Vdc 27,14 - 9 8 1,16 Switching Times (50 2 Load) +1.11V +0.31V Pulse In | Pulse Qut | -3.2V | +2.0V Propagation Delay 1746- 6 - - 15 4.0 6.0 - - ns 2 9,14 7 6 8 1,16 17-6+ 6 - - ~ ~ 2 9,14 6 17413- | 13 - ~ - - 14 29 13 17-134 |] 13 - - - - 14 29 13 te+ 6 - - 1 2.0 3.3 - - 2 9,14 6 Rise Time (20% to 80%) t13+ 13 - - i - - 14 29 13 te. 6 - ~ - - 2 9,14 6 Fall Time (20% to 80%) t13- 13 - - Y - - 14 29 13 (PanunUod) Z/ LOLOINMC 10172 (continued) SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C Vec1 Voc2 Vin +2.0 Vde Vout Input Pulse Generator PROPAGATION DELAY +1100 +0.31V Input Pulse t= t- = 2.04 0.2 ns (20 to 80%) Le ee ee 0.1 uF +1.91 Vde or +0.31 Vde,per test table TT" HF Ver = -3.2 Vd cE Unused outputs connected to a 50-ohm resistor to ground. All input and output cables to the scope are equal lengths of 60-ohm coaxial cable. Wire length should be <1/4 inch from TPin to input PIP and TPoyt to output pin. 3-164