Document No. DOC-14014-3 │www.psemi.com
Page 1 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
RF2
RF5
RF4
CMOS Control/
Driver and ESD
V1 V2
ESD
RF1
V3
RF3
ESD
50
ESD
50
ESD
50
ESD
50
ESD
50
RFC
VssEXT (optional)VDD
Figure 1. Functional Diagram
Figure 2. Package Type
24-lead 4x4 mm QFN
Product Specification
UltraCMOS® SP5T RF Switch
450–4000 MHz
PE42452
Features
Five symmetric, absorptive RF ports
High isolation
61 dB @ 900 MHz
55 dB @ 2100 MHz
52 dB @ 2700 MHz
44 dB @ 4000 MHz
High linearity
IIP2 of 96 dBm
IIP3 of 57 dBm
1.8V control logic compatible
105°C operating temperature
Fast switching time of 265 ns
Three pin CMOS logic control
External negative supply option
ESD performance
4kV HBM on RF pins to GND
1.5kV HBM on all pins
Product Description
The PE42452 is a HaRP™ technology-enhanced
absorptive SP5T RF switch designed for use in 3G/4G
wireless infrastructure and other high performance RF
applications.
This switch is a pin-compatible upgraded version of the
PE42451 with 1.8V control logic. It is comprised of five
symmetric RF ports and has very high isolation. An
integrated CMOS decoder facilitates a three-pin low
voltage CMOS control interface and an external negative
supply option. In addition, no external blocking
capacitors are required if 0V DC is present on the RF
ports.
The PE42452 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS® process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.
DOC-02114
Product Specification
PE42452
Page 2 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14014-3 │ UltraCM OS® RFIC Solutions
Table 1. Electrical Specifications @ 25°C (ZS = ZL = 50Ω) unless otherwise noted
Normal mode1: VDD = 3.3V, VssEXT = 0V or Bypass mode2: VDD = 3.3V, VssEXT = -3.3V
Notes: 1. Normal mode: single external positive supply used
2. Bypass mode: both external positive supply and external negative supply used
3. The input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for the operating RF input power (50Ω)
Parameter Path Condition Min Typ Max Unit
Operating frequency 450 4000 MHz
Insertion loss RFC–RFX
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
0.95
1.15
1.30
1.60
1.15
1.35
1.55
1.90
dB
dB
dB
dB
Isolation RFC–RFX
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
56
52
49
41
61
55
52
44
dB
dB
dB
dB
Return loss (active port) RFX 450–4000 MHz 16 dB
Return loss (terminated port) RFX 450–4000 MHz 23 dB
Input 0.1 dB compression point3 RFC–RFX 1950 MHz 35 dBm
Input IP2 RFC–RFX 1950 MHz 96 dBm
Input IP3 RFC–RFX 1950 MHz 57 dBm
Switching time 50% control to 10% or 90% RF 265 345 ns
Isolation RFX–RFX
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
56
51
49
41
60
53
52
42
dB
dB
dB
dB
Product Specification
PE42452
Page 3 of 11
Document No. DOC-14014-3 │w ww.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
GND
RFC
GND
GND
VssEXT
24
23
22
21
20
19 V3
GND
RF3
GND
GND
RF2
GND
7
8
9
10
11
12
Figure 3. Pin Configuration (Top View)
Notes: 1. RF pins 2, 5, 8, 11, 14, and 22 must be at 0V DC. The RF pins do
not require DC blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use VssEXT (pin 20, refer to Table 3) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 20, VssEXT = GND) to
enable internal negative voltage generator
Pin # Name Description
1, 3, 4, 6, 7,
9, 10, 12, 13,
15, 21, 23, 24 GND Ground
5 RF41 RF port 4
8 RF31 RF port 3
11 RF21 RF port 2
14 RF11 RF port 1
16 VDD Supply voltage
17 V1 Digital control logic input 1
18 V2 Digital control logic input 2
19 V3 Digital control logic input 3
20 VssEXT2 External Vss negative voltage control/
ground
22 RFC1 RF common
Pad GND Exposed pad: Ground for proper operation
2 RF51 RF port 5
Table 3. Operating Ranges
Parameter Symbol Min Typ Max Unit
Normal mode1
Supply voltage VDD 2.3 5.5 V
Supply current IDD 110 µA
Bypass mode2
Supply current IDD 50 µA
Negative supply
voltage VssEXT -3.6 -3.2 V
Normal or Bypass mode
Digital input high
(V1, V2, V3) VIH 1.17 3.6 V
Digital input low
(V1, V2, V3) VIL -0.3 0.6 V
Digital input current3 I
CTRL 1 µA
RF input power, CW PMAX,CW 33 dBm
RF input power into
terminated ports, CW PMAX,TERM 24 dBm
Operating
temperature range TOP -40 +105 °C
Supply voltage VDD 2.7 5.5 V
Notes: 1. Normal mode: connect pin 20 to GND to enable internal negative
voltage generator
2. Bypass mode: apply a negative voltage to VssEXT (pin 20) to
bypass and disable internal negative voltage generator
3. The pull-down resistor in the EVK schematic may increase control
current
Table 4. Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Parameter/Condition Symbol Min Max Unit
Supply voltage VDD -0.3 5.5 V
Voltage on any DC input VI -0.3 3.6 V
Maximum input power PMAX,ABS 34 dBm
Storage temperature range TST -60 +150 °C
ESD voltage HBM1
All pins
RF pins to ground VESD,HBM
1500
4000
V
V
ESD voltage MM2, all pins VESD,MM 100 V
ESD voltage CDM3, all pins VESD,CDM 500 V
Notes: 1. Human Body Model (MIL_STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model ( JEDEC JESD22-C101D)
Product Specification
PE42452
Page 4 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14014-3 │ UltraCM OS® RFIC Solutions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Mode V3 V2 V1
All off 0 0 0
RF1 on 0 0 1
RF2 on 0 1 0
RF3 on 0 1 1
RF4 on 1 0 0
RF5 on 1 0 1
All off 1 1 0
Unsupported 1 1 1
Table 5. Truth Table
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42452 in the 24-lead 4x4 QFN package is
MSL1.
Switching Frequency
The PE42452 has a maximum 25 kHz switching
rate in normal mode (pin 20 = GND). A faster
switching rate is available in bypass mode (pin 20
= VssEXT ). The rate at which the PE42452 can be
switched is then limited to the switching time as
specified in Table 1.
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Optional External Vss Control (VssEXT)
For applications the require a faster switching rate
or spur-free performance, this part can be
operated in bypass mode. Bypass mode requires
an external negative voltage in addition to an
external VDD supply voltage.
As specified in Table 3, the external negative
voltage (VssEXT) when applied to pin 20 will
disable and bypass the internal negative voltage
generator.
Spurious Performance
The typical low-frequency spurious performance
of the PE42452 in normal mode is –120 dBm
(pin 20 = GND). If spur-free performance is
desired, the internal negative voltage generator
can be disabled by applying a negative voltage to
VssEXT (pin 20).
Note: Logic State 111 is unsupported and should not be used under any
operating conditions
Product Specification
PE42452
Page 5 of 11
Document No. DOC-14014-3 │w ww.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise noted
Figure 5. Insertion Loss vs Temp (RFC–RFX) Figure 6. Insertion Loss vs VDD (RFC–RFX)
Figure 4. Insertion Loss (All Paths)
Product Specification
PE42452
Page 6 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14014-3 │ UltraCM OS® RFIC Solutions
Figure 7. Isolation vs Temp (RFC–RFX) Figure 8. Isolation vs VDD (RFC–RFX)
Figure 9. Isolation vs Temp (RFX–RFX)
Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise noted
Figure 10. Isolation vs VDD (RFX–RFX)
Product Specification
PE42452
Page 7 of 11
Document No. DOC-14014-3 │w ww.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
00.511.522.533.544.5
IIP3 (dBm)
Frequency (GHz)
RF1
RF2
RF3
RF4
RF5
Figure 11. Active Port Return Loss vs Temp Figure 12. Active Port Return Loss vs VDD
Figure 13. RFC Port Return Loss vs Temp
Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise noted
Figure 14. RFC Port Return Loss vs VDD
Figure 15. Return Loss (All Ports Terminated) Figure 16. IIP3 vs Frequency
Product Specification
PE42452
Page 8 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14014-3 │ UltraCM OS® RFIC Solutions
Evaluation Kit
The SP5T switch Evaluation Board was designed
to ease customer evaluation of Peregrine’s
PE42452. The RF common port is connected
through a 50Ω transmission line via the top SMA
connector. RF1, RF2, RF3, RF4 and RF5 are
connected through 50Ω transmission lines via side
SMA connectors. A through 50Ω transmission is
available via SMA connectors RFCAL1 and
RFCAL2. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The EVK board is constructed with four metal
layers on dielectric materials of Rogers 4003C and
4450 with a total thickness of 32 mils. Layer 1 and
layer 3 provide ground for the 50Ω transmission
lines. The 50Ω transmission lines are designed in
layer 2 for high isolation purpose and use
a stripline waveguide design with a trace width of
9.4 mils and trace metal thickness of 1.8 mils. The
board stack up for 50 ohm transmission lines has
8 mil thickness of Rogers 4003C between layer 1
and layer 2, and 10 mil thickness of Rogers 4450
between layer 2 and layer 3. Please consult
manufacturer's guidelines for proper board
material properties in your application. The PCB
should be designed in such a way that RF
transmission lines and sensitive DC I/O traces
such as VssEXT are heavily isolated from one
another, otherwise the true performance of the
PE42452 will not be yielded.
Figure 17. Evaluation Board Layout
PRT-29105
Product Specification
PE42452
Page 9 of 11
Document No. DOC-14014-3 │w ww.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 18. Evaluation Board Schematic
DOC-14027
Product Specification
PE42452
Page 10 of 11
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-14014-3 │ UltraCM OS® RFIC Solutions
Figure 19. Package Drawing
24-lead 4x4 mm QFN
DOC-58197
Figure 20. Marking Specifications
42452
YYWW
ZZZZZ
DOC-51207
= Pin 1 designator
YYWW = Date code
ZZZZZ = Las five digits of the lot number
Product Specification
PE42452
Page 11 of 11
Document No. DOC-14014-3 │w ww.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 21. Tape and Reel Drawing
Device Orientation in Tape
To p of
Device
Pin 1
Tape Feed Direction
A0 = 4.35
B0 = 4.35
K0 = 1.1
Table 6. Ordering Information
PE42452A-Z PE42452 SP5T RF switch Green 24-lead 4x4 mm QFN 3000 units/T&R
EK42452-01 PE42452 Evaluation kit Evaluation kit 1/Box
Ordering Code Description Package Shipping Method
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this data sheet is believed to b e reliable. However, P eregrine assume s no liability for the use
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
following U.S. Patents: http://patents.psemi.com.
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For sales and contact information please visit www.psemi.com.
