PSMN015-100B,118-CUT TAPE"" - NXP SEMICONDUCTORS

PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

Rev. 06 — 17 December 2009 Product data sheet

1. Product profile

1.1 General description

SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in

a plastic package using T renchMOS technology. This product is de signed and qualified for

use in computing, communications, consumer and industrial ap plications only.

1.2 Features and benefits

Low conduction losses due to low

on-state resistance

Rated for avalanche ruggedness

1.3 Applications

DC-to-DC convertors Switched-mode power supplies

1.4 Quick reference data

Ta ble 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤175 °C - - 100 V

IDdrain current Tmb =25°C; V

GS =10V;

see Figure 1 and 3--75A

Ptot total power

dissipation Tmb = 25 °C; see Figure 2 - - 300 W

Dynamic characteristics

QGD gate-drain charge VGS =10V; I

D=75A;

VDS =80V; T

j=25°C;

see Figure 11

-35-nC

Static characteristics

RDSon drain-source

on-state resistance VGS =10V; I

D=25A;

Tj=25°C;

see Figure 9 and 10

- 1215mΩ

Product data sheet Rev. 06 — 17 December 2009 2 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

2. Pinning information

[1] It is not possible to make a connection to pin 2.

3. Ordering information

4. Limiting values

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1G gate

SOT404 (D2PAK)

2D drain [1]

3S source

mb D mounting base; connected to

drain

bb076

Table 3. Ordering informa tion

Type number Package

Name Description Version

PSMN015-100B D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one

lead cropped) SOT404

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤175 °C - 100 V

VDGR drain-gate voltage Tj≤175 °C; Tj≥25 °C; RGS =20kΩ-100V

VGS gate-source voltage -20 20 V

IDdrain current VGS =10V; T

mb = 100 °C; see Figure 1 -60.8A

VGS =10V; T

mb =25°C; see Figure 1 and 3-75A

IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 3 -240A

Ptot total power dissipation Tmb =25°C; see Figure 2 -300W

Tstg storage temperature -55 175 °C

Tjjunction temperature -55 175 °C

Source-drain diode

ISsource current Tmb =25°C - 75 A

ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 240 A

Avalanche ruggedness

EDS(AL)S non-repetitive

drain-source avalanche

energy

VGS =10V; T

j(init) =25°C; I

D=36A; V

sup ≤50 V;

unclamped; tp= 0.11 ms; RGS =50Ω

-320mJ

Product data sheet Rev. 06 — 17 December 2009 3 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

Fig 1. Normalized continuous drain current as a

function of mounting base temperature Fig 2. Normalized total power dissipation as a

function of mounting base temperature

Fig 3. Safe operating area; continuous and peak drain curren ts as a function of drain-source voltage

03an67

120

0 50 100 150 200

Ider

(%)

Tmb (°C) Tmb (°C)

0 20015050 100

03aa16

120

Pder

(%)

03am53

VDS (V)

1 103

102

103

(A)

100 μs

10 ms

Limit RDSon = VDS

/ID

1 ms

tp = 10

μs

Product data sheet Rev. 06 — 17 December 2009 4 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from

junction to mounting

base

see Figure 4 --0.5K/W

Rth(j-a) thermal resistance from

junction to ambient mounted on a printed-circuit board;

minimum footprint; vertical in still air -50-K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

03am52

−1

−2

th(j-mb)

(K/W)

−3

(s)

−5

−1

−2

−4

−3

δ =

single pulse

= 0.5

0.2

0.1

0.05

0.02

Product data sheet Rev. 06 — 17 December 2009 5 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source

breakdown voltage ID=250µA; V

GS =0V; T

j=-55°C 89 - - V

ID=250µA; V

GS =0V; T

j=25°C 100 - - V

VGS(th) gate-source threshold

voltage ID=1mA; V

DS= VGS; Tj=175°C;

see Figure 8 1- - V

ID=1mA; V

DS= VGS; Tj=-55°C;

see Figure 8 --4.4V

ID=1mA; V

DS= VGS; Tj=25°C;

see Figure 8 234V

IDSS drain leakage current VDS =100V; V

GS =0V; T

j= 25 °C - 0.05 10 µA

VDS =100V; V

GS =0V; T

j= 175 °C - - 500 µA

IGSS gate leakage current VGS =20V; V

DS =0V; T

j= 25 °C - 2 100 nA

VGS =-20V; V

DS =0V; T

j= 25 °C - 2 100 nA

RDSon drain-source on-state

resistance VGS =10V; I

D=25A; T

j= 175 °C;

see Figure 9 and 10 - 32.4 40.5 mΩ

VGS =10V; I

D=25A; T

j=25°C;

see Figure 9 and 10 -1215mΩ

Dynamic character istics

QG(tot) total gate charge ID=75A; V

DS =80V; V

GS =10V;

Tj=25°C; see Figure 11 -90-nC

QGS gate-source charge - 20 - nC

QGD gate-drain charge - 35 - nC

Ciss input capacitance VDS =25V; V

GS = 0 V; f = 1 MHz;

Tj=25°C; see Figure 12 - 4900 - pF

Coss output capacitance - 390 - pF

Crss reverse transfer

capacitance - 220 - pF

td(on) turn-on delay time VDS =50V; R

L=1.8Ω; VGS =10V;

RG(ext) =5.6Ω; Tj=25°C -25-ns

trrise time - 65 - ns

td(off) turn-off delay time - 95 - ns

tffall time - 50 - ns

Source-drain diode

VSD source-drain voltage IS=25A; V

GS =0V; T

j=25°C;

see Figure 13 -0.81.1V

trr reverse recovery time IS=20A; dI

S/dt = -100 A/µs; VGS =0V;

VDS =25V; T

j=25°C -80-ns

Qrrecovered charge - 115 - nC

Product data sheet Rev. 06 — 17 December 2009 6 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a

function of gate-source vo ltage; typical values

Fig 7. Sub-threshold drain current as a function of

gate-source voltage Fig 8. Gate-source threshold voltage as a function of

junction temperature

03am54

0 0.2 0.4 0.6 0.8 1

VDS (V)

(A)

4.4 V

Tj = 25 °C

VGS = 4.2 V

10 V

4.6 V

4.8 V

5.2 V

5 V

5.6 V5.6 V6 V 5.6 V 5.4 V

03am56

0246

VGS (V)

(A)

VDS > ID x RDSon

Tj = 25 °C

175 °C

03aa35

VGS (V)

0642

10−4

10−5

10−2

10−3

10−1

(A)

10−6

min typ max

Tj (°C)

−60 180120060

03aa32

VGS(th)

(V)

max

typ

min

Product data sheet Rev. 06 — 17 December 2009 7 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values F ig 10. Normalized drain-source on-state resistance

factor as a functio n o f jun ction temperature

Fig 11. Gate-source voltage as a function of gate

charge; typical values Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

03am55

0 1020304050

ID (A)

RDSon

(mΩ)

VGS = 5 V

Tj = 25 °C

5.4 V

10 V

6 V

5.6 V

5.2 V

03al21

-60 0 60 120 180

(°C)

03am59

0 25 50 75 100

QG (nC)

VGS

(V)

ID = 75 A

Tj= 25 °C VDD = 20 V

80 V

03am58

102

103

104

10−1 1 10 102

VDS (V)

(pF) Ciss

Coss

Crss

Product data sheet Rev. 06 — 17 December 2009 8 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

Fig 13. So urce current as a function of source-drain voltage; typical values

03am57

100

0 0.3 0.6 0.9 1.2

VSD (V)

(A)

Tj = 25 °C

175 °C

VGS = 0 V

Product data sheet Rev. 06 — 17 December 2009 9 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

7. Package outline

Fig 14. Package outline SOT404 (D2PAK)

UNIT A

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

A1D1

max. EeL

pHDQc

2.54 2.60

2.20

15.80

14.80

2.90

2.10

11 1.60

1.20

10.30

9.70

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

DIMENSIONS (mm are the original dimensions)

SOT404

0 2.5 5 mm

scale

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT40

e e

mounting

base

05-02-11

06-03-16

Product data sheet Rev. 06 — 17 December 2009 10 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

8. Revision history

Table 7. Revisio n history

Document ID Release date Data sheet status Change notice Supersedes

PSMN015-100B_6 20091217 Product data sheet - PSMN015_100P_100B-05

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate .

•Type number PSMN015-10 0B separated from data sheet PSMN015_100P_100B-05.

PSMN015_100P_100B-05

(9397 750 12543) 20040114 Product data - -

Product data sheet Rev. 06 — 17 December 2009 11 of 12

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

9.2 Definitions

Draft— The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data s heet— A short data sheet is an extract from a full dat a sheet with

the same product type number(s) and title. A short data sheet is intended for

quick reference only and sh ould not be re lied upon to co ntain detailed and full

information. For detailed and full information see the relevant full data sheet,

which is available on request via the local NXP Semiconductors sales office.

In case of any inconsistency or conflict with th e short data sheet, the full data

sheet shall prevail.

9.3 Disclaimers

General— Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors d oes not give an y represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes— NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use— NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications— Applications that are described herein for any of th ese

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Quick reference data— The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values— Stress above one or more limiting values (as defined in

the Absolute Maximum Rati ngs System of I EC 60134) may cause perman ent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale— NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sal e, as published

athttp://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in t his docume nt may b e int erpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control— This document as well as the item(s) described here in may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

9.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

TrenchMOS— is a trademark of NXP B.V.

10. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

NXP Semiconductors PSMN015-100B

N-channel TrenchMOS SiliconMAX standard level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 December 2009

Document identifier: PSMN015-100B_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

10 Contact information. . . . . . . . . . . . . . . . . . . . . .11