74HC166D-Q100J - NEXPERIA - Datasheet.Directory

Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use http://www.nexperia.com

Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use

salesaddresses@nexperia.com (email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

1. General description

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift

and a serial output (Q7). When the p ara llel enable input (PE) is LOW, the data from D0 to

D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input

(CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH

transition of CP. When the clock enable input (CE) is LOW data is shifted on the

LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Input s include

clamp diodes which enable the use of current limiting resistors to interface inputs to

voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from 40 C to +85 C and from 40 C to +125 C

Synchronous parallel-to-serial applications

Synchronous serial input for easy expansion

Complies with JEDEC standard no. 7A

Input levels:

For 74HC166-Q100: CMOS level

For 74HCT166-Q100: TTL level

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

Multiple package options

3. Ordering information

74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Rev. 1 — 25 September 2013 Product data sheet

Table 1. Ordering information

Type number Package

Temper ature range Name Description Version

74HC166D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body

width 3.9 mm SOT109-1

74HCT166D-Q100

74HC166PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

Product data sheet Rev. 1 — 25 September 2013 2 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

4. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol

aaa-008816

Q7 13

115

PE DS

CP CE

9MR

aaa-008817

2,1D

≥1

SRG8

C1/2

14 13

2,1D

Fig 3. Functional diagram

aaa-008818

8-BIT PARALLEL/SERIAL-IN/

SERIAL-OUT SHIFT REGISTER

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 1 — 25 September 2013 3 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Fig 4. Logic diagra m

aaa-008819

D0 D1 D2 D3 D4 D5 D6 D7

RRD

Product data sheet Rev. 1 — 25 September 2013 4 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 5. Pin configu ration (SO16 and TSSOP16)

+&4

+&74

9&&





'



4



'

(

'

'

*1' 05

DDD

































Table 2. Pin description

Symbol Pin Description

DS 1 serial data input

D0 to D7 2, 3, 4, 5, 10, 11, 12, 14 parallel data inputs

CE 6 clock enable input (active LOW)

CP 7 clock input (LOW-to-HIGH edge-triggered)

GND 8 ground (0 V)

MR 9 asynchronous master reset (active LOW)

Q7 13 serial output from the last stage

PE 15 parallel enable input (active LOW)

VCC 16 positive supply voltage

Product data sheet Rev. 1 — 25 September 2013 5 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

6. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

 = LOW-to-HIGH clock transition.

Table 3. Function table[1]

Operating modes Inputs Qn registers Output

PE CE CP DS D0 to D7 Q0 Q1 to Q6 Q7

parallel load I I X I L L to L L

IIX h H H to H H

serial shift h I l X L q0 to q5 q6

hI h X H q0 to q5 q6

hold “do nothing”XHXXXq0q1 to q6q7

Fig 6. Typica l clear, shift, load, inhibit, and shift sequences

load aaa-008820clear

shift/

load

mode

control

inputs

parallel

inputs

output

inhibit

serial shiftserial shift

HH LHHH

Product data sheet Rev. 1 — 25 September 2013 6 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly with 8 mW/K above 70 C.

[3] Ptot derates linearly with 5.5 mW/K above 60 C.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI>V

CC +0.5V [1] -20 mA

IOK output clamping current VO < 0.5 V or VO>V

CC +0.5V [1] -20 mA

IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA

ICC supply current - 50 mA

IGND ground current 50 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb = 40 C to +125 C

SO16 package [2] - 500 mW

TSSOP16 package [3] - 500 mW

Product data sheet Rev. 1 — 25 September 2013 7 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating con ditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC166-Q100 74HCT166-Q100 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0- V

CC V

VOoutput voltage 0 - VCC 0- V

CC V

Tamb ambient temperature 40 - +125 40 - +125 C

t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V--83---ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC166-Q100

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.3 5 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =6.0V --0.1 - 1- 1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =6.0V --8.0- 80 - 160A

Product data sheet Rev. 1 — 25 September 2013 8 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

CIinput

capacitance -3.5-- - - - pF

74HCT166-Q100

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 5.2 mA; VCC = 4.5 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =4.5V --0.1 - 1- 1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =4.5V --8.0- 80 - 160A

ICC additional

supply current per input pin;

VI=V

CC 2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

Dn and DS inputs - 35 126 - 157.5 - 171.5 A

CP and CE inputs - 80 288 - 360 - 392 A

MR input - 40 144 - 180 - 196 A

PE input - 60 216 - 270 - 294 A

CIinput

capacitance -3.5-- - - - pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 1 — 25 September 2013 9 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC166-Q100

tpd propagation

delay CP to Q7; see Figure 7 [1]

VCC = 2.0 V - 50 150 - 190 - 225 ns

VCC = 4.5 V - 18 30 - 38 - 45 ns

VCC = 5.0 V; CL=15pF - 15 - - - - - ns

VCC = 6.0 V - 14 26 - 33 - 38 ns

MR to Q7; see Figure 8

VCC = 2.0 V - 47 160 - 200 - 240 ns

VCC = 4.5 V - 17 32 - 40 - 48 ns

VCC = 5.0 V; CL=15pF - 14 - - - - - ns

VCC = 6.0 V - 14 27 - 34 - 41 ns

tttransition

time output; see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

tWpulse width CP input HIGH or LOW;

see Figure 7

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

MR input LOW; see Figure 8

VCC = 2.0 V 100 25 - 125 - 150 - ns

VCC = 4.5 V 20 9 - 25 - 30 - ns

VCC = 6.0 V 17 7 - 21 - 26 - ns

trec recovery time MR to CP; see Figure 8

VCC = 2.0 V 0 19 - 0 - 0 - ns

VCC = 4.5 V 0 7- 0 - 0 - ns

VCC = 6.0 V 0 6- 0 - 0 - ns

tsu set-up time Dn, CE to CP; see Figure 9

VCC = 2.0 V 80 14 - 100 - 120 - ns

VCC = 4.5 V 16 5 - 20 - 24 - ns

VCC = 6.0 V 14 4 - 17 - 20 - ns

PE to CP; see Figure 9

VCC = 2.0 V 100 33 - 125 - 150 - ns

VCC = 4.5 V 20 12 - 25 - 30 - ns

VCC = 6.0 V 17 10 - 21 - 26 - ns

Product data sheet Rev. 1 — 25 September 2013 10 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

thhold time Dn, CE to CP; see Figure 9

VCC = 2.0 V 2 8- 2 - 2 - ns

VCC = 4.5 V 2 3- 2 - 2 - ns

VCC = 6.0 V 2 2- 2 - 2 - ns

PE to CP; see Figure 9

VCC = 2.0 V 0 28 - 0 - 0 - ns

VCC = 4.5 V 0 10 - 0 - 0 - ns

VCC = 6.0 V 0 8- 0 - 0 - ns

fmax maximum

frequency CP input; see Figure 7

VCC = 2.0 V 6 19 - 4.8 - 4 - MHz

VCC = 4.5 V 30 57 - 24 - 20 - MHz

VCC = 5.0 V; CL=15pF-63---- - MHz

VCC = 6.0 V 35 68 - 28 - 24 - MHz

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

[3] -41---- - pF

74HCT166-Q100

tpd propagation

delay CP to Q7; see Figure 7 [1]

VCC = 4.5 V - 23 40 - 50 - 60 ns

VCC = 5.0 V; CL=15pF - 20 - - - - - ns

MR to Q7; see Figure 8

VCC = 4.5 V - 22 40 - 50 - 60 ns

VCC = 5.0 V; CL=15pF - 19 - - - - - ns

tttransition

time output; see Figure 7 [2]

VCC = 4.5 V - 7 15 - 19 - 22 ns

tWpulse width CP input HIGH or LOW;

see Figure 7

VCC = 4.5 V 20 9 - 25 - 30 - ns

MR input LOW; see Figure 8

VCC = 4.5 V 25 11 - 31 - 38 - ns

trec recovery time MR to CP; see Figure 8

VCC = 4.5 V 0 7- 0 - 0 - ns

tsu set-up time Dn, CE to CP; see Figure 9

VCC = 4.5 V 16 8 - 20 - 24 - ns

PE to CP; see Figure 9

VCC = 4.5 V 30 15 - 38 - 45 - ns

thhold time Dn, CE to CP; see Figure 9

VCC = 4.5 V 0 3- 0 - 0 - ns

PE to CP; see Figure 9

VCC = 4.5 V 0 13 - 0 - 0 - ns

Table 7. Dynamic characteristics …continued

GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 1 — 25 September 2013 11 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

 (CL  VCC2  fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

11. Waveforms

fmax maximum

frequency CP input; see Figure 7

VCC = 4.5 V 25 45 - 20 - 17 - MHz

VCC = 5.0 V; CL=15pF-50---- - MHz

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

[3] -41---- - pF

Table 7. Dynamic characteristics …continued

GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum

frequency

aaa-008821

CP input

Q7 output

90 %

10 % 10 %

90 %

GND

VOH

VOL

tPHL tPLH

tTLH

tTHL

1/f

max

Product data sheet Rev. 1 — 25 September 2013 12 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Maste r reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.

aaa-008822

Q7 output

PHL

MR input V

GND

rec

GND

CP input

The shaded areas indicate when the input is permitted to change for predictable output performance

Measurement points are given in Table 8.

(1) CE may change only from HIGH-to-LOW while CP is LOW

Fig 9. Set-u p and hold times

aaa-008823

GND

see note (1)

CE input

PE input

Dn input VM

DS input

stable

CP input

condition: MR = HIGH

stable

tsu tsu tsu

tsu

thtW

tsu

Product data sheet Rev. 1 — 25 September 2013 13 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Table 8. Measurement points

Type Input Output

VIVMVM

74HC166-Q100 VCC 0.5VCC 0.5VCC

74HCT166-Q100 3 V 1.3 V 1.3 V

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig 10. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

VIVO

RLS1

open

Table 9. Test da ta

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC166-Q100 VCC 6ns 15pF, 50 pF 1kopen

74HCT166-Q100 3 V 6 ns 15 pF, 50 pF 1 kopen

Product data sheet Rev. 1 — 25 September 2013 14 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

12. Package outline

Fig 11. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 1 — 25 September 2013 15 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Fig 12. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 1 — 25 September 2013 16 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

13. Abbreviations

14. Revision history

Table 10. Abbr eviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT166_Q10 0 v.1 20130925 Product data sheet - -

Product data sheet Rev. 1 — 25 September 2013 17 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond tho se described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, lif e-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains dat a from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 1 — 25 September 2013 18 of 19

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a docume nt is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 September 2013

Document identi fier: 74HC_HCT166_Q100

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Recommended operating conditions. . . . . . . . 7

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16 Contact information. . . . . . . . . . . . . . . . . . . . . 18

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19