CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBLTM Architecture Functional Description[1] Features * Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Byte Write capability * 128K x 36 common I/O architecture * 3.3V power supply (VDD) * 2.5V/3.3V I/O power supply (VDDQ) The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device) * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Asynchronous output enable (OE) * Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package * Burst Capability--linear or interleaved burst order Write operations are controlled by the four Byte Write Select (BW[A:D]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. * "ZZ" Sleep mode option Logic Block Diagram A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWA BWB BWC BWD WRITE DRIVERS MEMORY ARRAY A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ E O U T P U T D A T A S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs DQPA DQPB DQPC DQPD E E READ LOGIC SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05524 Rev. *F * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 5, 2006 CY7C1350G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 4.5 ns Maximum Operating Current 325 265 240 225 205 mA Maximum CMOS Standby Current 40 40 40 40 40 mA Pin Configurations VSS CLK WE CEN OE ADV/LD 91 90 89 88 87 86 85 A VDD 92 A CE3 93 81 BWA 94 82 BWB 95 NC/9M BWC 96 83 BWD 97 NC/18M CE2 98 84 A CE1 99 A 1 80 DQC 2 79 DQB DQC 3 78 DQB VDDQ 4 77 VDDQ VSS 5 76 VSS DQC 6 75 DQB DQC 7 74 DQB DQC 8 73 DQB DQC 9 72 DQB VSS 10 71 VSS VDDQ 11 70 VDDQ DQC 12 69 DQB DQC 13 68 DQB NC 14 67 VSS VDD 15 66 NC NC 16 65 VSS 17 64 VDD ZZ DQD 18 63 DQA DQD 19 62 DQA VDDQ 20 61 VDDQ VSS 21 60 VSS DQD 22 59 DQA DQD 23 58 DQA DQD 24 57 DQA DQD 25 56 DQA VSS 26 55 VSS VDDQ 27 54 VDDQ DQD 28 53 DQA DQD 29 52 DQA DQPD 30 51 DQPA Document #: 38-05524 Rev. *F 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A A1 A0 NC/288M NC/144M VSS VDD NC/72M NC/36M A A A A A A A CY7C1350G A MODE 31 BYTE D DQPC A BYTE C 100 100-Pin TQFP Pinout DQPB BYTE B BYTE A Page 2 of 15 CY7C1350G Pin Configurations (continued) 119-Ball BGA Pinout A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ A A NC/18M A A VDDQ NC/576M CE2 A A A DQPC A VSS A VSS CE3 A DQPB NC NC/1G DQC ADV/LD VDD NC NC DQB DQC DQC VSS CE1 VSS DQB DQB VDDQ DQC VSS OE VSS DQB VDDQ DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS VSS VSS NC/9M BWB VSS VSS VSS DQB DQB VDD DQA DQB DQB VDDQ DQA DQD VDDQ DQD DQD BWD VSS BWA VSS DQA DQA DQA VDDQ DQD DQD VSS CEN A1 VSS DQA DQA DQD DQPD VSS A0 VSS DQPA DQA NC/144M A MODE VDD NC A NC/288M NC NC/72M A A A NC/36M ZZ VDDQ NC NC NC NC NC VDDQ WE VDD CLK NC Pin Definitions Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BW[A:D] InputSynchronous Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Document #: 38-05524 Rev. *F Page 3 of 15 CY7C1350G Pin Definitions (continued) Name I/O Description ZZ InputAsynchronous ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin has an internal pull-down. DQs I/OSynchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQP[A:D] I/OSynchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:D] is controlled by BW[A:D] correspondingly. MODE VDD VDDQ VSS Input Strap pin Power Supply Mode Input. Selects the burst order of the device. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. Ground NC Ground for the device. No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address expansion pins in this device and will be used as address pins in their respective densities. Functional Overview The CY7C1350G is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:D] can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core Document #: 38-05524 Rev. *F and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus, provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. Page 4 of 15 CY7C1350G On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:D]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQs and DQP[A:D] (or a subset for Byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW[A:D] signals. The CY7C1350G provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW[A:D]) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1350G is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:D] inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQP[A:D] are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:D] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) Second Address A1, A0 01 00 11 10 First Address A1, A0 00 01 10 11 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) Second Address A1, A0 01 10 11 00 First Address A1, A0 00 01 10 11 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Truth Table[2, 3, 4, 5, 6, 7, 8] CE ZZ ADV/LD CLK DQ Deselect Cycle Operation None Address Used H L L WE BWx OE CEN X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) Notes: 2. X ="Don't Care." H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 3. Write is defined by BWX, and WE. See Write Cycle Descriptions table. 4. When a write cycle is detected, all DQs are tri-stated, even during byte writes. 5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the DQs in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tri-state when OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active. Document #: 38-05524 Rev. *F Page 5 of 15 CY7C1350G Truth Table[2, 3, 4, 5, 6, 7, 8] (continued) CE ZZ ADV/LD CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H -- SNOOZE MODE None X H X X X X X X Tri-State Operation Address Used WE BWx OE CEN Partial Truth Table for Read/Write[2, 3, 9] Function WE BWD BWC BWB BWA Read H X X X X Write - No bytes written L H H H H Write Byte A - (DQA and DQPA) L H H H L Write Byte B - (DQB and DQPB) L H H L H Write Bytes A, B L H H L L Write Byte C - (DQC and DQPC) L H L H H Write Bytes C,A L H L H L Write Bytes C, B L H L L H Write Bytes C, B, A L H L L L Write Byte D - (DQD and DQPD) L L H H H Write Bytes D, A L L H H L Write Bytes D, B L L H L H Write Bytes D, B, A L L H L L Write Bytes D, C L L L H H Write Bytes D, C, A L L L H L Write Bytes D, C, B L L L L H Write All Bytes L L L L L ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD - 0.2V tZZS Device operation to ZZ ZZ > VDD - 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to snooze current This parameter is sampled tRZZI ZZ inactive to exit snooze current This parameter is sampled Min. Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done on which byte write is active. Document #: 38-05524 Rev. *F Page 6 of 15 CY7C1350G DC Input Voltage ....................................... -0.5V to VDD + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V Supply Voltage on VDDQ Relative to GND .......-0.5V to +VDD Range DC Voltage Applied to Outputs in tri-state ..................................................-0.5V to VDDQ + 0.5V Commercial Industrial Ambient Temperature (TA) 0C to +70C -40C to +85C VDD VDDQ 3.3V - 5% +10% 2.5V - 5% to VDD Electrical Characteristics Over the Operating Range[10, 11] Parameter Description Test Conditions Min. Max. Unit 3.135 3.6 V 2.375 VDD VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[10] VDDQ = 3.3V VIL VDDQ = 2.5V IX Input Leakage Current GND VI VDDQ except ZZ and MODE Input Current of MODE Input = VSS -30 for 3.3V I/O, IOH = -4.0 mA 2.4 for 2.5V I/O, IOH = -1.0 mA 2.0 for 3.3V I/O, IOL= 8.0 mA 0.4 V VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V Input LOW Voltage[10] VDDQ = 3.3V -0.3 0.8 V -0.3 0.7 V -5 5 A Input = VDD Input = VSS IOZ Output Leakage Current GND VI VDDQ, Output Disabled IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, Current f = fMAX = 1/tCYC Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-down Current--CMOS Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC A 5 A A -5 30 A 5 A 4-ns cycle, 250 MHz 325 mA 5-ns cycle, 200 MHz 265 mA 6-ns cycle, 166 MHz 240 mA Input = VDD ISB2 V 2.0 Input Current of ZZ ISB1 V 0.4 for 2.5V I/O, IOL=1.0 mA V V -5 7.5-ns cycle, 133 MHz 225 mA 10-ns cycle, 100MHz 205 mA 4-ns cycle, 250 MHz 120 mA 5-ns cycle, 200 MHz 110 mA 6-ns cycle, 166 MHz 100 mA 7.5-ns cycle, 133 MHz 90 mA 10-ns cycle, 100 MHz 80 mA 40 mA VDD = Max, Device Deselected, All speeds VIN 0.3V or VIN > VDDQ - 0.3V, f = 0 Notes: 10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05524 Rev. *F Page 7 of 15 CY7C1350G Electrical Characteristics Over the Operating Range[10, 11] (continued) Parameter ISB3 Description Test Conditions Automatic CE Power-Down Current--CMOS Inputs ISB4 VDD = Max, Device Deselected, or VIN 0.3V or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC Automatic CE Power-Down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 Max. Unit 4-ns cycle, 250 MHz Min. 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA 10-ns cycle, 100 MHz 65 mA All speeds 45 mA Capacitance[12] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance 100 TQFP Max. 119 BGA Max. Unit 5 5 pF TA = 25C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V 5 5 pF 5 7 pF 100 TQFP Package 119 BGA Package Unit 30.32 34.1 C/W 6.85 14.0 C/W Thermal Resistance[12] Parameter JA Description Test Conditions Thermal Resistance (Junction to Test conditions follow standard Ambient) test methods and procedures for Thermal Resistance (Junction to measuring thermal impedance, per EIA/JESD51. Case) JC AC Test Loads and Waveforms 3.3V I/O Test Load R = 317 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT Z0 = 50 10% RL = 50 90% 10% 90% GND 5 pF R = 351 1 ns 1 ns VT = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V I/O Test Load R = 1667 2.5V OUTPUT 10% RL = 50 R =1538 VT = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT Z0 = 50 (b) 1 ns 1 ns (c) Note: 12. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05524 Rev. *F Page 8 of 15 CY7C1350G Switching Characteristics Over the Operating Range[17, 18] -250 Parameter tPOWER Description [13] VDD (typical) to the first Access -200 -166 Max. -133 -100 Min. Max. Min. Max. Min. Min. Max. Min. Max. Unit 1 1 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 10 ns tCH Clock HIGH 1.7 2.0 2.5 3.0 3.5 ns tCL Clock LOW 1.7 2.0 2.5 3.0 3.5 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [14, 15, 16] 2.6 1.0 2.8 1.0 1.5 1.5 1.5 ns Clock to High-Z[14, 15, 16] 2.6 2.8 3.5 4.0 4.5 ns tOEV OE LOW to Output Valid 2.6 2.8 3.5 4.0 4.5 ns tOEHZ OE HIGH to Output 16] 0 High-Z[14, 15, 0 2.6 0 ns Clock to Low-Z OE LOW to Output 0 4.5 tCHZ tOELZ 0 4.0 tCLZ Low-Z[14, 15, 16] 0 3.5 0 2.8 0 0 3.5 ns 0 4.0 ns 4.5 ns Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tALS ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tWES GW, BWX Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tCENS CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 0.5 ns tWEH GW, BWX Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns tCENH CEN Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns Hold Times Notes: 13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated. 14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve tri-state prior to Low-Z under the same system conditions. 16. This parameter is sampled and not 100% tested. 17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 18. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05524 Rev. *F Page 9 of 15 CY7C1350G Switching Waveforms Read/Write Timing[19, 20, 21] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BW[A:D] A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON'T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 19. For this waveform ZZ is tied LOW. 20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05524 Rev. *F Page 10 of 15 CY7C1350G Switching Waveforms (continued) NOP, STALL, and DESELECT Cycles[19, 20, 22] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW[A:D] ADDRESS A5 tCHZ D(A1) Data In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) DON'T CARE Q(A2) D(A4) Q(A3) WRITE D(A4) STALL NOP READ Q(A5) Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[23, 24] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON'T CARE Notes: 22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. 23. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 24. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05524 Rev. *F Page 11 of 15 CY7C1350G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 100 Ordering Code 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1350G-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-166BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1350G-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Document #: 38-05524 Rev. *F Industrial Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-250AXI CY7C1350G-250BGXI Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-250AXC CY7C1350G-250BGXC Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-200AXI CY7C1350G-200BGXI 250 Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-200AXC CY7C1350G-200BGXC Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-166AXI CY7C1350G-166BGXI 200 Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-166AXC CY7C1350G-166BGXC Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-133AXI CY7C1350G-133BGXI Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-133AXC CY7C1350G-133BGXC Operating Range 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1350G-100BGI CY7C1350G-100BGXI 166 Package Type CY7C1350G-100AXC CY7C1350G-100BGXC 133 Package Diagram Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free Page 12 of 15 CY7C1350G Package Diagrams 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.000.20 1.400.05 14.000.10 81 100 80 1 20.000.10 22.000.20 0.300.08 0.65 TYP. 30 121 (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0 MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0-7 R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.600.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05524 Rev. *F A Page 13 of 15 CY7C1350G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) O0.05 M C O0.25 M C A B A1 CORNER O0.750.15(119X) O1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.000.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30 TYP. 14.000.20 0.15(4X) 0.15 C 2.40 MAX. B 0.900.05 0.25 C 12.00 51-85115-*B C 600.10 0.56 SEATING PLANE ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05524 Rev. *F Page 14 of 15 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1350G Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBLTM Architecture Document Number: 38-05524 REV. Issue ECN NO. Date Orig. of Change Description of Change ** 224380 See ECN RKF New data sheet *A 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section Added comment of BG lead-free package availability *B 332895 See ECN SYT Converted from Preliminary to Final Removed 225 MHz and 100 MHz speed grades Address Expansion balls in the pinouts for 119 BGA Package was modified as per JEDEC standards Modified VOL, VOH test conditions Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead-free package Updated Ordering Information by removing Shaded Parts *C 351194 See ECN PCI Updated Ordering Information Table *D 419264 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Modified test condition from VDDQ < VDD to VDDQ < VDD Modified test condition from VIH < VDD to VIH < VDD Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information *E 419705 See ECN RXU Added 100 MHz speed grade *F 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. Document #: 38-05524 Rev. *F Page 15 of 15