1
LTC1878
■
High Efficiency: Up to 95%
■
Very Low Quiescent Current: Only 10
µ
A
During Operation
■
600mA Output Current at V
IN
= 3.3V
■
2.65V to 6V Input Voltage Range
■
550kHz Constant Frequency Operation
■
Synchronizable from 400kHz to 700kHz
■
Selectable Burst Mode
TM
Operation or
Pulse Skipping Mode
■
No Schottky Diode Required
■
Low Dropout Operation: 100% Duty Cycle
■
0.8V Reference Allows Low Output Voltages
■
Shutdown Mode Draws < 1µA Supply Current
■
±2% Output Voltage Accuracy
■
Current Mode Control for Excellent Line and
Load Transient Response
■
Overcurrent and Overtemperature Protected
■
Available in 8-Lead MSOP Package
The LTC
®
1878 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 10µA and drops to < 1µA in shutdown. The 2.65V to
6V input voltage range makes the LTC1878 ideally suited
for single Li-Ion battery-powered applications. 100% duty
cycle provides low dropout operation, extending battery
life in portable systems.
Switching frequency is internally set at 550kHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC1878 can be
externally synchronized from 400kHz to 700kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low, preventing low
frequency ripple from interfering with audio circuitry.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feed-
back reference voltage. The LTC1878 is available in a
space saving 8-lead MSOP package.
For higher input voltage (11V abs max) applications, refer
to the LTC1877 data sheet.
■
Cellular Telephones
■
Wireless Modems
■
Personal Information Appliances
■
Portable Instruments
■
Distributed Power Systems
■
Battery-Powered Equipment
High Efficiency Step-Down Converter
High Efficiency
Monolithic Synchronous
Step-Down Regulator
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
Efficiency vs Output Load Current
47µF***
7
6
1
2
5
3
4
SW
V
FB
LTC1878
GND
10µH*
22µF**
CER
220pF
V
OUT
†
3.3V
*
**
***
†
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
SANYO POSCAP 6TPA47M
V
OUT
CONNECTED TO V
IN
FOR 2.65V < V
IN
< 3.3V
887k
20pF
280k
1878 TA01
SYNC
V
IN
RUN
I
TH
V
IN
2.65V
TO 6V
+
OUTPUT CURRENT (mA)
80
75
EFFICIENCY (%)
85
90
95
100
0.1 10 100 1000
1878 TA02
70 1
VIN = 6V
VIN = 4.2V
VIN = 3.6V
Burst Mode OPERATION
VOUT = 3.3V
L = 10µH
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
2
LTC1878
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
VFB
Feedback Current (Note 4) ●430 nA
V
FB
Regulated Output Voltage (Note 4) 0°C ≤ T
A
≤ 85°C 0.784 0.8 0.816 V
(Note 4) –40°C ≤ T
A
≤ 85°C●0.74 0.8 0.84 V
∆V
OVL
Output Overvoltage Lockout ∆V
OVL
= V
OVL
– V
FB
●20 50 110 mV
∆V
FB
Reference Voltage Line Regulation V
IN
= 2.65V to 6V (Note 4) 0.05 0.2 %/V
V
LOADREG
Output Voltage Load Regulation Measured in Servo Loop; V
ITH
= 0.9V to 1.2V ● 0.1 0.5 %
Measured in Servo Loop; V
ITH
= 1.6V to 1.2V ●–0.1 –0.5 %
V
IN
Input Voltage Range ●2.65 6 V
I
Q
Input DC Bias Current (Note 5)
Pulse Skipping Mode 2.65V < V
IN
< 6V, V
SYNC/MODE
= 0V, I
OUT
= 0A 230 350 µA
Burst Mode Operation V
SYNC/MODE
= V
IN
, I
OUT
= 0A 10 15 µA
Shutdown V
RUN
= 0V, V
IN
= 6V 0 1 µA
f
OSC
Oscillator Frequency V
FB
= 0.8V 495 550 605 kHz
V
FB
= 0V 80 kHz
f
SYNC
SYNC Capture Range 400 700 kHz
I
PLL LPF
Phase Detector Output Current
Sinking Capability f
PLLIN
< f
OSC
● 3 10 20 µA
Sourcing Capability f
PLLIN
> f
OSC
●–3 –10 –20 µA
R
PFET
R
DS(ON)
of P-Channel MOSFET I
SW
= 100mA 0.5 0.7 Ω
R
NFET
R
DS(ON)
of N-Channel MOSFET I
SW
= –100mA 0.6 0.8 Ω
LTC1878EMS8
T
JMAX
= 125°C, θ
JA
= 150°C/W
ORDER PART
NUMBER
(Note 1)
Input Supply Voltage (V
IN
)...........................–0.3V to 7V
I
TH
, PLL LPF Voltage ................................–0.3V to 2.7V
RUN, V
FB
Voltages ......................................–0.3V to V
IN
SYNC/MODE Voltage ..................................–0.3V to V
IN
SW Voltage ...................................–0.3V to (V
IN
+ 0.3V)
P-Channel MOSFET Source Current (DC) ........... 800mA
N-Channel MOSFET Sink Current (DC) ............... 800mA
Peak SW Sink and Source Current ........................ 1.5A
Operating Ambient Temperature Range
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
1
2
3
4
8
7
6
5
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
PLL LPF
SYNC/MODE
V
IN
SW
RUN
I
TH
V
FB
GND
MS8 PART MARKING
Consult factory for Industrial and Military grade parts.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
LTNX
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
3
LTC1878
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1878E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1878EMS8: T
J
= T
A
+ (P
D
)(150°C/W)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
PK
Peak Inductor Current V
IN
= 3.3V, V
FB
= 0.7V, Duty Cycle < 35% 0.8 1.0 1.25 A
I
LSW
SW Leakage V
RUN
= 0V, V
SW
= 0V or 6V, V
IN
= 6V ±0.01 ±1µA
V
SYNC/MODE
SYNC/MODE Threshold V
SYNC/MODE
Rising ●0.3 1.0 1.5 V
I
SYNC/MODE
SYNC/MODE Leakage Current ±0.01 ±1µA
V
RUN
RUN Threshold V
RUN
Rising ●0.3 0.7 1.5 V
I
RUN
RUN Input Current ±0.01 ±1µA
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
Note 4: The LTC1878 is tested in a feedback loop which servos V
FB
to the
balance point for the error amplifier (V
ITH
= 1.2V).
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Input Voltage
INPUT VOLTAGE (V)
2
EFFICIENCY (%)
75
80
85
57
1878 G01
70
65
60 34 6
90
95
100
8
Burst Mode OPERATION
V
OUT
= 2.5V
L = 10µH
I
LOAD
= 100mA I
LOAD
= 10mA
I
LOAD
= 1mA
I
LOAD
= 300mA
I
LOAD
= 0.1mA
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.1 10 100 1000
1878 G02
01
V
IN
= 3.6V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 4.2V
PULSE SKIPPING MODE
Burst Mode OPERATION
V
OUT
= 1.8V
L = 10µH
OUTPUT CURRENT (mA)
60
EFFICIENCY (%)
70
75
85
95
0.1 10 100 1000
1878 G03
50 1
80
65
55
90 L = 15µH
L = 10µH
Burst Mode OPERATION
V
IN
= 6V
V
OUT
= 2.5V
Efficiency vs Output Current Efficiency vs Output Current
4
LTC1878
Reference Voltage
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Oscillator Frequency
vs Temperature
Efficiency vs Output Current
OUTPUT CURRENT (mA)
75
EFFICIENCY (%)
85
95
70
80
90
0.1 10 100 1000
1878 G04
65 1
V
IN
= 3V
V
IN
= 6V
V
IN
= 3.6V
V
IN
= 4.2V
V
OUT
= 1.8V
L = 10µH
TEMPERATURE (°C)
–50
REFERENCE VOLTAGE (V)
0.814
0.809
0.804
0.799
0.794
0.789
0.784 25 75
1878 G05
–25 0 50 100 125
VIN = 3.6V
TEMPERATURE (°C)
–50
FREQUENCY (kHz)
605
595
585
575
565
555
545
535
525
515
505
495 10075
1878 G06
–25 05025 125
VIN = 3.6V
Oscillator Frequency
vs Supply Voltage
SUPPLY VOLTAGE (V)
0
OSCILLATOR FREQUENCY (kHz)
545
535
525
565
555
8
1878 G07
515
505
495 246
605
595
585
575
LOAD CURRENT (mA)
0
1.77
OUTPUT VOLTAGE (V)
1.78
1.80
1.81
1.82
200 400 500 900
1878 G08
1.79
100 300 600 700 800
1.83
PULSE SKIPPING MODE
V
IN
= 3.6V
L = 10µH
INPUT VOLTAGE (V)
10
R
DS(ON)
(Ω)
0.5
0.6
0.7
5678
1878 G09
0.4
0.3
0
0.1
234
0.2
0.9
0.8
SYNCHRONOUS
SWITCH
MAIN
SWITCH
Reference Voltage
vs Temperature
Output Voltage vs Load Current RDS(ON) vs Input Voltage
RDS(ON) vs Temperature DC Supply Current
vs Input Voltage DC Supply Current
vs Temperature
TEMPERATURE (°C)
–50 –25
0.3
R
DS(ON)
(Ω)
0.4
0.6
0.7
0.8
75 100
1.2
1878 G10
0.5
0 25 50 125
0.9
1.0
1.1
V
IN
= 3V
V
IN
= 5V
SYNCHRONOUS SWITCH
MAIN SWITCH
INPUT VOLTAGE (V)
01
0
DC SUPPLY CURRENT (µA)
100
250
245
1878 G11
50
200
150
367
V
OUT
= 1.8V
PULSE SKIPPING
MODE
Burst Mode
OPERATION
TEMPERATURE (°C)
–50
300
250
200
150
100
50
025 75
1878 G12
–25 0 50 125100
SUPPLY CURRENT (µA)
PULSE SKIPPING
MODE
Burst Mode
OPERATION
V
IN
= 3.6V
5
LTC1878
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Switch Leakage vs Temperature
TEMPERATURE (°C)
–50
SWITCH LEAKAGE (µA)
25
1878 G13
2.0
1.0
–25 0 50
0.5
0
2.5
1.5
75 100 125
MAIN
SWITCH
V
IN
= 7V
RUN = 0V
SYNCHRONOUS
SWITCH
10µs/DIV
V
IN
= 4.2V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 50mA
SW
5V/DIV
I
L
200mA/DIV
V
OUT
50mV/DIV
AC
COUPLED
1878 G14
Burst Mode OperationSwitch Leakage vs Input Voltage
INPUT VOLTAGE (V)
0
0
SWITCH LEAKAGE (nA)
0.2
0.4
0.6
0.8
2468
1878 G20
1.0
1.2
1357
SYNCHRONOUS
SWITCH
MAIN
SWITCH
RUN = 0V
Pulse Skipping Mode Operation
1µs/DIV
V
IN
= 4.2V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 50mA
SW
5V/DIV
I
L
200mA/DIV
V
OUT
20mV/DIV
AC
COUPLED
1878 G15
40µs/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 500mA
RUN
2V/DIV
I
L
500mA/DIV
V
OUT
1V/DIV
1878 G16
40µs/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 200mA TO 500mA
PULSE SKIPPING MODE
V
OUT
50mV/DIV
AC
COUPLED
I
L
500mA/DIV
I
TH
1V/DIV
1878 G17
Start-Up from Shutdown Load Step Response
Load Step Response
40µs/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 50mA TO 500mA
PULSE SKIPPING MODE
V
OUT
100mV/DIV
AC
COUPLED
I
L
500mA/DIV
I
TH
1V/DIV
1878 G18
Load Step Response
40µs/DIV
V
IN
= 3.6V
V
OUT
= 1.5V
L = 10µH
C
IN
= 22µF
C
OUT
= 47µF
I
LOAD
= 50mA TO 500mA
Burst Mode OPERATION
V
OUT
100mV/DIV
AC
COUPLED
I
L
500mA/DIV
I
TH
1V/DIV
1878 G19
6
LTC1878
+
–
+
–
+
–
+
–
+
–
OVDET
EA
+
–
I
RCMP
+–
I
COMP
8
7
3
1
RUN
PLL LPF
VCO
XYY = “0” ONLY WHEN X IS A CONSTANT “1”
BURST
DEFEAT
SLOPE
COMP
OSC
SYNC/MODE
0.6V
FREQ
SHIFT
V
REF
0.8V
0.85V
Ω
g
m
= 0.5m
0.8V REF
SHUTDOWN
0.55V
0.8V
SLEEP
V
IN
V
IN
V
IN
V
IN
I
TH
SLEEP
V
FB
EN
BURST
V
IN
2
S
R
RS LATCH SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI-
SHOOT-
THRU
Q
Q
6Ω
6
SW
5
GND
1878 BD
4
FU CTIO AL DIAGRA
UU
W
RUN (Pin 1): Run Control Input. Forcing this pin below
0.4V shuts down the LTC1878. In shutdown all functions
are disabled drawing <1µA supply current. Forcing this
pin above 1.2V enables the LTC1878. Do not leave RUN
floating.
I
TH
(Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.5V
to 1.9V.
V
FB
(Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
GND (Pin 4): Ground Pin.
SW (Pin 5): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
V
IN
(Pin 6): Main Supply Pin. Must be closely decoupled
to GND, Pin 4.
SYNC/MODE (Pin 7): External Clock Synchronization and
Mode Select Input. To synchronize with an external clock,
apply a clock with a frequency between 400kHz and
700kHz. To select Burst Mode operation, tie to V
IN
. Ground-
ing this pin selects pulse skipping mode. Do not leave this
pin floating.
PLL LPF (Pin 8): Output of the Phase Detector and Control
Input of Oscillator. Connect a series RC lowpass network
from this pin to ground if externally synchronized. If
unused, this pin may be left open.
UU
U
PI FU CTIO S
7
LTC1878
OPERATIO
U
Main Control Loop
The LTC1878 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current com-
parator, I
COMP
, resets the RS latch. The peak inductor
current at which I
COMP
resets the RS latch is controlled by
the voltage on the I
TH
pin, which is the output of error
amplifier EA. The V
FB
pin, described in the Pin Functions
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases, it causes a slight decrease in the feedback
voltage relative to the 0.8V reference, which in turn,
causes the I
TH
voltage to increase until the average induc-
tor current matches the new load current. While the top
MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse as indicated by
the current reversal comparator I
RCMP
, or the beginning of
the next clock cycle.
Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC1878 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V
IN
or connect it to a logic high
(V
SYNC/MODE
> 1.5V). To disable Burst Mode operation and
enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The ad-
vantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I
TH
pin indicates a lower
value. The voltage at the I
TH
pin drops when the inductor’s
average current is greater than the load requirement. As
the I
TH
voltage drops below approximately 0.55V, the
BURST comparator trips, causing the internal sleep line to
go high and forces off both power MOSFETs. The I
TH
pin
is then disconnected from the output of the EA amplifier
and parked a diode voltage above ground.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10µA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the I
TH
pin reconnects to
the output of the EA amplifier and the top MOSFET is again
turned on and this process repeats.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has ample time to decay, thereby pre-
venting runaway. The oscillator’s frequency will progres-
sively increase to 550kHz (or the synchronized frequency)
when V
FB
rises above 0.3V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1878 to
allow the internal oscillator to be synchronized to an
external source connected to the SYNC/MODE pin. The
output of the phase detector at the PLL LPF pin operates
over a 0V to 2.4V range corresponding to 400kHz to
700kHz. When locked, the PLL aligns the turn-on of the top
MOSFET to the rising edge of the synchronizing signal.
When the LTC1878 is clocked by an external source, Burst
Mode operation is disabled; the LTC1878 then operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, current comparator I
COMP
may remain
tripped for several cycles and force the main switch to stay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while provid-
ing reasonable low current efficiency.
Frequency synchronization is inhibited when the feedback
voltage V
FB
is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
8
LTC1878
INPUT VOLTAGE (V)
2.5
0
MAX OUTPUT CURRENT (mA)
200
400
600
800
1200
3.5 4.5 5.5 6.5
1878 F01
7.5
1000
VOUT = 1.5V
VOUT = 3.3V
VOUT = 2.5V
L = 10µH
Figure 1. Maximum Output Current vs Input Voltage Figure 2. Maximum Inductor Peak Current vs Duty Cycle
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Low Supply Operation
The LTC1878 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 1
shows the reduction in the maximum output current as a
function of input voltage for various output voltages.
Another important detail to remember is that at low input
supply voltages, the R
DS(ON)
of the P-channel switch
increases. Therefore, the user should calculate the power
dissipation when the LTC1878 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. As a result, the
maximum inductor peak current is reduced for duty cycles
>40%. This is shown in the decrease of the inductor peak
current as a function of duty cycle graph in Figure 2.
DUTY CYCLE (%)
0
MAXIMUM INDUCTOR PEAK CURRENT (mA)
1100
1000
900
800
700
600 80
1878 F02
20 40 60 100
V
IN
= 3.3V
OPERATIO
U
APPLICATIO S I FOR ATIO
WUUU
The basic LTC1878 application circuit is shown on the first
page. External component selection is driven by the load
requirement and begins with the selection of L followed by
C
IN
and C
OUT
.
Inductor Value Calculation
The inductor selection will depend on the operating fre-
quency of the LTC1878. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper-
ating at a higher frequency generally results in lower
efficiency because of increased internal gate charge losses.
The inductor value has a direct effect on ripple current. The
ripple current ∆I
L
decreases with higher inductance or
frequency and increases with higher V
IN
or V
OUT
.
9
LTC1878
Kool Mµ is a registered trademark of Magnetics, Inc.
∆=
()()
−
IfLVV
V
L OUT OUT
IN
11
(1)
Accepting larger values of ∆I
L
allows the use of low
inductance, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆I
L
= 0.4(I
MAX
).
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
250mA. Lower inductor values (higher ∆I
L
) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ
®
cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids with a “soft” saturation character-
istic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire, while inductors
wound on bobbins are generally easier to surface mount.
APPLICATIO S I FOR ATIO
WUUU
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Dale and Sumida.
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
CI
VVV
V
IN OMAX OUT IN OUT
IN
required I
RMS
≅−
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ∆V
OUT
is determined by:
∆≅∆ +
V I ESR fC
OUT L OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and ∆I
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆I
L
increases
with input voltage. For the LTC1878, the general rule for
proper operation is:
C
OUT
required ESR < 0.25Ω
The choice of using a smaller output capacitance
increases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple
voltage. The ITH pin compensation components can be
10
LTC1878
opti
mized to provide stable high performance transient
response regardless of the output capacitor selected.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic chip capacitor
available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
available in case heights ranging from 2mm to 4mm. Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
R
OUT =+
08 1 2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the har-
monics of the V
CO
center frequency. The PLL hold-in range
∆f
H
is equal to the capture range, ∆f
H
= ∆f
C
= ±150kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.
APPLICATIO S I FOR ATIO
WUUU
V
FB
GND
LTC1878
0.8V ≤ V
OUT
≤ 6V
R2
R1
1878 F03
Figure 3. Setting the LTC1878 Output Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC1878 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 400kHz to 700kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the
Figure 5. Phase-Locked Loop Block Diagram
SYNC/
MODE
PHASE
DETECTOR
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R
LP
C
LP
VCO
1878 F05
PLL LPF
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
00.4 0.8 1.2 1.6 2.0
800
700
600
500
400
300
OSCILLATOR FREQUENCY (kHz)
V
PLL LPF
(V)
1878 F04
If the external frequency (V
SYNC/MODE
) is greater than
550kHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 550kHz, current is sunk
continuously, pulling down the PLL LPF pin. If the
11
LTC1878
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
LOAD CURRENT (mA)
0.1 1
0.00001
POWER LOST (W)
0.001
1
10 100 1000
1878 F06
0.0001
0.01
0.1 VOUT = 1.5V
VOUT = 2.5V
VOUT = 3.3V
VIN = 4.2V
L = 10µH
Burst Mode OPERATION
Figure 6. Power Lost vs Load Current
APPLICATIO S I FOR ATIO
WUUU
external and internal frequencies are the same but exhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla-
tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components C
LP
and R
LP
smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V
PLL LPF
pin.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1878 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
12
LTC1878
Thermal Considerations
In most applications the LTC1878 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1878 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC1878 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and q
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC1878 in dropout at an
input voltage of 3V, a load current of 500mA, and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.7Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD2
• R
DS(ON)
= 0.175W
For the MSOP package, the θ
JA
is 150°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.175)(150) = 96°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stabil-
ity problem. The internal compensation provides adequate
compensation for most applications. But if additional
compensation is required, the I
TH
pin can be used for
external compensation using R
C
, C
C1
as shown in
Figure 7. (The 220pF capacitor, C
C2
, is typically needed for
noise decoupling.)
APPLICATIO S I FOR ATIO
WUUU
–
+
RUN
I
TH
V
FB
GND
PLL LPF
SYNC/MODE
SW
LTC1878
C
C2
C
C1
R
C
C
OUT
C
IN
1878 F07
L1
V
IN
BOLD LINES INDICATE
HIGH CURRENT PATHS
1
2
3
4
8
7
6
5
OPTIONAL
+
–
+
V
OUT
R2R1
V
IN
+
Figure 7. LTC1878 Layout Diagram
13
LTC1878
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1878. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1878 signal ground consists of the resistive
divider, the optional compensation network (R
C
and
C
C1
) and C
C2
. The power ground consists of the (–)
plate of C
IN
, the (–) plate of C
OUT
and Pin 4 of the
LTC1878. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star-
ground configuration.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and signal ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node SW away from sensitive small
signal nodes.
Design Example
As a design example, assume the LTC1878 is used in a
single lithium-ion battery-powered cellular phone applica-
tion. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
LfI
VV
V
LOUT OUT
IN
=
()
∆
()
−
11
(3)
Substituting V
OUT
= 2.5V, V
IN
= 4.2V, ∆I
L
=120mA and
f = 550kHz in equation (3) gives:
LV
kHz mA
V
VH=−
=µ
25
550 120 125
42 15 3
.
()
.
..
A 15µH inductor works well for this application. For best
efficiency choose a 1A inductor with less than 0.25Ω
series resistance.
C
IN
will require an RMS current rating of at least 0.15A at
temperature and C
OUT
will require an ESR of less than
0.25Ω. In most applications, the requirements for these
capacitors are fairly similar.
For the feedback resistors, choose R1 = 412k. R2 can
then be calculated from equation (2) to be:
RVR k use
OUT
208 1 1 875 5 8=−
=
.. ; 87k
Figure 8 shows the complete circuit along with its effi-
ciency curve.
APPLICATIO S I FOR ATIO
WUUU
14
LTC1878
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example
V
OUT
2.5V
*
**
***
220pF 22µF**
CER
15µH*
887k
47µF***
412k
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
V
IN
2.65V
TO 4.2V
SUMIDA CD54-150
TAIYO-YUDEN CERAMIC JMK325BJ226MM
SANYO POSCAP 6TPA47M
1878 F08a
+
20pF
OUTPUT CURRENT (mA)
75
EFFICIENCY (%)
80
85
90
95
0.1 10 100 1000
70 1
V
OUT
= 2.5V
L = 15µH
V
IN
= 3V
V
IN
= 4.2V
V
IN
= 3.6V
1878 F08b
TYPICAL APPLICATIO S
U
VOUT
2.5V
0.6A
CIN**
22µF
CER
20pF 887k COUT**
22µF
CER
*
**
220pF
10µH*
LTC1878
RUN
ITH
VFB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
VIN
SW
VIN
3V TO 4.2V
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
1878 TA03
412k
V
OUT
1.8V
0.5A
C
IN
**
22µF
CER
20pF 887k C
OUT
**
22µF
CER
*
**
220pF
10µH*
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
V
IN
2.7V TO 6V
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
1878 TA04
698k
Single Li-Ion to 2.5V/0.6A Regulator
Using All Ceramic Capacitors
3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator
Using All Ceramic Capacitors
15
LTC1878
TYPICAL APPLICATIO S
U
V
OUT
2.5V
0.3A
C
IN
**
22µF
CER
20pF 887k C
OUT
***
47µF
6.3V
*
**
***
220pF
15µH*
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
V
IN
2.65V TO 6V
SUMIDA CD54-150
TAIYO-YUDEN CERAMIC JMK325BJ226MM
SANYO POSCAP CTPA47M
1878 TA06
412k
+
Low Noise 2.5V/0.3A Regulator
V
OUT
2.5V
0.6A
C
IN
**
22µF
CER
20pF
EXT CLOCK
700kHz
887k C
OUT
**
22µF
CER
*
**
220pF
10µH*
10k
0.01µF
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
V
IN
3V TO 6V
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
1878 TA04
412k
Externally Synchronized 2.5V/0.6A Regulator
Using All Ceramic Capacitors
3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator
Using All Ceramic Capacitors
V
OUT
†
3.3V
0.5A
C
IN
**
22µF
CER
20pF 887k C
OUT
**
22µF
CER
*
**
†
220pF
10µH*
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
V
IN
2.7V TO 6V
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
V
OUT
CONNECTED TO V
IN
FOR 2.7V < V
IN
< 3.3V
1878 TA06
280k
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LTC1878
1878f LT/TP 1000 4K • PRINTED IN USA
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LINE AR TECHNOLOGY CORPORATION 2000
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout
V
OUT
2.5V
0.6A
C
IN
**
22µF
CER
20pF 887k C
OUT
**
22µF
CER
*
**
220pF
10µH*
LTC1878
RUN
I
TH
V
FB
GND
8
7
6
5
1
2
3
4
PLL LPF
SYNC/MODE
V
IN
SW
LTC1540
GND
V
–
IN
+
IN
–
8
7
6
5
1
2
3
4
OUT
V
+
REF
HYS
V
IN
2.7V TO 4.2V
TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM
1878 TA08
412k
44.2k
1%
1.58M
1%
1.18M
1% 0.01µF
0.1µF10k
2.37M
1%
TYPICAL APPLICATIO
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
U
PACKAGE DESCRIPTIO
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021 ± 0.006
(0.53 ± 0.015)
0° – 6° TYP
SEATING
PLANE
0.007
(0.18)
0.040 ± 0.006
(1.02 ± 0.15)
0.012
(0.30)
REF
0.006 ± 0.004
(0.15 ± 0.102)
0.034 ± 0.004
(0.86 ± 0.102)
0.0256
(0.65)
BSC 12
34
0.193 ± 0.006
(4.90 ± 0.15)
8765
0.118 ± 0.004*
(3.00 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
