Product Update Errata to Z8 Encore!(R) 64K Series UP006006-0604 Z8 Encore!(R) 64K Series with Date Codes 0344 and later The errata listed in Table 1 are found in the production Z8 Encore!(R) 64K Series devices with date codes 0344 and later, where the date code is YYWW (year and week of assembly). When reviewing the following errata, it is recommended that users also download the most recent version of the Product Specification. Data contained in this document is PRELIMINARY only. Table 1. Z8 Encore! 64K Series Errata Date Coded 0344 and Later No. Summary 1 Detailed Description Read Protect Option Error: Bit may be bypassed The Read Protect (RP) Option Bit does not prevent Flash access when bypassing the Flash Controller as described in ZiLOG Application Note AN0017 entitled Third Party Flash Programming Support of the Z8 Encore!(R) MCU. User code cannot be read through the On-Chip Debugger when read protect is enabled. User code can only be read out when bypassing the Flash Controller. Work-Around: None 2 3 START, STOP and NAK bits in the I2C Control register can be cleared by software writing a 0 to these bits. Error: The START, STOP and NAK bits in the I2C Control register can be cleared by software writing a 0 to these bits. The Product Specification states that they cannot be cleared by writing a 0. Device may not complete STOP Mode Recovery initiated by a GPIO pin transition. Error: When STOP Mode Recovery (SMR) is initiated by a GPIO pin transition, multiple pin transitions within 200s (approx.) of each other may cause the device to only partially wake up from STOP mode. In this situation, the device idles in a state between STOP mode and normal operation. The crystal oscillator is oscillating, but code does not execute. Work-Around: None When stuck in this idle state, assertion of the external RESET pin does not initiate a system Reset. Work-Arounds: (1) Add external filtering to the STOP Mode Recovery pin input signal to prevent multiple transitions in less than 200s, and (2) Enable the Watch-Dog Timer (WDT) in STOP Mode to allow a WDT to complete the STOP Mode Recovery in the event the device does not successfully complete the STOP Mode Recovery initated by the GPIO pin transition. ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * Internet: www.zilog.com Errata to Z8 Encore! 64K Series Z8 Encore!(R) 64K Series with Date Codes Prior to 0344 2 The errata listed in Table 2 are found in the production Z8 Encore!(R) 64K Series devices with date codes prior to 0344, where the date code is YYWW (year and week of assembly). When reviewing the following errata, it is recommended that users also download the most recent version of the Product Specification. Data contained in this document is PRELIMINARY only. Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334 No. Summary Detailed Description 1 Error: When the CPU exits from HALT mode, it fails to reset the master Interrupt Request Enable (IRQE) bit (bit 7 of the Interrupt Control Register). When the CPU exits from HALT mode, it fails to reset the master Interrupt Request Enable (IRQE) bit. WDT interrupts cause the Program Counter (PC) and Flags to be pushed twice on the stack. The first push is the PC and Flags from where the interrupt occured. The second push is the starting address and Flags of the Interrupt Service Routine (ISR). This problem also affects exits from HALT mode caused by other interrupt sources if more than one interrupt is pending. If only a single interrupt is pending then the routine is executed normally except that interrupts are not disableda Work-Around: To mimic standard interrupt operation, the ISR should execute a Disable Interrupts (DI) instruction to reset the master Interrupt Request Enable (IRQE) bit to 0. Futher, on WDT interrupts before exiting, the ISR should add three (3) to the Stack Pointer (SP). On Normal interrupts the ISR should check the Program Counter on the stack. If the PC on the stack contains the starting address of the ISR, then the ISR should add three (3) to the Stack Pointer (SP). This problem only affects exits from HALT mode. 2 Error: System Reset latency may exceed When exiting STOP mode and after a POR/VBO reset, the System Reset specification limits. Latency is 514 WDT cycles plus 16 System Clock cycles rather than the 66 WDT cycles plus 16 System Clock cycles as specified. Workaround: None. This error is unlikely to affect system operation. 3 UART NEWFRM status bit does not function. Error: The NEWFRM status bit (Bit 2 of the UART Status 1 register) does not indicate the start of a new frame. Workaround: None. UP006006-0604 PRELIMINARY Errata to Z8 Encore! 64K Series 3 Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334 (Continued) No. Summary Detailed Description 4 Error: Setting Bit 7 (MPMD[1]) of the UART Control 1 register to 1 does not produce the desired effect of enabling the UART Address Compare and associated interrupt functionality. UART Address Compare function does not work. Workaround: Leave MPMD[1] in its reset state of 0. 5 UART Baud Rate Generator cannot be used as simple timer. Error: Setting BRGCTL (Bit 2 of the UART Control 1 register) to 1 when the UART receiver is disabled does not enable UART Baud Rate Generator interrupt. Thus, the UART Baud Rate Generator cannot be used as a simple timer. Workaound: Use one of the 4 standard Timers or the Baud Rate Generators in the SPI or I2C blocks to perform the desired timing operations. 6 Unlocking the Flash Controller allows program and erase operations on all Flash pages. Error: During the Flash Controller unlock sequence, the specification indicates that a second write to the Flash Page Select register is required (step 5 of the sequence) to unlock the Flash Controller for the selected Flash page. The Flash controller unlocks for all Flash pages after steps 1-4 of the unlock sequence are complete. Workaround: None. 7 8 Setting bits in the Flash Sector Protect register to 1 does not lock sectors. Error: Writing bits in the Flash Sector Protect register to 1 fails to prevent program and erase operations on the selected Flash memory sector. Watch-Dog Timer cannot be disabled in STOP mode. Error: The Watch-Dog Timer and its associated internal RC oscillator cannot be disabled in STOP mode. Workaround: None. Workaound: None. 9 Watch-Dog Timer oscillator frequency is out of specification. Error: The typical Watch-Dog Timer internal oscillator frequency is 50KHz rather than the currently specified 10KHz. This can result in WDT timeout values that are less than expected. Workaround: Increase the WDT reload value by a factor of 5 to compensate for the frequency error. UP006006-0604 PRELIMINARY Errata to Z8 Encore! 64K Series 4 Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334 (Continued) No. Summary Detailed Description 10 Error: Operating currents in the various mode (Normal, HALT, and STOP) may be higher than typical values. Operating currents. Workaround: None. 11 RESET pin is not fil- Error: tered. The RESET pin does not properly filter the input signal. The device may enter Reset when the RESET pin is asserted for less than the specified 4 system clock cycles (from Normal mode). Workaround: Add external filtering to the printed-circuit board. 12 Timers can not be cascaded. Error: Setting the CSC bit (Bit 4) of the the Timer Control 0 Registers does not cascade the timers as indicated by the spec. Woraround: Timers can be cascaded using the Timer Out and Timer In functions through the general-purpose I/O pins. 13 ADC generates extra interrupts Error: The ADC continues to generate interrupts in CONTINUOUS mode after the first interrupt before the results of the next conversion is complete. Workaround: Do not use CONTINUOUS mode. Use SINGLE-SHOT mode instead. UP006006-0604 PRELIMINARY Errata to Z8 Encore! 64K Series This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. (c)2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. UP006006-0604 PRELIMINARY 5