ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • Internet: www.zilog.com
Z8 Encore!
®
64K Series with Date Codes 0344 and later
The errata listed in Table 1 are found in the production Z8 Encore!
®
64K Series devices with date codes
0344 and later, where the date code is YYWW (year and week of assembly). When reviewing the follow-
ing errata, it is recommended that users also download the most recent version of the Product Specifica-
tion. Data contained in this document is PRELIMINARY only.
Table 1. Z8 Encore! 64K Series Errata Date Coded 0344 and Later
No. Summary Detailed Description
1 Read Protect Opti on
Bit may be bypassed Error:
The Read Protect (RP) Option Bit does not prevent Flash access when
bypassing the Flash Controller as described in ZiLOG Application Note
AN0017 entitled Third Party Flash Programming Support of the
Z8 Encore!
®
MCU.
User code cannot be read through the On-Chip Debugger when read protect
is enabled. User code can only be read out wh en byp assing th e Flash Cont rol-
ler.
Work-Around:
None
2 START, STOP and
NAK bits in the I2C
Control register can
be cleared by soft-
ware writing a 0 to
these bits.
Error:
The START, STOP and NAK bits in the I2C Control register can be cleared by
software writing a 0 to these bits. The Product Specification states that they
cannot be cleared by writing a 0.
Work-Around:
None
3 Device may no t
complete STOP
Mode Recovery initi-
ated by a GPIO pin
transition.
Error:
When STOP Mo de Recove ry (SMR) is initiated by a GPIO pin transition, m ulti-
ple pin transition s with in 20 0 µs (approx.) of each other may cause the device
to only p artially wake up from ST OP mode. In this situation, the device idles in
a state bet ween STOP mode and normal operation. The crystal oscillator is
oscillating, but code does not execute.
When stuck in this idle state, assertion of the external RESET pi n does n ot in i-
tiate a system Reset.
Work-Arounds:
(1) Add external filtering to the STOP Mode Recovery pin input signal to pre-
vent multiple transitions in less than 200µs, and
(2) Enable the Watch-Dog Timer (WDT) in STOP Mode to allow a WDT to
complete the ST O P Mode Re cove ry i n the event the device does not success-
fully complete the STOP Mode Recovery initated by the GPIO pin transition.
Product Update
Errata to Z8 Encore!
®
64K Series
UP006006-0604
Errata to Z8 Encore! 64K Series
UP006006-0604 PRELIMINARY
2
Z8 Encore!
®
64K Series with Date Codes Prior to 0344
The errata listed in Table 2 are found in the production Z8 Encore!
®
64K Series devices with date codes
prior to 0344, where the date code is YYWW (year and week of assembly). When reviewing the following
errata, it is recommended that users also download the most recent version of the Product Specification.
Data contained in this document is PRELIMINARY only.
Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334
No. Summary Detailed Description
1 When the CPU exit s
from HALT mode, it
fails to reset the
master Interrupt
Request Enable
(IRQE) bit.
Error:
When the CPU exits from HALT mode, it fails to reset the master Interrupt
Request Enable (IRQE) bit (bit 7 of the Interrupt Con tr ol Reg ist er ).
WDT interrupts cause the Program Counter (PC) and Flags to be pushed
twice on the stack. Th e first push is th e PC and Flag s from where t he interrup t
occured. The second push is the starting address and Flags of the Interrupt
Service Routine (ISR).
This problem also affects exits from HALT mode caused by other interrupt
sources if more tha n one interrupt is pending. If only a single int errupt is pend -
ing then the routine is executed normally except that interrupts are not dis-
ableda
Work-Around:
To mimic standard interrupt operation, the ISR should execute a Disable Inter-
rupts (DI) instruction to reset the master Interrupt Request Enable (IRQE) bit
to 0.
Futher, on WDT interrupts before exiting, the ISR should add three (3) to the
Stack Pointer (SP). On Normal interrupts the ISR should check the Program
Counter on the stack. If the PC on the stack contains the starting address of
the ISR, then the ISR should add three (3) to the Stack Pointer (SP). This
problem only affects exits from HALT mode.
2 System Reset
latency may exceed
specification limits.
Error:
When exiting STOP mode and after a POR/VBO reset, the System Reset
Latency is 514 WDT cycles plus 16 System Clock cycles rather than the 66
WDT cycles plus 16 System Clock cycles as specified.
Workaround:
None. This error is unlikely to affect system operation.
3UART NEWFRM
status bit does not
function.
Error:
The NEWFRM st atus bit (Bit 2 of the UAR T S tat us 1 register) does not indicat e
the start of a new frame.
Workaround:
None.
Errata to Z8 Encore! 64K Series
UP006006-0604 PRELIMINARY
3
4 UART Address
Compare function
does not work.
Error:
Setting Bit 7 (MPMD[1]) of the UART Control 1 register to 1 does not produce
the desired effect of en ab lin g the U ART Address Compare and associ at ed
interrupt fun c t ion a l it y.
Workaround:
Leave MPMD[1] in its reset state of 0.
5 UART Baud Rate
Generator cannot be
used as simple
timer.
Error:
Setting BRGCTL (Bit 2 of the UART Control 1 register) to 1 when the UART
receiver is disabled does not enable UART Baud Rate Generator interrupt.
Thus, the UART Baud Rate Generator cannot be used as a simple timer.
Workaound:
Use one of the 4 standard Timers or the Baud Rate Generators in the SPI or
I2C blocks to perform the desired timing operations.
6 Unlocking the Flash
Controller allows
program and erase
operations on all
Flash pages.
Error:
During the Flash Controller unlo ck sequence, th e specification indicates that a
second write to the Flash Page Select register is required (step 5 of the
sequence) to unlock the Flash Controller for the selected Flash page. The
Flash controller unlocks for all Flash pages after steps 1-4 of the unlock
sequence are complete.
Workaround:
None.
7 Setting bits in the
Flash Sector Pro-
tect register to 1
does not lock sec-
tors.
Error:
Writing bits in the Flash Sector Protect register to 1 fails to prevent program
and erase operations on the selected Flash memory sector.
Workaround:
None.
8 Watch-Dog Timer
cannot be disabled
in STOP mode.
Error:
The Watch-Dog Timer and its associated internal RC oscillator cannot be dis-
abled in STOP mode.
Workaound:
None.
9 Watch-Dog Timer
oscillator frequency
is out of specifica-
tion.
Error:
The typical Watch-Dog Timer internal oscillator frequency is 50KHz rather
than the current ly specified 10KHz. This can resu lt in WDT timeout values t hat
are less than expected.
Workaround:
Increase the WDT reload value by a factor of 5 to compensate for the fre-
quency error.
Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334 (Continued)
No. Summary Detailed Description
Errata to Z8 Encore! 64K Series
UP006006-0604 PRELIMINARY
4
10 Operating currents. Error:
Operating currents in the various mode (Normal, HALT, and STOP) may be
higher than typical values.
Workaround:
None.
11 RESET pin is not fil-
tered. Error:
The RESET pin does not properly fil ter the inpu t signal. Th e device may enter
Reset when the RESET pin is asserted for less than the specified 4 system
clock cycles (from Normal mode).
Workaround:
Add external filtering to the printed-circuit board.
12 Timers can not be
cascaded. Error:
Setting the CSC bit (Bit 4) of the the Timer Control 0 Registers does not cas-
cade the timers as indicated by the spec.
Woraround:
Timers can be cascaded using the Timer Out and Timer In functions through
the general-purpose I/O pins.
13 ADC generates
extra interrupts Error:
The ADC continues to generate interrupts in CONTINUOUS mode after the
first interrupt before the results of the next conversion is complete.
Workaround:
Do not use CONTINUOUS mode. Use SINGLE-SHOT mode instead.
Table 2. Z8 Encore! 64K Series Errata Date Coded Prior to 0334 (Continued)
No. Summary Detailed Description
Errata to Z8 Encore! 64K Series
UP006006-0604 PRELIMINARY
5
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ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
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