DM9602CW - Fairchild Semiconductor

August 1986

Revised February 2000

DM9602 Dual Retriggerable, Resettable One Shots

DM9602

Dual Retriggerable, Resettable One Shots

General Descript ion

These dual resettable, retriggerable one shots have two

inputs per function; one which is active HIGH, and one

which is active LOW. This allows the designer to employ

either leading-edge or trailing-edge triggering, which is

independent of input transition times. When input condi-

tions for triggering are met, a new cycle starts and the

external capacitor is al lowed to rapid ly discharg e and then

charge again. The retriggerable feature permits output

pulse widths to be extended. In fact a continuous tr ue out-

put can be maint aine d by having an input cycl e time whi ch

is shorter than the ou tpu t cycle tim e. The ou tpu t pulse may

then be terminated at any time by applying a LOW logic

level to the RESET pin. Retriggering may be inhibited by

either connec ting the Q output to a n active HIGH input, or

the Q output to an active LOW input.

Features

■70 ns to ∞ output width range

■Resettable and retriggerable—0% to 100% duty cycle

■TTL input gating—leading or trailing edge triggering

■Complementary TTL outputs

■Optional retrigger lock-out capability

■Pulse width com pensat ed for VCC an d temper atu re vari -

ations

Ordering Code:

Connection Diagram

Function Table

H = HI GH Voltage Lev el

L = LOW Voltage Lev el

X = Don’t Care

Logic Diagrams

Order Number Package Number Package Description

DM9602N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Numbers Operation

ABCLR

H→L L H Trigger

HL→H H Trigger

XXL Reset

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DM9602

Operating Rules

1. An external resistor (RX) and external capacitor (CX)

are required as shown in the Logic Diagram.

2. The value of CX may vary from 0 to any necessary

value available. If, however, the capacitor has leakages

approaching 3.0 µA or if stray capacitance from either

terminal to ground is more than 50 pF, the timing equa-

tions may not represent the pulse width obtained.

3. The output pulse with (t) is defined as follows:

where: RX is in kΩ, CX is in pF

t is in ns

for CX < 103 pF, see Figure 1.

for K vs. CX see Figure 6.

4. If electrolytic type capacitors are to be used, the follow-

ing three configurations are recommended:

1. Use with low leakage capacitors:

The no rmal RC con figuration can b e used pred ict-

ably only if the forward capacitor leakage at 5.0V is

less than 3 µA, and the inverse ca pacitor leakage

at 1.0V is less than 5 µA over the operation al tem-

peratu re range.

R < 0.6 RX (Max)

2. Use with high inverse leakage current electrolytic

capacitors:

The diode in this configuration prevents high

inverse leakage currents through the capacitor by

preventing an i n ver se vo ltage across the cap aci to r.

The use of this configuration is not recommended

with retriggerable operation.

t ≈ 0.3 RCX

3. Use to obtain extended pulse widths:

This configuration ca n be used to obtain extende d

pulse widths, because of th e larger timing resistor

allowed by beta multiplication. Electrolytics with

high inverse leakage currents can be used.

R < RX (0.7) ( hFE Q1 ) o r < 2.5 MΩ, whichever is the

lesser

RX (min) < RY < RX (max)

(5 kΩ ≤ RY ≤ 10 kΩ is recommended)

Q1: NPN silicon transistor with hFE requirements of

above equations, such as 2N5961 or 2N5962.

t ≈ 0.3 RCX

This con figuration is no t recommend ed with retrigg erable ope ra-

tion.

5. To obtain varia ble pulse width by remote trim ming, the

following circuit is recommended:

6. Under any operating condition, CX and RX (min) must

be kept as close to the circuit as possible t o minimize

stray capacitance and reduce noise pickup.

7. Input Trigger Pulse Rules (See Triggering Truth Table)

Input to Pin 5(11) , (Pin 3(13) = HIGH)

Pin 4(12) = LOW

t1, t3 = Min. Positive Input Pulse Width > 40 ns

t2, t4 = Min. Negative Input Pulse Width > 40 ns

Input to Pin 4(12) (Pin 3(13) = HIGH)

Pin 5(11) = HIGH

8. The retriggerable pulse width is calculated as shown

below:

The re trigger pulse width is equ al to the pulse width (t) plus a dela y

time. For pulse widths greater than 500 ns, tW can be approximated as

t. Retrig gering wil l not occu r if the retrigger p ulse come s within ≈ 0.3

CX (ns) aft er t he initial trig ger pulse (i. e. , during th e dischar ge cy c le).

9. Reset Operation—An overriding clear (active LOW

level) is provided on each one shot. By applying a LOW

to the rese t, any ti ming cy cle can be termi nated or any

new cycle inhibited until the LOW reset input is

removed. Trigger inputs will not produce spikes in the

output when the reset is held LOW.

10. VCC and Ground wiring should conform to good high

frequency standards so that switching transients on

VCC and Ground leads do not cause interaction

between one shots. Use of a 0.01 to 0.1 µF bypass

capacitor between VCC and Ground located near the

DM9602 is recommended.

Note 1: F or f urther det ailed dev ic e charac t eris t ic s and outp ut perform anc e,

please ref er to the N SC one-shot applica ti on note, AN-366.

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DM9602

Typical Performance Characteristics

FIGURE 1. Output Pulse Width vs. Timing Resistance

and Cap aci tan ce for CX < 103 pF

FIGURE 2. Normalized Output Pulse Width

vs. Ambient Temperature

FIGURE 3. Pulse Width vs. Timing Resistor

FIGURE 4. Normalized Output Pulse Width

vs. Supply Voltage

FIGURE 5. Minimum Output Pulse Width

vs. Ambient Temperature

FIGURE 6. Typical “K” Coefficient Variation

vs. Timing Capacitance

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DM9602

Absolute Maximum Ratings(N o te 2) Note 2: Th e “Absolute M aximum Rat ings” are thos e values bey ond which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 3: Unless ot herwise not ed, RX = 10k for all tests.

Note 4: All typic als are at VCC = 5V, TA = 25°C.

Note 5: Ground PIN 1(15) for VOL on PIN 7(9) or VOH an d I OS on PIN 6(10) and apply momentary ground to PIN 4(12). Open PIN 1(15) for VOL on PIN 6(10)

or VOH and I OS on PIN 7 (9).

Note 6: Not more than one output should be shorted at a time.

Supply Voltage 7V

Input Vol tag e 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level TA = −55°C

Input Voltage TA = 0°C1.9

TA = 25°C1.8 V

TA = 75°C1.65

TA = 125 °C

VIL LOW Level TA = −55°C

Input Voltage TA = 0°C0.85

TA = 25°C0.85V

TA = 75°C0.85

TA = 125 °C

IOH HIGH Level Output Current −0.8 mA

IOL LOW Level Output Current 16 mA

TAFree Air Operating Temperature 0 75 °C

Symbol Parameter Condi tions (Note 3) Min Typ Max Units

(Note 4)

VIInput Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 V

Output Voltage VIL = Max, VIH = Min (Note 5)

VOL LOW Level VCC = Min, IOL = Max 0.45 V

Output Voltage VIL = Max, VIH = Min (Note 5)

IIH HIGH Level Input Curre nt VCC = Max, VI = 4.5V 60 µA

IIL LOW Level VCC = Max VI = 0.45V −1.6 mA

Input Current VCC = Min VI = 0.45V −1.41

IOS Short Circuit Output Current VCC = Max, VOUT = 1V (Note 5)(Note 6) −35 mA

ICC Supply Current VCC = Max 39 50 mA

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DM9602

Switching Characteristics

VCC = 5V, TA = 25°C

Symbol Parameter Conditions Min Max Units

tPLH Propagation Delay Time, Negative Trigger Input CL = 15 pF 40 ns

LOW-to-HIGH Level Output to True Output CX = 0

tPHL Propagation Delay Time, Negative Trigger Input RX = 5 kΩ48 ns

HIGH-to-LOW Level Output To Complement Output

tPW(MIN) Minimum True Output 100

Pulse Width ns

Minimum Complement 110

Pulse Width

tPW Pulse Width RX = 10 kΩ3.08 3.76 µs

CX = 1000 pF

CSTRAY Maximum Allowable Wiring Pins 2, 14 to GND 50 pF

Capacitance

RXExternal Timing Resistor 550kΩ

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DM9602 Dual Retriggerable, Resettable One Shots

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of any c ir cuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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