Dual, Wideband, Fixed Gain
BUFFER AMPLIFIER With Disable
OPA2682
®
FEATURES
●INTERNALLY FIXED GAIN: +2 or ±1
●HIGH BANDWIDTH (G = +2): 240MHz
●LOW SUPPLY CURRENT: 6mA/ch
●LOW DISABLED CURRENT: 320µA/ch
●HIGH OUTPUT CURRENT: 150mA
●OUTPUT VOLTAGE SWING: ±4.0V
●±5V OR SINGLE +5V OPERATION
APPLICATIONS
●BROADBAND VIDEO LINE DRIVERS
●VIDEO MULTIPLEXERS
●MULTIPLE LINE VIDEO DA
●PORTABLE INSTRUMENTS
●ADC BUFFERS
●ACTIVE FILTERS
TM
DESCRIPTION
The OPA2682 provides an easy to use, broadband fixed
gain, dual buffer amplifier. Depending on the external con-
nections, the internal resistor network may be used to pro-
vide either a fixed gain of +2 video buffer or a gain of +1 or
–1 voltage buffer. Operating on a very low 6mA/ch supply
current, the OPA2682 offers a slew rate and output power
normally associated with a much higher supply current. A
new output stage architecture delivers high output current
with a minimal headroom and crossover distortion. This
gives exceptional single supply operation. Using a single
+5V supply, the OPA2682 can deliver a 1V to 4V output
swing with over 100mA drive current and 200MHz band-
width. This combination of features makes the OPA2682 an
ideal RGB line driver or single-supply ADC input driver.
OPA2682 RELATED PRODUCTS
SINGLES DUALS TRIPLES
Voltage Feedback OPA680 OPA2680 OPA3680
Current Feedback OPA681 OPA2681 OPA3681
Fixed Gain OPA682 OPA2682 OPA3682
The OPA2682’s low 6mA/ch supply current is precisely
trimmed at 25°C. This trim, along with low drift over tempera-
ture, guarantees lower maximum supply current than competing
products that report only a room temperature nominal supply
current. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or
holding it high, gives normal operation. If pulled low, the
OPA2682 supply current drops to less than 320µA/ch while the
output goes into a high impedance state. This feature may be
used for either power savings or for video MUX applications.
©1998 Burr-Brown Corporation PDS-1477B Printed in U.S.A. October, 1999
High-Speed Instrumentation
Differential Amplifier
OPA2682
OPA2682
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
For most current data sheet and other
product information, visit www.burr-brown.com
1/2
OPA2682
1/2
OPA2682
OPA680
400Ω400Ω
400Ω
499Ω499Ω
249Ω249Ω
400Ω
V
2
V
OUT
= 2 • (V
1
– V
2
)
V
1
SBOS102
2
®
OPA2682
SPECIFICATIONS: VS = ±5V
G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted.
OPA2682U, N
TYP GUARANTEED(1)
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX
LEVEL
(2 )
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth (VO < 0.5Vp-p) G = +1 330 MHz min C
G = +2 240 220 210 190 MHz min B
G = –1 220 MHz typ C
Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5Vp-p 150 50 45 45 MHz min B
Peaking at a Gain of +1 VO < 0.5Vp-p 0.8 2 4 dB max B
Large-Signal Bandwidth G = +2, VO = 5Vp-p 210 MHz typ C
Slew Rate G = +2, 4V Step 2100 1600 1600 1200 V/µs min B
Rise/Fall Time G = +2, VO = 0.5V Step 1.7 ns typ C
G = +2, VO = 5V Step 2.0 ns typ C
Settling Time to 0.02% G = +2, VO = 2V Step 12 ns typ C
0.1% G = +2, VO = 2V Step 8 ns typ C
Harmonic Distortion G = +2, f = 5MHz, VO = 2Vp-p
2nd Harmonic RL = 100Ω–63 dBc typ C
RL = ≥ 500Ω–81 dBc typ C
3rd Harmonic RL = 100Ω–78 dBc typ C
RL = ≥ 500Ω–95 dBc typ C
Input Voltage Noise f > 1MHz 2.2 3.0 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B
Differential Gain NTSC, RL = 150Ω0.001 % typ C
NTSC, RL = 37.5Ω0.008 % typ C
Differential Phase NTSC, RL = 150Ω0.01 deg typ C
NTSC, RL = 37.5Ω0.05 deg typ C
Channel-to-Channel Crosstalk f = 5MHz –70 dBc typ C
DC PERFORMANCE(3)
Gain Error G = +1 ±0.2 % typ C
G = +2 ±0.3 –2.5, +1.5 % max A
G = –1 –1.0 % typ C
Internal RF and RG
Maximum 400 480 510 520 Ωmax A
Minimum 400 320 310 290 Ωmin A
Average Drift 0.13 0.13 0.13 %/°C max B
Input Offset Voltage VCM = 0V ±1.3 ±5±6.5 ±7.5 mV max A
Average Offset Voltage Drift VCM = 0V +35 +40 µV/°C max B
Non-Inverting Input Bias Current VCM = 0V +30 +55 ±65 ±85 µA max A
Average Non-Inverting Input Bias Current Drift VCM = 0V –400 –400 nA/°C max B
Inverting Input Bias Current VCM = 0V ±10 ±40 ±50 ±55 µA max A
Average Inverting Input Bias Current Drift VCM = 0V –125 –150 nA°C max B
INPUT
Common-Mode Input Range ±3.5 ±3.4 ±3.3 ±3.2 V min B
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C
OUTPUT
Voltage Output Swing No Load ±4.0 ±3.8 ±3.7 ±3.6 V min A
100Ω Load ±3.9 ±3.7 ±3.6 ±3.3 V min A
Current Output, Sourcing +190 +160 +140 +80 mA min A
Sinking –150 –135 –130 –80 mA min A
Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 typ C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
®
OPA2682
SPECIFICATIONS: VS = ±5V (Cont.)
G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted.
OPA2682U, N
TYP GUARANTEED(1)
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX
LEVEL
(2 )
DISABLE/POWER DOWN (DIS Pin) SO-14 Only
Power Down Supply Current (+VS)V
DIS = 0, Both Channels –640 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 70 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, RL = 150Ω±50 mV typ C
Turn Off Glitch G = +2, RL= 150Ω±20 mV typ C
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) VDIS = 0, Each Channel 100 160 160 160 µA max A
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage Range ±6±6±6 V max A
Max Quiescent Current VS = ±5V 6 6.4 6.5 6.6 mA/chan max A
Min Quiescent Current VS = ±5V 6 5.6 5.5 5.0 mA/chan min A
Power Supply Rejection Ratio (–PSRR) Input Referred 56 50 48 47 dB min A
TEMPERATURE RANGE
Specification: P, U, N
–40 to +85
°C typ C
Thermal Resistance,
θ
JA
U SO-8 125 °C/W typ C
N SO-14 100 °C/W typ C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature
+23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B)
Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode
voltage.
4
®
OPA2682
SPECIFICATIONS: VS = +5V
G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VCM = 2.5V (Figure 2 for AC performance only), unless otherwise noted.
OPA2682U, N
TYP GUARANTEED(1)
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX
LEVEL
(2)
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth (VO < 0.5Vp-p) G = +1 290 MHz min C
G = +2 220 180 140 110 MHz min B
G = –1 200 MHz typ C
Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5Vp-p 100 50 35 23 MHz min B
Peaking at a Gain of +1 VO < 0.5Vp-p 0.4 2 4 dB max B
Large-Signal Bandwidth G = +2, VO = 2Vp-p 210 MHz typ C
Slew Rate G = +2, 2V Step 830 700 680 570 V/µs min B
Rise/Fall Time G = +2, VO = 0.5V Step 1.5 ns typ C
G = +2, VO = 2V Step 2.0 ns typ C
Settling Time to 0.02% G = +2, VO = 2V Step 14 ns typ C
0.1% G = +2, VO = 2V Step 9 ns typ C
Harmonic Distortion G = +2, f = 5MHz, VO = 2Vp-p
2nd Harmonic RL = 100Ω to VS/2 –61 dBc typ C
RL = ≥ 500Ω to VS/2 –69 dBc typ C
3rd Harmonic RL = 100Ω to VS/2 –69 dBc typ C
RL = ≥ 500Ω to VS/2 –73 dBc typ C
Input Voltage Noise f > 1MHz 2.2 3.0 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 14 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B
DC PERFORMANCE(3)
Gain Error G = +1 ±0.2 % typ C
G = +2 ±0.3 –2.5, +1.5 % max A
G = –1 –1.0 % typ C
Internal RF and RG
Minimum 400 480 510 520 Ωmin B
Maximum 400 320 310 290 Ωmax B
Average Drift 0.13 0.13 0.13 %/°C max B
Input Offset Voltage VCM = 2.5V ±1±5±6±7 mV max A
Average Offset Voltage Drift VCM = 2.5V +15 +20 µV/°C max B
Non-Inverting Input Bias Current VCM = 2.5V +40 +65 ±75 ±95 µA max A
Average Non-Inverting Input Bias Current Drift VCM = 2.5V –300 –350 nA/°C max B
Inverting Input Bias Current VCM = 2.5V ±5±20 ±25 ±35 µA max A
Average Inverting Input Bias Current Drift VCM = 2.5V –125 –175 nA°C max B
INPUT
Least Positive Input Voltage 1.5 1.6 1.7 1.8 V min B
Most Positive Input Voltage 3.5 3.4 3.3 3.2 V max B
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C
OUTPUT
Most Positive Output Voltage No Load 4.0 3.8 3.7 3.5 V min A
RL = 100Ω3.9 3.7 3.6 3.4 V min A
Least Positive Output Voltage No Load 1.0 1.2 1.3 1.5 V min A
RL = 100Ω1.1 1.3 1.4 1.6 V min A
Current Output, Sourcing +150 +110 +110 +60 mA min A
Sinking –110 –75 –70 –50 mA min A
Output Impedance G = +2, f = 100kHz 0.03 Ωtyp C
5
®
OPA2682
SPECIFICATIONS: VS = +5V (Cont.)
G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VCM = 2.5V (Figure 2 for AC performance only), unless otherwise noted.
OPA2682U, N
TYP GUARANTEED(1)
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX
LEVEL
(2)
DISABLE/POWER DOWN (DIS Pin) SO-14 Only
Power Down Supply Current (+VS)V
DIS = 0, Both Channels –540 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 65 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, RL = 150Ω, VIN = VCM ±50 mV typ B
Turn Off Glitch G = +2, RL = 150Ω, VIN = VCM ±20 mV typ B
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) VDIS = 0, Each Channel 100 µA typ C
POWER SUPPLY
Specified Single Supply Operating Voltage 5 V typ C
Maximum Single Supply Operating Voltage 12 12 12 V max A
Max Quiescent Current VS = ±5V 4.8 5.3 5.4 5.4 mA/chan max A
Min Quiescent Current VS = ±5V 4.8 4.1 3.7 3.6 mA/chan min A
Power Supply Rejection Ratio (–PSRR) Input Referred 48 dB typ C
TEMPERATURE RANGE
Specification: P, U, N
–40 to +85
°C typ C
Thermal Resistance,
θ
JA
U SO-8 125 °C/W typ C
N SO-14 100 °C/W typ C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature
+23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B)
Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode
voltage.
6
®
OPA2682
PIN CONFIGURATIONS
Top View SO-8 SO-14
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PACKAGE
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA
OPA2682U SO-8 Surface Mount 182 –40°C to +85°C OPA2682U OPA2682U Rails
"""""OPA2682U/2K5 Tape and Reel
OPA2682N SO-14 Surface Mount 235 –40°C to +85°C OPA2682N OPA2682N Rails
"""""OPA2682N/2K5 Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “OPA2682U/2K5” will get a single 2500-piece Tape and Reel.
ABSOLUTE MAXIMUM RATINGS
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation(1) ............................ See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range............................................................................ ±VS
Storage Temperature Range: ........................................–40°C to +125°C
Lead Temperature (soldering, 10s).............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
NOTE:: (1) Packages must be derated based on specified
θ
JA. Maximum TJ
must be observed.
PACKAGE/ORDERING INFORMATION
1
2
3
4
8
7
6
5
+V
S
Out B
–In B
+In B
400Ω
400Ω
400Ω
400Ω
Out A
–In A
+In A
–V
S
OPA2682U
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Out A
NC
NC
+V
S
NC
NC
Out B
400Ω400Ω
–In A
+In A
DIS A
–V
S
DIS B
+In B
–In B
400Ω400Ω
OPA2682N
NC = No Connection
7
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = ±5V
G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
Frequency (50MHz/div)
0 500MHz250MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = –1
G = +1
G = +2
8
7
6
5
4
3
2
1
0
–1
–2
Frequency (25MHz/div)
0 250MHz125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
2Vp-p
R
L
= 100Ω
1Vp-p
4Vp-p
7Vp-p
400
300
200
100
0
–100
–200
–300
–400
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
V
O
= 0.5Vp-p
+4
+3
+2
+1
0
–1
–2
–3
–4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
V
O
= 5Vp-p
CHANNEL-TO-CHANNEL CROSSTALK
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Frequency (MHz)
1 10 100
Crosstalk (10dB/div)
2.0
1.6
1.2
0.8
0.4
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (50ns/div)
Output Voltage (400mV/div)
6.0
4.0
2.0
0
VDIS (2V/div)
VDIS
Output Voltage
VIN = +1V (SO-14 Only)
8
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).
2nd HARMONIC DISTORTION
vs FREQUENCY
–50
–60
–70
–80
–90
Harmonic Distortion (dBc)
0.1 10
120
G = –1
G = +2
G = +1
VO = 2Vp-p
Frequency (MHz)
HARMONIC DISTORTION
vs LOAD RESISTANCE
–50
–60
–70
–80
–90
Harmonic Distortion (dBc)
10 100 1000
V
O
= 2Vp-p
f
0
= 5MHz
R
L
(Ω)
2nd Harmonic
3rd Harmonic
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage (Vp-p)
–50
–60
–70
–80
–90
Harmonic Distortion (dBc)
0.1 1 5
f = 5MHz
2nd Harmonic
3rd Harmonic
3rd HARMONIC DISTORTION
vs FREQUENCY
–50
–60
–70
–80
–90
Harmonic Distortion (dBc)
0.1 10
120
G = –1 G = +2
G = +1
V
O
= 2Vp-p
Frequency (MHz)
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100 1k 10k 100k 1M 10M
Current Noise (pA/√Hz)
Voltage Noise (nV/√Hz)
Non-Inverting Input Current Noise
Inverting Input Current Noise
12.2pA/√Hz
15.1pA/√Hz
Voltage Noise 2.2nV/√Hz
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
–8–6–4–20246810
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50Ω Load
9
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).
60
50
40
30
20
10
0
RECOMMENDED RS vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100
RS (Ω)
15
12
9
6
3
0
–3
–6
–9
–12
–15
Frequency (30MHz/div)
0 300MHz150MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain to Capacitive Load (3dB/div)
1/2
OPA2682
R
S
V
IN
V
O
C
L
1kΩ
400Ω
400Ω
1kΩ is optional.
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
70
65
60
55
50
45
40
35
30
25
20
Frequency (Hz)
10
2
10
3
10
4
10
5
10
6
10
7
10
8
POWER SUPPLY REJECTION RATIO vs FREQUENCY
Rejection Ratio (dB)
+PSRR
–PSRR
20
15
10
5
0
200
150
100
50
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (°C)
–40 –20 0 20 40 60 80 100 120 140
Supply Current (5.0mA/div)
Output Current (mA)
Quiescent Supply Current
Sourcing Output Current
Sinking Output Current
0.05
0.04
0.03
0.02
0.01
0
Number of 150Ω Loads
1234
COMPOSITE VIDEO dG/dP
Positive Video
Negative Sync
dP
dG
dG/dP (%/°)
5
4
3
2
1
0
–1
–2
–3
–4
–5
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (°C)
–40 –20
V
IO
0 20 40 60 80 100 120 140
Input Offset Voltage (mV)
50
40
30
20
10
0
–10
–20
–30
–40
–50
Input Bias Currents (µA)
Non-Inverting Input Bias Current
Inverting Input Bias Current
10
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).
5
4
3
2
1
0
–1
–2
–3
–4
–5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
–300 –200 –100 0 100 200 300
V
O
(Volts)
100Ω Load Line
50Ω Load Line
25Ω
Load Line
Output Current Limited
1W Internal
Power Limit
1W Internal
Power Limit
Output Current Limit
One Channel
Only
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE
Frequency (Hz)
10k 100M100k 1M 10M
Output Impedance (Ω)
1/2
OPA2682
400Ω
+5
–5
400Ω
50ΩZO
11
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = +5V
G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2).
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
Frequency (50MHz/div)
0 500MHz250MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +1
G = –1
G = +2
8
7
6
5
4
3
2
1
0
–1
–2
Frequency (25MHz/div)
0 250125
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
R
L
= 100Ω to 2.5V V
O
= 0.5Vp-p
V
O
= 1Vp-p
V
O
= 2Vp-p
2.10
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
V
O
= 0.5Vp-p
4.5
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
0.5
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
V
O
= 2Vp-p
70
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100
R
S
(Ω)
15
12
9
6
3
0
–3
–6
–9
–12
–15
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (20MHz/div)
0 200MHz100MHz
Gain to Capacitive Load (3dB/div)
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
1/2
OPA2682
400Ω
400Ω
57.6Ω
806Ω
806Ω
1kΩ
V
IN
+5V
0.1µF
V
O
R
S
(1kΩ is optional)
C
L
0.1µF
12
®
OPA2682
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
G = +2 and RL = 100Ω to VCM = +2.5V, unless otherwise noted (see Figure 2).
–40
–50
–60
–70
–80
–90
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL
Single-Tone Load Power (dBm)
–14 2–12 –10 –8 –6 –4 –2 0
3rd-Order Spurious (dBc)
50MHz
20MHz
10MHz
Load Power at Matched 50Ω Load
dBc = dB Below Carriers
HARMONIC DISTORTION
vs SUPPLY VOLTAGE
–50
–60
–70
–80
–90
Harmonic Distortion (dBc)
56789101112
V
O
= 2Vp-p
f
0
= 5MHz
Total Supply Voltage (V)
2nd Harmonic
3rd Harmonic
13
®
OPA2682
APPLICATIONS INFORMATION
WIDEBAND BUFFER OPERATION
The OPA2682 gives the exceptional AC performance of a
wideband, current-feedback op amp with a highly linear,
high power output stage. It features internal RF and RG
resistors which make it easy to select a gain of +2, +1, or
–1 without any external resistors. Requiring only 6mA/ch
quiescent current, the OPA2682 will swing to within 1V of
either supply rail and deliver in excess of 135mA (guaran-
teed) at room temperature. This low output headroom re-
quirement, along with supply voltage independent biasing,
gives remarkable single (+5V) supply operation. The
OPA2682 will deliver greater than 200MHz bandwidth driv-
ing a 2Vp-p output into 100Ω on a single +5V supply.
Previous current-boosted output stage amplifiers have typi-
cally suffered from very poor crossover distortion as the
output current goes through zero. The OPA2682 achieves a
comparable power gain with much better linearity. The
primary advantage of the internal current-feedback op amp
over a voltage-feedback op amp is that AC performance
(bandwidth and distortion) is relatively independent of sig-
nal gain.
Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the ±5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50Ω with a resistor
to ground and the output impedance is set to 50Ω with a
series output resistor. Voltage swings reported in the speci-
fications are taken directly at the input and output pins
while load powers (dBm) are defined at a matched 50Ω
load. For the circuit of Figure 1, the total effective load will
be 100Ω || 800Ω = 89Ω. The disable control line (DIS) is
typically left open (SO-14 only) to guarantee normal ampli-
fier operation. In addition to the usual power supply
decoupling capacitors to ground, a 0.1µF capacitor can be
included between the two power supply pins. This optional
added capacitor will typically improve the 2nd harmonic
distortion performance by 3dB to 6dB.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-
cation and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single Supply Specifica-
tion and Test Circuit.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Specifica-
tions and Typical Performance Curves. Though not a “rail-
to-rail” design, the OPA2682 requires minimal input and
output voltage headroom compared to other fixed-gain buffer
amplifiers. It will deliver a 3Vp-p output swing on a single
+5V supply with greater than 150MHz bandwidth. The key
requirement of broadband single-supply operation is to main-
tain input and output signal swings within the usable voltage
ranges at both the input and the output. The circuit of Figure
2 establishes an input midpoint bias using a simple resistive
divider from the +5V supply (two 806Ω resistors). The input
signal is then AC-coupled into this midpoint voltage bias.
The input voltage can swing to within 1.5V of either supply
pin, giving a 2Vp-p input signal range centered between the
supply pins. The input impedance matching resistor (57.6Ω)
used for testing is adjusted to give a 50Ω input match when
the parallel combination of the biasing divider network is
included. The gain resistor (RG) is AC-coupled, giving the
circuit a DC gain of +1, which puts the input DC bias voltage
(2.5V) on the output as well. On a single +5V supply, the
output voltage can swing to within 1V of either supply pin
while delivering more than 75mA output current. A demand-
ing 100Ω load to a midpoint bias is used in this characteriza-
tion circuit. The new output stage used in the OPA2682 can
deliver large bipolar output currents into this midpoint load
with minimal crossover distortion, as shown by the +5V
supply, 3rd harmonic distortion plots.
HIGH SPEED INSTRUMENTATION AMPLIFIER
The front page shows an instrumentation amplifier based on
the OPA2682. The differential gain for this circuit is 2.0. The
inputs are high impedance, with only 1pF to ground at each
input. The loads on the OPA2682 outputs were made equal in
order to achieve the best harmonic distortion possible.
1/2
OPA2682
+5V
+V
S
–V
S
–5V
50Ω Load
50Ω50Ω
50Ω Source
R
G
400Ω
R
F
400Ω
+
6.8µF0.1µF
+
6.8µF0.1µF
V
IN
1/2
OPA2682
+5V
+V
S
V
S
/2
806Ω100ΩV
O
V
IN
806Ω
R
G
400Ω
R
F
400Ω
0.1µF
0.1µF
+
6.8µF0.1µF
50Ω Source
57.6Ω
14
®
OPA2682
DIFFERENTIAL ADC DRIVER
The circuit in Figure 3 converts a single-ended input to a
differential signal which drives the ADS823 converter. The
common-mode biasing uses a simple resistor divider con-
nected to the ADC’s reference voltages. Connecting the top
op amp’s RG to its non-inverting input provides a bias
current path for the non-inverting input. This connection
also improves distortion performance because both op amps
operate with nearly equal noise gains.
MULTIPLEXED VIDEO AMPLIFIER
The multiplexed video amplifier in Figure 4 “wire-ORs” the
two output signals together. The “make-before-break” dis-
able characteristic of the OPA2682N ensures that the output
is always under control. To avoid large switching glitches,
switch during the sync or retrace portions of the video
signal—the two inputs should be almost equal at these
times. Because the output is always under control, the
switching glitches for two 0V inputs are < 20mV. This
circuit also ensures that the maximum differential voltage
across the inputs of the unselected channel do not exceed the
±1.2V Maximum Rating when using standard video signal
levels.
The two output resistors isolate the outputs from each other
when switching between channels. The feedback network of
the disabled amplifier forms part of the output impedance
and attenuates the output signal slightly. The 68.1Ω value
compensates for the attenuation, and still provides good
back-matching for the cable (return loss > 20dB).
FIGURE 3. Wideband, AC-Coupled, Single-Supply A/D Driver.
FIGURE 4. Two-Channel Video Multiplexer (SO-14 only).
1/2
OPA2682N
1/2
OPA2682N
2kΩ
68.1Ω
75Ω Cable
RG-59
68.1Ω
75Ω
400Ω400Ω
Video 1
+5V
+5V
2kΩ
75Ω
400Ω400Ω
Video 2
–5V
V
DIS
DIS
DIS
V
OUT
V
OUT
< 2.6V
1/2
OPA2682
1/2
OPA2682
ADS823
10-Bit
60MSPS
100Ω
100Ω
50pF
2.5V
0.10µF
50pF
0.10µF0.10µF 0.10µF
+5V +5V
400Ω400Ω
2kΩ2kΩ
400Ω400Ω
+In +VS
–In
GND REFB
(+1.5V)
REFT
(+3.5V)
VIN
15
®
OPA2682
AC-COUPLED DIFFERENTIAL LOWPASS FILTER
The circuit in Figure 5 gives a single +5V supply, 3rd-
order Chebyshev lowpass filter with 0.5dB of ripple in the
passband and a –3dB bandwidth of 20MHz. This filter is
based on the KRC active filter topology, which uses an
amplifier with a fixed gain ≥ 1. The OPA2682 makes a
good amplifier for this type of filter. The component
values have been pre-distorted to compensate for the op
amp’s parasitic effects.
DESIGN-IN TOOLS
APPLICATIONS SUPPORT
The Burr-Brown Applications Department is available for
design assistance at 1-800-548-6132 (US/Canada only). The
Burr-Brown internet web page (http://www.burr-brown.com)
has the latest data sheets and other design aids.
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evalua-
tion of circuit performance using the OPA2682 in its two
package styles. These are available free as an unpopulated
PC board delivered with descriptive documentation. The
summary information for these boards is shown in the table
below.
MACROMODELS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA2682 is available through the
Burr-Brown Internet web page (http://www.burr-brown.com).
These models do a good job of predicting small-signal AC
and transient performance under a wide variety of operating
conditions. They do not do as well in predicting the har-
monic distortion, temperature performance, or dG/dφ char-
acteristics. These models do not attempt to distinguish
between the package types in their small-signal AC perfor-
mance.
OPERATING SUGGESTIONS
GAIN SETTING
Setting the gain with the OPA2682 is very easy. For a gain
of +2, ground the –IN pin and drive the +IN pin with the
signal. For a gain of +1, leave the –IN pin open and drive the
+IN pin with the signal. For a gain of –1, ground the +IN pin
and drive the –IN pin with the signal. Since the internal
resistor values change significantly over temperature and
process, external resistors should not be used to modify the
gain.
OUTPUT CURRENT AND VOLTAGE
The OPA2682 provides output voltage and current capabili-
ties that are unsurpassed in a low-cost, monolithic op amp.
Under no-load conditions at 25°C, the output voltage typi-
cally swings closer than 1V to either supply rail; the guar-
anteed swing limit is within 1.2V of either rail. Into a 15Ω
load (the minimum tested load), it is guaranteed to deliver
more than ±135mA.
FIGURE 5. Single-Supply, 3rd-Order Differential Chebyshev Low-Pass Filter.
DEMO LITERATURE
BOARD REQUEST
PRODUCT PACKAGE NUMBER NUMBER
OPA2682U 8-Lead SO-8 DEM-OPA268xU MKT-352
OPA2682N 14-Lead SO-14 DEM-OPA268xN MKT-353
Contact the Burr-Brown applications support line
(1-800-548-6132) to request any of these boards, using the
literature request number.
1/2
OPA2682
1/2
OPA2682
205Ω105Ω51.1Ω
205Ω
1.10kΩ
1.10kΩ
1kΩ
1kΩ
105Ω51.1Ω
0.10µF
0.10µF
82pF
82pF
0.10µF18pF
+5V
400Ω400Ω
400Ω400Ω
0.10µF
V
IN
180pF V
OUT
+5V
16
®
OPA2682
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage x current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the T ypical
Performance Curves. The X and Y axes of this graph show
the zero-voltage output current limit and the zero-current
output voltage limit, respectively. The four quadrants give a
more detailed view of the OPA2682’s output drive capabili-
ties, noting that the graph is bounded by a “Safe Operating
Area” of 1W maximum internal power dissipation. Superim-
posing resistor load lines onto the plot shows that the
OPA2682 can drive ±2.5V into 25Ω or ±3.5V into 50Ω
without exceeding the output capabilities or the 1W dissipa-
tion limit for a single channel. A 100Ω load line (the
standard test circuit load) shows the full ±3.9V output swing
capability, as shown in the Typical Specifications.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor in the
power supply leads. This will, under heavy output loads,
reduce the available output voltage swing. A 5Ω series
resistor in each power supply lead will limit the internal
power dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing only
0.5V for up to 100mA desired load currents. Always place
the 0.1µF power supply decoupling capacitors after these
supply current limiting resistors, and directly at the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed amplifier like the
OPA2682 can be very susceptible to decreased stability and
closed-loop response peaking when a capacitive load is
placed directly on the output pin. When the amplifier’s open-
loop output resistance is considered, this capacitive load
introduces an additional pole in the signal path that can
decrease the phase margin. Several external solutions to this
problem have been suggested. When the primary consider-
ations are frequency response flatness, pulse response fidel-
ity , and/or distortion, the simplest and most ef fective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds a
zero at a higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus increasing
the phase margin and improving stability.
The Typical Performance Curves show the recommended RS
vs Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA2682. Long PC board
traces, unmatched cables, and connections to multiple devices
can easily cause this value to be exceeded. Always consider
this effect carefully, and add the recommended series resistor
as close as possible to the OPA2682 output pin (see Board
Layout Guidelines).
DISTORTION PERFORMANCE
The OPA2682 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda-
mental signal reaches very high frequency or power levels, the
2nd harmonic will dominate the distortion with a negligible
3rd harmonic component. Increasing the load impedance im-
proves 2nd harmonic distortion directly. Remember that the
total load includes the feedback network-in the non-inverting
configuration (see Figure 1); this is the sum of RF + RG, while
in the inverting configuration it is just RF. Also, providing an
additional supply decoupling capacitor (0.1µF) between the
supply pins (for bipolar operation) improves the 2nd-order
distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases
harmonic distortion directly. The Typical Performance Curves
show the 2nd harmonic increasing at a little less than the
expected 2X rate while the 3rd harmonic increases at a little
less than the expected 3X rate. Where the test power doubles,
the difference between it and the 2nd harmonic decreases less
than the expected 6dB while the difference between it and the
3rd decreases by less than the expected 12dB. This also shows
up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues to
hold them low even as the fundamental power reaches very
high levels. As the Typical Performance Curves show, the
spurious intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental power
level increases, the dynamic range does not decrease signifi-
cantly. For two tones centered at 20MHz, with 10dBm/tone
into a matched 50Ω load (i.e., 2Vp-p for each tone at the load,
which requires 8Vp-p for the overall 2-tone envelope at the
output pin), the Typical Performance Curves show 62dBc
difference between the test-tone power and the 3rd-order
intermodulation spurious levels. This exceptional performance
improves further when operating at lower frequencies.
17
®
OPA2682
NOISE PERFORMANCE
The OPA2682 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/√Hz) is significantly lower than
earlier solutions while the input voltage noise (2.2nV√Hz) is
lower than most unity gain stable, wideband, voltage-feed-
back op amps. This low input voltage noise was achieved at
the price of higher non-inverting input current noise
(12pA/√Hz). As long as the AC source impedance looking out
of the non-inverting node is less than 100Ω, this current noise
will not contribute significantly to the total output noise. The
op amp input voltage noise and the two input current noise
terms combine to give low output noise under a wide variety
of operating conditions. Figure 6 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA√Hz.
FIGURE 6. Noise Model.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the output
noise voltage using the terms shown in Figure 6.
(1)
Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input-referred spot noise voltage at
the non-inverting input as shown in Equation 2.
Evaluating these two equations for the OPA2682 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.7nV/√Hz and a total equivalent input
spot noise voltage of 4.4nV/√Hz. This total input-referred
spot noise voltage is higher than the 2.2nV/√Hz specifica-
tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor.
(2)
E
N
=E
NI2
+I
BN
R
S
()
2
+4kTR
S
+I
BI
R
F
NG
2
+4kTR
F
NG
E
O
=E
NI2
+I
BN
R
S
()
2
+4kTR
S
()
NG
2
+I
BI
R
F
()
2
+4kTR
F
NG
DC ACCURACY
The OPA2682 provides exceptional bandwidth in high gains,
giving fast pulse settling but only moderate DC accuracy.
The Typical Specifications show an input offset voltage
comparable to high speed voltage-feedback amplifiers. How-
ever, the two input bias currents are somewhat higher and
are unmatched. Bias current cancellation techniques will not
reduce the output DC offset for OPA2682. Since the two
input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of each
input to reduce their error contribution to the output is
ineffective. Evaluating the configuration of Figure 1, using
worst-case +25°C input offset voltage and the two input bias
currents, gives a worst-case output offset range equal to:
±(NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF)
where NG = non-inverting signal gain
= ±(2 • 5.0mV) + (55µA • 25Ω • 2) ± (480Ω • 40µA)
= ±10mV + 2.8mV ± 19.2mV
= –26.4mV → +32.0mV
Minimizing the resistance seen by the non-inverting input
will give the best DC offset performance.
DISABLE OPERATION (SO-14 Only)
The OPA2682N provides an optional disable feature that
may be used either to reduce system power or to implement
a simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA2682N will operate nor-
mally. To disable, the control pin must be asserted low.
Figure 7 shows a simplified internal circuit for the disable
control feature.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to turn
on the two diodes in Q1’s emitter. As VDIS is pulled low,
additional current is pulled through the 15kΩ resistor even-
tually turning on these two diodes (≈ 100µA). At this point,
any further current pulled out of VDIS goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
25kΩ110kΩ
15kΩ
I
S
Control –V
S
+V
S
V
DIS
Q1
FIGURE 7. Simplified Disable Control Circuit.
4kT
R
G
R
G
R
F
R
S
OPA2682
I
BI
E
O
I
BN
4kT = 1.6 • 10
–20
E
RS
E
NI
√4kTR
S
√4kTR
F
18
®
OPA2682
mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode is only that required to operate the circuit of
Figure 7. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2682N is operating in a gain of
+1, this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a gain
of +2, the total feedback network resistance (RF + RG) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as at a gain of –1, the input and
output will be connected through the feedback network
resistance (RF + RG) giving relatively poor input to output
isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 8
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
Operating junction temperature (TJ) is given by TA + PD •
θ
JA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at a
voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition PDL = VS2/(4 • RL) where RL
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA2682U (SO-8 package) in the circuit of Figure 1 oper-
ating at the maximum specified ambient temperature of
+85°C with both outputs driving a grounded 100Ω load to
+2.5V:
PD = 10V • 13.2mA + 2 [52/(4 • (20Ω || 800Ω)) = 273mW
Maximum TJ = +85°C + (0.27W • 125°C/W) = 119°C
This worst-case condition is still well within rated maximum
TJ for this 100Ω load. Heavier loads may, however, exceed
the 175°C maximum junction temperature rating. Careful
attention to internal power dissipation is required, and forced
air cooling may be required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2682 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability; on the non-inverting input,
it can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power sup-
ply pins to high frequency 0.1µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections (on pins 4 and 7) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling capaci-
tors, effective at lower frequency, should also be used on the
main supply pins. These may be placed somewhat farther
from the device and may be shared among several devices in
the same area of the PC board.
FIGURE 8. Disable/Enable Glitch.
40
20
0
–20
–40
Time (20ns/div)
Output Voltage (20mV/div)
Output Voltage
(0V Input)
V
DIS
0.2V
4.8V
The transition edge rate (dV/dt) of the DIS control line will
influence this glitch. For the plot of Figure 8, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
VDIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2682,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.
19
®
OPA2682
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA2682. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially-
leaded resistors can also provide good high-frequency per-
formance. Keep the leads and PC board trace lengths as
short as possible. Never use wirewound type resistors in a
high frequency application. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, consider
the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the plot of Recommended RS vs Capacitive
Load. Low parasitic capacitive loads (< 5pF) may not need
an RS since the OPA2682 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is required,
and the 6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched im-
pedance transmission line using microstrip or stripline tech-
niques (consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher impedance
environment will improve distortion as shown in the Distor -
tion vs Load plots. With a characteristic board trace imped-
ance defined based on board material and trace dimensions,
a matching series resistor into the trace from the output of
the OPA2682 is used, as well as a terminating shunt resistor
at the input of the destination device. Remember also that
the terminating impedance will be the parallel combination
of the shunt resistor and the input impedance of the destina-
tion device: this total effective impedance should be set to
match the trace impedance. The high output voltage and
current capability of the OPA2682 allows multiple destina-
tion devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the 6dB
attenuation of a doubly-terminated transmission line is unac-
ceptable, a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this case and
set the series resistor value as shown in the plot of Recom-
mended RS vs Capacitive Load. This will not preserve signal
integrity as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will be
some signal attenuation due to the voltage divider formed by
the series output into the terminating impedance.
e) Socketing a high-speed part like the OPA2682 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA2682
onto the board.
INPUT AND ESD PROTECTION
The OPA2682 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD
protection using internal diodes to the power supplies as
shown in Figure 9.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA2682), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.
External
Pin
+V
CC
–V
CC
Internal
Circuitry
FIGURE 9. Internal ESD Protection.
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