FEATURES Dual-channel, 1024-position resolution 25 k, 250 k nominal resistance Maximum 8% nominal resistor tolerance error Low temperature coefficient: 35 ppm/C 2.7 V to 5 V single supply or 2.5 V dual supply SPI-compatible serial interface Nonvolatile memory stores wiper settings Power-on refreshed with EEMEM settings Permanent memory write protection Resistance tolerance stored in EEMEM 26 bytes extra nonvolatile memory for user-defined information 1M programming cycles 100-year typical data retention APPLICATIONS DWDM laser diode driver, optical supervisory systems Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5235 is a dual-channel, nonvolatile memory,1 digitally controlled potentiometer2 with 1024-step resolution, offering guaranteed maximum low resistor tolerance error of 8%. The device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the AD5235 via an SPI(R)-compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, 6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM1 for userdefined information such as memory data for other components, look-up table, or system identification information. 1 2 FUNCTIONAL BLOCK DIAGRAM CS AD5235 ADDR DECODE RDAC1 REGISTER A1 W1 CLK SDI SERIAL INTERFACE SDO PR WP RDY EEMEM1 POWER-ON RESET VDD RDAC1 RDAC2 REGISTER B1 A2 W2 EEMEM CONTROL B2 EEMEM2 RTOL* 26 BYTES USER EEMEM RDAC2 VSS GND 02816-001 Data Sheet Nonvolatile Memory, Dual 1024-Position Digital Potentiometer AD5235 *RAB TOLERANCE Figure 1. In the scratchpad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance between Terminal W and Terminal A and Terminal W and Terminal B. This setting can be stored into the EEMEM and is restored automatically to the RDAC register during system power-on. The EEMEM content can be restored dynamically or through external PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the independent or simultaneous linear-step increment or decrement commands can be used to move the RDAC wiper up or down, one step at a time. For logarithmic 6 dB changes in the wiper setting, the left or right bit shift command can be used to double or halve the RDAC wiper setting. The AD5235 patterned resistance tolerance is stored in the EEMEM. The actual end-to-end resistance can, therefore, be known by the host processor in readback mode. The host can execute the appropriate resistance step through a software routine that simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5235 is available in a thin, 16-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of -40C to +85C. The terms nonvolatile memory and EEMEM are used interchangeably. The terms digital potentiometer and RDAC are used interchangeably. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2004-2012 Analog Devices, Inc. All rights reserved. AD5235 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programming the Variable Resistor ......................................... 22 Applications ....................................................................................... 1 Programming the Potentiometer Divider ............................... 22 General Description ......................................................................... 1 Programming Examples ............................................................ 23 Functional Block Diagram .............................................................. 1 EVAL-AD5235SDZ Evaluation Kit .......................................... 23 Revision History ............................................................................... 3 Applications Information .............................................................. 24 Specifications..................................................................................... 4 Bipolar Operation from Dual Supplies.................................... 24 Electrical Characteristics--25 k, 250 k Versions ............... 4 Gain Control Compensation .................................................... 24 Interface Timing and EEMEM Reliability Characteristics-- 25 k, 250 k Versions ............................................................... 6 High Voltage Operation ............................................................ 24 Absolute Maximum Ratings ............................................................ 8 Bipolar Programmable Gain Amplifier ................................... 25 ESD Caution .................................................................................. 8 10-Bit Bipolar DAC .................................................................... 25 Pin Configuration and Function Descriptions ............................. 9 Programmable Voltage Source with Boosted Output ........... 25 Typical Performance Characteristics ........................................... 10 Programmable Current Source ................................................ 26 Test Circuits................................................................................. 14 Programmable Bidirectional Current Source ......................... 26 Theory of Operation ...................................................................... 16 Programmable Low-Pass Filter ................................................ 27 Scratchpad and EEMEM Programming.................................. 16 Programmable Oscillator .......................................................... 27 Basic Operation .......................................................................... 16 Optical Transmitter Calibration with ADN2841 ................... 28 EEMEM Protection .................................................................... 17 Resistance Scaling ...................................................................... 28 Digital Input and Output Configuration................................. 17 Serial Data Interface ................................................................... 17 Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations ......................................................... 29 Daisy-Chain Operation ............................................................. 18 RDAC Circuit Simulation Model ............................................. 29 Terminal Voltage Operating Range .......................................... 18 Outline Dimensions ....................................................................... 30 Advanced Control Modes ......................................................... 20 Ordering Guide .......................................................................... 30 DAC.............................................................................................. 24 RDAC Structure .......................................................................... 21 Rev. F | Page 2 of 32 Data Sheet AD5235 REVISION HISTORY 6/12--Rev. E to Rev. F 7/04--Rev. A to Rev. B Changes to Table 1 Conditions ........................................................ 4 Removed Positive Supply Current RDY and/or SDO Floating Parameters and Negative Supply Current RDY and/or SDO Floating Parameters, Table 1 ............................................................ 5 Added Endnote 2 to Ordering Guide ...........................................30 Updated Formatting .......................................................... Universal Edits to Features, General Description, and Block Diagram ...... 1 Changes to Specifications................................................................. 3 Replaced Timing Diagrams ............................................................. 6 Changes to Absolute Maximum Ratings........................................ 7 Changes to Pin Function Descriptions .......................................... 8 Changes to Typical Performance Characteristics ......................... 9 Additional Test Circuit (Figure 36)................................................. 9 Edits to Theory of Operation ........................................................ 14 Edits to Applications ....................................................................... 23 Updated Outline Dimensions........................................................ 27 4/11--Rev. D to Rev. E Changes to Figure 12 ......................................................................11 4/11--Rev. C to Rev. D Changes to EEMEM Performance .............................. Throughout Changes to Features and General Descriptions Sections ............. 1 Changes to Specifications Section................................................... 4 Changes to Pin 5, Pin 13, Pin 14 Descriptions .............................. 9 Changes to Typical Performance Characteristics Section .........10 Changes to Table 7 ..........................................................................19 Changes to Table 9 ..........................................................................21 Changes to Rheostat Operation Section, Table 12, Table 13 .....22 Changes to Table 16, Table 19, and EVAL-AD5235SDZ Evaluation Kit Section ....................................................................23 Changes to RDAC Circuit Simulation Model Section ...............29 Updated Outline Dimensions ........................................................30 Changes to Ordering Guide ...........................................................30 8/02--Rev. 0 to Rev. A Change to Features and General Description ............................... 1 Change to Specifications .................................................................. 2 Change to Calculating Actual End-to-End Terminal Resistance Section ........................................................................... 14 4/09--Rev. B to Rev. C Changes to Figure 1........................................................................... 1 Changes to Specifications ................................................................. 3 Changes to SDO, Description Column, Table 4............................ 8 Changes to Figure 18 ......................................................................11 Changes to Theory of Operation Section ....................................14 Changes to Serial Data Interface Section .....................................15 Changes to Linear Increment and Decrement Instructions Section, Logarithmic Taper Mode Adjustment Section, and Figure 42 ...........................................................................................18 Changes to Rheostat Operations Section .....................................20 Changes to Bipolar Programmable Gain Amplifier Section, Figure 49, Table 21, and 10-Bit Bipolar DAC Section ................23 Changes to Programmable Oscillator Section and Figure 56 ...25 Changes to Ordering Guide ...........................................................28 Rev. F | Page 3 of 32 AD5235 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS--25 k, 250 k VERSIONS VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = -2.5 V, VA = VDD, VB = VSS, -40C < TA < +85C, unless otherwise noted. These specifications apply to versions with a date code 1209 or later. Table 1. Parameter DC CHARACTERISTICS--RHEOSTAT MODE (All RDACs) Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance Nominal Resistance Match DC CHARACTERISTICS-- POTENTIOMETER DIVIDER MODE (All RDACs) Resolution Differential Nonlinearity 3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 4 Capacitance Ax, Bx 5 Capacitance Wx5 Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Symbol Conditions Min R-DNL R-INL RAB/RAB (RAB/RAB)/T x 106 RW RWB RWB -1 -2 -8 N DNL INL (VW/VW)/T x 106 Code = midscale VWFSE VWZSE Code = full scale Code = zero scale CW ICM VIH VIL VIH VIL VIH Input Logic Low VIL Output Logic High (SDO, RDY) VOH Output Logic Low VOL Input Current Input Capacitance5 IIL CIL Max Unit +1 +2 +8 LSB LSB % ppm/C 60 % 10 +1 +1 Bits LSB LSB ppm/C 0 4 LSB LSB VDD 11 V pF 80 pF 35 IW = 1 V/RWB, code = midscale VDD = 5 V VDD = 3 V 30 50 0.1 RAB1/RAB2 VA, VB, VW CA, CB Typ 1 -1 -1 15 -6 0 VSS f = 1 MHz, measured to GND, code = midscale f = 1 MHz, measured to GND, code = midscale VW = VDD/2 With respect to GND, VDD = 5 V With respect to GND, VDD = 5 V With respect to GND, VDD = 3 V With respect to GND, VDD = 3 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V (see Figure 38) IOL = 1.6 mA, VLOGIC = 5 V (see Figure 38) VIN = 0 V or VDD 0.01 2.4 0.8 2.1 0.6 2.0 0.5 4.9 A V V V V V V V 5 Rev. F | Page 4 of 32 1 0.4 V 1 A pF Data Sheet Parameter POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current AD5235 Symbol Conditions Min VDD VDD/VSS IDD ISS VSS = 0 V 2.7 2.25 EEMEM Store Mode Current IDD (store) EEMEM Restore Mode Current 7 ISS (store) IDD (restore) Power Dissipation 8 Power Supply Sensitivity5 DYNAMIC CHARACTERISTICS5, 9 Bandwidth Total Harmonic Distortion VW Settling Time ISS (restore) PDISS PSS BW THDW tS Resistor Noise Density Crosstalk (CW1/CW2) eN_WB CT Analog Crosstalk CTA VIH = VDD or VIL = GND VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VSS = GND, ISS 0 VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND, VSS = GND, ISS 0 VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10% -3 dB, RAB = 25 k/250 k VA = 1 V rms, VB = 0 V, f = 1 kHz, code = midscale RAB = 25 k RAB = 250 k VA = VDD, VB = 0 V, VW = 0.50% error band, from zero scale to midscale RAB = 25 k RAB = 250 k RAB = 25 k/250 k VA1 = VDD, VB1 = VSS , measured VW2 with VW1 making full-scale change, RAB = 25 k/250 k VAB2 = 5 V p-p, f = 1 kHz, measured VW1, Code 1 = midscale, Code 2 = full scale, RAB = 25 k/250 k -4 Typ 1 Max Unit 2 5.5 2.75 5 V V A -2 2 A mA -2 320 mA A -320 10 0.006 30 0.01 A W %/% 125/12 kHz 0.009 0.035 % % 4 36 20/64 30/60 s s nV/Hz nV-s -110/-100 dB Typicals represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IWB = (VDD - 1)/RWB (see Figure 27). 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28). 4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2. 7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register. 8 PDISS is calculated from (IDD x VDD) + (ISS x VSS). 9 All dynamic characteristics use VDD = +2.5 V and VSS = -2.5 V. 1 2 Rev. F | Page 5 of 32 AD5235 Data Sheet INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS--25 k, 250 k VERSIONS Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 2.7 V and VDD = 5 V. Table 2. Parameter Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulse Width Data Setup Time Data Hold Time CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay 2 CLK to SDO Data Hold Time CS High Pulse Width 3 CS High to CS High3 RDY Rise to CS Fall CS Rise to RDY Fall Time Store EEMEM Time 4, 5 Read EEMEM Time4 CS Rise to Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) 6 Preset Response Time to Wiper Setting6 Power-On EEMEM Restore Time6 FLASH/EE MEMORY RELIABILITY Endurance 7 Symbol t1 t2 t3 t4, t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t16 t17 tPRW tPRESP tEEMEM Conditions Clock level high or low From positive CLK transition From positive CLK transition RP = 2.2 k, CL < 20 pF RP = 2.2 k, CL < 20 pF Min 20 10 1 10 5 5 Typ 1 40 50 50 0 10 4 0 0.15 15 7 Applies to Instructions 0x2, 0x3 Applies to Instructions 0x8, 0x9, 0x10 10 50 PR pulsed low to refresh wiper positions 30 30 TA = 25C 1 100 Data Retention 8 Max 100 0.3 50 30 Unit ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms s ns ns s s MCycles kCycles Years Typicals represent average readings at 25C and VDD = 5 V. Propagation delay depends on the value of VDD, RPULL-UP, and CL. 3 Valid for commands that do not activate the RDY pin. 4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 s; CMD_9, CMD_10 ~ 7 s; CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 s. 5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles. 6 Not shown in Figure 2 and Figure 3. 7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at -40C, +25C, and +85C. 8 Retention lifetime equivalent at junction temperature (TJ) = 85C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. 1 2 Rev. F | Page 6 of 32 Data Sheet AD5235 Timing Diagrams CPHA = 1 CS t12 t13 t3 t1 t2 CLK CPOL = 1 t5 B23 B0 t17 t4 t7 SDI t6 HIGH OR LOW B23 (MSB) t8 t11 t10 B23 (MSB) B24* SDO HIGH OR LOW B0 (LSB) t9 B0 (LSB) t14 t15 t16 02816-002 RDY *THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2. CPHA = 1 Timing Diagram CPHA = 0 CS t12 t1 t2 B23 CLK CPOL = 0 t3 t5 t13 t17 B0 t4 t7 t6 SDI HIGH OR LOW HIGH OR LOW B23 (MSB IN) B0 (LSB) t10 t8 t11 t9 SDO B23 (MSB OUT) B0 (LSB) * t14 t15 t16 *THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 3. CPHA = 0 Timing Diagram Rev. F | Page 7 of 32 02816-003 RDY AD5235 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND IA, IB, IW Pulsed 1 Continuous Digital Input and Output Voltage to GND Operating Temperature Range 2 Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Thermal Resistance Junction-to-Ambient JA,TSSOP-16 Junction-to-Case JC, TSSOP-16 Package Power Dissipation Rating -0.3 V to +7 V +0.3 V to -7 V 7V VSS - 0.3 V to VDD + 0.3 V 20 mA 2 mA -0.3 V to VDD + 0.3 V -40C to +85C 150C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 215C 220C 150C/W 28C/W (TJ max - TA)/JA Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Includes programming of nonvolatile memory. 1 Rev. F | Page 8 of 32 Data Sheet AD5235 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 RDY 2 15 CS SDO 3 14 PR AD5235 13 WP TOP VIEW (Not to Scale) 12 VDD A1 6 11 A2 W1 7 10 W2 B1 8 9 B2 SDI GND 4 VSS 5 02816-005 CLK 1 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 Mnemonic CLK SDI SDO 4 5 GND VSS 6 7 8 9 10 11 12 13 A1 W1 B1 B2 W2 A2 VDD WP 14 PR 15 16 CS RDY Description Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 k to 10 k is needed. Ground Pin, Logic Ground Reference. Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink 2 mA for 15 ms when storing data to EEMEM. Terminal A of RDAC1. Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0. Terminal B of RDAC1. Terminal B of RDAC2. Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1. Terminal A of RDAC2. Positive Power Supply. Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe. CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used. Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale until EEMEM is loaded with a new value by the user. PR is activated at the logic high transition. Tie PR to VDD, if not used. Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and PR. Rev. F | Page 9 of 32 AD5235 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 +85C +25C -40C 0.15 0.15 DNL ERROR (LSB) 0.05 0 -0.05 0.05 0 -0.05 -0.10 0 200 400 600 800 1000 DIGITAL CODE -0.15 02816-006 -0.20 Figure 5. INL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 25 k 0 200 400 600 800 Figure 8. R-DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 25 k 200 0.16 0.14 POTENTIOMETER MODE TEMPCO (ppm/C) +85C +25C -40C 0.12 0.10 0.08 0.06 0.04 0.02 0 -0.02 1000 DIGITAL CODE 02816-009 -0.10 -0.15 25k 250k 180 160 140 120 100 80 60 40 20 0 0 200 400 600 800 1000 DIGITAL CODE 0 02816-007 -0.04 256 512 768 Figure 9. (VW/VW)/T x 106 Potentiometer Mode Tempco Figure 6. DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 25 k 200 0.20 +85C +25C -40C 25k 250k 180 RHEOSTAT MODE TEMPCO (ppm/C) 0.15 0.10 0.05 0 -0.05 -0.10 1023 CODE (Decimal) 02816-010 DNL ERROR (LSB) 0.10 -0.15 160 140 120 100 80 60 40 -0.20 0 200 400 600 DIGITAL CODE 800 1000 02816-008 20 Figure 7. R-INL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 25 k Rev. F | Page 10 of 32 0 0 256 512 768 CODE (Decimal) Figure 10. (RWB/RWB)/T x 106 Rheostat Mode Tempco 1023 02816-011 INL ERROR (LSB) 0.10 INL ERROR (LSB) +85C +25C -40C Data Sheet AD5235 60 2.7V 3.0V 3.3V 5.0V 5.5V 40 300 IDD (A) 30 200 20 100 10 0 200 400 600 800 1000 CODE (Decimal) 0 02816-012 0 0 1 2 3 4 02816-015 WIPER ON RESISTANCE () 50 2.7V 3.0V 3.3V 5.0V 5.5V 400 5 VDIO (V) Figure 11. Wiper On Resistance vs. Code Figure 14. IDD vs. Digital Input Voltage 3 IDD IDD IDD IDD IDD 2 0.12 = 2.7V = 3.3V = 3.0V = 5.0V = 5.5V 0.10 250k 0.08 THD + N (%) IDD/ISS (A) 1 0 -1 0.06 0.04 -20 25k 0.02 0 20 40 60 80 85 TEMPERATURE (C) 0 10 100 1k 10k 100k FREQUENCY (Hz) Figure 12. IDD vs. Temperature 02816-115 -3 -40 = 2.7V = 3.3V = 3.0V = 5.0V = 5.5V 02816-013 -2 ISS ISS ISS ISS ISS Figure 15. THD + Noise vs. Frequency 50 10 FULL SCALE MIDSCALE ZERO SCALE 40 1 0.1 250k 25k 0.01 10 0 1 2 3 4 5 6 7 8 FREQUENCY (MHz) 9 10 Figure 13. IDD vs. Clock Frequency, RAB = 25 k 0.001 0.0001 0.001 0.01 0.1 AMPLITUDE (V rms) Figure 16. THD + Noise vs. Amplitude Rev. F | Page 11 of 32 1 10 02816-116 THD + N (%) 20 02816-014 I DD (A) 30 AD5235 Data Sheet 0 3 VDD = 5V 10% AC VSS = 0V, VA = 4V, VB = 0V MEASURED AT VW WITH CODE = 0x200 TA = 25C -10 0 -20 -3 PSRR (dB) GAIN (dB) RAB = 25k RAB = 250k -6 f-3dB = 12kHz f-3dB = 125kHz RAB = 250k -30 RAB = 25k -40 -50 -60 -9 VDD/VSS = 2.5V VA = 1V rms D = MIDSCALE 100k 1M FREQUENCY (Hz) -80 10 100 1k 10k 100k 1M FREQUENCY (Hz) 02816-019 10k 02816-016 -12 1k -70 Figure 20. PSRR vs. Frequency Figure 17. -3 dB Bandwidth vs. Resistance (See Figure 33) 0 CODE 0x200 -10 0x100 0x080 GAIN (dB) -20 VDD 0x040 0x020 -30 0x010 VW (FULL SCALE) 0x008 -40 0x004 -50 VDD = 5V VA = 5V VB = 0V TA = 25C 1V/DIV 0x001 -60 10k 100k 1M FREQUENCY (Hz) 10s/DIV 02816-017 1k Figure 21. Power-On Reset Figure 18. Gain vs. Frequency vs. Code, RAB = 25 k (See Figure 33) 2.5196 0 CODE 0x200 -10 2.512 0x080 AMPLITUDE (V) GAIN (dB) 2.508 0x040 0x020 -30 0x010 -40 0x008 2.504 2.500 2.496 2.492 0x004 -50 VDD = VSS = 5V CODE = 0x200 TO 0x1FF 2.516 0x100 -20 02816-020 0x002 2.488 0x002 2.484 0x001 -60 100k 1M FREQUENCY (Hz) 0 20 40 60 80 100 120 TIME (s) Figure 22. Midscale Glitch Energy, RAB = 25 k Figure 19. Gain vs. Frequency vs. Code, RAB = 250 k (See Figure 33) Rev. F | Page 12 of 32 144 02816-021 10k 02816-018 2.4796 1k Data Sheet AD5235 2.60 2.3795 2.376 2.372 WIPER VOLTAGE (V) 2.55 AMPLITUDE (V) 2.368 2.364 2.360 2.356 2.352 2.50 2.45 2.348 2.40 2.3399 60 80 100 120 144 TIME (s) 0 0.5 1.0 1.5 Figure 25. Digital Feedthrough Figure 23. Midscale Glitch Energy, RAB = 250 k THEORECTICAL (IWB_MAX - mA) 100 CS (5V/DIV) 2.0 TIME (s) VDD = 5V TA = 25C CLK (5V/DIV) SDI (5V/DIV) VA = VB = OPEN TA = 25C 10 1 RAB = 25k 0.1 RAB = 250k 0.01 IDD (2mA/DIV) 0 128 256 384 512 640 CODE (Decimal) Figure 26. IWB_MAX vs. Code Figure 24. IDD vs. Time when Storing Data to EEMEM Rev. F | Page 13 of 32 768 896 1023 02816-025 40 02816-022 20 02816-023 0 02816-126 2.344 AD5235 Data Sheet TEST CIRCUITS Figure 27 to Figure 37 define the test conditions used in the Specifications section. NC A DUT B 5V IW W VIN VMS OFFSET BIAS 02816-026 NC = NO CONNECT VOUT OP279 OFFSET GND B Figure 27. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) 02816-030 DUT A W Figure 31. Inverting Gain 5V W B W OFFSET GND A 02816-027 VMS A W VMS2 W VIN VW DUT 2.5V 02816-028 RW = [VMS1 - VMS2]/IW 0.1V ISW CODE = 0x00 PSRR (dB) = 20 LOG VMS PSS (%/%) = ( VDD W + ) B 0.1V ISW - VMS% VDD% 02816-029 W VMS A = NC Figure 30. Power Supply Sensitivity (PSS, PSRR) VSS TO VDD 02816-033 V+ = VDD 10% B -15V RSW = VA ~ VOUT Figure 33. Gain vs. Frequency DUT V+ OP42 B OFFSET GND Figure 29. Wiper Resistance A +15V A B VDD B Figure 32. Noninverting Gain IW = VDD/RNOMINAL VMS1 DUT OFFSET BIAS Figure 28. Potentiometer Divider Nonlinearity Error (INL, DNL) DUT VOUT 02816-031 A V+ OP279 VIN V+ = VDD 1LSB = V+/2N 02816-032 DUT Figure 34. Incremental On Resistance Rev. F | Page 14 of 32 Data Sheet AD5235 NC A VSS GND B ICM W TO OUTPUT PIN 02816-034 VCM NC NC = NO CONNECT VDD NC B1 A2 RDAC2 W2 W1 VSS VOUT B2 CTA = 20 LOG[VOUT/VIN] NC = NO CONNECT CL 50pF IOH Figure 37. Load Circuit for Measuring VOH and VOL (The diode bridge test circuit is equivalent to the application circuit with RPULL-UP of 2.2 k.) 02816-035 A1 RDAC1 VOH (MIN) OR VOL (MAX) 200A Figure 35. Common-Mode Leakage Current VIN IOL 02816-036 VDD DUT 200A Figure 36. Analog Crosstalk Rev. F | Page 15 of 32 AD5235 Data Sheet THEORY OF OPERATION The AD5235 digital potentiometer is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing unlimited changes of resistance settings. The scratchpad register can be programmed with any position setting using the standard SPI serial interface by loading the 24-bit data-word. In the format of the data-word, the first four bits are commands, the following four bits are addresses, and the last 16 bits are data. When a specified value is set, this value can be stored in a corresponding EEMEM register. During subsequent power-ups, the wiper setting is automatically loaded to that value. Storing data to the EEMEM register takes about 15 ms and consumes approximately 2 mA. During this time, the shift register is locked, preventing any changes from taking place. The RDY pin pulses low to indicate the completion of this EEMEM storage. There are also 13 addresses with two bytes each of user-defined data that can be stored in the EEMEM register from Address 2 to Address 14. The scratchpad RDAC register directly controls the position of the digital potentiometer wiper. For example, when the scratchpad register is loaded with all 0s, the wiper is connected to Terminal B of the variable resistor. The scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the EEMEM registers have a program erase/write cycle limitation. BASIC OPERATION The basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loading the serial data input register with Instruction 11 (0xB), Address 0, and the desired wiper position data. When the proper wiper position is determined, the user can load the serial data input register with Instruction 2 (0x2), which stores the wiper position data in the EEMEM register. After 15 ms, the wiper position is permanently stored in nonvolatile memory. Table 5 provides a programming example listing the sequence of the serial data input (SDI) words with the serial data output appearing at the SDO pin in hexadecimal format. The following instructions facilitate the programming needs of the user (see Table 7 for details): 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. SCRATCHPAD AND EEMEM PROGRAMMING Do nothing. Restore EEMEM content to RDAC. Store RDAC setting to EEMEM. Store RDAC setting or user data to EEMEM. Decrement by 6 dB. Decrement all by 6 dB. Decrement by one step. Decrement all by one step. Reset EEMEM content to RDAC. Read EEMEM content from SDO. Read RDAC wiper setting from SDO. Write data to RDAC. Increment by 6 dB. Increment all by 6 dB. Increment by one step. Increment all by one step. Table 5. Write and Store RDAC Settings to EEMEM Registers Table 14 to Table 20 provide programming examples that use some of these commands. SDI 0xB00100 SDO 0xXXXXXX 0x20XXXX 0xB00100 0xB10200 0x20XXXX 0x21XXXX 0xB10200 Action Writes data 0x100 to the RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Stores RDAC1 register content into the EEMEM1 register. Writes Data 0x200 to the RDAC2 register, Wiper W2 moves to 1/2 full-scale position. Stores RDAC2 register contents into the EEMEM2 register. At system power-on, the scratchpad register is automatically refreshed with the value previously stored in the corresponding EEMEM register. The factory-preset EEMEM value is midscale. The scratchpad register can also be refreshed with the contents of the EEMEM register in three different ways. First, executing Instruction 1 (0x1) restores the corresponding EEMEM value. Second, executing Instruction 8 (0x8) resets the EEMEM values of both channels. Finally, pulsing the PR pin refreshes both EEMEM settings. Operating the hardware control PR function requires a complete pulse signal. When PR goes low, the internal logic sets the wiper at midscale. The EEMEM value is not loaded until PR returns high. Rev. F | Page 16 of 32 Data Sheet AD5235 EEMEM PROTECTION VDD WP INPUT 300 DIGITAL INPUT AND OUTPUT CONFIGURATION All digital inputs are ESD protected, high input impedance that can be driven directly from most digital sources. Active at logic low, PR and WP must be tied to VDD, if they are not used. No internal pull-up resistors are present on any digital input pins. To avoid floating digital pins that might cause false triggering in a noisy environment, add pull-up resistors. This is applicable when the device is detached from the driving source when it is programmed. The SDO and RDY pins are open-drain digital outputs that only need pull-up resistors if these functions are used. To optimize the speed and power trade-off, use 2.2 k pull-up resistors. The equivalent serial data input and output logic is shown in Figure 38. The open-drain output SDO is disabled whenever chip-select (CS) is in logic high. ESD protection of the digital inputs is shown in Figure 39 and Figure 40. PR VALID COMMAND COUNTER WP COMMAND PROCESSOR AND ADDRESS DECODE 5V RPULL-UP CLK SERIAL REGISTER (FOR DAISY CHAIN ONLY) SDO CS 02816-037 GND AD5235 SDI Figure 38. Equivalent Digital Input and Output Logic VDD Figure 40. Equivalent WP Input Protection SERIAL DATA INTERFACE The AD5235 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). The 24-bit serial data-word must be loaded with MSB first. The format of the word is shown in Table 6. The command bits (C0 to C3) control the operation of the digital potentiometer according to the command shown in Table 7. A0 to A3 are the address bits. A0 is used to address RDAC1 or RDAC2. Address 2 to Address 14 are accessible by users for extra EEMEM. Address 15 is reserved for factory usage. Table 9 provides an address map of the EEMEM locations. D0 to D9 are the values for the RDAC registers. D0 to D15 are the values for the EEMEM registers. The AD5235 has an internal counter that counts a multiple of 24 bits (a frame) for proper operation. For example, AD5235 works with a 24-bit or 48-bit word, but it cannot work properly with a 23-bit or 25-bit word. To prevent data from mislocking (due to noise, for example), the counter resets, if the count is not a multiple of four when CS goes high but remains in the register if it is multiple of four. In addition, the AD5235 has a subtle feature that, if CS is pulsed without CLK and SDI, the part repeats the previous command (except during power-up). As a result, care must be taken to ensure that no excessive noise exists in the CLK or CS line that might alter the effective number-of-bits pattern. The SPI interface can be used in two slave modes: CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits that dictate SPI timing in the following MicroConverters(R) and microprocessors: ADuC812, ADuC824, M68HC11, MC68HC16R1, and MC68HC916R1. INPUTS 300 GND 02816-038 LOGIC PINS GND 02816-039 The write protect (WP) pin disables any changes to the scratchpad register contents, except for the EEMEM setting, which can still be restored using Instruction 1, Instruction 8, and the PR pulse. Therefore, WP can be used to provide a hardware EEMEM protection feature. Figure 39. Equivalent ESD Digital Input Protection Rev. F | Page 17 of 32 AD5235 Data Sheet DAISY-CHAIN OPERATION The serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting and EEMEM values using Instruction 10 and Instruction 9, respectively. The remaining instructions (Instruction 0 to Instruction 8, Instruction 11 to Instruction 15) are valid for daisy-chaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC (see Figure 41). The SDO pin contains an open-drain N-Ch FET that requires a pull-up resistor, if this function is used. As shown in Figure 41, users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-to-SDI interface may require additional time delay between subsequent devices. When two AD5235s are daisy-chained, 48 bits of data are required. The first 24 bits (formatted 4-bit command, 4-bit address, and 16-bit data) go to U2, and the second 24 bits with the same format go to U1. Keep CS low until all 48 bits are clocked into their respective serial registers. CS is then pulled high to complete the operation. VDD AD5235 SDI U1 SDO CS CLK AD5235 CLK CS Figure 41. Daisy-Chain Configuration Using SDO TERMINAL VOLTAGE OPERATING RANGE The positive VDD and negative VSS power supplies of the AD5235 define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 42). VDD Power-Up Sequence Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 42), it is important to power VDD and VSS first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD and VSS are powered unintentionally. For example, applying 5 V across Terminal A and Terminal B prior to VDD causes the VDD terminal to exhibit 4.3 V. It is not destructive to the device, but it might affect the rest of the user's system. The ideal power-up sequence is GND, VDD and VSS, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD and VSS. Regardless of the power-up sequence and the ramp rates of the power supplies, when VDD and VSS are powered, the power-on preset activates, which restores the EEMEM values to the RDAC registers. SDI U2 SDO 02816-040 MOSI MICROCONTROLLER SCLK SS RP 2.2k The GND pin of the AD5235 is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5235 ground terminal should be joined remotely to the common ground (see Figure 43). The digital input control signals to the AD5235 must be referenced to the device ground pin (GND) and must satisfy the logic level defined in the Specifications section. An internal level-shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. Layout and Power Supply Bypassing It is a good practice to employ compact, minimum lead-length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. Bypass supply leads to the device with 0.01 F to 0.1 F disk or chip ceramic capacitors. Also, apply low ESR, 1 F to 10 F tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance (see Figure 43). AD5235 A VDD C3 10F + W C1 0.1F C4 10F + B C2 0.1F VSS VDD VSS 02816-041 VSS 02816-042 GND Figure 43. Power Supply Bypassing Figure 42. Maximum Terminal Voltages Set by VDD and VSS Rev. F | Page 18 of 32 Data Sheet AD5235 In Table 6, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are applicable to EEMEM. Table 6. 24-Bit Serial Data-Word RDAC EEMEM MSB C3 C2 C3 C2 C1 C1 Command Byte 0 C0 0 0 0 C0 A3 A2 A1 A0 A0 X D15 X D14 X D13 Data Byte 1 X X D12 D11 X D10 D9 D9 D8 D8 D7 D7 D6 D6 Data Byte 0 D5 D4 D3 D5 D4 D3 D2 D2 D1 D1 LSB D0 D0 Command instruction codes are defined in Table 7. Table 7. Command Operation Truth Table 1, 2, 3 Command Byte 0 D9 X B8 D8 X Data Byte 0 B7 B0 D7 ... D0 X ... X ... X X X ... X X ... X X X ... X A0 D15 ... D8 D7 ... D0 0 A0 X ... X X X ... X X X X X ... X X X ... X 0 0 0 A0 X ... X X X ... X 1 X X X X X ... X X X ... X 0 0 0 0 0 0 X ... X X X ... X 0 0 1 A3 A2 A1 A0 X ... X X X ... X 1 0 1 0 0 0 0 A0 X ... X X X ... X 11 1 0 1 1 0 0 0 A0 X ... D9 D8 D7 ... D0 125 1 1 0 0 0 0 0 A0 X ... X X X ... X 135 1 1 0 1 X X X X X ... X X X ... X 145 1 1 1 0 0 0 0 A0 X ... X X X ... X 155 1 1 1 1 X X X X X ... X X X ... X Command Number 0 B23 C3 0 C2 0 C1 0 C0 0 A3 X A2 X 1 0 0 0 1 0 2 0 0 1 0 34 0 0 1 45 0 1 55 0 65 Data Byte 1 A1 X B16 A0 X B15 X X ... ... 0 0 A0 X 0 0 0 A0 1 A3 A2 A1 0 0 0 0 1 0 1 X 0 1 1 0 75 0 1 1 8 1 0 9 1 10 Operation NOP. Do nothing. See Table 19 Restore EEMEM (A0) contents to RDAC (A0) register. See Table 16. Store wiper setting. Store RDAC (A0) setting to EEMEM (A0). See Table 15. Store contents of Serial Register Data Byte 0 and Serial Register Data Bytes 1 (total 16 bits) to EEMEM (ADDR). See Table 18. Decrement by 6 dB. Right-shift contents of RDAC (A0) register, stop at all 0s. Decrement all by 6 dB. Right-shift contents of all RDAC registers, stop at all 0s. Decrement contents of RDAC (A0) by 1, stop at all 0s. Decrement contents of all RDAC registers by 1, stop at all 0s. Reset. Refresh all RDACs with their corresponding EEMEM previously stored values. Read contents of EEMEM (ADDR) from SDO output in the next frame. See Table 19. Read RDAC wiper setting from SDO output in the next frame. See Table 20. Write contents of Serial Register Data Byte 0 and Serial Register Data Byte 1 (total 10 bits) to RDAC (A0). See Table 14. Increment by 6 dB: Left-shift contents of RDAC (A0), stop at all 1s. See Table 17. Increment all by 6 dB. Left-shift contents of all RDAC registers, stop at all 1s. Increment contents of RDAC (A0) by 1, stop at all 1s. See Table 15. Increment contents of all RDAC registers by 1, stop at all 1s. The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a full 24-bit data-word to completely clock out the contents of the serial register. 2 The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register. 3 Execution of these operations takes place when the CS strobe returns to logic high. 4 Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting. 5 The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1. 1 Rev. F | Page 19 of 32 AD5235 Data Sheet ADVANCED CONTROL MODES the RDAC register is then set to Code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale and the data is shifted left, then the data in the RDAC register is automatically set to full scale. This makes the left-shift function as ideal a logarithmic adjustment as possible. The AD5235 digital potentiometer includes a set of user programming features to address the wide number of applications for these universal adjustment devices. Key programming features include the following: * * Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB Step Increment and Decrement Linear Increment and Decrement Instructions The increment and decrement instructions (Instruction 14, Instruction 15, Instruction 6, and Instruction 7) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement where both wiper positions are changed at the same time. For an increment command, executing Instruction 14 automatically moves the wiper to the next resistance segment position. The master increment command, Instruction 15, moves all resistor wipers up by one position. Logarithmic Taper Mode Adjustment Four programming instructions produce logarithmic taper increment and decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where both wiper positions are changed at the same time. The 6 dB increment is activated by Instruction 12 and Instruction 13, and the 6 dB decrement is activated by Instruction 4 and Instruction 5. For example, starting with the wiper connected to Terminal B, executing 11 increment instructions (Command Instruction 12) moves the wiper in 6 dB steps from 0% of the RAB (Terminal B) position to 100% of the RAB position of the AD5235 10-bit potentiometer. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale 1023 code position. Further 6 dB per increment instructions do not change the wiper position beyond its full scale (see Table 8). Left-Shift (+6 dB/Step) 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 Right-Shift(-6 dB/Step) 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000 Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each Right-Shift 4 command and Right-Shift 5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. Figure 44 shows plots of log error [20 x log10 (error/code)] for the AD5235. For example, Code 3 log error = 20 x log10 (0.5/3) = -15.56 dB, which is the worst case. The log error plot is more significant at the lower codes (see Figure 44). 0 -20 The 6 dB step increments and 6 dB step decrements are achieved by shifting the bit internally to the left or right, respectively. The following information explains the nonideal 6 dB step adjustment under certain conditions. Table 8 illustrates the operation of the shifting function on the RDAC register data bits. Each table row represents a successive shift operation. Note that the left-shift 12 and 13 instructions were modified such that, if the data in the RDAC register is equal to zero and the data is shifted left, Rev. F | Page 20 of 32 -40 -60 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 CODE (From 1 to 1023 by 2.0 x 103) Figure 44. Log Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits Are Ideal) 02816-043 * The Right-Shift 4 instruction and Right-Shift 5 instruction are ideal only if the LSB is 0 (ideal logarithmic = no error). If the LSB is 1, the right-shift function generates a linear half-LSB error, which translates to a number-of-bits dependent logarithmic error, as shown in Figure 44. Figure 44 shows the error of the odd numbers of bits for the AD5235. Scratchpad programming to any desirable values Nonvolatile memory storage of the scratchpad RDAC register value in the EEMEM register Increment and decrement instructions for the RDAC wiper register Left and right bit shift of the RDAC wiper register to achieve 6 dB level changes 26 extra bytes of user-addressable nonvolatile memory GAIN (dB) * * Data Sheet AD5235 For example, if RAB_RATED = 250 k and the data in the SDO shows XXXX XXXX 1001 1100 0000 1111, RAB_ACTUAL can be calculated as follows: Using CS to Re-Execute a Previous Command Another subtle feature of the AD5235 is that a subsequent CS strobe, without clock and data, repeats a previous command. MSB: 1 = positive Next 7 LSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 x 2-8 = 0.06 % tolerance = 28.06% Therefore, RAB_ACTUAL = 320.15 k Using Additional Internal Nonvolatile EEMEM The AD5235 contains additional user EEMEM registers for storing any 16-bit data such as memory data for other components, look-up tables, or system identification information. Table 9 provides an address map of the internal storage registers shown in the functional block diagram (see Figure 1) as EEMEM1, EEMEM2, and 26 bytes (13 addresses x 2 bytes each) of User EEMEM. RDAC STRUCTURE The patent-pending RDAC contains multiple strings of equal resistor segments with an array of analog switches that acts as the wiper connection. The number of positions is the resolution of the device. The AD5235 has 1024 connection points, allowing it to provide better than 0.1% setability resolution. Figure 45 shows an equivalent structure of the connections among the three terminals of the RDAC. The SWA and SWB are always on, while the switches, SW(0) to SW(2N - 1), are on one at a time, depending on the resistance position decoded from the data bits. Because the switch is not ideal, there is a 50 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics, if accurate prediction of the output resistance is needed. Table 9. EEMEM Address Map Address 0000 0001 0010 0011 ... 1110 1111 EEMEM Content for ... RDAC11 RDAC2 USER12 USER2 ... USER13 RAB1 tolerance3 RDAC data stored in EEMEM locations is transferred to the corresponding RDAC register at power-on, or when Instruction 1, Instruction 8, and PR are executed. 2 USERx are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using Instruction 3 and Instruction 9, respectively. 3 Read only. 1 SWA A Calculating Actual End-to-End Terminal Resistance SW(2N-1) The resistance tolerance is stored in the EEMEM register during factory testing. The actual end-to-end resistance can, therefore, be calculated, which is valuable for calibration, tolerance matching, and precision applications. Note that this value is read only and the RAB2 matches with RAB1, typically 0.1%. RDAC WIPER REGISTER AND DECODER The resistance tolerance in percentage is contained in the last 16 bits of data in EEMEM Register 15. The format is the sign magnitude binary format with the MSB designate for sign (0 = negative and 1 = positive), the next 7 MSB designate the integer number, and the 8 LSB designate the decimal number (see Table 11). RS W SW(2N-2) RS SW(1) RS SW(0) RS = RAB/2N DIGITAL CIRCUITRY OMITTED FOR CLARITY SWB B 02816-044 EEMEM No. 1 2 3 4 ... 15 16 Figure 45. Equivalent RDAC Structure Table 10. Nominal Individual Segment Resistor Values Device Resolution 1024-Step 25 k 24.4 250 k 244 Table 11. Calculating End-to-End Terminal Resistance Bit Sign Mag D15 D14 D13 Sign 26 25 D12 D11 D10 D9 24 23 22 21 7 Bits for Integer Number D8 20 . Decimal Point Rev. F | Page 21 of 32 D7 D6 D5 D4 D3 D2 D1 D0 2-1 2-2 2-3 2-4 2-5 2-6 8 Bits for Decimal Number 2-7 2-8 AD5235 Data Sheet PROGRAMMING THE VARIABLE RESISTOR Table 12. RWB (D) at Selected Codes for RAB = 25 k Rheostat Operation D (Dec) 1023 512 1 0 The nominal resistance of the RDAC between Terminal A and Terminal B, RAB, is available with 25 k and 250 k with 1024 positions (10-bit resolution). The final digits of the part number determine the nominal resistance value, for example, 25 k = 24.4 ; 250 k = 244 . The 10-bit data-word in the RDAC latch is decoded to select one of the 1024 possible settings. The following description provides the calculation of resistance, RWB, at different codes of a 25 k part. The first connection of the wiper starts at Terminal B for Data 0x000. RWB(0) is 30 because of the wiper resistance, and it is independent of the nominal resistance. The second connection is the first tap point where RWB(1) becomes 24.4 + 30 = 54.4 for Data 0x001. The third connection is the next tap point representing RWB(2) = 48.8 + 30 = 78.8 for Data 0x002, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(1023) = 25006 . See Figure 45 for a simplified diagram of the equivalent RDAC circuit. When RWB is used, Terminal A can be left floating or tied to the wiper. Like the mechanical potentiometer that the RDAC replaces, the AD5235 part is symmetrical. The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. Figure 46 shows the symmetrical programmability of the various terminal connections. When RWA is used, Terminal B can be left floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is RWA (D) = RWB 1024 - D x R AB + RW 1024 (2) For example, the output resistance values in Table 13 are set for the given RDAC latch codes (applies to RAB = 25 k digital potentiometers). 75 Table 13. RWA(D) at Selected Codes for RAB = 25 k 50 D (Dec) 1023 512 1 0 25 0 256 512 CODE (Decimal) 768 1023 02816-045 RWA(D), RWB(D) (% RWF) RWA Output State Full scale Midscale 1 LSB Zero scale (wiper contact resistor) Note that, in the zero-scale condition, a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. 100 0 RWB(D) () 25,006 12,530 54.4 30 Figure 46. RWA(D) and RWB(D) vs. Decimal Code The general equation that determines the programmed output resistance between Terminal Bx and Terminal Wx is RWB (D) = D x R AB + RW 1024 (1) where: D is the decimal equivalent of the data contained in the RDAC register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance. For example, the output resistance values in Table 12 are set for the given RDAC latch codes (applies to RAB = 25 k digital potentiometers). RWA(D) () 54.4 12,530 25,006 25,030 Output State Full scale Midscale 1 LSB Zero scale (wiper contact resistance) The typical distribution of RAB from channel to channel is 0.2% within the same package. Device-to-device matching is process lot dependent upon the worst case of 30% variation. However, the change in RAB with temperature has a 35 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the input voltages applied to Terminal A and Terminal B. For example, connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the wiper that can be any value from 0 V to 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A to Terminal B divided by the 2N position resolution of the potentiometer divider. Rev. F | Page 22 of 32 Data Sheet AD5235 Because the AD5235 can also be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltages applied to Terminal A and Terminal B is VW (D) = D x V AB + V B 1024 Table 16. Restoring the EEMEM Values to RDAC Registers SDI 0x10XXXX SDO 0xXXXXXX Action Restores the EEMEM1 value to the RDAC1 register. (3) Equation 3 assumes that VW is buffered so that the effect of wiper resistance is minimized. Operation of the digital potentiometer in divider mode results in more accurate operation over temperature. Here, the output voltage is dependent on the ratio of the internal resistors and not the absolute value; therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between Terminal A, Terminal B, and Terminal W as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD. Table 17. Using Left-Shift by One to Increment 6 dB Steps SDI 0xC0XXXX SDO 0xXXXXXX 0xC1XXXX 0xC0XXXX Action Moves Wiper 1 to double the present data contained in the RDAC1 register. Moves Wiper 2 to double the present data contained in the RDAC2 register. PROGRAMMING EXAMPLES Table 18. Storing Additional User Data in EEMEM The following programming examples illustrate a typical sequence of events for various features of the AD5235. See Table 7 for the instructions and data-word format. The instruction numbers, addresses, and data appearing at the SDI and SDO pins are in hexadecimal format. SDI 0x32AAAA SDO 0xXXXXXX 0x335555 0x32AAAA Table 14. Scratchpad Programming SDI 0xB00100 SDO 0xXXXXXX 0xB10200 0xB00100 Action Writes Data 0x100 into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Loads Data 0x200 into RDAC2 register, Wiper W2 moves to 1/2 full-scale position. Table 19. Reading Back Data from Memory Locations SDI 0x92XXXX SDO 0xXXXXXX 0x00XXXX 0x92AAAA Table 15. Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM SDI 0xB00100 SDO 0xXXXXXX 0xE0XXXX 0xB00100 0xE0XXXX 0xE0XXXX 0x20XXXX 0xXXXXXX Action Writes Data 0x100 into RDAC1 register, Wiper W1 moves to 1/4 fullscale position. Increments RDAC1 register by one to 0x101. Increments RDAC1 register by one to 0x102. Continue until desired wiper position is reached. Stores RDAC2 register data into EEMEM1. Optionally, tie WP to GND to protect EEMEM values. The EEMEM values for the RDACs can be restored by poweron, by strobing the PR pin, or by the two commands shown in Table 16. Action Stores Data 0xAAAA in the extra EEMEM location USER1. (Allowable to address in 13 locations with a maximum of 16 bits of data.) Stores Data 0x5555 in the extra EEMEM location USER2. (Allowable to address in 13 locations with a maximum of 16 bits of data.) Action Prepares data read from USER1 EEMEM location. NOP Instruction 0 sends a 24-bit word out of SDO, where the last 16 bits contain the contents in USER1 EEMEM location. Table 20. Reading Back Wiper Settings SDI 0xB00200 0xC0XXXX SDO 0xXXXXXX 0xB00200 0xA0XXXX 0xC0XXXX 0xXXXXXX 0xA003FF Action Writes RDAC1 to midscale. Doubles RDAC1 from midscale to full scale. Prepares reading wiper setting from RDAC1 register. Reads back full-scale value from SDO. EVAL-AD5235SDZ EVALUATION KIT Analog Devices, Inc., offers a user-friendly EVAL-AD5235SDZ evaluation kit that can be controlled by a PC in conjunction with the SDP platform. The driving program is self-contained; no programming languages or skills are needed. Rev. F | Page 23 of 32 AD5235 Data Sheet APPLICATIONS INFORMATION BIPOLAR OPERATION FROM DUAL SUPPLIES The AD5235 can be operated from 2.5 V dual supplies, which enable control of ground referenced ac signals or bipolar operation. AC signals as high as VDD and VSS can be applied directly across Terminal A to Terminal B with the output taken from Terminal W. See Figure 47 for a typical circuit connection. +2.5V SS VDD CS CLK SDI SCLK MOSI W MICROCONTROLLER GND 2.5V p-p 1.25V p-p AD5235 B GND Similarly, W and A terminal capacitances are connected to the output (not shown); their effect at this node is less significant and the compensation can be avoided in most cases. HIGH VOLTAGE OPERATION A VSS D = MIDSCALE -2.5V 02816-046 VDD Alternatively, it avoids the ringing or oscillation at the worst case. For critical applications, find C2 empirically to suit the oscillation. In general, C2 in the range of a few picofarads to no more than a few tenths of picofarads is usually adequate for the compensation. Figure 47. Bipolar Operation from Dual Supplies The digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across Terminal A to Terminal B, Terminal W to Terminal A or Terminal W to Terminal B does not exceed |5 V|. When high voltage gain is needed, set a fixed gain in the op amp and let the digital potentiometer control the adjustable input. Figure 49 shows a simple implementation. C GAIN CONTROL COMPENSATION R A digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 48. B A Figure 49. 15 V Voltage Span Control W Similarly, a compensation capacitor, C, may be needed to dampen the potential ringing when the digital potentiometer changes steps. This effect is prominent when stray capacitance at the inverted node is augmented by a large feedback resistor. Typically, a picofarad Capacitor C is adequate to combat the problem. VO 02816-047 VI 0V TO 15V 02816-048 AD5235 V- W Figure 48. Typical Noninverting Gain Amplifier When the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/O term with 20 dB/dec, whereas a typical op amp gain bandwidth product (GBP) has -20 dB/dec characteristics. A large R2 and finite C1 can cause the frequency of this zero to fall well below the crossover frequency. Therefore, the rate of closure becomes 40 dB/dec, and the system has a 0 phase margin at the crossover frequency. If an input is a rectangular pulse or step function, the output can ring or oscillate. Similarly, it is also likely to ring when switching between two gain values; this is equivalent to a stop change at the input. DAC For DAC operation (see Figure 50), it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. The buffer serves the purpose of impedance conversion and can drive heavier loads. Depending on the op amp GBP, reducing the feedback resistor might extend the frequency of the zero far enough to overcome the problem. A better approach is to include a compensation capacitor, C2, to cancel the effect caused by C1. Optimum compensation occurs when R1 x C1 = R2 x C2. This is not an option because of the variation of R2. As a result, one can use the previous relationship and scale C2 as if R2 were at its maximum value. Doing this might overcompensate and compromise the performance when R2 is set at low values. Rev. F | Page 24 of 32 5V 1 U1 VIN AD5235 VOUT GND 2 5V 3 A B AD1582 W V+ AD8601 VO V- A1 Figure 50. Unipolar 10-Bit DAC 02816-049 B U1 VO A1 A R2 250k C1 11pF V+ 5V C2 2.2pF R1 47k 2R 15V Data Sheet AD5235 BIPOLAR PROGRAMMABLE GAIN AMPLIFIER For applications requiring bipolar gain, Figure 51 shows one implementation. Digital Potentiometer U1 sets the adjustment range; the wiper voltage (VW2) can, therefore, be programmed between VI and -KVI at a given U2 setting. Configure OP2177 (A2) as a noninverting amplifier that yields a transfer function of VIN VOUT R2 W1 VDD C OP2177 U1 V- A1 5 -2.5V -2.5VREF V+ AD8552 V- U1 = U2 = AD5235 -2.5V Figure 52. 10-Bit Bipolar DAC VSS PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT 2D2 1 V I 1024 For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 53). VI R2 = 9 x R1 -10 -5 0 5 9.92 10-BIT BIPOLAR DAC 2N7002 AD5235 A Table 21. Result of Bipolar Gain Amplifier R1 = R2 -2 -1 0 1 1.984 VO (5) Table 21 shows the result of adjusting D2, with OP2177 (A2) configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 1024-step resolution. R1 = , R2 = 0 -1 -0.5 0 0.5 0.992 +2.5V A1 In the simpler (and much more usual) case where K = 1, VO is simplified to D2 0 256 512 768 1023 A2 W1 U1 U1 = MIDSCALE R1 Figure 51. Bipolar Programmable Gain Amplifier R2 VO 1 R1 B1 VSS -KV I V+ AD5235 A2 A1 B SIGNAL CC U2 W RBIAS IL V+ AD8601 LD V- 02816-052 B1 B2 ADR421 02816-050 A1 TRIM GND VO V- B2 A2 VI +2.5VREF V+ A2 6 VO V- 02816-051 2 U3 OP2177 V+ AD8552 W2 VI VDD U2 (6) +2.5V (4) where K is the ratio of RWB1/RWA1 set by U1. W1 2D2 VO 1 VREF 1024 U2 VO R2 D2 1 (1 K ) K V I R1 1024 AD5235 Without consideration of the wiper resistance, the output of this circuit is approximately Figure 53. Programmable Booster Voltage Source In this circuit, the inverting input of the op amp forces VO to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch FET N1 (see Figure 53). N1 power handling must be adequate to dissipate (VI - VO) x IL power. This circuit can source a 100 mA maximum with a 5 V supply. For precision applications, a voltage reference, such as ADR421, ADR03, or ADR370, can be applied at Terminal A of the digital potentiometer. If the circuit in Figure 51 is changed with the input taken from a precision reference, U1 is set to midscale, and AD8552 (A2) is configured as a buffer, a 10-bit bipolar DAC can be realized (as shown in Figure 52). Compared to the conventional DAC, this circuit offers comparable resolution but not the precision because of the wiper resistance effects. Degradation of the nonlinearity and temperature coefficient is prominent near the low values of the adjustment range. Alternatively, this circuit offers a unique nonvolatile memory feature that, in some cases, outweighs any shortfalls in precision. Rev. F | Page 25 of 32 AD5235 Data Sheet PROGRAMMABLE CURRENT SOURCE A programmable current source can be implemented with the circuit shown in Figure 54. +5V U1 VS 3 SLEEP OUTPUT GND REF191 6 0V TO (2.048V + VL) R2A + R2B R1 IL = x VW R2B B C1 1F W RS 102 A 4 +5V V+ (8) R2 15k R1 150k - AD5235 For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 55). If the resistors are matched, the load current is OP1177 U2 -5V +15V VL RL 100 IL - 02861-053 V- + -2.048V TO VL +2.5V Figure 54. Programmable Current Source VREF x D RS x 1024 V+ OP2177 + V- A2 +15V A The REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across Terminal W to Terminal B of the digital potentiometer divided by RS. IL = C1 10pF (7) The circuit is simple but be aware that there are two issues. First, dual-supply op amps are ideal because the ground potential of REF191 can swing from -2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system is reduced by half. Second, the voltage compliance at VL is limited to 2.5 V, or equivalently, a 125 load. When higher voltage compliance is needed, consider digital potentiometers, such as, AD5260, AD5280, and AD7376. Figure 55 shows an alternate circuit for high voltage compliance. To achieve higher current, such as when driving a high power LED, replace U1 with an LDO, reduce RS, and add a resistor in series with the A terminal of the digital potentiometer. This limits the current of the potentiometer and increases the current adjustment resolution. + AD5235 W B -2.5V V+ OP2177 - V- R2B 50 -15V R1 150k A1 -15V R2A 14.95k VL RL 500 IL 02816-054 2 PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE Figure 55. Programmable Bidirectional Current Source R2B, in theory, can be made as small as necessary to achieve the current needed within the A2 output current driving capability. In this circuit, OP2177 delivers 5 mA in either direction, and the voltage compliance approaches 15 V. Without the additions of C1 and C2, the output impedance (looking into VL) can be ZO = R1' R2B (R1 + R2A) R1 R2' - R1' (R2A + R2B) (9) ZO can be infinite, if Resistors R1' and R2' match precisely with R1 and R2A + R2B, respectively, which is desirable. On the other hand, if the resistors do not match, ZO can be negative and cause oscillation. As a result, C1, in the range of a few picofarad, is needed to prevent oscillation from the negative impedance. Rev. F | Page 26 of 32 Data Sheet AD5235 PROGRAMMABLE LOW-PASS FILTER In analog-to-digital conversions (ADCs), it is common to include an antialiasing filter to band limit the sampling signal. Therefore, the dual-channel AD5235 can be used to construct a second-order Sallen-Key low-pass filter, as shown in Figure 56. C1 At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R', C = C', and R2 = R2A /(R2B + RDIODE), the oscillation frequency is O = +2.5V A VI B W R B V+ W AD8601 A R RWA (D) = 02816-055 -2.5V ADJUSTED CONCURRENTLY The design equations are VO = VI f 2 f S2 + S + f 2 Q O = 1 R1 R2 C1 C2 (11) 1 1 + R1 C1 R2 C2 (12) (10) First, users should select convenient values for the capacitors. To achieve maximally flat bandwidth, where Q = 0.707, let C1 be twice the size of C2 and let R1 equal R2. As a result, the user can adjust R1 and R2 concurrently to the same setting to achieve the desirable bandwidth. PROGRAMMABLE OSCILLATOR 2 VO = I D R2B + VD 3 In Figure 56 and Figure 57, the frequency tuning requires that both RDACs be adjusted concurrently to the same settings. Because the two channels might be adjusted one at a time, an intermediate state occurs that might not be acceptable for some applications. Of course, the increment/decrement instructions (Instruction 5, Instruction 7, Instruction 13, and Instruction 15) can all be used. Different devices can also be used in daisy-chain mode so that parts can be programmed to the same settings simultaneously. B R 25k A A W +2.5V 2.2nF W + B U1 V+ VO OP1177 - V- -2.5V R = R' = AD5235 R2B = AD5231 D1 = D2 = 1N4148 R2B 10k B W R1 1k A R2A 2.1k D1 D2 AMPLITUDE ADJUSTMENT 02816-056 C 2.2nF R' 25k C' (15) VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium is reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output. In a classic Wien bridge oscillator, the Wien network (R||C, R'C') provides positive feedback, whereas R1 and R2 provide negative feedback (see Figure 57). VP (14) When the frequency is set, the oscillation amplitude can be turned by R2B because Figure 56. Sallen-Key Low-Pass Filter FREQUENCY ADJUSTMENT 1024 - D x R AB + RW 1024 At resonance, setting R2/R1 = 2 balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure that the oscillation can start. On the other hand, the alternate turn-on of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2, momentarily stabilizing the oscillation. VO V- U1 C2 Q= (13) where R is equal to RWA such that : R2 R1 1 1 or fO = RC 2RC Figure 57. Programmable Oscillator with Amplitude Control Rev. F | Page 27 of 32 AD5235 Data Sheet OPTICAL TRANSMITTER CALIBRATION WITH ADN2841 RESISTANCE SCALING The AD5235, together with the multirate 2.7 Gbps laser diode driver, ADN2841, forms an optical supervisory system in which the dual digital potentiometers can be used to set the laser average optical power and extinction ratio (see Figure 58). The AD5235 is particularly suited for the optical parameter settings because of its high resolution and superior temperature coefficient characteristics. The AD5235 offers 25 k or 250 k nominal resistance. When users need lower resistance but must maintain the number of adjustment steps, they can parallel multiple devices. For example, Figure 59 shows a simple scheme of paralleling two channels of RDACs. To adjust half the resistance linearly per step, program both RDACs concurrently with the same settings. A2 A1 W1 B2 W2 02816-058 B1 VCC VCC Figure 59. Reduce Resistance by Half with Linear Adjustment Characteristics IMPD In voltage divider mode, by paralleling a discrete resistor, as shown in Figure 60, a proportionately lower voltage appears at Terminal A to Terminal B. This translates into a finer degree of precision because the step size at Terminal W is smaller. The voltage can be found as ADN2841 PSET IMODP B1 RDAC1 IBIAS A2 W2 EEMEM CLKN B2 RDAC2 VW (D) = ERSET CLKN CLKP DATAP DATAN (RAB // R2) D x x VDD R3 + RAB // R2 1024 (16) VDD R3 02816-057 SDI DATAN CONTROL DATAP CLK A1 W1 EEMEM CLKP CS R2 Figure 58. Optical Supervisory System A R1 W B 0 Figure 60. Lowering the Nominal Resistance Figure 59 and Figure 60 show that the digital potentiometers change steps linearly. Alternatively, pseudo log taper adjustment is usually preferred in applications such as audio control. Figure 61 shows another type of resistance scaling. In this configuration, the smaller the R2 with respect to RAB, the more the pseudo log taper characteristic of the circuit behaves. A1 B1 W1 R 02816-060 The ADN2841 is a 2.7 Gbps laser diode driver that uses a unique control algorithm to manage the average power and extinction ratio of the laser after its initial factory calibration. The ADN2841 stabilizes the data transmission of the laser by continuously monitoring its optical power and correcting the variations caused by temperature and the degradation of the laser over time. In the ADN2841, the IMPD monitors the laser diode current. Through its dual-loop power and extinction ratio control calibrated by the dual RDACs of the AD5235, the internal driver controls the bias current, IBIAS, and consequently the average power. It also regulates the modulation current, IMODP, by changing the modulation current linearly with slope efficiency. Therefore, any changes in the laser threshold current or slope efficiency are compensated for. As a result, the optical supervisory system minimizes the laser characterization efforts and, therefore, enables designers to apply comparable lasers from multiple sources. 02816-059 AD5235 Figure 61. Resistor Scaling with Pseudo Log Adjustment Characteristics The equation is approximated as REQUIVALENT = D x R AB + 51, 200 D x R AB + 51, 200 + 1024 x R (17) Users should also be aware of the need for tolerance matching as well as for temperature coefficient matching of the components. Rev. F | Page 28 of 32 Data Sheet AD5235 RDAC CIRCUIT SIMULATION MODEL In rheostat mode operation, such as gain control, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems (see Figure 62). Because of the inherent matching of the silicon process, it is practical to apply the dual-channel device in this type of application. As such, R1 can be replaced by one of the channels of the digital potentiometer and programmed to a specific value. R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. This approach also tracks the resistance drift over time. As a result, these less than ideal parameters become less sensitive to system variations. The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5235 (25 k resistor) measures 125 kHz at half scale. Figure 17 provides the large signal bode plot characteristics of the two available resistor versions, 25 k and 250 k. A parasitic simulation model is shown in Figure 64. A 80pF W The following code provides a macro model net list for the 25 k RDAC: C1 - AD8601 + VO 02816-061 U1 * REPLACED WITH ANOTHER CHANNEL OF RDAC Figure 62. Linear Gain Control with Tracking Resistance Tolerance, Drift, and Temperature Coefficient Note that the circuit in Figure 63 can track tolerance, temperature coefficient, and drift in this particular application. The characteristic of the transfer function is, however, a pseudo log rather than a linear gain function. A R .PARAM D = 1024, RDAC = 25E3 * .SUBCKT DPOT (A, W, B) * CA A 0 11E-12 RWA A W {(1-D/1024)* RDAC + 30} CW W 0 80E-12 RWB W B {D/1024 * RDAC + 30} CB B 0 11E-12 * .ENDS DPOT B C1 W Vi + U1 VO 02816-062 - AD8601 CB 11pF Figure 64. RDAC Circuit Simulation Model (RDAC = 25 k) W Vi B CA 11pF B R2 A R1* RDAC 25k 02816-063 RESISTANCE TOLERANCE, DRIFT, AND TEMPERATURE COEFFICIENT MISMATCH CONSIDERATIONS Figure 63. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift Rev. F | Page 29 of 32 AD5235 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 0.75 0.60 0.45 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD5235BRUZ25 AD5235BRUZ25-RL7 AD5235BRUZ250 AD5235BRUZ250-R7 EVAL-AD5235SDZ RAB (k) 25 25 250 250 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Package Option RU-16 RU-16 RU-16 RU-16 Ordering Quantity 96 1,000 96 1,000 1 Branding 3 5235B25 5235B25 5235B250 5235B250 Z = RoHS Compliant Part. The evaluation board is shipped with the 25 k RAB resistor option; however, the board is compatible with all available resistor value options. 3 Line 1 contains the ADI logo followed by the date code, YYWW. Line 2 contains the model number followed by the end-to-end resistance value (note: D = 250 k). --OR-- Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YYWW. 1 2 Rev. F | Page 30 of 32 Data Sheet AD5235 NOTES Rev. F | Page 31 of 32 AD5235 Data Sheet NOTES (c)2004-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02816-0-6/12(F) Rev. F | Page 32 of 32