Nonvolatile Memory, Dual
1024-Position Digital Potentiometer
Data Sheet
AD5235
Rev. F
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FEATURES
Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C
2.7 V to 5 V single supply or ±2.5 V dual supply
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined
information
1M programming cycles
100-year typical data retention
APPLICATIONS
DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
GENERAL DESCRIPTION
The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer2 with 1024-step resolution, offering
guaranteed maximum low resistor tolerance error of ±8%.
The device performs the same electronic adjustment function
as a mechanical potentiometer with enhanced resolution, solid
state reliability, and superior low temperature coefficient per-
formance. The versatile programming of the AD5235 via an
SPI®-compatible serial interface allows 16 modes of operation
and adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log taper
adjustment, wiper setting readback, and extra EEMEM1 for user-
defined information such as memory data for other components,
look-up table, or system identification information.
FUNCTIONAL BLOCK DIAGRAM
ADDR
DECODE
AD5235
RDAC1
SERIAL
INTERFACE
CS
CLK
SDI
SDO
PR
WP
RDY
RDAC1
REGISTER
EEMEM1
RDAC2
REGISTER
EEMEM2
26 BYT E S
RTOL* USER EEMEM
POWER-ON
RESET
W1
B1
RDAC2
W2
B2
A1
V
DD
A2
V
SS
GND
02816-001
EEMEM
CONTROL
*RAB TOLE RANCE
Figure 1.
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC2 register, which sets the
resistance between Terminal W and Terminal A and Terminal W
and Terminal B. This setting can be stored into the EEMEM
and is restored automatically to the RDAC register during
system power-on.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at
a time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.
The AD5235 patterned resistance tolerance is stored in the
EEMEM. The actual end-to-end resistance can, therefore, be
known by the host processor in readback mode. The host can
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.
The AD5235 is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
AD5235 Data Sheet
Rev. F | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—25 kΩ, 250 kΩ Versions ............... 4
Interface Timing and EEMEM Reliability Characteristics—
25 kΩ, 250 kΩ Versions ............................................................... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Test Circuits ................................................................................. 14
Theory of Operation ...................................................................... 16
Scratchpad and EEMEM Programming .................................. 16
Basic Operation .......................................................................... 16
EEMEM Protection .................................................................... 17
Digital Input and Output Configuration................................. 17
Serial Data Interface ................................................................... 17
Daisy-Chain Operation ............................................................. 18
Terminal Voltage Operating Range .......................................... 18
Advanced Control Modes ......................................................... 20
RDAC Structure .......................................................................... 21
Programming the Variable Resistor ......................................... 22
Programming the Potentiometer Divider ............................... 22
Programming Examples ............................................................ 23
EVAL-AD5235SDZ Evaluation Kit .......................................... 23
Applications Information .............................................................. 24
Bipolar Operation from Dual Supplies.................................... 24
Gain Control Compensation .................................................... 24
High Voltage Operation ............................................................ 24
DAC .............................................................................................. 24
Bipolar Programmable Gain Amplifier ................................... 25
10-Bit Bipolar DAC .................................................................... 25
Programmable Voltage Source with Boosted Output ........... 25
Programmable Current Source ................................................ 26
Programmable Bidirectional Current Source ......................... 26
Programmable Low-Pass Filter ................................................ 27
Programmable Oscillator .......................................................... 27
Optical Transmitter Calibration with ADN2841 ................... 28
Resistance Scaling ...................................................................... 28
Resistance Tolerance, Drift, and Temperature Coefficient
Mismatch Considerations ......................................................... 29
RDAC Circuit Simulation Model ............................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Data Sheet AD5235
Rev. F | Page 3 of 32
REVISION HISTORY
6/12—Rev. E to Rev. F
Changes to Table 1 Conditions ........................................................ 4
Removed Positive Supply Current RDY and/or SDO Floating
Parameters and Negative Supply Current RDY and/or SDO
Floating Parameters, Table 1 ............................................................ 5
Added Endnote 2 to Ordering Guide ........................................... 30
4/11—Rev. D to Rev. E
Changes to Figure 12 ...................................................................... 11
4/11—Rev. C to Rev. D
Changes to EEMEM Performance .............................. Throughout
Changes to Features and General Descriptions Sections ............. 1
Changes to Specifications Section ................................................... 4
Changes to Pin 5, Pin 13, Pin 14 Descriptions .............................. 9
Changes to Typical Performance Characteristics Section ......... 10
Changes to Table 7 .......................................................................... 19
Changes to Table 9 .......................................................................... 21
Changes to Rheostat Operation Section, Table 12, Table 13 ..... 22
Changes to Table 16, Table 19, and EVAL-AD5235SDZ
Evaluation Kit Section .................................................................... 23
Changes to RDAC Circuit Simulation Model Section ............... 29
Updated Outline Dimensions ........................................................ 30
Changes to Ordering Guide ........................................................... 30
4/09—Rev. B to Rev. C
Changes to Figure 1........................................................................... 1
Changes to Specifications ................................................................. 3
Changes to SDO, Description Column, Table 4 ............................ 8
Changes to Figure 18 ...................................................................... 11
Changes to Theory of Operation Section .................................... 14
Changes to Serial Data Interface Section ..................................... 15
Changes to Linear Increment and Decrement Instructions
Section, Logarithmic Taper Mode Adjustment Section, and
Figure 42 ........................................................................................... 18
Changes to Rheostat Operations Section ..................................... 20
Changes to Bipolar Programmable Gain Amplifier Section,
Figure 49, Table 21, and 10-Bit Bipolar DAC Section ................ 23
Changes to Programmable Oscillator Section and Figure 56 ... 25
Changes to Ordering Guide ........................................................... 28
7/04—Rev. A to Rev. B
Updated Formatting .......................................................... Universal
Edits to Features, General Description, and Block Diagram ...... 1
Changes to Specifications................................................................. 3
Replaced Timing Diagrams ............................................................. 6
Changes to Absolute Maximum Ratings........................................ 7
Changes to Pin Function Descriptions .......................................... 8
Changes to Typical Performance Characteristics ......................... 9
Additional Test Circuit (Figure 36)................................................. 9
Edits to Theory of Operation ........................................................ 14
Edits to Applications ....................................................................... 23
Updated Outline Dimensions........................................................ 27
8/02—Rev. 0 to Rev. A
Change to Features and General Description ............................... 1
Change to Specifications .................................................................. 2
Change to Calculating Actual End-to-End Terminal
Resistance Section ........................................................................... 14
AD5235 Data Sheet
Rev. F | Page 4 of 32
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted.
These specifications apply to versions with a date code 1209 or later.
Table 1.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (All RDACs)
Resistor Differential Nonlinearity
2
R-DNL
R
WB
−1
+1
LSB
Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB
Nominal Resistor Tolerance ∆RAB/RAB −8 +8 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW IW = 1 V/RWB, code = midscale
VDD = 5 V 30 60 Ω
VDD = 3 V 50 Ω
Nominal Resistance Match RAB1/RAB2 ±0.1 %
DC CHARACTERISTICS—
POTENTIOMETER DIVIDER MODE
(All RDACs)
Resolution N 10 Bits
Differential Nonlinearity3 DNL −1 +1 LSB
Integral Nonlinearity3 INL −1 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T × 106 Code = midscale 15 ppm/°C
Full-Scale Error VWFSE Code = full scale −6 0 LSB
Zero-Scale Error VWZSE Code = zero scale 0 4 LSB
RESISTOR TERMINALS
Terminal Voltage Range4 VA, VB, VW VSS VDD V
Capacitance Ax, Bx5 CA, CB f = 1 MHz, measured to GND,
code = midscale
11 pF
Capacitance Wx5 CW f = 1 MHz, measured to GND,
code = midscale
80 pF
Common-Mode Leakage Current5, 6 ICM VW = VDD/2 0.01 ±1 µA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
2.0 V
Input Logic Low VIL With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
0.5 V
Output Logic High (SDO, RDY) VOH RPULL-UP = 2.2 kΩ to 5 V (see
Figure 38)
4.9 V
Output Logic Low
V
OL
I
OL
= 1.6 mA, V
LOGIC
= 5 V (see
Figure 38)
0.4
V
Input Current IIL VIN = 0 V or VDD ±1 µA
Input Capacitance5 CIL 5 pF
Data Sheet AD5235
Rev. F | Page 5 of 32
Parameter Symbol Conditions Min Typ 1 Max Unit
POWER SUPPLIES
Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA
Negative Supply Current
I
SS
V
DD
= +2.5 V, V
SS
= −2.5 V
VIH = VDD or VIL = GND −4 −2 µA
EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
2 mA
ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA
EEMEM Restore Mode Current7 IDD (restore) VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
320 µA
ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA
Power Dissipation8 PDISS VIH = VDD or VIL = GND 10 30 µW
Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.006 0.01 %/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth BW −3 dB, RAB = 25 kΩ/250 kΩ 125/12 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,
f = 1 kHz, code = midscale
R
AB
= 25 kΩ
0.009
%
RAB = 250 kΩ 0.035 %
VW Settling Time tS VA = VDD, VB = 0 V, VW = 0.50% error
band, from zero scale to midscale
RAB = 25 kΩ 4 µs
RAB = 250 kΩ 36 µs
Resistor Noise Density
e
N_WB
R
AB
= 25 kΩ/250 kΩ
20/64
nV/√Hz
Crosstalk (CW1/CW2) CT VA1 = VDD, VB1 = VSS , measured VW2
with VW1 making full-scale change,
RAB = 25 kΩ/250 kΩ
30/60
nV-s
Analog Crosstalk CTA VAB2 = 5 V p-p, f = 1 kHz, measured
VW1, Code 1 = midscale, Code 2 =
full scale, RAB = 25 kΩ/250 kΩ
−110/−100
dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IWB = (VDD − 1)/RWB (see Figure 27).
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28).
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.
7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.
8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
AD5235 Data Sheet
Rev. F | Page 6 of 32
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter Symbol Conditions Min Typ 1 Max Unit
Clock Cycle Time (tCYC) t1 20 ns
CS Setup Time t2 10 ns
CLK Shutdown Time to CS Rise t3 1 tCYC
Input Clock Pulse Width
t
4
, t
5
Clock level high or low
10
ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire t8 40 ns
CS to SDO-SPI Line Release t9 50 ns
CLK to SDO Propagation Delay
2
t
10
R
P
= 2.2 kΩ, C
L
< 20 pF
50
ns
CLK to SDO Data Hold Time
t
11
R
P
= 2.2 kΩ, C
L
< 20 pF
0
ns
CS High Pulse Width3 t12 10 ns
CS High to CS High3 t13 4 tCYC
RDY Rise to CS Fall t14 0 ns
CS Rise to RDY Fall Time t15 0.15 0.3 ms
Store EEMEM Time4, 5 t16 Applies to Instructions 0x2, 0x3 15 50 ms
Read EEMEM Time
4
t
16
Applies to Instructions 0x8, 0x9, 0x10
7
30
µs
CS Rise to Clock Rise/Fall Setup t17 10 ns
Preset Pulse Width (Asynchronous)6 tPRW 50 ns
Preset Response Time to Wiper Setting6 tPRESP PR pulsed low to refresh wiper positions 30 µs
Power-On EEMEM Restore Time6 tEEMEM 30 µs
FLASH/EE MEMORY RELIABILITY
Endurance7 TA = 25°C 1 MCycles
100 kCycles
Data Retention
8
100
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3 Valid for commands that do not activate the RDY pin.
4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 µs.
5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6 Not shown in Figure 2 and Figure 3.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5235
Rev. F | Page 7 of 32
Timing Diagrams
CPOL = 1
t
12
t
13
t
3
t
17
t
9
t
11
t
5
t
4
t
2
t
1
CLK
t8
B24* B23 (MS B) B0 (L S B)
B23 (MS B)
HIGH
OR LOW HIGH
OR LOW
B23 B0
B0 (L S B)
RDY
CPHA = 1
t10
t7
t6
t14 t15 t16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB O F T HE CHARACTER PRE V IO USLY TRANS M IT TED.
THE CP O L = 1 MICRO CONTROL LER CO M M AND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
SDO
SDI
02816-002
CS
Figure 2. CPHA = 1 Timing Diagram
t12
t13
t3
t17
t9
t
11
t5
t4
t2
t
1
CLK
CPOL = 0
t
8
B23 (MSB OUT) B0 (LSB)
SDO
B23 (MSB IN)
B23 B0
HIGH
OR LOW HIGH
OR LOW
B0 (LSB)
SDI
RDY
CPHA = 0
t
10
t
7
t
6
t
14
t
15
t
16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
*
CS
02816-003
Figure 3. CPHA = 0 Timing Diagram
AD5235 Data Sheet
Rev. F | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
VSS to GND +0.3 V to −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW
Pulsed1 ±20 mA
Continuous ±2 mA
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec)
215°C
Infrared (15 sec) 220°C
Thermal Resistance
Junction-to-Ambient θJA,TSSOP-16 150°C/W
Junction-to-Case θJC, TSSOP-16 28°C/W
Package Power Dissipation
(T
J
max − T
A
)/θ
JA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Includes programming of nonvolatile memory.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD5235
Rev. F | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDI
SDO
GND
A1
VSS
W1
CLK
B1
CS
PR
WP
VDD
A2
02816-005
W2
B2
RDY
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5235
TOP VIEW
(No t t o Scal e)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
4
GND
Ground Pin, Logic Ground Reference.
5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
6 A1 Terminal A of RDAC1.
7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
8 B1 Terminal B of RDAC1.
9 B2 Terminal B of RDAC2.
10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
11 A2 Terminal A of RDAC2.
12 VDD Positive Power Supply.
13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.
14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PR.
AD5235 Data Sheet
Rev. F | Page 10 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
DIGITAL CODE
0200 400 600 1000
INL ERRO R ( LSB)
800
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15 –40°C
+25°C
+85°C
02816-006
Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
DIGITAL CODE
0200 400 600 1000
DNL E RROR (L S B)
800
0.16
–0.04
–0.02
0.02
0
0.04
0.06
0.08
0.10
0.12
0.14
02816-007
–40°C
+25°C
+85°C
Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
DIGITAL CODE
0200 400 600 1000
INL ERRO R ( LSB)
800
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15 –40°C
+25°C
+85°C
02816-008
Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
DIGITAL CODE
0200 400 600 1000
DNL E RROR (L S B)
800
0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
02816-009
–40°C
+25°C
+85°C
Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
CODE ( Decimal)
POTENTIOMETER MODE TEMPCO (ppm/°C)
200
180
160
140
120
100
80
60
40
20
001023768512256
25kΩ
250kΩ
02816-010
Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco
02816-011
CODE ( Decimal)
RHEOSTAT MODE TEMPCO (p p m/° C)
200
180
160
140
120
100
80
60
40
20
001023768512256
25kΩ
250kΩ
Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco
Data Sheet AD5235
Rev. F | Page 11 of 32
CODE ( Decimal)
0200 400 800600 1000
WIPER ON RESISTANCE (Ω)
60
50
40
30
20
10
0
2.7V
3.0V
3.3V
5.0V
5.5V
02816-012
Figure 11. Wiper On Resistance vs. Code
TEMPERATURE (°C)
–40 –20 020 40 60 8580
I
DD
/I
SS
(µA)
3
–3
–2
–1
0
1
2
I
DD
= 2.7V
I
DD
= 3.3V
I
DD
= 3.0V
I
DD
= 5.5V
I
DD
= 5.0V
I
SS
= 2.7V
I
SS
= 3.3V
I
SS
= 3.0V
I
SS
= 5.5V
I
SS
= 5.0V
02816-013
Figure 12. IDD vs. Temperature
FREQUENCY (MHz)
11098765432
IDD (µ A)
50
10
20
30
40
0
FULL SCALE
MIDSCALE
ZE RO SCAL E
02816-014
Figure 13. IDD vs. Clock Frequency, RAB = 25 kΩ
0
100
200
300
400
I
DD
(µA)
VDIO (V)
2.7V
3.0V
3.3V
5.0V
5.5V
02816-015
012345
Figure 14. IDD vs. Digital Input Voltage
0.12
0
0.02
0.04
0.06
0.08
0.10
10 100 1k 10k 100k
THD + N ( %)
FRE QUENCY ( Hz )
250kΩ
25kΩ
02816-115
Figure 15. THD + Noise vs. Frequency
10
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 110
THD + N ( %)
AMPLITUDE (V rms)
250kΩ
25kΩ
02816-116
Figure 16. THD + Noise vs. Amplitude
AD5235 Data Sheet
Rev. F | Page 12 of 32
FREQUENCY (Hz)
02816-016
1k 10k 100k 1M
GAI N (dB)
3
–3
0
–6
–9
–12
V
DD
/V
SS
=±2.5V
V
A
= 1V rms
D = MI DS CALE
f
–3dB
= 12kHz
R
AB
= 250kΩ
R
AB
= 25k Ω
f
–3dB
= 125kHz
Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 33)
FREQUENCY (Hz)
02816-017
1k 10k 100k 1M
GAI N (dB)
0
–20
–10
–30
–40
–50
–60
CODE 0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
Figure 18. Gain vs. Frequency vs. Code, RAB = 25 kΩ (See Figure 33)
FREQUENCY (Hz)
02816-018
1k 10k 100k 1M
0
–20
–10
–30
–40
–50
–60
GAI N (dB)
CODE 0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
Figure 19. Gain vs. Frequency vs. Code, RAB = 250 kΩ (See Figure 33)
FRE QUENCY ( Hz )
10 100 1k 10k 100k 1M
PSRR (d B)
–80
–60
–70
–50
–40
–30
–20
–10
0
RAB = 250kΩ
VDD = 5V ± 10% AC
VSS = 0V, VA = 4V , VB = 0V
MEAS URE D AT VWWITH CODE = 0x200
TA= 25° C
RAB = 25k Ω
02816-019
Figure 20. PSRR vs. Frequency
02816-020
V
DD
= 5V
V
A
= 5V
V
B
= 0V
T
A
= 25° C
1V/DIV
10µs/DIV
V
DD
V
W
(FULL SCALE)
Figure 21. Power-On Reset
TIME (µs)
020 40 60 80 100 120 144
AMPL IT UDE (V)
2.5196
2.484
2.488
2.492
2.496
2.500
2.504
2.508
2.512
2.516
2.4796
V
DD
= V
SS
= 5V
CODE = 0x200 TO 0x1F F
02816-021
Figure 22. Midscale Glitch Energy, RAB = 25 kΩ
Data Sheet AD5235
Rev. F | Page 13 of 32
TIME (µs)
AMPL IT UDE (V)
020 40 60 80 100 120 144
2.3795
2.344
2.348
2.352
2.356
2.360
2.364
2.368
2.372
2.376
2.3399
02816-022
Figure 23. Midscale Glitch Energy, RAB = 250 kΩ
02816-023
CS (5V/DIV)
CLK ( 5V /DIV )
SDI (5V/DIV)
I
DD
(2mA/ DIV)
V
DD
= 5V
T
A
= 25° C
Figure 24. IDD vs. Time when Storing Data to EEMEM
2.60
2.55
2.50
2.45
2.40 00.5 1.0 1.5 2.0
WIPER VOL T AGE (V)
TIME (µs)
02816-126
Figure 25. Digital Feedthrough
CODE ( Decimal)
02816-025
100
1
0.01 1023
THE ORECT ICAL ( IWB_MAX – mA)
0.1
10
896768640512384128 2560
VA = VB = OPEN
TA = 25° C
RAB = 25k Ω
RAB = 250kΩ
Figure 26. IWB_MAX vs. Code
AD5235 Data Sheet
Rev. F | Page 14 of 32
TEST CIRCUITS
Figure 27 to Figure 37 define the test conditions used in the Specifications section.
AW
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
02816-026
Figure 27. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
AW
B
DUT
V
MS
V+
02816-027
V+ = V
DD
1LSB = V + /2
N
Figure 28. Potentiometer Divider Nonlinearity Error (INL, DNL)
AW
B
DUT I
W
= V
DD
/R
NOMINAL
V
MS1
V
MS2
V
W
02816-028
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 29. Wiper Resistance
AW
BV
MS
V+ = V
DD
±10%
PSRR (dB) = 20 LOG V
MS
ΔV
DD
()
~
V
A
V
DD
ΔV
MS%
ΔV
DD%
PSS (%/%) =
V+
02816-029
Δ
Figure 30. Power Supply Sensitivity (PSS, PSRR)
OFFSET BIAS
OFFSET
GND
ABDUT
W5V
V
IN
V
OUT
OP279
02816-030
Figure 31. Inverting Gain
OFFSET BIAS
OFFSET
GND ABDUT
W
5V
V
IN
V
OUT
OP279
02816-031
Figure 32. Noninverting Gain
OFFSET
GND
A
B
DUT W
+15V
V
IN
V
OUT
OP42
–15V
2.5V
02816-032
Figure 33. Gain vs. Frequency
+
–
DUT CODE = 0x00
0.1V
V
SS
TO V
DD
R
SW
=0.1V
I
SW
I
SW
W
B
A = NC
02816-033
Figure 34. Incremental On Resistance
Data Sheet AD5235
Rev. F | Page 15 of 32
DUT
V
SS
I
CM
W
B
V
DD
NC
NC
V
CM
GND
A
NC = NO CONNECT
02816-034
Figure 35. Common-Mode Leakage Current
02816-035
A1
RDAC1 RDAC2
W1
NC
B1
A2
W2
B2
CTA = 20 LOG[VOUT/VIN]
NC = NO CONNECT
VIN VOUT
VSS
VDD
Figure 36. Analog Crosstalk
02816-036
200µA IOL
200µA IOH
VOH (MIN)
OR
VOL (MAX)
TO OUTPUT
PIN CL
50pF
Figure 37. Load Circuit for Measuring VOH and VOL
(The diode bridge test circuit is equivalent to the
application circuit with RPULL-UP of 2.2 kΩ.)
AD5235 Data Sheet
Rev. F | Page 16 of 32
THEORY OF OPERATION
The AD5235 digital potentiometer is designed to operate as a
true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratchpad register, allowing unlimited changes of resistance
settings. The scratchpad register can be programmed with any
position setting using the standard SPI serial interface by loading
the 24-bit data-word. In the format of the data-word, the first four
bits are commands, the following four bits are addresses, and the
last 16 bits are data. When a specified value is set, this value can
be stored in a corresponding EEMEM register. During subsequent
power-ups, the wiper setting is automatically loaded to that value.
Storing data to the EEMEM register takes about 15 ms and
consumes approximately 2 mA. During this time, the shift
register is locked, preventing any changes from taking place.
The RDY pin pulses low to indicate the completion of this
EEMEM storage. There are also 13 addresses with two bytes
each of user-defined data that can be stored in the EEMEM
register from Address 2 to Address 14.
The following instructions facilitate the programming needs
of the user (see Table 7 for details):
0. Do nothing.
1. Restore EEMEM content to RDAC.
2. Store RDAC setting to EEMEM.
3. Store RDAC setting or user data to EEMEM.
4. Decrement by 6 dB.
5. Decrement all by 6 dB.
6. Decrement by one step.
7. Decrement all by one step.
8. Reset EEMEM content to RDAC.
9. Read EEMEM content from SDO.
10. Read RDAC wiper setting from SDO.
11. Write data to RDAC.
12. Increment by 6 dB.
13. Increment all by 6 dB.
14. Increment by one step.
15. Increment all by one step.
Table 14 to Table 20 provide programming examples that use
some of these commands.
SCRATCHPAD AND EEMEM PROGRAMMING
The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratchpad
register is loaded with all 0s, the wiper is connected to Terminal B
of the variable resistor. The scratchpad register is a standard
logic register with no restriction on the number of changes
allowed, but the EEMEM registers have a program erase/write
cycle limitation.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the proper
wiper position is determined, the user can load the serial data
input register with Instruction 2 (0x2), which stores the wiper
position data in the EEMEM register. After 15 ms, the wiper
position is permanently stored in nonvolatile memory.
Table 5 provides a programming example listing the sequence
of the serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.
Table 5. Write and Store RDAC Settings to EEMEM Registers
SDI SDO Action
0xB00100 0xXXXXXX Writes data 0x100 to the RDAC1 register,
Wiper W1 moves to 1/4 full-scale position.
0x20XXXX 0xB00100 Stores RDAC1 register content into the
EEMEM1 register.
0xB10200 0x20XXXX Writes Data 0x200 to the RDAC2 register,
Wiper W2 moves to 1/2 full-scale position.
0x21XXXX 0xB10200 Stores RDAC2 register contents into the
EEMEM2 register.
At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets the EEMEM values
of both channels. Finally, pulsing the PR pin refreshes both
EEMEM settings. Operating the hardware control PR function
requires a complete pulse signal. When PR goes low, the internal
logic sets the wiper at midscale. The EEMEM value is not
loaded until PR returns high.
Data Sheet AD5235
Rev. F | Page 17 of 32
EEMEM PROTECTION
The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature.
DIGITAL INPUT AND OUTPUT CONFIGURATION
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to VDD, if they are not used. No
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.
The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.
The equivalent serial data input and output logic is shown in
Figure 38. The open-drain output SDO is disabled whenever
chip-select (CS) is in logic high. ESD protection of the digital
inputs is shown in Figure 39 and Figure 40.
VALID
COMMAND
COUNTER
COMMAND
PROCESSOR
AND ADDRESS
DECODE
(F OR DAIS Y
CHAIN ONLY )
SERIAL
REGISTER
CLK
SDI
5V
R
PULL-UP
SDO
GND
PR WP
AD5235
02816-037
CS
Figure 38. Equivalent Digital Input and Output Logic
LOGIC
PINS
V
DD
GND
INPUTS
300
Ω
02816-038
Figure 39. Equivalent ESD Digital Input Protection
V
DD
GND
INPUT
300
Ω
02816-039
WP
Figure 40. Equivalent WP Input Protection
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS, and CLK). The 24-bit serial data-word must be
loaded with MSB first. The format of the word is shown in Table 6.
The command bits (C0 to C3) control the operation of the digital
potentiometer according to the command shown in Table 7. A0
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage. Table 9 provides an
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.
The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when CS goes high but remains in the register if it
is multiple of four. In addition, the AD5235 has a subtle feature
that, if CS is pulsed without CLK and SDI, the part repeats the
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the CLK or
CS line that might alter the effective number-of-bits pattern.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer
to the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.
AD5235 Data Sheet
Rev. F | Page 18 of 32
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 41). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 41, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then p<