AD5235BRUZ25-RL7 - ANALOG DEVICES

Nonvolatile Memory, Dual

1024-Position Digital Potentiometer

Data Sheet

AD5235

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Dual-channel, 1024-position resolution

25 kΩ, 250 kΩ nominal resistance

Maximum ±8% nominal resistor tolerance error

Low temperature coefficient: 35 ppm/°C

2.7 V to 5 V single supply or ±2.5 V dual supply

SPI-compatible serial interface

Nonvolatile memory stores wiper settings

Power-on refreshed with EEMEM settings

Permanent memory write protection

Resistance tolerance stored in EEMEM

26 bytes extra nonvolatile memory for user-defined

information

1M programming cycles

100-year typical data retention

APPLICATIONS

DWDM laser diode driver, optical supervisory systems

Mechanical potentiometer replacement

Instrumentation: gain, offset adjustment

Programmable voltage-to-current conversion

Programmable filters, delays, time constants

Programmable power supply

Low resolution DAC replacement

Sensor calibration

GENERAL DESCRIPTION

The AD5235 is a dual-channel, nonvolatile memory,1 digitally

controlled potentiometer2 with 1024-step resolution, offering

guaranteed maximum low resistor tolerance error of ±8%.

The device performs the same electronic adjustment function

as a mechanical potentiometer with enhanced resolution, solid

state reliability, and superior low temperature coefficient per-

formance. The versatile programming of the AD5235 via an

SPI®-compatible serial interface allows 16 modes of operation

and adjustment including scratchpad programming, memory

storing and restoring, increment/decrement, ±6 dB/step log taper

adjustment, wiper setting readback, and extra EEMEM1 for user-

defined information such as memory data for other components,

look-up table, or system identification information.

FUNCTIONAL BLOCK DIAGRAM

ADDR

DECODE

AD5235

RDAC1

SERIAL

INTERFACE

CLK

SDI

SDO

RDY

RDAC1

EEMEM1

RDAC2

EEMEM2

26 BYT E S

RTOL* USER EEMEM

POWER-ON

RESET

RDAC2

GND

02816-001

EEMEM

CONTROL

*RAB TOLE RANCE

Figure 1.

In the scratchpad programming mode, a specific setting can

be programmed directly to the RDAC2 register, which sets the

resistance between Terminal W and Terminal A and Terminal W

and Terminal B. This setting can be stored into the EEMEM

and is restored automatically to the RDAC register during

system power-on.

The EEMEM content can be restored dynamically or through

external PR strobing, and a WP function protects EEMEM

contents. To simplify the programming, the independent or

simultaneous linear-step increment or decrement commands

can be used to move the RDAC wiper up or down, one step at

a time. For logarithmic ±6 dB changes in the wiper setting, the

left or right bit shift command can be used to double or halve the

RDAC wiper setting.

The AD5235 patterned resistance tolerance is stored in the

EEMEM. The actual end-to-end resistance can, therefore, be

known by the host processor in readback mode. The host can

execute the appropriate resistance step through a software

routine that simplifies open-loop applications as well as

precision calibration and tolerance matching applications.

The AD5235 is available in a thin, 16-lead TSSOP package.

The part is guaranteed to operate over the extended industrial

temperature range of −40°C to +85°C.

1 The terms nonvolatile memory and EEMEM are used interchangeably.

2 The terms digital potentiometer and RDAC are used interchangeably.

AD5235 Data Sheet

Rev. F | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Electrical Characteristics—25 kΩ, 250 kΩ Versions ............... 4

Interface Timing and EEMEM Reliability Characteristics—

25 kΩ, 250 kΩ Versions ............................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Test Circuits ................................................................................. 14

Theory of Operation ...................................................................... 16

Scratchpad and EEMEM Programming .................................. 16

Basic Operation .......................................................................... 16

EEMEM Protection .................................................................... 17

Digital Input and Output Configuration................................. 17

Serial Data Interface ................................................................... 17

Daisy-Chain Operation ............................................................. 18

Terminal Voltage Operating Range .......................................... 18

Advanced Control Modes ......................................................... 20

RDAC Structure .......................................................................... 21

Programming the Variable Resistor ......................................... 22

Programming the Potentiometer Divider ............................... 22

Programming Examples ............................................................ 23

EVAL-AD5235SDZ Evaluation Kit .......................................... 23

Applications Information .............................................................. 24

Bipolar Operation from Dual Supplies.................................... 24

Gain Control Compensation .................................................... 24

High Voltage Operation ............................................................ 24

DAC .............................................................................................. 24

Bipolar Programmable Gain Amplifier ................................... 25

10-Bit Bipolar DAC .................................................................... 25

Programmable Voltage Source with Boosted Output ........... 25

Programmable Current Source ................................................ 26

Programmable Bidirectional Current Source ......................... 26

Programmable Low-Pass Filter ................................................ 27

Programmable Oscillator .......................................................... 27

Optical Transmitter Calibration with ADN2841 ................... 28

Resistance Scaling ...................................................................... 28

Resistance Tolerance, Drift, and Temperature Coefficient

Mismatch Considerations ......................................................... 29

RDAC Circuit Simulation Model ............................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

Data Sheet AD5235

Rev. F | Page 3 of 32

REVISION HISTORY

6/12—Rev. E to Rev. F

Changes to Table 1 Conditions ........................................................ 4

Removed Positive Supply Current RDY and/or SDO Floating

Parameters and Negative Supply Current RDY and/or SDO

Floating Parameters, Table 1 ............................................................ 5

Added Endnote 2 to Ordering Guide ........................................... 30

4/11—Rev. D to Rev. E

Changes to Figure 12 ...................................................................... 11

4/11—Rev. C to Rev. D

Changes to EEMEM Performance .............................. Throughout

Changes to Features and General Descriptions Sections ............. 1

Changes to Specifications Section ................................................... 4

Changes to Pin 5, Pin 13, Pin 14 Descriptions .............................. 9

Changes to Typical Performance Characteristics Section ......... 10

Changes to Table 7 .......................................................................... 19

Changes to Table 9 .......................................................................... 21

Changes to Rheostat Operation Section, Table 12, Table 13 ..... 22

Changes to Table 16, Table 19, and EVAL-AD5235SDZ

Evaluation Kit Section .................................................................... 23

Changes to RDAC Circuit Simulation Model Section ............... 29

Updated Outline Dimensions ........................................................ 30

Changes to Ordering Guide ........................................................... 30

4/09—Rev. B to Rev. C

Changes to Figure 1........................................................................... 1

Changes to Specifications ................................................................. 3

Changes to SDO, Description Column, Table 4 ............................ 8

Changes to Figure 18 ...................................................................... 11

Changes to Theory of Operation Section .................................... 14

Changes to Serial Data Interface Section ..................................... 15

Changes to Linear Increment and Decrement Instructions

Section, Logarithmic Taper Mode Adjustment Section, and

Figure 42 ........................................................................................... 18

Changes to Rheostat Operations Section ..................................... 20

Changes to Bipolar Programmable Gain Amplifier Section,

Figure 49, Table 21, and 10-Bit Bipolar DAC Section ................ 23

Changes to Programmable Oscillator Section and Figure 56 ... 25

Changes to Ordering Guide ........................................................... 28

7/04—Rev. A to Rev. B

Updated Formatting .......................................................... Universal

Edits to Features, General Description, and Block Diagram ...... 1

Changes to Specifications................................................................. 3

Replaced Timing Diagrams ............................................................. 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Pin Function Descriptions .......................................... 8

Changes to Typical Performance Characteristics ......................... 9

Additional Test Circuit (Figure 36)................................................. 9

Edits to Theory of Operation ........................................................ 14

Edits to Applications ....................................................................... 23

Updated Outline Dimensions........................................................ 27

8/02—Rev. 0 to Rev. A

Change to Features and General Description ............................... 1

Change to Specifications .................................................................. 2

Change to Calculating Actual End-to-End Terminal

Resistance Section ........................................................................... 14

AD5235 Data Sheet

Rev. F | Page 4 of 32

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted.

These specifications apply to versions with a date code 1209 or later.

Table 1.

Parameter Symbol Conditions Min Typ 1 Max Unit

DC CHARACTERISTICS—RHEOSTAT

MODE (All RDACs)

Resistor Differential Nonlinearity

R-DNL

−1

LSB

Resistor Integral Nonlinearity2 R-INL RWB −2 +2 LSB

Nominal Resistor Tolerance ∆RAB/RAB −8 +8 %

Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C

Wiper Resistance RW IW = 1 V/RWB, code = midscale

VDD = 5 V 30 60 Ω

VDD = 3 V 50 Ω

Nominal Resistance Match RAB1/RAB2 ±0.1 %

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

(All RDACs)

Resolution N 10 Bits

Differential Nonlinearity3 DNL −1 +1 LSB

Integral Nonlinearity3 INL −1 +1 LSB

Voltage Divider Temperature

Coefficient

(∆VW/VW)/∆T × 106 Code = midscale 15 ppm/°C

Full-Scale Error VWFSE Code = full scale −6 0 LSB

Zero-Scale Error VWZSE Code = zero scale 0 4 LSB

RESISTOR TERMINALS

Terminal Voltage Range4 VA, VB, VW VSS VDD V

Capacitance Ax, Bx5 CA, CB f = 1 MHz, measured to GND,

code = midscale

11 pF

Capacitance Wx5 CW f = 1 MHz, measured to GND,

code = midscale

80 pF

Common-Mode Leakage Current5, 6 ICM VW = VDD/2 0.01 ±1 µA

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V

Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V

Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V

Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V

Input Logic High VIH With respect to GND, VDD = +2.5 V,

VSS = −2.5 V

2.0 V

Input Logic Low VIL With respect to GND, VDD = +2.5 V,

VSS = −2.5 V

0.5 V

Output Logic High (SDO, RDY) VOH RPULL-UP = 2.2 kΩ to 5 V (see

Figure 38)

4.9 V

Output Logic Low

= 1.6 mA, V

LOGIC

= 5 V (see

Figure 38)

0.4

Input Current IIL VIN = 0 V or VDD ±1 µA

Input Capacitance5 CIL 5 pF

Data Sheet AD5235

Rev. F | Page 5 of 32

Parameter Symbol Conditions Min Typ 1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD VSS = 0 V 2.7 5.5 V

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V

Positive Supply Current IDD VIH = VDD or VIL = GND 2 5 µA

Negative Supply Current

= +2.5 V, V

= −2.5 V

VIH = VDD or VIL = GND −4 −2 µA

EEMEM Store Mode Current IDD (store) VIH = VDD or VIL = GND,

VSS = GND, ISS ≈ 0

2 mA

ISS (store) VDD = +2.5 V, VSS = −2.5 V −2 mA

EEMEM Restore Mode Current7 IDD (restore) VIH = VDD or VIL = GND,

VSS = GND, ISS ≈ 0

320 µA

ISS (restore) VDD = +2.5 V, VSS = −2.5 V −320 µA

Power Dissipation8 PDISS VIH = VDD or VIL = GND 10 30 µW

Power Supply Sensitivity5 PSS ∆VDD = 5 V ± 10% 0.006 0.01 %/%

DYNAMIC CHARACTERISTICS5, 9

Bandwidth BW −3 dB, RAB = 25 kΩ/250 kΩ 125/12 kHz

Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,

f = 1 kHz, code = midscale

= 25 kΩ

0.009

RAB = 250 kΩ 0.035 %

VW Settling Time tS VA = VDD, VB = 0 V, VW = 0.50% error

band, from zero scale to midscale

RAB = 25 kΩ 4 µs

RAB = 250 kΩ 36 µs

Resistor Noise Density

N_WB

= 25 kΩ/250 kΩ

20/64

nV/√Hz

Crosstalk (CW1/CW2) CT VA1 = VDD, VB1 = VSS , measured VW2

with VW1 making full-scale change,

RAB = 25 kΩ/250 kΩ

30/60

nV-s

Analog Crosstalk CTA VAB2 = 5 V p-p, f = 1 kHz, measured

VW1, Code 1 = midscale, Code 2 =

full scale, RAB = 25 kΩ/250 kΩ

−110/−100

1 Typicals represent average readings at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. IWB = (VDD − 1)/RWB (see Figure 27).

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28).

4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

5 Guaranteed by design and not subject to production test.

6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.

7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.

8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).

9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

AD5235 Data Sheet

Rev. F | Page 6 of 32

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS

Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input

control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are

measured using both VDD = 2.7 V and VDD = 5 V.

Table 2.

Parameter Symbol Conditions Min Typ 1 Max Unit

Clock Cycle Time (tCYC) t1 20 ns

CS Setup Time t2 10 ns

CLK Shutdown Time to CS Rise t3 1 tCYC

Input Clock Pulse Width

, t

Clock level high or low

Data Setup Time t6 From positive CLK transition 5 ns

Data Hold Time t7 From positive CLK transition 5 ns

CS to SDO-SPI Line Acquire t8 40 ns

CS to SDO-SPI Line Release t9 50 ns

CLK to SDO Propagation Delay

= 2.2 kΩ, C

< 20 pF

CLK to SDO Data Hold Time

= 2.2 kΩ, C

< 20 pF

CS High Pulse Width3 t12 10 ns

CS High to CS High3 t13 4 tCYC

RDY Rise to CS Fall t14 0 ns

CS Rise to RDY Fall Time t15 0.15 0.3 ms

Store EEMEM Time4, 5 t16 Applies to Instructions 0x2, 0x3 15 50 ms

Read EEMEM Time

Applies to Instructions 0x8, 0x9, 0x10

µs

CS Rise to Clock Rise/Fall Setup t17 10 ns

Preset Pulse Width (Asynchronous)6 tPRW 50 ns

Preset Response Time to Wiper Setting6 tPRESP PR pulsed low to refresh wiper positions 30 µs

Power-On EEMEM Restore Time6 tEEMEM 30 µs

FLASH/EE MEMORY RELIABILITY

Endurance7 TA = 25°C 1 MCycles

100 kCycles

Data Retention

100

Years

1 Typicals represent average readings at 25°C and VDD = 5 V.

2 Propagation delay depends on the value of VDD, RPULL-UP, and CL.

3 Valid for commands that do not activate the RDY pin.

4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;

CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 µs.

5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.

6 Not shown in Figure 2 and Figure 3.

7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.

8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV

derates with junction temperature in the Flash/EE memory.

Data Sheet AD5235

Rev. F | Page 7 of 32

Timing Diagrams

CPOL = 1

CLK

B24* B23 (MS B) B0 (L S B)

B23 (MS B)

HIGH

OR LOW HIGH

OR LOW

B23 B0

B0 (L S B)

RDY

CPHA = 1

t10

t14 t15 t16

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB O F T HE CHARACTER PRE V IO USLY TRANS M IT TED.

THE CP O L = 1 MICRO CONTROL LER CO M M AND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

SDO

SDI

02816-002

Figure 2. CPHA = 1 Timing Diagram

t12

t13

t17

CLK

CPOL = 0

B23 (MSB OUT) B0 (LSB)

SDO

B23 (MSB IN)

B23 B0

HIGH

OR LOW HIGH

OR LOW

B0 (LSB)

SDI

RDY

CPHA = 0

*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

02816-003

Figure 3. CPHA = 0 Timing Diagram

AD5235 Data Sheet

Rev. F | Page 8 of 32

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V

VSS to GND +0.3 V to −7 V

VDD to VSS 7 V

VA, VB, VW to GND VSS − 0.3 V to VDD + 0.3 V

IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA

Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range2 −40°C to +85°C

Maximum Junction Temperature (TJ max) 150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature, Soldering

Vapor Phase (60 sec)

215°C

Infrared (15 sec) 220°C

Thermal Resistance

Junction-to-Ambient θJA,TSSOP-16 150°C/W

Junction-to-Case θJC, TSSOP-16 28°C/W

Package Power Dissipation

max − T

)/θ

1 Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

2 Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Data Sheet AD5235

Rev. F | Page 9 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDI

SDO

GND

VSS

CLK

VDD

02816-005

RDY

AD5235

TOP VIEW

(No t t o Scal e)

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.

2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.

3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO

output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and

after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI

bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This

previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up

resistor in the range of 1 kΩ to 10 kΩ is needed.

GND

Ground Pin, Logic Ground Reference.

5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink

2 mA for 15 ms when storing data to EEMEM.

6 A1 Terminal A of RDAC1.

7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.

8 B1 Terminal B of RDAC1.

9 B2 Terminal B of RDAC2.

10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.

11 A2 Terminal A of RDAC2.

12 VDD Positive Power Supply.

13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.

14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

at the logic high transition. Tie PR to VDD, if not used.

15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

Instruction 9, Instruction 10, and PR.

AD5235 Data Sheet

Rev. F | Page 10 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

DIGITAL CODE

0200 400 600 1000

INL ERRO R ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15 –40°C

+25°C

+85°C

02816-006

Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

DIGITAL CODE

0200 400 600 1000

DNL E RROR (L S B)

800

0.16

–0.04

–0.02

0.02

0.04

0.06

0.08

0.10

0.12

0.14

02816-007

–40°C

+25°C

+85°C

Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

DIGITAL CODE

0200 400 600 1000

INL ERRO R ( LSB)

800

0.20

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15 –40°C

+25°C

+85°C

02816-008

Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

DIGITAL CODE

0200 400 600 1000

DNL E RROR (L S B)

800

0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

02816-009

–40°C

+25°C

+85°C

Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ

CODE ( Decimal)

POTENTIOMETER MODE TEMPCO (ppm/°C)

200

180

160

140

120

100

001023768512256

25kΩ

250kΩ

02816-010

Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco

02816-011

CODE ( Decimal)

RHEOSTAT MODE TEMPCO (p p m/° C)

200

180

160

140

120

100

001023768512256

25kΩ

250kΩ

Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco

Data Sheet AD5235

Rev. F | Page 11 of 32

CODE ( Decimal)

0200 400 800600 1000

WIPER ON RESISTANCE (Ω)

2.7V

3.0V

3.3V

5.0V

5.5V

02816-012

Figure 11. Wiper On Resistance vs. Code

TEMPERATURE (°C)

–40 –20 020 40 60 8580

(µA)

–3

–2

–1

= 2.7V

= 3.3V

= 3.0V

= 5.5V

= 5.0V

= 2.7V

= 3.3V

= 3.0V

= 5.5V

= 5.0V

02816-013

Figure 12. IDD vs. Temperature

FREQUENCY (MHz)

11098765432

IDD (µ A)

FULL SCALE

MIDSCALE

ZE RO SCAL E

02816-014

Figure 13. IDD vs. Clock Frequency, RAB = 25 kΩ

100

200

300

400

(µA)

VDIO (V)

2.7V

3.0V

3.3V

5.0V

5.5V

02816-015

012345

Figure 14. IDD vs. Digital Input Voltage

0.12

0.02

0.04

0.06

0.08

0.10

10 100 1k 10k 100k

THD + N ( %)

FRE QUENCY ( Hz )

250kΩ

25kΩ

02816-115

Figure 15. THD + Noise vs. Frequency

0.001

0.01

0.1

0.0001 0.001 0.01 0.1 110

THD + N ( %)

AMPLITUDE (V rms)

250kΩ

25kΩ

02816-116

Figure 16. THD + Noise vs. Amplitude

AD5235 Data Sheet

Rev. F | Page 12 of 32

FREQUENCY (Hz)

02816-016

1k 10k 100k 1M

GAI N (dB)

–3

–6

–9

–12

=±2.5V

= 1V rms

D = MI DS CALE

–3dB

= 12kHz

= 250kΩ

= 25k Ω

–3dB

= 125kHz

Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 33)

FREQUENCY (Hz)

02816-017

1k 10k 100k 1M

GAI N (dB)

–20

–10

–30

–40

–50

–60

CODE 0x200

0x100

0x080

0x040

0x020

0x010

0x008

0x004

0x002

0x001

Figure 18. Gain vs. Frequency vs. Code, RAB = 25 kΩ (See Figure 33)

FREQUENCY (Hz)

02816-018

1k 10k 100k 1M

–20

–10

–30

–40

–50

–60

GAI N (dB)

CODE 0x200

0x100

0x080

0x040

0x020

0x010

0x008

0x004

0x002

0x001

Figure 19. Gain vs. Frequency vs. Code, RAB = 250 kΩ (See Figure 33)

FRE QUENCY ( Hz )

10 100 1k 10k 100k 1M

PSRR (d B)

–80

–60

–70

–50

–40

–30

–20

–10

RAB = 250kΩ

VDD = 5V ± 10% AC

VSS = 0V, VA = 4V , VB = 0V

MEAS URE D AT VWWITH CODE = 0x200

TA= 25° C

RAB = 25k Ω

02816-019

Figure 20. PSRR vs. Frequency

02816-020

= 5V

= 0V

= 25° C

1V/DIV

10µs/DIV

(FULL SCALE)

Figure 21. Power-On Reset

TIME (µs)

020 40 60 80 100 120 144

AMPL IT UDE (V)

2.5196

2.484

2.488

2.492

2.496

2.500

2.504

2.508

2.512

2.516

2.4796

= V

= 5V

CODE = 0x200 TO 0x1F F

02816-021

Figure 22. Midscale Glitch Energy, RAB = 25 kΩ

Data Sheet AD5235

Rev. F | Page 13 of 32

TIME (µs)

AMPL IT UDE (V)

020 40 60 80 100 120 144

2.3795

2.344

2.348

2.352

2.356

2.360

2.364

2.368

2.372

2.376

2.3399

02816-022

Figure 23. Midscale Glitch Energy, RAB = 250 kΩ

02816-023

CS (5V/DIV)

CLK ( 5V /DIV )

SDI (5V/DIV)

(2mA/ DIV)

= 5V

= 25° C

Figure 24. IDD vs. Time when Storing Data to EEMEM

2.60

2.55

2.50

2.45

2.40 00.5 1.0 1.5 2.0

WIPER VOL T AGE (V)

TIME (µs)

02816-126

Figure 25. Digital Feedthrough

CODE ( Decimal)

02816-025

100

0.01 1023

THE ORECT ICAL ( IWB_MAX – mA)

0.1

896768640512384128 2560

VA = VB = OPEN

TA = 25° C

RAB = 25k Ω

RAB = 250kΩ

Figure 26. IWB_MAX vs. Code

AD5235 Data Sheet

Rev. F | Page 14 of 32

TEST CIRCUITS

Figure 27 to Figure 37 define the test conditions used in the Specifications section.

DUT

NC = NO CONNECT

02816-026

Figure 27. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)

DUT

V+

02816-027

V+ = V

1LSB = V + /2

Figure 28. Potentiometer Divider Nonlinearity Error (INL, DNL)

DUT I

= V

NOMINAL

MS1

MS2

02816-028

= [V

MS1

– V

MS2

]/I

Figure 29. Wiper Resistance

V+ = V

±10%

PSRR (dB) = 20 LOG V

ΔV

()

ΔV

MS%

ΔV

DD%

PSS (%/%) =

V+

02816-029

Figure 30. Power Supply Sensitivity (PSS, PSRR)

OFFSET BIAS

OFFSET

GND

ABDUT

W5V

OUT

OP279

02816-030

Figure 31. Inverting Gain

OFFSET BIAS

OFFSET

GND ABDUT

OUT

OP279

02816-031

Figure 32. Noninverting Gain

OFFSET

GND

DUT W

+15V

OUT

OP42

–15V

2.5V

02816-032

Figure 33. Gain vs. Frequency

–

DUT CODE = 0x00

0.1V

TO V

=0.1V

A = NC

02816-033

Figure 34. Incremental On Resistance

Data Sheet AD5235

Rev. F | Page 15 of 32

DUT

GND

NC = NO CONNECT

02816-034

Figure 35. Common-Mode Leakage Current

02816-035

RDAC1 RDAC2

CTA = 20 LOG[VOUT/VIN]

NC = NO CONNECT

VIN VOUT

VSS

VDD

Figure 36. Analog Crosstalk

02816-036

200µA IOL

200µA IOH

VOH (MIN)

VOL (MAX)

TO OUTPUT

PIN CL

50pF

Figure 37. Load Circuit for Measuring VOH and VOL

(The diode bridge test circuit is equivalent to the

application circuit with RPULL-UP of 2.2 kΩ.)

AD5235 Data Sheet

Rev. F | Page 16 of 32

THEORY OF OPERATION

The AD5235 digital potentiometer is designed to operate as a

true variable resistor. The resistor wiper position is determined

by the RDAC register contents. The RDAC register acts as a

scratchpad register, allowing unlimited changes of resistance

settings. The scratchpad register can be programmed with any

position setting using the standard SPI serial interface by loading

the 24-bit data-word. In the format of the data-word, the first four

bits are commands, the following four bits are addresses, and the

last 16 bits are data. When a specified value is set, this value can

be stored in a corresponding EEMEM register. During subsequent

power-ups, the wiper setting is automatically loaded to that value.

Storing data to the EEMEM register takes about 15 ms and

consumes approximately 2 mA. During this time, the shift

The RDY pin pulses low to indicate the completion of this

EEMEM storage. There are also 13 addresses with two bytes

each of user-defined data that can be stored in the EEMEM

The following instructions facilitate the programming needs

of the user (see Table 7 for details):

0. Do nothing.

1. Restore EEMEM content to RDAC.

2. Store RDAC setting to EEMEM.

3. Store RDAC setting or user data to EEMEM.

4. Decrement by 6 dB.

5. Decrement all by 6 dB.

6. Decrement by one step.

7. Decrement all by one step.

8. Reset EEMEM content to RDAC.

9. Read EEMEM content from SDO.

10. Read RDAC wiper setting from SDO.

11. Write data to RDAC.

12. Increment by 6 dB.

13. Increment all by 6 dB.

14. Increment by one step.

15. Increment all by one step.

Table 14 to Table 20 provide programming examples that use

some of these commands.

SCRATCHPAD AND EEMEM PROGRAMMING

The scratchpad RDAC register directly controls the position of

the digital potentiometer wiper. For example, when the scratchpad

of the variable resistor. The scratchpad register is a standard

logic register with no restriction on the number of changes

allowed, but the EEMEM registers have a program erase/write

cycle limitation.

BASIC OPERATION

The basic mode of setting the variable resistor wiper position

(programming the scratchpad register) is accomplished by

loading the serial data input register with Instruction 11 (0xB),

Address 0, and the desired wiper position data. When the proper

wiper position is determined, the user can load the serial data

input register with Instruction 2 (0x2), which stores the wiper

position data in the EEMEM register. After 15 ms, the wiper

position is permanently stored in nonvolatile memory.

Table 5 provides a programming example listing the sequence

of the serial data input (SDI) words with the serial data output

appearing at the SDO pin in hexadecimal format.

Table 5. Write and Store RDAC Settings to EEMEM Registers

SDI SDO Action

0xB00100 0xXXXXXX Writes data 0x100 to the RDAC1 register,

Wiper W1 moves to 1/4 full-scale position.

0x20XXXX 0xB00100 Stores RDAC1 register content into the

EEMEM1 register.

0xB10200 0x20XXXX Writes Data 0x200 to the RDAC2 register,

Wiper W2 moves to 1/2 full-scale position.

0x21XXXX 0xB10200 Stores RDAC2 register contents into the

EEMEM2 register.

At system power-on, the scratchpad register is automatically

refreshed with the value previously stored in the corresponding

EEMEM register. The factory-preset EEMEM value is midscale.

The scratchpad register can also be refreshed with the contents

of the EEMEM register in three different ways. First, executing

Instruction 1 (0x1) restores the corresponding EEMEM value.

Second, executing Instruction 8 (0x8) resets the EEMEM values

of both channels. Finally, pulsing the PR pin refreshes both

EEMEM settings. Operating the hardware control PR function

requires a complete pulse signal. When PR goes low, the internal

logic sets the wiper at midscale. The EEMEM value is not

loaded until PR returns high.

Data Sheet AD5235

Rev. F | Page 17 of 32

EEMEM PROTECTION

The write protect (WP) pin disables any changes to the

scratchpad register contents, except for the EEMEM setting,

which can still be restored using Instruction 1, Instruction 8,

and the PR pulse. Therefore, WP can be used to provide a

hardware EEMEM protection feature.

DIGITAL INPUT AND OUTPUT CONFIGURATION

All digital inputs are ESD protected, high input impedance that

can be driven directly from most digital sources. Active at logic

low, PR and WP must be tied to VDD, if they are not used. No

internal pull-up resistors are present on any digital input pins.

To avoid floating digital pins that might cause false triggering

in a noisy environment, add pull-up resistors. This is applicable

when the device is detached from the driving source when it is

programmed.

The SDO and RDY pins are open-drain digital outputs that only

need pull-up resistors if these functions are used. To optimize

the speed and power trade-off, use 2.2 kΩ pull-up resistors.

The equivalent serial data input and output logic is shown in

Figure 38. The open-drain output SDO is disabled whenever

chip-select (CS) is in logic high. ESD protection of the digital

inputs is shown in Figure 39 and Figure 40.

VALID

COMMAND

COUNTER

COMMAND

PROCESSOR

AND ADDRESS

DECODE

(F OR DAIS Y

CHAIN ONLY )

SERIAL

CLK

SDI

PULL-UP

SDO

GND

PR WP

AD5235

02816-037

Figure 38. Equivalent Digital Input and Output Logic

LOGIC

PINS

GND

INPUTS

300

Ω

02816-038

Figure 39. Equivalent ESD Digital Input Protection

GND

INPUT

300

Ω

02816-039

Figure 40. Equivalent WP Input Protection

SERIAL DATA INTERFACE

The AD5235 contains a 4-wire SPI-compatible digital interface

(SDI, SDO, CS, and CLK). The 24-bit serial data-word must be

loaded with MSB first. The format of the word is shown in Table 6.

The command bits (C0 to C3) control the operation of the digital

potentiometer according to the command shown in Table 7. A0

to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.

Address 2 to Address 14 are accessible by users for extra EEMEM.

Address 15 is reserved for factory usage. Table 9 provides an

address map of the EEMEM locations. D0 to D9 are the values

for the RDAC registers. D0 to D15 are the values for the EEMEM

registers.

The AD5235 has an internal counter that counts a multiple of

24 bits (a frame) for proper operation. For example, AD5235

works with a 24-bit or 48-bit word, but it cannot work properly

with a 23-bit or 25-bit word. To prevent data from mislocking

(due to noise, for example), the counter resets, if the count is not a

multiple of four when CS goes high but remains in the register if it

is multiple of four. In addition, the AD5235 has a subtle feature

that, if CS is pulsed without CLK and SDI, the part repeats the

previous command (except during power-up). As a result, care

must be taken to ensure that no excessive noise exists in the CLK or

CS line that might alter the effective number-of-bits pattern.

The SPI interface can be used in two slave modes: CPHA = 1,

CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer

to the control bits that dictate SPI timing in the following

MicroConverters® and microprocessors: ADuC812, ADuC824,

M68HC11, MC68HC16R1, and MC68HC916R1.

AD5235 Data Sheet

Rev. F | Page 18 of 32

DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes. It can be

used to read the contents of the wiper setting and EEMEM values

using Instruction 10 and Instruction 9, respectively. The remaining

instructions (Instruction 0 to Instruction 8, Instruction 11 to

Instruction 15) are valid for daisy-chaining multiple devices in

simultaneous operations. Daisy-chaining minimizes the number

of port pins required from the controlling IC (see Figure 41). The

SDO pin contains an open-drain N-Ch FET that requires a pull-up

resistor, if this function is used. As shown in Figure 41, users need

to tie the SDO pin of one package to the SDI pin of the next package.

Users may need to increase the clock period because the pull-up

resistor and the capacitive loading at the SDO-to-SDI interface may

require additional time delay between subsequent devices.

When two AD5235s are daisy-chained, 48 bits of data are

required. The first 24 bits (formatted 4-bit command, 4-bit

address, and 16-bit data) go to U2, and the second 24 bits with

the same format go to U1. Keep CS low until all 48 bits are

clocked into their respective serial registers. CS is then pulled

high to complete the operation.

CLK

2.2k

Ω

SDI SDO

AD5235

CLK

SDI SDO

AD5235

SCLK SS

MOSI

MICRO-

CONTROLLER

02816-040

Figure 41. Daisy-Chain Configuration Using SDO

TERMINAL VOLTAGE OPERATING RANGE

The positive VDD and negative VSS power supplies of the AD5235

define the boundary conditions for proper 3-terminal digital

potentiometer operation. Supply signals present on Terminal A,

Terminal B, and Terminal W that exc e ed VDD or VSS are clamped by

the internal forward-biased diodes (see Figure 42).

02816-041

Figure 42. Maximum Terminal Voltages Set by VDD and VSS

The GND pin of the AD5235 is primarily used as a digital

ground reference. To minimize the digital ground bounce,

the AD5235 ground terminal should be joined remotely to

the common ground (see Figure 43). The digital input control

signals to the AD5235 must be referenced to the device ground

pin (GND) and must satisfy the logic level defined in the

Specifications section. An internal level-shift circuit ensures

that the common-mode voltage range of the three terminals

extends from VSS to VDD, regardless of the digital input level.

Power-Up Sequence

Because there are diodes to limit the voltage compliance at

Terminal A, Terminal B, and Terminal W (see Figure 42), it

is important to power VDD and VSS first before applying any

voltage to Terminal A, Terminal B, and Terminal W. Otherwise,

the diode is forward-biased such that VDD and VSS are powered

unintentionally. For example, applying 5 V across Terminal A

and Terminal B prior to VDD causes the VDD terminal to exhibit

4.3 V. It is not destructive to the device, but it might affect the

rest of the user’s system. The ideal power-up sequence is GND,

VDD and VSS, digital inputs, and VA, VB, and VW. The order of

powering VA, VB, VW, and the digital inputs is not important as

long as they are powered after VDD and VSS.

Regardless of the power-up sequence and the ramp rates of the

power supplies, when VDD and VSS are powered, the power-on

preset activates, which restores the EEMEM values to the RDAC

registers.

Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum lead-length

layout design. The leads to the input should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with

quality capacitors for optimum stability. Bypass supply leads to

the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.

Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic

capacitors at the supplies to minimize any transient disturbance

(see Figure 43).

AD5235

GND

02816-042

10µF

0.1µF

Figure 43. Power Supply Bypassing

Data Sheet AD5235

Rev. F | Page 19 of 32

In Table 6, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are

applicable to EEMEM.

Table 6. 24-Bit Serial Data-Word

MSB

Command Byte 0

Data Byte 1

Data Byte 0

LSB

RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Command instruction codes are defined in Table 7.

Table 7. Command Operation Truth Table1, 2, 3

Command

Number

Command Byte 0 Data Byte 1 Data Byte 0

Operation

B23 B16 B15 B8 B7 B0

C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0

0 0 0 0 0 X X X X X … X X X … X NOP. Do nothing. See Table 19

1 0 0 0 1 0 0 0 A0 X … X X X … X

Restore EEMEM (A0) contents to RDAC (A0)

2 0 0 1 0 0 0 0 A0 X … X X X … X Store wiper setting. Store RDAC (A0) setting to

EEMEM (A0). See Table 15.

34 0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0 Store contents of Serial Register Data Byte 0

and Serial Register Data Bytes 1 (total 16 bits)

to EEMEM (ADDR). See Table 18.

45 0 1 0 0 0 0 0 A0 X … X X X … X Decrement by 6 dB. Right-shift contents of

RDAC (A0) register, stop at all 0s.

55 0 1 0 1 X X X X X … X X X … X Decrement all by 6 dB. Right-shift contents of

all RDAC registers, stop at all 0s.

…

Decrement contents of RDAC (A0) by 1,

stop at all 0s.

…

Decrement contents of all RDAC registers by 1,

stop at all 0s.

8 1 0 0 0 0 0 0 0 X … X X X … X Reset. Refresh all RDACs with their corresponding

EEMEM previously stored values.

9 1 0 0 1 A3 A2 A1 A0 X … X X X … X Read contents of EEMEM (ADDR) from

SDO output in the next frame. See Table 19.

10 1 0 1 0 0 0 0 A0 X … X X X … X Read RDAC wiper setting from SDO output

in the next frame. See Table 20.

11 1 0 1 1 0 0 0 A0 X … D9 D8 D7 … D0 Write contents of Serial Register Data Byte 0

and Serial Register Data Byte 1 (total 10 bits)

to RDAC (A0). See Table 14.

125 1 1 0 0 0 0 0 A0 X … X X X … X Increment by 6 dB: Left-shift contents of RDAC

(A0), stop at all 1s. See Table 17.

1 1 0 1 X X X X X … X X X … X Increment all by 6 dB. Left-shift contents of

all RDAC registers, stop at all 1s.

1 1 1 0 0 0 0 A0 X … X X X … X Increment contents of RDAC (A0) by 1,

stop at all 1s. See Table 15.

155 1 1 1 1 X X X X X … X X X … X Increment contents of all RDAC registers by 1,

stop at all 1s.

1 The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or

Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a

full 24-bit data-word to completely clock out the contents of the serial register.

2 The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.

3 Execution of these operations takes place when the CS strobe returns to logic high.

4 Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting.

5 The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1.

AD5235 Data Sheet

Rev. F | Page 20 of 32

ADVANCED CONTROL MODES

The AD5235 digital potentiometer includes a set of user

programming features to address the wide number of

applications for these universal adjustment devices.

Key programming features include the following:

• Scratchpad programming to any desirable values

• Nonvolatile memory storage of the scratchpad RDAC

• Increment and decrement instructions for the RDAC

wiper register

• Left and right bit shift of the RDAC wiper register to

achieve ±6 dB level changes

• 26 extra bytes of user-addressable nonvolatile memory

Linear Increment and Decrement Instructions

The increment and decrement instructions (Instruction 14,

Instruction 15, Instruction 6, and Instruction 7) are useful for

linear step adjustment applications. These commands simplify

microcontroller software coding by allowing the controller to

send just an increment or decrement command to the device.

The adjustment can be individual or in a ganged potentiometer

arrangement where both wiper positions are changed at the

same time.

For an increment command, executing Instruction 14

automatically moves the wiper to the next resistance segment

position. The master increment command, Instruction 15,

moves all resistor wipers up by one position.

Logarithmic Taper Mode Adjustment

Four programming instructions produce logarithmic taper

increment and decrement of the wiper position control by

an individual potentiometer or by a ganged potentiometer

arrangement where both wiper positions are changed at the

same time. The 6 dB increment is activated by Instruction 12

and Instruction 13, and the 6 dB decrement is activated by

Instruction 4 and Instruction 5. For example, starting with the

wiper connected to Terminal B, executing 11 increment

instructions (Command Instruction 12) moves the wiper in 6 dB

steps from 0% of the RAB (Terminal B) position to 100% of the RAB

position of the AD5235 10-bit potentiometer. When the wiper

position is near the maximum setting, the last 6 dB increment

instruction causes the wiper to go to the full-scale 1023 code

position. Further 6 dB per increment instructions do not

change the wiper position beyond its full scale (see Table 8).

The 6 dB step increments and 6 dB step decrements are achieved

by shifting the bit internally to the left or right, respectively. The

following information explains the nonideal ±6 dB step adjustment

under certain conditions. Table 8 illustrates the operation of the

shifting function on the RDAC register data bits. Each table row

represents a successive shift operation. Note that the left-shift

12 and 13 instructions were modified such that, if the data in

the RDAC register is equal to zero and the data is shifted left,

the RDAC register is then set to Code 1. Similarly, if the data in

the RDAC register is greater than or equal to midscale and the data

is shifted left, then the data in the RDAC register is automatically

set to full scale. This makes the left-shift function as ideal a

logarithmic adjustment as possible.

The Right-Shift 4 instruction and Right-Shift 5 instruction are

ideal only if the LSB is 0 (ideal logarithmic = no error). If the

LSB is 1, the right-shift function generates a linear half-LSB

error, which translates to a number-of-bits dependent logarithmic

error, as shown in Figure 44. Figure 44 shows the error of the odd

numbers of bits for the AD5235.

Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB

Step Increment and Decrement

Left-Shift (+6 dB/Step) Right-Shift(–6 dB/Step)

00 0000 0000 11 1111 1111

00 0000 0001 01 1111 1111

00 0000 0010 00 1111 1111

00 0000 0100 00 0111 1111

00 0000 1000 00 0011 1111

00 0001 0000 00 0001 1111

00 0010 0000

00 0000 1111

00 0100 0000 00 0000 0111

00 1000 0000 00 0000 0011

01 0000 0000 00 0000 0001

10 0000 0000 00 0000 0000

11 1111 1111

00 0000 0000

11 1111 1111 00 0000 0000

Actual conformance to a logarithmic curve between the data

contents in the RDAC register and the wiper position for each

Right-Shift 4 command and Right-Shift 5 command execution

contains an error only for odd numbers of bits. Even numbers of

bits are ideal. Figure 44 shows plots of log error [20 × log10

(error/code)] for the AD5235. For example, Code 3 log error = 20 ×

log10 (0.5/3) = −15.56 dB, which is the worst case. The log error plot

is more significant at the lower codes (see Figure 44).

CODE ( From 1 t o 1023 by 2.0 ×10

)

GAIN (d B)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

02816-043

–40

–20

–60

–80

Figure 44. Log Error Conformance for Odd Numbers of Bits Only

(Even Numbers of Bits Are Ideal)

Data Sheet AD5235

Rev. F | Page 21 of 32

Using CS to Re-Execute a Previous Command

Another subtle feature of the AD5235 is that a subsequent CS

strobe, without clock and data, repeats a previous command.

Using Additional Internal Nonvolatile EEMEM

The AD5235 contains additional user EEMEM registers for

storing any 16-bit data such as memory data for other components,

look-up tables, or system identification information. Table 9 pro-

vides an address map of the internal storage registers shown in the

functional block diagram (see Figure 1) as EEMEM1, EEMEM2,

and 26 bytes (13 addresses × 2 bytes each) of User EEMEM.

Table 9. EEMEM Address Map

EEMEM No. Address EEMEM Content for …

1 0000 RDAC11

2 0001 RDAC2

3 0010 USER12

4 0011 USER2

… … …

15 1110 USER13

16 1111 RAB1 tolerance3

1 RDAC data stored in EEMEM locations is transferred to the corresponding

RDAC register at power-on, or when Instruction 1, Instruction 8, and PR are

executed.

2 USERx are internal nonvolatile EEMEM registers available to store and

retrieve constants and other 16-bit information using Instruction 3 and

Instruction 9, respectively.

3 Read only.

Calculating Actual End-to-End Terminal Resistance

The resistance tolerance is stored in the EEMEM register during

factory testing. The actual end-to-end resistance can, therefore,

be calculated, which is valuable for calibration, tolerance matching,

and precision applications. Note that this value is read only and

the RAB2 matches with RAB1, typically 0.1%.

The resistance tolerance in percentage is contained in the last

16 bits of data in EEMEM Register 15. The format is the sign

magnitude binary format with the MSB designate for sign

(0 = negative and 1 = positive), the next 7 MSB designate the

integer number, and the 8 LSB designate the decimal number

(see Table 11).

For example, if RAB_RATED = 250 kΩ and the data in the SDO

shows XXXX XXXX 1001 1100 0000 1111, RAB_ACTUAL can be

calculated as follows:

MSB: 1 = positive

Next 7 LSB: 001 1100 = 28

8 LSB: 0000 1111 = 15 × 2−8 = 0.06

% tolerance = 28.06%

Therefore, RAB_ACTUAL = 320.15 kΩ

RDAC STRUCTURE

The patent-pending RDAC contains multiple strings of equal

resistor segments with an array of analog switches that acts as

the wiper connection. The number of positions is the resolution of

the device. The AD5235 has 1024 connection points, allowing it to

provide better than 0.1% setability resolution. Figure 45 shows

an equivalent structure of the connections among the three

terminals of the RDAC. The SWA and SWB are always on, while

the switches, SW(0) to SW(2N − 1), are on one at a time, depending

on the resistance position decoded from the data bits. Because

the switch is not ideal, there is a 50 Ω wiper resistance, RW.

Wiper resistance is a function of supply voltage and temperature.

The lower the supply voltage or the higher the temperature, the

higher the resulting wiper resistance. Users should be aware of

the wiper resistance dynamics, if accurate prediction of the

output resistance is needed.

(1)

(0)

SW(2

N–

SW(2

N–

RDAC

WIPER

AND

DECODER

= R

DIGITAL

CIRCUITRY

OMITTED FOR

CLARITY

02816-044

Figure 45. Equivalent RDAC Structure

Table 10. Nominal Individual Segment Resistor Values

Device Resolution

25 kΩ

250 kΩ

1024-Step 24.4 244

Table 11. Calculating End-to-End Terminal Resistance

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Sign

Mag Sign 26 25 24 23 22 21 20 . 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8

7 Bits for Integer Number Decimal

Point

8 Bits for Decimal Number

AD5235 Data Sheet

Rev. F | Page 22 of 32

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminal A

and Terminal B, RAB, is available with 25 kΩ and 250 kΩ with

1024 positions (10-bit resolution). The final digits of the part

number determine the nominal resistance value, for example,

25 kΩ = 24.4 Ω; 250 kΩ = 244 Ω.

The 10-bit data-word in the RDAC latch is decoded to select one

of the 1024 possible settings. The following description provides

the calculation of resistance, RWB, at different codes of a 25 kΩ

part. The first connection of the wiper starts at Terminal B for

Data 0x000. RWB(0) is 30 Ω because of the wiper resistance, and

it is independent of the nominal resistance. The second connection

is the first tap point where RWB(1) becomes 24.4 Ω + 30 Ω = 54.4 Ω

for Data 0x001. The third connection is the next tap point

representing RWB(2) = 48.8 Ω + 30 Ω = 78.8 Ω for Data 0x002,

and so on. Each LSB data value increase moves the wiper up the

resistor ladder until the last tap point is reached at RWB(1023) =

25006 Ω. See Figure 45 for a simplified diagram of the equivalent

RDAC circuit. When RWB is used, Terminal A can be left

floating or tied to the wiper.

CODE ( Decimal)

100

001023256

RWA(D), RWB(D) (% RWF)

512 768

02816-045

Figure 46. RWA(D) and RWB(D) vs. Decimal Code

The general equation that determines the programmed output

resistance between Terminal Bx and Terminal Wx is

WB RR

DR +×= 1024

)(

(1)

where:

D is the decimal equivalent of the data contained in the RDAC

RAB is the nominal resistance between Terminal A and Terminal B.

RW is the wiper resistance.

For example, the output resistance values in Table 12 are set for

the given RDAC latch codes (applies to RAB = 25 kΩ digital

potentiometers).

Table 12. RWB (D) at Selected Codes for RAB = 25 kΩ

D (Dec) RWB(D) (Ω) Output State

1023 25,006 Full scale

512 12,530 Midscale

1 54.4 1 LSB

0 30 Zero scale (wiper contact resistor)

Note that, in the zero-scale condition, a finite wiper resistance

of 50 Ω is present. Care should be taken to limit the current

flow between W and B in this state to no more than 20 mA to

avoid degradation or possible destruction of the internal switches.

Like the mechanical potentiometer that the RDAC replaces, the

AD5235 part is symmetrical. The resistance between Wiper W

and Terminal A also produces a digitally controlled complementary

resistance, RWA . Figure 46 shows the symmetrical

programmability of the various terminal connections. When RWA

is used, Terminal B can be left floating or tied to the wiper.

Setting the resistance value for RWA starts at a maximum value

of resistance and decreases as the data loaded in the latch is

increased in value.

The general transfer equation for this operation is

ABWA

DR +×

−

=1024

1024

)(

(2)

For example, the output resistance values in Table 13 are set for

the given RDAC latch codes (applies to RAB = 25 kΩ digital

potentiometers).

Table 13. RWA(D) at Selected Codes for RAB = 25 kΩ

D (Dec) RWA(D) (Ω) Output State

1023 54.4 Full scale

512 12,530 Midscale

1 25,006 1 LSB

0 25,030 Zero scale (wiper contact resistance)

The typical distribution of RAB from channel to channel is

±0.2% within the same package. Device-to-device matching is

process lot dependent upon the worst case of ±30% variation.

However, the change in RAB with temperature has a 35 ppm/°C

temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an output

voltage at the wiper terminal that is proportional to the input

voltages applied to Terminal A and Terminal B. For example,

connecting Terminal A to 5 V and Terminal B to ground

produces an output voltage at the wiper that can be any value

from 0 V to 5 V. Each LSB of voltage is equal to the voltage

applied across Terminal A to Terminal B divided by the 2N

position resolution of the potentiometer divider.

Data Sheet AD5235

Rev. F | Page 23 of 32

Because the AD5235 can also be supplied by dual supplies, the

general equation defining the output voltage at VW with respect

to ground for any given input voltages applied to Terminal A

and Terminal B is

DV +×= 1024

)(

(3)

Equation 3 assumes that VW is buffered so that the effect of wiper

resistance is minimized. Operation of the digital potentiometer in

divider mode results in more accurate operation over temperature.

Here, the output voltage is dependent on the ratio of the internal

resistors and not the absolute value; therefore, the drift improves

to 15 ppm/°C. There is no voltage polarity restriction between

Terminal A, Terminal B, and Terminal W as long as the

terminal voltage (VTERM) stays within VSS < VTERM < VDD.

PROGRAMMING EXAMPLES

The following programming examples illustrate a typical sequence

of events for various features of the AD5235. See Table 7 for the

instructions and data-word format. The instruction numbers,

addresses, and data appearing at the SDI and SDO pins are in

hexadecimal format.

Table 14. Scratchpad Programming

SDI SDO Action

0xB00100 0xXXXXXX Writes Data 0x100 into RDAC1 register,

Wiper W1 moves to 1/4 full-scale

position.

0xB10200 0xB00100 Loads Data 0x200 into RDAC2 register,

Wiper W2 moves to 1/2 full-scale

position.

Table 15. Incrementing RDAC Followed by Storing the

Wiper Setting to EEMEM

SDI SDO Action

0xB00100 0xXXXXXX Writes Data 0x100 into RDAC1

scale position.

0xE0XXXX 0xB00100 Increments RDAC1 register by one to

0x101.

0xE0XXXX 0xE0XXXX Increments RDAC1 register by one to

0x102. Continue until desired wiper

position is reached.

0x20XXXX 0xXXXXXX Stores RDAC2 register data into

EEMEM1. Optionally, tie WP to GND to

protect EEMEM values.

The EEMEM values for the RDACs can be restored by power-

on, by strobing the PR pin, or by the two commands shown in

Table 16.

Table 16. Restoring the EEMEM Values to RDAC Registers

SDI SDO Action

0x10XXXX 0xXXXXXX Restores the EEMEM1 value to the

RDAC1 register.

Table 17. Using Left-Shift by One to Increment 6 dB Steps

SDI SDO Action

0xC0XXXX 0xXXXXXX Moves Wiper 1 to double the

present data contained in the

RDAC1 register.

0xC1XXXX 0xC0XXXX Moves Wiper 2 to double the

present data contained in the

RDAC2 register.

Table 18. Storing Additional User Data in EEMEM

SDI SDO Action

0x32AAAA 0xXXXXXX Stores Data 0xAAAA in the extra

EEMEM location USER1. (Allowable to

address in 13 locations with a

maximum of 16 bits of data.)

0x335555 0x32AAAA Stores Data 0x5555 in the extra

EEMEM location USER2. (Allowable to

address in 13 locations with a

maximum of 16 bits of data.)

Table 19. Reading Back Data from Memory Locations

SDI SDO Action

0x92XXXX

0xXXXXXX

Prepares data read from USER1

EEMEM location.

0x00XXXX 0x92AAAA NOP Instruction 0 sends a 24-bit word

out of SDO, where the last 16 bits

contain the contents in USER1 EEMEM

location.

Table 20. Reading Back Wiper Settings

SDI SDO Action

0xB00200

0xXXXXXX

Writes RDAC1 to midscale.

0xC0XXXX 0xB00200 Doubles RDAC1 from midscale to full

scale.

0xA0XXXX 0xC0XXXX Prepares reading wiper setting from

RDAC1 register.

0xXXXXXX

0xA003FF

Reads back full-scale value from SDO.

EVAL-AD5235SDZ EVALUATION KIT

Analog Devices, Inc., offers a user-friendly EVAL-AD5235SDZ

evaluation kit that can be controlled by a PC in conjunction

with the SDP platform. The driving program is self-contained;

no programming languages or skills are needed.

AD5235 Data Sheet

Rev. F | Page 24 of 32

APPLICATIONS INFORMATION

BIPOLAR OPERATION FROM DUAL SUPPLIES

The AD5235 can be operated from ±2.5 V dual supplies, which

enable control of ground referenced ac signals or bipolar operation.

AC signals as high as VDD and VSS can be applied directly across

Terminal A to Terminal B with the output taken from Termin a l W.

See Figure 47 for a typical circuit connection.

±2.5V p-p

AD5235

GND

SDI

CLK

SCLK

MOSI

GND

MICRO-

CONTROLLER

±1.25V p-p

+2.5V

–2.5V

D = MI DS CALE

02816-046

Figure 47. Bipolar Operation from Dual Supplies

GAIN CONTROL COMPENSATION

A digital potentiometer is commonly used in gain control such

as the noninverting gain amplifier shown in Figure 48.

U1 V

02816-047

250kΩ

47kΩ

11pF

B A

2.2pF

Figure 48. Typical Noninverting Gain Amplifier

When the RDAC B terminal parasitic capacitance is connected

to the op amp noninverting node, it introduces a zero for the 1/βO

term with 20 dB/dec, whereas a typical op amp gain bandwidth

product (GBP) has −20 dB/dec characteristics. A large R2 and

finite C1 can cause the frequency of this zero to fall well below

the crossover frequency. Therefore, the rate of closure becomes

40 dB/dec, and the system has a 0° phase margin at the crossover

frequency. If an input is a rectangular pulse or step function, the

output can ring or oscillate. Similarly, it is also likely to ring when

switching between two gain values; this is equivalent to a stop

change at the input.

Depending on the op amp GBP, reducing the feedback resistor

might extend the frequency of the zero far enough to overcome

the problem. A better approach is to include a compensation

capacitor, C2, to cancel the effect caused by C1. Optimum

compensation occurs when R1 × C1 = R2 × C2. This is not

an option because of the variation of R2. As a result, one can

use the previous relationship and scale C2 as if R2 were at its

maximum value. Doing this might overcompensate and

compromise the performance when R2 is set at low values.

Alternatively, it avoids the ringing or oscillation at the worst

case. For critical applications, find C2 empirically to suit the

oscillation. In general, C2 in the range of a few picofarads to

no more than a few tenths of picofarads is usually adequate

for the compensation.

Similarly, W and A terminal capacitances are connected to the

output (not shown); their effect at this node is less significant

and the compensation can be avoided in most cases.

HIGH VOLTAGE OPERATION

The digital potentiometer can be placed directly in the feedback or

input path of an op amp for gain control, provided that the voltage

across Term inal A to Terminal B, Terminal W to Terminal A or

Terminal W to Terminal B does not exceed |5 V|. When high

voltage gain is needed, set a fixed gain in the op amp and let the

digital potentiometer control the adjustable input. Figure 49

shows a simple implementation.

2RR

A1 V+

V–

15V

0V TO 15V

02816-048

AD5235

Figure 49. 15 V Voltage Span Control

Similarly, a compensation capacitor, C, may be needed to dampen

the potential ringing when the digital potentiometer changes

steps. This effect is prominent when stray capacitance at the

inverted node is augmented by a large feedback resistor. Typically,

a picofarad Capacitor C is adequate to combat the problem.

DAC

For DAC operation (see Figure 50), it is common to buffer the

output of the digital potentiometer unless the load is much larger

than RWB. The buffer serves the purpose of impedance

conversion and can drive heavier loads.

AD8601

V+

V–

02816-049

AD1582

GND

OUT

U11

AD5235

Figure 50. Unipolar 10-Bit DAC

Data Sheet AD5235

Rev. F | Page 25 of 32

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

For applications requiring bipolar gain, Figure 51 shows one

implementation. Digital Potentiometer U1 sets the adjustment

range; the wiper voltage (VW2) can, therefore, be programmed

between VI and −KVI at a given U2 setting. Configure OP2177

(A2) as a noninverting amplifier that yields a transfer function of























 KK

O)1(

1024

1 (4)

where K is the ratio of RWB1/RWA 1 set by U1.

V+

V–

OP2177

AD5235

V+

V–

OP2177

AD5235

B1 –KV

A2 B2

02816-050

Figure 51. Bipolar Programmable Gain Amplifier

In the simpler (and much more usual) case where K = 1, VO is

simplified to

V























 1

1024

1 (5)

Table 21 shows the result of adjusting D2, with OP2177 (A2)

configured as a unity gain, a gain of 2, and a gain of 10. The

result is a bipolar amplifier with linearly programmable gain

and 1024-step resolution.

Table 21. Result of Bipolar Gain Amplifier

D2 R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1

0 −1 −2 −10

256 −0.5 −1 −5

512 0 0 0

768 0.5 1 5

1023 0.992 1.984 9.92

10-BIT BIPOLAR DAC

If the circuit in Figure 51 is changed with the input taken from a

precision reference, U1 is set to midscale, and AD8552 (A2) is

configured as a buffer, a 10-bit bipolar DAC can be realized (as

shown in Figure 52). Compared to the conventional DAC, this

circuit offers comparable resolution but not the precision because

of the wiper resistance effects. Degradation of the nonlinearity

and temperature coefficient is prominent near the low values

of the adjustment range. Alternatively, this circuit offers a unique

nonvolatile memory feature that, in some cases, outweighs any

shortfalls in precision.

Without consideration of the wiper resistance, the output of this

circuit is approximately

REF

V











 1

1024

22 (6)

V+

V–

AD8552

V+

V–

AD8552

–2.5V

REF

U1 = U2 = AD5235

A1 B1

+2.5V

REF

OUT

TRIM 5

GND

ADR421

+2.5

–2.5V

+2.5V

02816-051

U1 = MIDSCAL E

Figure 52. 10-Bit Bipolar DAC

PROGRAMMABLE VOLTAGE SOURCE WITH

BOOSTED OUTPUT

For applications that require high current adjustment, such as a

laser diode driver or tunable laser, a boosted voltage source can

be considered (see Figure 53).

AD5235

V+

V–

AD8601

2N7002 R

BIAS

SIGNAL C

02816-052

Figure 53. Programmable Booster Voltage Source

In this circuit, the inverting input of the op amp forces VO to be

equal to the wiper voltage set by the digital potentiometer. The

load current is then delivered by the supply via the N-Ch FET N1

(see Figure 53). N1 power handling must be adequate to dissipate

(VI − VO) × IL power. This circuit can source a 100 mA maximum

with a 5 V supply.

For precision applications, a voltage reference, such as ADR421,

ADR03, or ADR370, can be applied at Terminal A of the digital

potentiometer.

AD5235 Data Sheet

Rev. F | Page 26 of 32

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the

circuit shown in Figure 54.

V+

V–

OP1177

SLEEP

REF191

GND

OUTPUT

1µF

AD5235

102Ω

100Ω

+5V

–2.048V TO VL

–5V

0V TO (2. 048V + VL)

+5V

–

02861-053

Figure 54. Programmable Current Source

The REF191 is a unique low supply headroom and high current

handling precision reference that can deliver 20 mA at 2.048 V.

The load current is simply the voltage across Terminal W to

Terminal B of the digital potentiometer divided by RS.

1024×

REF

(7)

The circuit is simple but be aware that there are two issues.

First, dual-supply op amps are ideal because the ground potential

of REF191 can swing from −2.048 V at zero scale to VL at full

scale of the potentiometer setting. Although the circuit works

under single supply, the programmable resolution of the system

is reduced by half. Second, the voltage compliance at VL is

limited to 2.5 V, or equivalently, a 125 Ω load. When higher

voltage compliance is needed, consider digital potentiometers,

such as, AD5260, AD5280, and AD7376. Figure 55 shows an

alternate circuit for high voltage compliance.

To achieve higher current, such as when driving a high power

LED, replace U1 with an LDO, reduce RS, and add a resistor in

series with the A terminal of the digital potentiometer. This

limits the current of the potentiometer and increases the current

adjustment resolution.

PROGRAMMABLE BIDIRECTIONAL CURRENT

SOURCE

For applications that require bidirectional current control or

higher voltage compliance, a Howland current pump can be a

solution (see Figure 55). If the resistors are matched, the load

current is

WL V

R2B

R2BR2A

I×

= (8)

–15V

OP2177

V+

V–

+15V

–

10pF

15k

Ω

150k

Ω

R2B

Ω

500

Ω

R2A

14.95k

Ω

150k

Ω

OP2177

V+

V–

+15V

–

–15V

AD5235

+2.5V

–2.5V

02816-054

Figure 55. Programmable Bidirectional Current Source

R2B, in theory, can be made as small as necessary to achieve the

current needed within the A2 output current driving capability.

In this circuit, OP2177 delivers ±5 mA in either direction, and

the voltage compliance approaches 15 V. Without the additions

of C1 and C2, the output impedance (looking into VL) can be

ZO =

)(

R2BR2AR1'R2'R1

R2AR1R2BR1'

+−

(9)

ZO can be infinite, if Resistors R1' and R2' match precisely with

R1 and R2A + R2B, respectively, which is desirable. On the other

hand, if the resistors do not match, ZO can be negative and cause

oscillation. As a result, C1, in the range of a few picofarad, is

needed to prevent oscillation from the negative impedance.

Data Sheet AD5235

Rev. F | Page 27 of 32

PROGRAMMABLE LOW-PASS FILTER

In analog-to-digital conversions (ADCs), it is common to

include an antialiasing filter to band limit the sampling signal.

Therefore, the dual-channel AD5235 can be used to construct a

second-order Sallen-Key low-pass filter, as shown in Figure 56.

AD8601

+2.5V

ADJUSTED

CONCURRENTLY

–2.5V

V+

V–

02816-055

C2 U1

Figure 56. Sallen-Key Low-Pass Filter

The design equations are

ω+

= (10)

C2C1R2R1

=ω

(11)

Q =

C2R2

C1R1 +

(12)

First, users should select convenient values for the capacitors.

To achieve maximally flat bandwidth, where Q = 0.707, let C1

be twice the size of C2 and let R1 equal R2. As a result, the user

can adjust R1 and R2 concurrently to the same setting to

achieve the desirable bandwidth.

PROGRAMMABLE OSCILLATOR

In a classic Wien bridge oscillator, the Wien network (R||C, R'C')

provides positive feedback, whereas R1 and R2 provide negative

feedback (see Figure 57).

02816-056

OP1177

V+

V–

+2.5V

–

–2.5V

R2A

2.1kΩ

R2B

10kΩ

B A

1kΩAMPLITUDE

ADJUSTMENT

R = R' = AD5235

R2B = AD5231

D1 = D2 = 1N4148

25kΩ

2.2nF

FREQUENCY

ADJUSTMENT

2.2nF

Figure 57. Programmable Oscillator with Amplitude Control

At the resonant frequency, fO, the overall phase shift is zero, and

the positive feedback causes the circuit to oscillate. With R = R',

C = C', and R2 = R2A /(R2B + RDIODE), the oscillation frequency is

=ω

fOπ

(13)

where R is equal to RWA such that :

ABWA

DR +×

−

=1024

1024

)(

(14)

At resonance, setting R2/R1 = 2 balances the bridge. In practice,

R2/R1 should be set slightly larger than 2 to ensure that the

oscillation can start. On the other hand, the alternate turn-on

of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2,

momentarily stabilizing the oscillation.

When the frequency is set, the oscillation amplitude can be

turned by R2B because

VR2BIV +=

(15)

VO, ID, and VD are interdependent variables. With proper

selection of R2B, an equilibrium is reached such that VO

converges. R2B can be in series with a discrete resistor to

increase the amplitude, but the total resistance cannot be too

large to saturate the output.

In Figure 56 and Figure 57, the frequency tuning requires that

both RDACs be adjusted concurrently to the same settings.

Because the two channels might be adjusted one at a time, an

intermediate state occurs that might not be acceptable for some

applications. Of course, the increment/decrement instructions

(Instruction 5, Instruction 7, Instruction 13, and Instruction 15)

can all be used. Different devices can also be used in daisy-chain

mode so that parts can be programmed to the same settings

simultaneously.

AD5235 Data Sheet

Rev. F | Page 28 of 32

OPTICAL TRANSMITTER CALIBRATION WITH

ADN2841

The AD5235, together with the multirate 2.7 Gbps laser diode

driver, ADN2841, forms an optical supervisory system in which

the dual digital potentiometers can be used to set the laser average

optical power and extinction ratio (see Figure 58). The AD5235

is particularly suited for the optical parameter settings because

of its high resolution and superior temperature coefficient

characteristics.

CLK

SDI

EEMEM

ADN2841

PSET

ERSET

IMODP

IBIAS

02816-057

IMPD

DATAP

DATAN

CLKP

CLKN

CLKP

DATAP

DATAN

EEMEM

CONTROL

AD5235

RDAC1

RDAC2

Figure 58. Optical Supervisory System

The ADN2841 is a 2.7 Gbps laser diode driver that uses a

unique control algorithm to manage the average power and

extinction ratio of the laser after its initial factory calibration.

The ADN2841 stabilizes the data transmission of the laser by

continuously monitoring its optical power and correcting the

variations caused by temperature and the degradation of the

laser over time. In the ADN2841, the IMPD monitors the laser

diode current. Through its dual-loop power and extinction

ratio control calibrated by the dual RDACs of the AD5235, the

internal driver controls the bias current, IBIAS, and consequently

the average power. It also regulates the modulation current,

IMODP, by changing the modulation current linearly with slope

efficiency. Therefore, any changes in the laser threshold current

or slope efficiency are compensated for. As a result, the optical

supervisory system minimizes the laser characterization efforts

and, therefore, enables designers to apply comparable lasers

from multiple sources.

RESISTANCE SCALING

The AD5235 offers 25 kΩ or 250 kΩ nominal resistance. When

users need lower resistance but must maintain the number of

adjustment steps, they can parallel multiple devices. For example,

Figure 59 shows a simple scheme of paralleling two channels of

RDACs. To adjust half the resistance linearly per step, program

both RDACs concurrently with the same settings.

B1 W1 W2

02816-058

Figure 59. Reduce Resistance by Half with Linear Adjustment Characteristics

In voltage divider mode, by paralleling a discrete resistor, as

shown in Figure 60, a proportionately lower voltage appears at

Terminal A to Terminal B. This translates into a finer degree of

precision because the step size at Terminal W is smaller. The

voltage can be found as

R2RR3

R2R

DV ××

=1024//

)//(

)(

(16)

R2 A

02816-059

Figure 60. Lowering the Nominal Resistance

Figure 59 and Figure 60 show that the digital potentiometers

change steps linearly. Alternatively, pseudo log taper adjustment

is usually preferred in applications such as audio control. Figure 61

shows another type of resistance scaling. In this configuration,

the smaller the R2 with respect to RAB, the more the pseudo log

taper characteristic of the circuit behaves.

B1 W1 R

02816-060

Figure 61. Resistor Scaling with Pseudo Log Adjustment Characteristics

The equation is approximated as

RRD

QUIVALENT

×++×

+×

=1024200,51

200,51

(17)

Users should also be aware of the need for tolerance matching

as well as for temperature coefficient matching of the components.

Data Sheet AD5235

Rev. F | Page 29 of 32

RESISTANCE TOLERANCE, DRIFT, AND

TEMPERATURE COEFFICIENT MISMATCH

CONSIDERATIONS

In rheostat mode operation, such as gain control, the tolerance

mismatch between the digital potentiometer and the discrete

resistor can cause repeatability issues among various systems

(see Figure 62). Because of the inherent matching of the silicon

process, it is practical to apply the dual-channel device in this

type of application. As such, R1 can be replaced by one of the

channels of the digital potentiometer and programmed to a

specific value. R2 can be used for the adjustable gain. Although it

adds cost, this approach minimizes the tolerance and temperature

coefficient mismatch between R1 and R2. This approach also

tracks the resistance drift over time. As a result, these less than

ideal parameters become less sensitive to system variations.

AD8601

–

R1*

*REPLACED W ITH ANOTHER

CHANNEL O F RDAC

02816-061

Figure 62. Linear Gain Control with Tracking Resistance Tolerance,

Drift, and Temperature Coefficient

Note that the circuit in Figure 63 can track tolerance, temperature

coefficient, and drift in this particular application. The characteristic

of the transfer function is, however, a pseudo log rather than a

linear gain function.

AD8601

–

02816-062

A B

Figure 63. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive

loads dominate the ac characteristics of the RDACs. Configured

as a potentiometer divider, the −3 dB bandwidth of the AD5235

(25 kΩ resistor) measures 125 kHz at half scale. Figure 17 provides

the large signal bode plot characteristics of the two available

resistor versions, 25 kΩ and 250 kΩ. A parasitic simulation model

is shown in Figure 64.

RDAC

25k

Ω

80pF

11pF

02816-063

Figure 64. RDAC Circuit Simulation Model (RDAC = 25 kΩ)

The following code provides a macro model net list for the

25 kΩ RDAC:

.PARAM D = 1024, RDAC = 25 E3

.SUBCKT DPOT (A, W, B)

CA A 0 11E-12

RWA A W {(1-D/1024)* RDAC + 30}

CW W 0 80E-12

RWB W B {D/1024 * RDAC + 30}

CB B 0 11E-12

.ENDS DPOT

AD5235 Data Sheet

Rev. F | Page 30 of 32

OUTLINE DIMENSIONS

16 9

PI N 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX 0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COM P LIANT T O JEDEC S TANDARDS MO-153- AB

Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 RAB (kΩ)

Temperature

Range

Package

Description

Package

Option

Ordering

Quantity Branding3

AD5235BRUZ25 25 −40°C to +85°C 16-Lead TSSOP RU-16 96 5235B25

AD5235BRUZ25-RL7 25 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 5235B25

AD5235BRUZ250 250 −40°C to +85°C 16-Lead TSSOP RU-16 96 5235B250

AD5235BRUZ250-R7

250

−40°C to +85°C

16-Lead TSSOP

RU-16

1,000

5235B250

EVAL-AD5235SDZ

Evaluation Board

1 Z = RoHS Compliant Part.

2 The evaluation board is shipped with the 25 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

3 Line 1 contains the ADI logo followed by the date code, YYWW. Line 2 contains the model number followed by the end-to-end resistance value (note: D = 250 kΩ).

—OR—

Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YYWW.

Data Sheet AD5235

Rev. F | Page 31 of 32

NOTES

AD5235 Data Sheet

Rev. F | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

D02816-0-6/12(F)