dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 Family Silicon Errata and Data Sheet Clarification For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkitTM 3: The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04 and dsPIC33FJ128GPX02/X04 family devices that you have received conform functionally to the current Device Data Sheet (DS70292F), except for the anomalies described in this document. 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/ X04 silicon. Note: 4. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A5). Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device and Revision ID values for the various dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 silicon revisions are shown in Table 1. Data Sheet clarifications and corrections start on page 11, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the MPLAB ICD 3 programmer/debugger or PICkit 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. SILICON DEVREV VALUES Part Number Device ID(1) Revision ID for Silicon Revision(2) A1 dsPIC33FJ32GP302 0x0605 dsPIC33FJ32GP304 0x0607 dsPIC33FJ64GP202 0x0615 dsPIC33FJ64GP204 0x0617 dsPIC33FJ64GP802 0x061D dsPIC33FJ64GP804 0x061F Note 1: 2: A2 A3 A4 A5 0x3001 0x3002 0x3002 0x3003 0x3004 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) for detailed information on Device and Revision IDs for your specific device. (c) 2009-2011 Microchip Technology Inc. DS80443H-page 1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 TABLE 1: SILICON DEVREV VALUES (CONTINUED) Revision ID for Silicon Revision(2) Device ID(1) Part Number A1 dsPIC33FJ128GP202 0x0625 dsPIC33FJ128GP204 0x0627 dsPIC33FJ128GP802 0x062D dsPIC33FJ128GP804 0x062F Note 1: 2: TABLE 2: A2 A3 A4 A5 0x3001 0x3002 0x3002 0x3003 0x3004 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) for detailed information on Device and Revision IDs for your specific device. SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A1 A2 A3 A4 A5 UART IR Mode 1. The 16x baud clock signal on the BCLK pin is present only when the module is transmitting. X X X X X UART High-Speed Mode 2. When the UART is in 4x mode (BRGH = 1) and using two Stop bits (STSEL = 1), it may sample the first Stop bit instead of the second one. X X X X X SPI Transmit Operation 3. The SPI Transmit Buffer Full (SPITBF) flag does not get set immediately after writing to the buffer. X X X X X SPI Frame Mode 4. The SPI module will generate incorrect frame synchronization pulses in Frame Master mode if FRMDLY = 1. X X X X X I2CTM SFR Writes 5. The BCL bit in I2CSTAT can only be cleared with Word instructions, and can be corrupted with byte instructions and bit operations. X X X X X I2C 10-bit Addressing 6. When the I2C module is configured for 10-bit addressing using the same address bits (A10 and A9) as other I2C devices, A10 and A9 bits may not work as expected. X X X X X I2C 10-bit Addressing 7. When the I2C module is configured as a 10-bit slave with an address of 0x02, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02. X X X X X I2C -- 8. With the I2C module enabled, the PORT bits and external Interrupt Input functions (if any) associated with SCL and SDA pins will not reflect the actual digital logic levels on the pins. X X X X X I2C 10-bit Addressing 9. The 10-bit slave does not set the RBF flag or load the I2CxRCV register, on address match if the Least Significant bits (LSbs) of the address are the same as the 7-bit reserved addresses. X X X X X I2C -- 10. After the ACKSTAT bit is set when receiving a NACK, it may be cleared by the reception of a Start or Stop bit. X X X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80443H-page 2 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Number Affected Revisions(1) Issue Summary A1 A2 A3 A4 A5 UART Interrupts 11. The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. X X X X X UART IR Mode 12. When the UART module is operating in 8-bit mode (PDSEL = 0x) and using the IrDA(R) encoder/decoder (IREN = 1), the module incorrectly transmits a data payload of 80h as 00h. X X X X X Comparator Output Pin 13. When the CMCON<CxOUTEN> bit is set, the Comparator output pin cannot be used as a general purpose I/O pin even if the Comparator is disabled. X X X X X Internal Voltage Regulator Sleep Mode 14. When the VREGS bit (RCON<8>) is set to a logic `0' the device may reset and higher Sleep current may be observed. X X X X X PSV Operations -- 15. An address error trap occurs in certain addressing modes when accessing the first four bytes of any PSV page. X X X X X ECANTM Sleep Mode 16. The WAKIF bit in the CxINTF register cannot be cleared by software instruction after the device is interrupted from Sleep due to activity on the CAN bus. X X X X X ECAN Receive Operation 17. The ECAN module may not store the received data in the correct location. X X X CPU EXCH Instruction 18. The EXCH instruction does not execute correctly. X X X X X SPI Transmit Operation 19. Writing to the SPIxBUF register as soon as TBF bit is cleared will cause SPI module to ignore the written data. X X X X X UART Break Character Generation 20. The UART module will not generate back-to-back Break characters. X X X X X Audio DAC Voltage Specifications 21. The Audio DAC positive and negative output differential voltages may not meet the specifications listed in the data sheet. X X X ADC Current Consumption in Sleep Mode 22. If the ADC module is in an enabled state when the device enters Sleep mode, the power-down current (IPD) of the device may exceed the device data sheet specifications. X X X X X JTAG Boundary Scan 23. On 28-pin devices, Boundary Scan does not function correctly for pin 7. X X X X X RTCC Operation During Reset 24. The RTCC module gets reset on any device Reset, instead of getting reset only on a POR or BOR. X X X X X All 150C Operation 25. These revisions of silicon only support 140C operation instead of 150C for Hi-Temp operating temperature. X X X I/O Port Data Direction Setting 26. When the RB8 pin is in open-drain configuration, the data direction depends upon the TRISB9 bit instead of the TRISB8 bit. X X X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. (c) 2009-2011 Microchip Technology Inc. DS80443H-page 3 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Item Number Affected Revisions(1) Issue Summary A1 A2 A3 A4 A5 CPU Interrupt Disable 27. When a previous DISI instruction is active (i.e., the DISICNT register is non-zero), and the value of the DISICNT register is updated manually, the DISICNT register freezes and disables interrupts permanently. X X X X X CPU div.sd 28. When using the div.sd instruction, the overflow bit is not getting set when an overflow occurs. X X X X X UART TX Interrupt 29. A transmit (TX) Interrupt may occur before the data transmission is complete. X X X X X JTAG Flash Programming 30. JTAG Flash programming is not supported. X X X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80443H-page 4 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 Silicon Errata Issues Note: 4. Module: SPI This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A5). 1. Module: UART The SPI module will generate incorrect frame synchronization pulses when configured in Frame Master mode if the start of data is selected to coincide with the start of the frame synchronization pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1). However, the module functions correctly in Frame Slave mode, and also in Frame Master mode if FRMDLY = 0. Work around When the UART is configured for IR interface operations (UxMODE<9:8> = 11), the 16x baud clock signal on the BCLK pin is present only when the module is transmitting. The pin is idle at all other times. If DMA is not being used, manually drive the SSx pin (x = 1 or 2) high using the associated PORT register, and then drive it low after the required 1 bit-time pulse width. This operation needs to be performed when the transmit buffer is written. Work around If DMA is being used, and if no other peripheral modules are using DMA transfers, use a timer interrupt to periodically generate the frame synchronization pulse (using the method described above) after every 8 or 16-bit periods (depending on the data word size, configured using the MODE16 bit). Configure one of the output compare modules to generate the required baud clock signal when the UART is receiving data or in an Idle state. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X If FRMDLY = 0, no work around is needed. Affected Silicon Revisions 2. Module: UART When the UART is in 4x mode (BRGH = 1) and using two Stop bits (STSEL = 1), it may sample the first Stop bit instead of the second one. This issue does not affect the other UART configurations. Work around Use the 16x baud rate option (BRGH = 0) and adjust the baud rate accordingly. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X A1 A2 A3 A4 A5 X X X X X 5. Module: I2CTM The BCL bit in I2CSTAT can only be cleared with Word instructions, and can be corrupted with byte instructions and bit operations. Work around Use Word instructions to clear BCL. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 3. Module: SPI The SPI Transmit Buffer Full (SPITBF) flag does not get set immediately after writing to the buffer. Work around After a write to the SPI buffer, poll the SPITBF flag until the flag gets set, indicating that the transmit buffer is not full. Afterwards, poll the SPITBF flag again until the flag gets cleared, indicating that the transmit has started and that the transmit buffer is empty and another write can occur. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X (c) 2009-2011 Microchip Technology Inc. DS80443H-page 5 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 6. Module: I2C 9. Module: I2C If there are two I2C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are configured for 10-bit Addressing mode, and have the same value in the A10 and A9 bits of their addresses, then when the Slave select address is sent from the Master, both the Master and Slave acknowledge it. When the Master sends out the read operation, both the Master and the Slave enter into Read mode and both of them transmit the data. The resultant data will be the ANDing of the two transmissions. In 10-bit Addressing mode, some address matches do not set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: Work around Work around In all I2C devices, the addresses as well as bits A10 and A9 should be different. Ensure that the lower address byte in 10-bit Addressing mode does not match any 7-bit reserved addresses. Affected Silicon Revisions * * * * 001111000X 011111001X 101111010X 111111011X Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X A1 A2 A3 A4 A5 X X X X X 2 7. Module: I C When the I2C module is configured as a 10-bit slave with and address of 0x02, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02; however, the module acknowledges both address bytes. 10. Module: I2C When the I2C module is operating in either Master or Slave mode, after the ACKSTAT bit is set when receiving a NACK, it may be cleared by the reception of a Start or Stop bit. Work around Work around None. Store the value of the ACKSTAT bit immediately after receiving a NACK from the master. Affected Silicon Revisions Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 8. Module: A1 A2 A3 A4 A5 X X X X X I2C With the I2C module enabled, the PORT bits and external interrupt input functions (if any) associated with the SCL and SDA pins do not reflect the actual digital logic levels on the pins. 11. Module: UART The UART error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. Work around Work around If the SDA and/or SCL pins need to be polled, these pins should be connected to other port pins in order to be read correctly. This issue does not affect the operation of the I2C module. Read the error flags in the UxSTA register whenever a byte is received to verify the error status. In most cases, these bits will be correct, even if the UART error interrupt fails to occur. Affected Silicon Revisions Affected Silicon Revisions A1 A2 A3 A4 A5 A1 A2 A3 A4 A5 X X X X X X X X X X DS80443H-page 6 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 12. Module: UART 15. Module: PSV Operations When the UART is operating in 8-bit mode (PDSEL = 0x) and using the IrDA encoder/decoder (IREN = 1), the module incorrectly transmits a data payload of 80h as 00h. An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: Work around * MOV.D * Register Indirect Addressing (Word or Byte mode) with pre/post-decrement None. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 13. Module: Comparator If CMCON<CxOUTEN> bit is set and the comparator module CMCON<CxEN> bit is disabled, the remappable comparator output pins, C1OUT and C2OUT, cannot be used as general purpose I/O pins. Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes. For applications using the C language, MPLAB C30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 tool suite for further details. Affected Silicon Revisions Work around When the comparator module is disabled the CMCON<CxOUTEN> bit should be reset so that the remappable comparator output pins C1OUT and C2OUT are not driven onto the output pad. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 14. Module: Internal Voltage Regulator When the VREGS bit (RCON<8>) is set to a logic `0', the device may reset and a higher Sleep current may be observed. Work around Ensure VREGS bit (RCON<8>) is set to a logic `1' for device Sleep mode operation. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X A1 A2 A3 A4 A5 X X X X X 16. Module: ECANTM The WAKIF bit in the CxINTF register cannot be cleared by software instruction after the device is interrupted from Sleep due to activity on the CAN bus. When the device wakes up from Sleep due to CAN bus activity, the ECAN module is placed in operational mode. The ECAN Event interrupt occurs due to the WAKIF flag. Trying to clear the flag in the Interrupt Service Routine (ISR) may not clear the flag. The WAKIF bit being set will not cause repetitive Interrupt Service Routine execution. Work around Although the WAKIF bit does not clear, the device Sleep and ECAN Wake function continue to work as expected. If the ECAN event is enabled, the CPU will enter the Interrupt Service Routine due to the WAKIF flag getting set. The application can maintain a secondary flag, which tracks the device Sleep and Wake events. Affected Silicon Revisions (c) 2009-2011 Microchip Technology Inc. A1 A2 A3 A4 A5 X X X X X DS80443H-page 7 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 17. Module: ECAN 19. Module: SPI The ECAN module may not store received data in the correct location. When this occurs, the receive buffers will become corrupted. In addition, it is also possible for the transmit buffers to become corrupted. This issue is more likely to occur as the CAN bus speed approaches 1 Mbps. Work around Do not use the DMA with ECAN in Peripheral Indirect mode. Use the DMA in Register Indirect mode, Continuous mode enabled and Ping Pong mode disabled. The receive DMA channel count should be set to 8 words. The transmit DMA channel count should be set for the actual message size (maximum of 7 words for Extended CAN messages and 6 words for Standard CAN Messages). To simplify application error handling while using this mode, only one TX buffer should be used. While message filtering is not affected, messages will not be stored at distinct RX buffers. Instead all messages are stored contiguously in memory. The start of this memory is pointed to by the receive DMA channel. The application must still clear RXFUL flags and other interrupt flags. The application must manage the RX buffer memory. Affected Silicon Revisions A1 A2 A3 X X X A4 A5 18. Module: CPU Writing to the SPIxBUF register as soon as the TBF bit is cleared will cause the SPI module to ignore the written data. Applications which use SPI with DMA will not be affected by this erratum. Work around After the TBF bit is cleared, wait for a minimum duration of one SPI Clock before writing to the SPIxBuf register. Alternatively, do one of the following: * Poll the RBF bit and wait for it to get set before writing to the SPIxBUF register * Poll the SPI Interrupt flag and wait for it to get set before writing to the SPIxBUF register * Use an SPI Interrupt Service Routine * Use DMA Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 20. Module: UART The UART module will not generate consecutive break characters. Trying to perform a back-to-back Break character transmission will cause the UART module to transmit the dummy character used to generate the first Break character instead of transmitting the second Break character. Break characters are generated correctly if they are followed by non-Break character transmission. The EXCH instruction does not execute correctly. Work around Work around None. If writing source code in assembly, recommended work around is to replace: the EXCH Wsource, Wdestination with: Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X PUSH Wdestination MOV Wsource, Wdestination POP Wsource If using the MPLAB C30 C compiler, specify the compiler option: -merrata=exch (Project > Build Options > Projects > MPLAB C30 > Use Alternate Settings). Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X DS80443H-page 8 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 21. Module: Audio DAC 23. Module: JTAG The Audio DAC positive differential output voltage and negative differential output voltage (parameters DA01 and DA02, respectively) may not meet the specifications listed in the data sheet. On 28-pin devices, JTAG Boundary Scan does not function correctly for pin 7. Both pins 6 and 7 respond to stimulus applied to pin 7. Work around None. Do not include pin 7 in the JTAG Boundary Scan chain for 28-pin devices. Affected Silicon Revisions Affected Silicon Revisions A1 A2 A3 X X X A4 A5 22. Module: ADC Work around A1 A2 A3 A4 A5 X X X X X 24. Module: RTCC If the ADC module is in an enabled state when the device enters Sleep mode as a result of executing a PWRSAV #0 instruction, the device power-down current (IPD) may exceed the specifications listed in the device data sheet. This may happen even if the ADC module is disabled by clearing the ADON bit prior to entering Sleep mode. The RTCC module gets reset on any device Reset, instead of getting reset only on a POR or BOR. Work around 1: Affected Silicon Revisions In order to remain within the IPD specifications listed in the device data sheet, the user software must completely disable the ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV #0 instruction. Note: The ADC module must be reinitialized by the user application before resuming ADC operation. Work around 2: If the ADC module was previously initialized and enabled, before entering Sleep, execute the lines of code provided in Example 1. Note: Work around None. A1 A2 A3 A4 A5 X X X X X 25. Module: All The affected silicon revisions listed below are not warranted for operation at 150C. Work around Only use the affected revisions of silicon for Hi-Temp operating range from -40C to +140C. Affected Silicon Revisions A1 A2 A3 X X X A4 A5 Unlike Work around 1, the user application does not need to reinitialize the ADC module; however, it is necessary to re-enable the ADC module by setting the ADON bit after waking from Sleep. EXAMPLE 1: AD1CON1bits.ADON = 0; __asm__ volatile ("REPEAT #50"); __asm__ volatile ("NOP"); Sleep(); //Disable the ADC module //Wait 50 Tcy //Repeat NOP 51 times // Execute PWRSAV #0 and go to Sleep Affected Silicon Revisions A1 A2 A3 X X X A4 A5 (c) 2009-2011 Microchip Technology Inc. DS80443H-page 9 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 26. Module: I/O Port 29. Module: UART When the ODCB8 bit is set to `1' (open-drain configuration), the data direction on the RB8 pin is controlled by the TRISB9 bit instead of the TRISB8 bit. Work around Do not use the RB8 pin in open-drain configuration while simultaneously using the RB9 pin. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 27. Module: CPU When using UTXISEL = 01 (Interrupt when last character is shifted out of the Transmit Shift Register) and the final character is being shifted out through the Transmit Shift Register, the Transmit (TX) Interrupt may occur before the final bit is shifted out. Work around If it is critical that the interrupt processing occur only when all transmit operations are complete. Hold off the interrupt routine processing by adding a loop at the beginning of the routine that polls the Transmit Shift Register Empty bit (TRMT) before processing the rest of the interrupt. Affected Silicon Revisions When a previous DISI instruction is active (i.e., the DISICNT register is non-zero), and the value of the DISICNT register is updated manually, the DISICNT register freezes and disables interrupts permanently. Work around Avoid updating the DISICNT register manually. Instead, use the DISI #n instruction with the required value for 'n'. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X A1 A2 A3 A4 A5 X X X X X 30. Module: JTAG JTAG Flash programming is not supported. Work around None. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X 28. Module: CPU When using the Signed 32-by-16-bit Division instruction, div.sd, the overflow bit does not always get set when an overflow occurs. Work around Test for and handle overflow conditions outside of the div.sd instruction. Affected Silicon Revisions A1 A2 A3 A4 A5 X X X X X DS80443H-page 10 (c) 2009-2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70292F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. No issues to report at this time. (c) 2009-2011 Microchip Technology Inc. DS80443H-page 11 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 APPENDIX A: REVISION HISTORY Rev A Document (3/2009) Initial release of this document; issued for revision A1, A2 and A3 silicon. Includes silicon issues 1-2 (UART), 3-4 (SPI), 5-10 (I2CTM), 11-12 (UART), 13 (Comparator), 14 (Internal Voltage Regulator), 15 (PSV Operations), 16-17 (ECANTM), 18 (CPU) and 19 (SPI). This document replaces the following errata document: "dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 Rev. A1/A2/A3 Silicon Errata" (DS80371) Rev B Document (4/2009) Corrected part numbers. Rev C Document (8/2009) Added silicon issue 20 (UART). Added data sheet Characteristics). clarification 1 (Electrical Rev D Document (1/2010) Added Rev. A4 silicon information. Added silicon issue 21 (Audio DAC). Rev E Document (6/2010) Updated silicon issue 18 (CPU). Added silicon issues 22 (ADC), 23 (JTAG) and 24 (RTCC), and data sheet clarification 2 (DC Characteristics: I/O Pin Input Specifications). Rev F Document (10/2010) Updated the work around in silicon issue 22 (ADC). Added silicon issue 25 (All). Rev G Document (3/2011) Removed data sheet clarification 1. Updated the Affected Silicon Revisions for item 25 in Table 2 and in silicon issue 25 (All). Added silicon issue 26 (I/O Port). Rev H Document (11/2011) Updated the current Device Data Sheet revision to "F". Added Rev. A5 silicon information. Added silicon issues 27 (CPU), 28 (CPU), 29 (UART), and 30 (JTAG). DS80443H-page 12 (c) 2009-2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-825-3 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009-2011 Microchip Technology Inc. DS80443H-page 13 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS80443H-page 14 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 08/02/11 (c) 2009-2011 Microchip Technology Inc.