4Gb: x4, x8, x16 DDR3L-RS SDRAM Description 1.35V DDR3L-RS SDRAM MT41K1G4 - 128 Meg x 4 x 8 banks MT41K512M8 - 64 Meg x 8 x 8 banks MT41K256M16 - 32 Meg x 16 x 8 banks Description Features * Self refresh temperature (SRT) * Automatic self refresh (ASR) * Temperature-compensated self refresh (TCSR) mode * Very low current self refresh mode when room temperature The 1.35V DDR3L-RS SDRAM device is a low-current self refresh version of the 1.35V DDR3L SDRAM device via the TCSR feature. Unless stated otherwise, the DDR3L-RS SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3L SDRAM data sheet located on www.micron.com. Options Features * * * * * * * * * * * * * * * * Marking * Configuration - 1 Gig x 4 - 512 Meg x 8 - 256 Meg x 16 * FBGA package (Pb-free) - x4, x8 - 78-ball (10.5mm x 12mm) Rev. D - 78-ball (9mm x 10.5mm) Rev. E * FBGA package (Pb-free) - x16 - 96-ball FBGA (10mm x 14mm) Rev. D - 96-ball FBGA (9mm x 14mm) Rev. E * Timing - cycle time - 1.071ns @ CL = 13 (DDR3-1866) - 1.25ns @ CL = 11 (DDR3-1600) - 1.5ns @ CL = 9 (DDR3-1333) - 1.875ns @ CL = 7 (DDR3-1066) * Temperature - Commercial (0C T C +95C) * Power Saving - TCSR * Revision VDD = V DDQ = 1.35V (1.283-1.45V) Backward-compatible to V DD = V DDQ = 1.5V 0.075V Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Programmable posted CAS additive latency (AL) Programmable CAS (WRITE) latency (CWL) Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Write leveling Output driver calibration Multipurpose register TC of 0C to +95C - 64ms, 8192-cycle refresh at 0C to +85C - 32ms at +85C to +95C 1G4 512M8 256M16 RA RH RE HA -107 -125 -15E -187E None M :D/:E Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -1071, 2, 3 1866 13-13-13 13.91 13.91 13.91 -1251, 2 1600 11-11-11 13.75 13.75 13.75 -15E1 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 Notes: tRCD (ns) tRP (ns) CL (ns) 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL =11 (-125). PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Description Table 2: Addressing Parameter Configuration 1 Gig x 4 512 Meg x 8 256 Meg x 16 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 64K (A[15:0]) 64K (A[15:0]) 32K (A[14:0]) Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) 1KB 1KB 2KB Column address Page size Figure 1: DDR3L-RS Part Numbers Example Part Number: MT41K512M8RH-125M:E Configuration Package Speed PS Revision { MT41K : Configuration :D/:E 1 Gig x 4 1G4 512 Meg x 8 512M8 Power Saving TCSR 256 Meg x 16 256M16 M Temperature Package Note: Revision Commercial 78-ball 10.5mm x 12mm FBGA RA 78-ball 9mm x 10.5mm FBGA RH 96-ball 10mm x 14mm FBGA RE 96-ball 9mm x 14mm FBGA HA -107 None Speed Grade tCK = 1.071ns, CL = 13 -15E tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 9 -187E tCK = 1.87ns, CL = 7 -125 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron's FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 2: 78-Ball FBGA - x4, x8 (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 A15 VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N Notes: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. Ball descriptions listed in Table 3 (page 5) are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 3). 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Figure 3: 96-Ball FBGA - x16 (Top View) A B 1 2 3 VDDQ DQ13 VSSQ 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS C 4 5 6 D E F G H J K L M N P R T Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. A slash defines a selectable function. 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions Symbol Type Description [15:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in the DDR3 SDRAM data sheet. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions (Continued) Symbol Type DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to REFDQ. DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. VDD Supply Power supply: 1.35V, 1.283-1.45V operational; compatible to 1.5V operation. VDDQ Supply DQ power supply: 1.35V, 1.283-1.45V operational; compatible to 1.5V operation. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data:REFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF - No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN Description External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA - x16 Ball Descriptions Symbol Type Description [14:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in the DDR3 SDRAM data sheet. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA - x16 Ball Descriptions (Continued) Symbol Type Description RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. VDD Supply Power supply: 1.35V, 1.283-1.45V operational; compatible to 1.5V operation. VDDQ Supply DQ power supply: 1.35V, 1.283-1.45V operational; compatible to 1.5V operation. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC - PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Package Dimensions Package Dimensions Figure 4: 78-Ball FBGA - x4, x8 (RA) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 78X O0.45 Dimensions apply to solder balls postreflow on O0.35 SMD ball pads. Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N 12 0.1 9.6 CTR 0.8 TYP 1.1 0.1 0.8 TYP 6.4 CTR 0.25 MIN 10.5 0.1 Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. All dimensions are in millimeters. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Package Dimensions Figure 5: 78-Ball FBGA - x4, x8 (RH) 0.155 Seating plane A 78X O0.45 Dimensions apply to solder balls postreflow on O0.35 SMD ball pads. 0.12 A 1.8 CTR Nonconductive overmold Ball A1 ID (covered by SR) 9 8 7 3 2 Ball A1 ID 1 A B C D E F 10.5 0.1 G 9.6 CTR H J K L M N 0.8 TYP 0.8 TYP 1.1 0.1 6.4 CTR 0.25 MIN 9 0.1 Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. All dimensions are in millimeters. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Package Dimensions Figure 6: 96-Ball FBGA - x16 (RE) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 96X O0.45 Dimensions apply to solder balls post-reflow on O0.35 SMD ball pads Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 14 0.1 12 CTR 0.8 TYP 1.1 0.1 0.8 TYP 0.25 MIN 6.4 CTR 10 0.1 Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. All dimensions are in millimeters. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Package Dimensions Figure 7: 96-Ball FBGA - x16 (HA) 0.155 Seating plane 96X O0.45 Dimensions apply to solder balls post-reflow on O0.35 SMD ball pads. 1.8 CTR Nonconductive overmold 9 8 7 3 A 2 0.12 A Ball A1 Index (covered by SR) 1 Ball A1 Index A B C D E F G H 12 CTR J 14 0.1 K L M N P R 0.8 TYP T 1.1 0.1 0.8 TYP 6.4 CTR 0.25 MIN 9 0.1 Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. All dimensions are in millimeters. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Characteristics - IDD Specifications Electrical Characteristics - IDD Specifications Table 5: IDD Maximum Limits - Die Rev. D Speed Bin Symbol Width DDR3L-RS -1066 DDR3L-RS -1333 DDR3L-RS -1600 Unit Notes Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 x4,x8 60 65 75 mA 1 x16 75 80 90 mA 1 Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 x4 70 75 80 mA 1 x8 77 82 87 mA 1 Parameter x16 105 110 115 mA 1 Precharge power-down current: Slow exit IDD2P0 All 15 15 15 mA 1 Precharge power-down current: Fast exit IDD2P1 All 28 30 35 mA 1 Precharge quiet standby current IDD2Q All 39 42 47 mA 1 Precharge standby current IDD2N All 39 42 47 mA 1 Precharge standby ODT current IDD2NT x4, x8 40 45 50 mA 1 x16 45 50 55 mA 1 Active power-down current IDD3P All 45 50 55 mA 1 Active standby current IDD3N x4, x8 47 52 57 mA 1 x16 60 65 70 mA 1 x4 125 145 165 mA 1 x8 137 157 177 mA 1 x16 210 230 270 mA 1 x4 105 125 145 mA 1 x8 115 135 155 mA 1 x16 170 190 215 mA 1 Burst read operating current IDD4R Burst write operating current IDD4W Burst refresh current IDD5B All 200 205 215 mA 1 Room temperature self refresh IDD6 All 5.8 5.8 5.8 mA 2 +45C temperature self refresh IDD6 All 6.0 6.0 6.0 mA 3 Elevated temperature self refresh IDD6 All 10 10 10 mA 4 Extended temperature self refresh IDD6ET All banks interleaved read current IDD7 Reset current IDD8 Notes: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. 2. 3. 4. 5. All 12 12 12 mA 5 All 16 16 16 mA 6 All 22 22 22 mA 7 x4,x8 200 240 280 mA 1 x16 255 280 315 mA 1 all IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1 TC = +85C; SRT is disabled, ASR is disabled. Value is maximum. TC Room Temperature; SRT is disabled, ASR is enabled. Value is typical. TC +45C; SRT is disabled, ASR is enabled. Value is typical. TC = +80C; SRT is disabled, ASR is enabled. Value is typical. +45C < TC +80C; SRT is disabled, ASR is enabled. Value is maximum. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Characteristics - IDD Specifications 6. TC = +95C; SRT is disabled, ASR is enabled. Value is typical. 7. +85C < TC +95C; SRT is disabled, ASR is enabled. Value is maximum. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Characteristics - IDD Specifications Table 6: IDD Maximum Limits - Die Rev. E Speed Bin Parameter DDR3L-RS -1066 DDR3L-RS -1333 DDR3L-RS -1600 DDR3L-RS -1866 x4,x8 44 47 55 58 mA 1 x16 55 58 66 69 mA 1 x4 53 57 61 65 mA 1 x8 59 62 66 70 mA 1 Symbol Width Unit Notes Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 x16 80 84 87 91 mA 1 Precharge power-down current: Slow exit IDD2P0 All 12 12 12 12 mA 1 Precharge power-down current: Fast exit IDD2P1 All 24 26 30 35 mA 1 Precharge quiet standby current IDD2Q All 22 24 27 30 mA 1 Precharge standby current IDD2N All 22 24 26 29 mA 1 Precharge standby ODT current IDD2NT x4, x8 27 30 34 37 mA 1 x16 30 34 37 40 mA 1 Active power-down current IDD3P All 27 30 33 36 mA 1 Active standby current IDD3N x4, x8 29 32 35 38 mA 1 x16 37 40 43 46 mA 1 x4 105 122 139 160 mA 1 x8 115 132 149 170 mA 1 x16 176 193 227 244 mA 1 x4 80 95 110 125 mA 1 x8 87 103 118 133 mA 1 x16 129 144 163 186 mA 1 Burst read operating current IDD4R Burst write operating current IDD4W Burst refresh current IDD5B All 141 144 151 158 mA 1 Room temperature self refresh IDD6 All 3.5 3.5 3.5 3.5 mA 2 +45C temperature self refresh IDD6A All 3.7 3.7 3.7 3.7 mA 3 Elevated temperature self refresh IDD6 All 7 7 7 7 mA 4 All 8.5 8.5 8.5 8.5 mA 5 Extended temperature self refresh IDD6ET All 14 14 14 14 mA 6 All 18 18 18 18 mA 7 All banks interleaved read current IDD7 x8 152 182 213 243 mA 1 194 213 239 266 Reset current IDD8 Notes: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. 2. 3. 4. 5. 6. x16 all IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1 mA 1 TC = +85C; SRT is disabled, ASR is disable. Value is maximum. Room Temperature; SRT is disabled, ASR is enabled. Value is typical. TC +45C; SRT is disabled, ASR is enabled). Value is typical. TC = +80C; SRT is disabled, ASR is enabled). Value is typical. +45C < TC +80C; SRT is disabled, ASR is enabled. Value is maximum. TC = +95C; SRT is disabled, ASR is enabled. Value is typical. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Temperature Compensated Self Refresh (TCSR) 7. +85C < TC +95C; SRT is disabled, ASR is enabled. Value is maximum. Temperature Compensated Self Refresh (TCSR) Temperature compensated self refresh (TCSR) feature substantially reduces the self refresh current (IDD6). TCSR takes affect when when T C is less than 45C and the auto self refresh (ASR) function is enabled. ASR is required to utilize the TCSR feature and is enabled manually via Mode Register 2 (MR2[6]). See Figure 8 (page 16). Enabling ASR also automatically changes the DRAM self refresh rate from 1x to 2x when the case temperature exceeds +85C. This allows the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of +95C while in self refresh mode. When ASR is disabled and T C is 0C to 85C, the self refresh mode's refresh rate is assumed to be at the normal rate (sometimes referred to as 1x refresh rate). Also, if ASR is disabled and T C is 85C to 95C, the user must select the SRT extended temperature self refresh rate (sometimes referred to as 2x refresh rate). SRT is selected via mode register 2 (MR2[7]) register. See Figure 8 (page 16). SPD settings should always support 05h (101 binary) in Byte 31. Mode Register 2 (MRS) The mode register 2 (MR2) controls additional functions and features not available in the other mode registers. The auto self refresh (ASR) function is of particular interest for the DDR3L-RS SDRAM because the Micron DDR3L-RS SDRAM goes into TCSR mode when ASR has been enabled. This function is controlled via the bits shown in the figure below. Figure 8: Mode Register 2 (MR2) Definition BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 0 01 01 01 RTT(WR) 01 SRT ASR Mode register 2 (MR2) 5 01 1 M15 M14 0 0 0 1 1 Mode Register PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 3 M5 M4 M3 2 1 0 01 01 01 CAS Write Latency (CWL) 5 CK (tCK 2.5ns) Mode register set 0 (MR0) 0 Normal (0C to 85C) 0 0 0 1 Mode register set 1 (MR1) 1 Extended (0C to 95C) 0 0 1 0 Mode register set 2 (MR2) 0 1 0 1 Mode register set 3 (MR3) 0 1 1 1 0 0 8 CK (1.5ns > tCK 1.25ns) 9 CK (1.25ns > tCK 1.07ns) 10 CK (1.071ns > tCK 0.938ns) M10 M9 Note: M7 Self Refresh Temperature 4 CWL Dynamic ODT (R TT(WR) ) 0 0 RTT(WR) disabled 0 1 RZQ/4 1 0 RZQ/2 1 1 Reserved 6 CK (2.5ns > tCK 1.875ns) 7 CK (1.875ns > tCK 1.5ns) Auto Self Refresh (Optional) 1 0 1 M6 1 1 0 Reserved 0 Disabled: Manual 1 1 1 Reserved 1 Enabled: Automatic 1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Electrical Specifications Table 7: Input/Output Capacitance Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet DDR3L-800 DDR3L-1066 DDR3L-1333 Capacitance DDR3L-1600 DDR3L-1866 Parameters Symbol Min Max Min Max Min Max Min Max Min Max Units Single-end I/O: DQ, DM CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF Differential I/O: DQS, DQS#, TDQS, TDQS# CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF Inputs (CTRL, CMD,ADDR) CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF Table 8: DC Electrical Characteristics and Operating Conditions - 1.35V Operation All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Supply voltage VDD 1.283 1.35 I/O supply voltage VDDQ 1.283 1.35 Notes: Units Notes 1.45 V 1, 2, 3, 4 1.45 V 1, 2, 3, 4 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (for example, 1 sec). 2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 9 (page 29)). Table 9: DC Electrical Characteristics and Operating Conditions - 1.5V Operation All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Supply voltage VDD 1.425 1.5 I/O supply voltage VDDQ 1.425 1.5 Notes: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN Units Notes 1.575 V 1, 2, 3 1.575 V 1, 2, 3 1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 9 (page 29)). 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 10: Input Switching Conditions - Command and Address Parameter/Condition Input high AC voltage: Logic 1 Symbol VIH(AC160)min DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units 1 160 160 - mV 1 Input high AC voltage: Logic 1 VIH(AC135)min 135 135 135 mV Input high AC voltage: Logic 1 VIH(AC125)min1 - - 125 mV Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90)min -90 -90 -90 mV 1 Input low AC voltage: Logic 0 VIL(AC125)min - - -125 mV Input low AC voltage: Logic 0 VIL(AC135)min1 -135 -135 -135 mV Input low AC voltage: Logic 0 1 -160 -160 - mV Note: VIL(AC160)min 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135) of 365ps; independently, the data inputs may use either VIH(AC160),min or VIH(AC135),min. Table 11: Input Switching Conditions - DQ and DM Parameter/Condition Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Symbol VIH(AC160)min DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units 1 160 160 - mV 1 135 135 135 mV VIH(AC135)min 1 Input high AC voltage: Logic 1 VIH(AC130)min - - 130 mV Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90)min -90 -90 -90 mV 1 - - -130 mV Input low AC voltage: Logic 0 VIL(AC135)min 1 -135 -135 -135 mV Input low AC voltage: Logic 0 VIL(AC160)min1 -160 -160 - mV Input low AC voltage: Logic 0 Note: VIL(AC130)min 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the data inputs must use either VIH(AC160),min with tIS(AC160) of 90ps or VIH(AC135),min with tIS(AC135) of 140ps; independently, the address/command inputs may use either VIH(AC160),min or VIH(AC135),min. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 12: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Units Differential input logic high - slew VIH,diff(AC)slew 180 N/A mV Differential input logic low - slew VIL,diff(AC)slew N/A -180 mV Differential input logic high VIH,diff(AC) 2 x (VIH(AC) - VREF) VDD/VDDQ mV Differential input logic low VIL,diff(AC) VSS/VSSQ 2 x (VIL(AC) - VREF) mV VSEH VDDQ/2 + 160 VDDQ mV Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes VSEL Single-ended low level for CK, CK# VDD/2 + 160 VDD mV VSSQ VDDQ/2 - 160 mV VSS VDD/2 - 160 mV Table 13: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback DDR3L-800/1066/1333/1600 tDVAC tDVAC DDR3L-1866 tDVAC tDVAC tDVAC Slew Rate (V/ns) at 320mV (ps) at 270mV (ps) at 270mV (ps) at 250mV (ps) at 260mV (ps) >4.0 189 201 163 168 176 4.0 189 201 163 168 176 3.0 162 179 140 147 154 2.0 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 55 1.2 Note1 44 5 22 24 1.0 Note1 Note1 Note1 Note1 Note1 <1.0 Note1 Note1 Note1 Note1 Note1 Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 14: RTT Effective Impedance Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [9, 6, 2] RTT Resistor VOUT Min 0, 1, 0 120 RTT,120PD240 RTT,120PU240 120 0, 0, 1 60 RTT,60PD120 RTT,60PU120 60 0, 1, 1 40 RTT,40PD80 RTT,40PU80 40 1, 0, 1 30 RTT,30PD60 RTT,30PU60 30 1, 0, 0 20 RTT,20PD40 RTT,20PU40 20 PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN Nom Max Units 0.2 x VDDQ 0.6 1.0 1.15 RZQ/1 0.5 x VDDQ 0.9 1.0 1.15 RZQ/1 0.8 x VDDQ 0.9 1.0 1.45 RZQ/1 0.2 x VDDQ 0.9 1.0 1.45 RZQ/1 0.5 x VDDQ 0.9 1.0 1.15 RZQ/1 0.8 x VDDQ 0.6 1.0 1.15 RZQ/1 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/2 0.2 x VDDQ 0.6 1.0 1.15 RZQ/2 0.5 x VDDQ 0.9 1.0 1.15 RZQ/2 0.8 x VDDQ 0.9 1.0 1.45 RZQ/2 0.2 x VDDQ 0.9 1.0 1.45 RZQ/2 0.5 x VDDQ 0.9 1.0 1.15 RZQ/2 0.8 x VDDQ 0.6 1.0 1.15 RZQ/2 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/4 0.2 x VDDQ 0.6 1.0 1.15 RZQ/3 0.5 x VDDQ 0.9 1.0 1.15 RZQ/3 0.8 x VDDQ 0.9 1.0 1.45 RZQ/3 0.2 x VDDQ 0.9 1.0 1.45 RZQ/3 0.5 x VDDQ 0.9 1.0 1.15 RZQ/3 0.8 x VDDQ 0.6 1.0 1.15 RZQ/3 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/6 0.2 x VDDQ 0.6 1.0 1.15 RZQ/4 0.5 x VDDQ 0.9 1.0 1.15 RZQ/4 0.8 x VDDQ 0.9 1.0 1.45 RZQ/4 0.2 x VDDQ 0.9 1.0 1.45 RZQ/4 0.5 x VDDQ 0.9 1.0 1.15 RZQ/4 0.8 x VDDQ 0.6 1.0 1.15 RZQ/4 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/8 0.2 x VDDQ 0.6 1.0 1.15 RZQ/6 0.5 x VDDQ 0.9 1.0 1.15 RZQ/6 0.8 x VDDQ 0.9 1.0 1.45 RZQ/6 0.2 x VDDQ 0.9 1.0 1.45 RZQ/6 0.5 x VDDQ 0.9 1.0 1.15 RZQ/6 0.8 x VDDQ 0.6 1.0 1.15 RZQ/6 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/12 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 15: Reference Settings for ODT Timing Measurements Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Measured Parameter RTT,nom Setting RTT(WR) Setting tAON tAOF tAONPD tAOFPD tADC VSW1 VSW2 RZQ/4 (60) N/A 50mV 100mv RZQ/12 (20) N/A 100mV 200mV RZQ/4 (60) N/A 50mV 100mv RZQ/12 (20) N/A 100mV 200mV RZQ/4 (60) N/A 50mV 100mv RZQ/12 (20) N/A 100mV 200mV RZQ/4 (60) N/A 50mV 100mv RZQ/12 (20) N/A 100mV 200mV RZQ/12 (20) RZQ/2 (20) 200mV 250mV Table 16: 34 Driver Impedance Characteristics Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [5, 1] RON Resistor VOUT Min 0, 1 34.3 RON,34PD RON,34PU Pull-up/pull-down mismatch (MMPUPD) Note: Nom Max1 Units 0.2 x VDDQ 0.6 1.0 1.15 RZQ/7 0.5 x VDDQ 0.9 1.0 1.15 RZQ/7 0.8 x VDDQ 0.9 1.0 1.45 RZQ/7 0.2 x VDDQ 0.9 1.0 1.45 RZQ/7 0.5 x VDDQ 0.9 1.0 1.15 RZQ/7 0.8 x VDDQ 0.6 1.0 1.15 RZQ/7 VIL(AC) to VIH(AC) -10 N/A 10 % 1. A larger maximum limit will result in slightly lower minimum currents. Table 17: 40 Driver Impedance Characteristics Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [5, 1] RON Resistor VOUT Min 0, 0 40 RON,40PD RON,40PU Pull-up/pull-down mismatch (MMPUPD) Note: PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN Nom Max1 Units 0.2 x VDDQ 0.6 1.0 1.15 RZQ/6 0.5 x VDDQ 0.9 1.0 1.15 RZQ/6 0.8 x VDDQ 0.9 1.0 1.45 RZQ/6 0.2 x VDDQ 0.9 1.0 1.45 RZQ/6 0.5 x VDDQ 0.9 1.0 1.15 RZQ/6 0.8 x VDDQ 0.6 1.0 1.15 RZQ/6 VIL(AC) to VIH(AC) -10 N/A 10 % 1. A larger maximum limit will result in slightly lower minimum currents. 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 18: Single-Ended Output Driver Characteristics Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Parameter/Condition Symbol Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.09 x VDDQ and VOH(AC) = VREF + 0.09 x VDDQ SRQse Min Max Units 1.75 6 V/ns Min Max Units Table 19: Differential Output Driver Characteristics Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Parameter/Condition Symbol Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = -0.18 x VDDQ and VOH,diff(AC) = 0.18 x VDDQ SRQdiff 3.5 12 V/ns Output differential crosspoint voltage VOX(AC) VREF - 135 VREF + 135 mV Table 20: Electrical Characteristics and AC Operating Conditions Note 1 applies to base timing specifications DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units DQ Input Timing Data setup time to DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# Base (specification) tDS VREF @ 1 V/ns Base (specification) tDS tDH tDS - N/A - N/A - N/A - ps 250 - 200 - N/A - N/A - N/A - ps 140 - 90 - 45 - 25 - N/A - ps 275 - 225 - 180 - 160 - N/A - ps 160 - 110 - 75 - 55 - N/A - ps 250 - 200 - 165 - 145 - N/A - ps N/A - N/A - N/A - N/A - 70 - ps N/A - N/A - N/A - N/A - 135 - ps N/A - N/A - N/A - N/A - 75 - ps N/A - N/A - N/A - N/A - 110 - ps (AC130) VREF @ 2 V/ns Base (specification) 40 (DC90) VREF @ 1 V/ns Base (specification) - (AC135) VREF @ 1 V/ns Base (specification) 90 (AC160) tDH (DC90) VREF @ 2 V/ns Command and Address Timing CTRL, CMD, ADDR setup to CK, CK# CTRL, CMD, ADDR setup to CK, CK# Base (specification) tIS VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 215 - 140 - 80 - 60 - N/A - ps 375 - 300 - 240 - 220 - N/A - ps 365 - 290 - 205 - 185 - 65 - ps 500 - 425 - 340 - 320 - 200 - ps (AC160) tIS (AC135) 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 20: Electrical Characteristics and AC Operating Conditions (Continued) Note 1 applies to base timing specifications DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Parameter Symbol Min Max Min Max Min Max Min Max Min CTRL, CMD, ADDR setup to CK, CK# tIS N/A - N/A - N/A - N/A - 150 - ps N/A - N/A - N/A - N/A - 275 - ps 285 - 210 - 150 - 130 - 110 - ps 375 - 300 - 240 - 220 - 200 - ps Base (specification) (AC125) VREF @ 1 V/ns tIH CTRL, CMD, Base ADDR hold (specification) from CK, CK# V REF @ 1 V/ns Notes: Max Units (DC90) 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min with tDS(AC160) of 90ps or VIH(AC135),min with tDS(AC135) of 140ps. 2. When DQ single-ended slew rate is 1V/ns, the DQS differential slew rate is 2V/ns; when DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns; Table 21: Derating Values for tIS/tIH - AC160/DC90-Based tIS, tIH Derating (ps) - AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns tIS tIH CK, CK# Differential Slew Rate 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -1 -3 -1 -3 -1 -3 7 5 15 13 23 21 31 31 39 47 0.8 -3 -8 -3 -8 -3 -8 5 1 13 9 21 17 29 27 37 43 0.7 -5 -13 -5 -13 -5 -13 3 -5 11 3 19 11 27 21 35 37 0.6 -8 -20 -8 -20 -8 -20 0 -12 8 -4 16 4 24 14 32 30 0.5 -20 -30 -20 -30 -20 -30 -12 -22 -4 -14 4 -6 12 4 20 20 0.4 -40 -45 -40 -45 -40 -45 -32 -37 -24 -29 -16 -21 -8 -11 0 5 PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 22: Derating Values for tIS/tIH - AC135/DC90-Based tIS, tIH Derating (ps) - AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns tIS tIH CK, CK# Differential Slew Rate 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 -3 2 -3 2 -3 10 5 18 13 26 21 34 31 42 47 0.8 3 -8 3 -8 3 -8 11 1 19 9 27 17 35 27 43 43 0.7 6 -13 6 -13 6 -13 14 -5 22 3 30 11 38 21 46 37 0.6 9 -20 9 -20 9 -20 17 -12 25 -4 33 4 41 14 49 30 0.5 5 -30 5 -30 5 -30 13 -22 21 -14 29 -6 37 4 45 20 0.4 -3 -45 -3 -45 -3 -45 6 -37 14 -29 22 -21 30 -11 38 5 Table 23: Derating Values for tIS/tIH - AC125/DC90-Based tIS, tIH Derating (ps) - AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns tIS tIH CK, CK# Differential Slew Rate 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95 1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 3 -3 3 -3 3 -3 11 5 19 13 27 21 35 31 43 47 0.8 6 -8 6 -8 6 -8 14 1 22 9 30 17 38 27 46 43 0.7 10 -13 10 -13 10 -13 18 -5 26 3 34 11 42 21 50 37 0.6 16 -20 16 -20 16 -20 24 -12 32 -4 40 4 48 14 56 30 0.5 15 -30 15 -30 15 -30 23 -22 31 -14 39 -6 47 4 55 20 0.4 13 -45 13 -45 13 -45 21 -37 29 -29 37 -21 45 -11 53 5 PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 24: Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition DDR3L-800/1066/1333/1600 tVAC Slew Rate (V/ns) at 160mV (ps) tVAC DDR3L-1866 at 135mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps) >2.0 70 209 200 205 2.0 53 198 200 205 1.5 47 194 178 184 1.0 35 186 133 143 0.9 31 184 118 129 0.8 26 181 99 111 0.7 20 177 75 89 0.6 12 171 43 59 0.5 Note 1 164 Note 1 18 <0.5 Note 1 164 Note 1 18 Note: 1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than VIL(AC) level. Table 25: Derating Values for tDS/tDH - AC160/DC90-Based tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 80 45 80 45 80 45 1.5 53 30 53 30 53 30 61 38 1.0 0 0 0 0 0 0 8 8 16 16 -1 -3 -1 -3 7 5 15 13 23 21 -3 -8 5 1 13 9 21 17 29 27 -3 -5 11 3 19 11 27 21 35 37 8 -4 16 4 24 14 32 30 4 6 12 4 20 20 -8 -11 0 5 0.9 0.8 0.7 0.6 0.5 0.4 PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications Table 26: Derating Values for tDS/tDH - AC135/DC90-Based tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 68 45 68 45 68 45 1.5 45 30 45 30 45 30 53 38 1.0 0 0 0 0 0 0 8 8 16 16 2 -3 2 -3 10 5 18 13 26 21 3 -8 11 1 19 9 27 17 35 27 14 -5 22 3 30 11 38 21 46 37 25 -4 33 4 41 14 49 30 39 -6 37 4 45 20 30 -11 38 5 0.9 0.8 0.7 0.6 0.5 0.4 PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQ Slew Rate V/ns PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN Table 27: Derating Values for tDS/tDH - AC130/DC100-Based at 2V/ns DQS, DQS# Differential Slew Rate 8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 4.0 33 23 33 23 33 23 3.5 28 19 28 19 28 19 28 19 3.0 22 15 22 15 22 15 22 15 22 15 13 9 13 9 13 9 13 9 13 9 0 0 0 0 0 0 0 0 0 0 -22 -15 -22 -15 -22 -15 -22 -15 -14 -7 -65 -45 -65 -45 -65 -45 -57 -37 -49 -29 -62 -48 -62 -48 -54 -40 -46 -32 -38 -24 -61 -53 -53 -45 -45 -37 -37 -29 -29 -19 -49 -50 -41 -42 -33 -34 -25 -24 -17 -8 -37 -49 -29 -41 -21 -31 -13 -15 -31 -51 -23 -41 -15 -25 -28 -56 -20 -40 2.5 2.0 1.5 1.0 27 0.9 0.8 0.7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 0.6 0.5 0.4 4Gb: x4, x8, x16 DDR3L-RS SDRAM Electrical Specifications tDS 4Gb: x4, x8, x16 DDR3L-RS SDRAM Initialization Table 28: Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps) tVAC at 130mV (ps) >2.0 165 113 95 2.0 165 113 95 1.5 138 90 73 1.0 85 45 30 0.9 67 30 16 0.8 45 11 Note1 0.7 16 Note1 - 0.6 Note1 Note1 - 0.5 Note1 Note1 - <0.5 Note1 Note1 - Note: 1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than VIL(AC) level. Initialization If the SDRAM is powered up and initialized for the 1.35V operating voltage range, voltage can be increased to the 1.5V operating range provided that: * Just prior to increasing the 1.35V operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. * The 1.5V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. * The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to any READ command. * The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating voltages are stable and prior to any READ command. If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage can be reduced to the 1.35V operation range provided that: * Just prior to reducing the 1.5V operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. * The 1.35V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. * The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to any READ command. * The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating voltages are stable and prior to any READ command. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8, x16 DDR3L-RS SDRAM Initialization VDD Voltage Switching After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 9 is maintained. Figure 9: VDD Voltage Switching Tb Ta CK, CK# Tc Te Td (( )) (( )) (( )) (( )) (( )) (( )) Tf Ti Th Tg Tj Tk (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) Valid tXPR tMRD tMRD (( )) (( )) Valid (( )) (( )) (( )) (( )) Valid (( )) (( )) (( )) (( )) (( )) (( )) tCKSRX VDD, VDDQ (DDR3) TMIN = 10ns (( )) (( )) (( )) (( )) VDD, VDDQ (DDR3L) TMIN = 10ns TMIN = 200s T = 500s RESET# CKE (( )) (( )) tIS (( )) (( )) TMIN = 10ns (( )) tDLLK tIS (( )) (( )) MRS (( )) (( )) MRS (( )) (( )) (( )) (( )) MR2 (( )) (( )) MR3 (( )) (( )) Command (( )) (( )) (( )) (( )) BA (( )) (( )) (( )) (( )) ODT (( )) (( )) (( )) (( )) (( )) (( )) RTT (( )) (( )) (( )) Note 1 tMRD MRS MR1 tMOD (( )) (( )) MRS (( )) (( )) (( )) (( )) MR0 (( )) (( )) tZQinit ZQCL (( )) (( )) Note 1 tIS tIS (( (( (( (( )) )) )) )) Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW (( (( (( (( )) )) )) )) (( )) (( )) (( )) (( )) (( )) Time break (( )) Note: Valid Don't Care 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8488935b 4Gb_1_35V_DDR3L-RS.pdf - Rev. H 10/12 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2011 Micron Technology, Inc. All rights reserved.