Rev. 1.0 9/14 Copyright © 2014 by Silico n Laboratories Si5322
Si5322
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Features
Applications
Description
The Si5322 is a low jitter, precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and
Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44
to 707 MHz and generates two equal frequency-multiplied clock outputs
ranging from 19.44 to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET,
Ethernet, and Fibre Channel rates. The Si5322 is based on Silicon
Laboratories' 3rd-generation DSPLL® technology, which provides any-
frequency synthesis in a highl y-integ rated PLL solution tha t eliminates the
need for external VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5322 is ideal for providing clock multiplication in high
performance timing applications.
Not recommended for new
designs. For alternatives , see the
Si533x family of products.
Selectable output frequencies
ranging from 19.44 to 1050 MHz
Low jitter clock outputs with jitter
generation as low as 0.6 psRMS
(50kHz–80MHz)
Integrated loop filter with
selectable loop bandwidth
(150 kHz to 1.3 MHz)
Dual clock inputs with manual o r
automatically controlled
switching
Dual clock outputs with
selectable signal format:
LVPECL, LVDS, CML, CMOS
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOS alarm output
Pin-programmable settings
On-chip voltage regulator for
1.8 V ±5%, 2.5 or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead
QFN
Pb-free, RoHS compliant
SONET/SDH OC-48/STM-16
and OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line
cards
ITU G.709 line cards
Optical modules
Test and measurement
Ordering Information:
See page 18.
Pin Assignments
1
2
3
2930313233343536
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
AUTOSEL
RST
C2B
C1B
GND
VDD
GND
VDD
VDD
CKIN2+
CKIN2–
DBL2_BY
VDD
CKIN1+
CKIN1–
CS_CA
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CKOUT1–
SFOUT1
GND
VDD
SFOUT0
CKOUT2–
CKOUT2+
NC
GND
Pad
FRQSEL0
GND
918 19
28
NC
NC
GND
CKOUT1+
Si5322
2 Rev. 1.0
Functional Block Diagram
DSPLL®
Loss of Signa l
Clock Select
Bandwidth Selec t
Frequency Select
Disable/BYPASS
Signal Format
CKOUT2
CKIN1 CKOUT1
CKIN2
Control
Manual/Auto Switch
Signal Detect VDD (1.8, 2.5, or 3.3 V)
GND
Si5322
Rev. 1.0 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3. Pin Descriptions: Si5322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Land Pattern: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.1. Si5322 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Si5322
4 Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Temperature Range TA–40 25 85 ºC
Supply Voltage VDD 3.3 V no m i na l 2.97 3.3 3.63 V
2.5 V no m ina l 2.25 2.5 2.75 V
1.8 V no m ina l 1.71 1.8 1.89 V
Note: All minimum and maximu m spec ifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current
(Supply current is indepen-
dent of VDD)
IDD LVPECL Format
622.08 MHz Out
All CKOUTs Enabled1
— 251 279 mA
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled1
— 217 243 mA
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
— 204 234 mA
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled
— 194 220 mA
CKIN Input Pins
Input Common Mode
Voltage
(Input Threshold Voltage)
VICM 1.8 V ±5% 0.9 — 1.4 V
2.5 V ±10% 1.0 — 1.7 V
3.3 V ±10% 1.1 — 1.95 V
Input Resistance CKNRIN Single-ended 20 40 60 k
Input Voltage Level Limits CKNVIN See Note 20—V
DD V
Single-Ended Input Voltage
Swing VISE fCKIN <212.5 MHz
See Figure 2. 0.2 — — VPP
fCKIN > 212.5 MHz
See Figure 2. 0.25 — — VPP
Notes:
1. LVPECL outputs require nominal VDD >2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
Si5322
Rev. 1.0 5
Differential Input
Voltage Swing VID fCKIN <212.5 MHz
See Figure 2. 0.2 — — VPP
fCKIN > 212.5 MHz
See Figure 2. 0.25 — — VPP
Output Clocks (CKOUTn)1
Common Mode CKOVCM LVPECL 100 load
line-to-line VDD –
1.42 —V
DD –
1.25 V
Differential Output Swing CKOVD LVPECL 100 load
line-to-line 1.1 — 1.9 VPP
Single-ended Output Swing CKOVSE LVPECL 100 load
line-to-line 0.5 — 0.93 VPP
Differential Output Voltage CKOVD CML 100 load
line-to-line 350 425 500 mVPP
Common Mode
Output Voltage CKOVCM CML 100 load
line-to-line —V
DD –
0.36 —V
Differential
Output Voltage CKOVD LVDS 100 load
line-to-line 500 700 900 mVPP
Low swing LVDS 100 load
line-to-line 350 425 500 mVPP
Common Mode
Output Voltage CKOVCM LVDS 100 load
line-to-line 1.125 1.2 1.275 V
Differential Output
Resistance CKORD CML, LVDS, LVPECL — 200 —
Output Voltage Low CKOVOLLH CMOS — — 0.4 V
Output Voltage High CKOVOHLH VDD =1.71V
CMOS 0.8 x VDD —— V
Output Drive Current CKOIO CMOS
Driving into CKOVOL for out-
put low or CKOVOH for output
high. CKOUT+ and CKOUT–
shorted externally.
—
—7.5
32 —
—mA
mA
VDD =1.8V
VDD =3.3V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. LVPECL outputs require nominal VDD >2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
Si5322
6 Rev. 1.0
2-Level LVCMOS Input Pins
Input Voltage Low VIL VDD =1.71V — — 0.5 V
VDD =2.25V — — 0.7 V
VDD =2.97V — — 0.8 V
Input Voltage High VIH VDD =1.89V 1.4 — — V
VDD =2.25V 1.8 — — V
VDD =3.63V 2.5 — — V
Input Low Current IIL ——50 µA
Input High Current IIH ——50 µA
Weak Internal Input Pull-up
Resistor RPUP —75— k
Weak Internal Input
Pull-down Resistor RPDN —75— k
3-Level Input Pins
Input Voltage Low VILL ——
0.15 x VDD V
Input Voltage Mid VIMM 0.45 x VDD —0.55 x VDD V
Input Voltage High VIHH 0.85 x VDD —— V
Input Low Current IILL3–20 — — µA
Input Mid Current IIMM3–2 — 2 µA
Input High Current IIHH3——20 µA
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. LVPECL outputs require nominal VDD >2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
Si5322
Rev. 1.0 7
Figure 1. Voltage Characteristics
Figure 2. Rise/Fall Time Characteristics
LVCMOS Output Pins
Output Voltage Low VOL IO=2mA
VDD =1.71V ——0.4 V
IO=2mA
VDD =2.97V ——0.4 V
Output Voltage High VOH IO=–2mA
VDD =1.71V VDD –0.4 — — V
IO=–2mA
VDD =2.97V VDD –0.4 — — V
Disabled Leakage Current IOZ RST = 0 –100 — 100 µA
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. LVPECL outputs require nominal VDD >2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
VISE, VOSE
VID,VOD
D iffe r e n tia l I/ Os
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL – VID = (S IG NAL +) – (S IGNA L – )
V
ICM , VOCM
tFtR
80%
20%
C KIN , CKOU T
Si5322
8 Rev. 1.0
Table 3. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Conditio n Min Typ Max Units
CKIN Input Pins
Input Frequency CKNF19.44 — 707.35 MHz
Input Duty Cycle
(Minimum Puls e Width) CKNDC
Whichever is smaller
(i.e., the 40%/60% limit ation
applies only to high clock
frequencies)
40 — 60 %
2——ns
Input Capacitance CKNCIN —— 3pF
Input Rise/Fall Time CKNTRF 20–80%
See Figure 2 ——11ns
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable) CKOF 19.44 — 1050 MHz
Maximum Output Frequency in
CMOS Format CKOFMC — — 212.5 MHz
Single-ended Output Rise/Fall
(20–80%) CKOTRF
CMOS Output
VDD =1.71
Cload = 5 pF
—— 8ns
CMOS Output
VDD =2.97
Cload = 5 pF
—— 2ns
Differential Output Rise/Fall Time CKOTRF 20 to 80 %, fOUT = 622.08 — 230 350 ps
Output Duty Cycle Differential
Uncertainty CKODC 100 Load
Line to Line
Measured at 50% Point
(not for CMOS)
——±40ps
LVCMOS Input Pins
Minimum Reset Pulse Width tRSTMIN 1——µs
Input Capacitance CIN —— 3pF
LVCMOS Output Pins
Rise/Fall Times tRF CLOAD =20pf
See Figure 2 —25—ns
LOSn Trigger Window LOSTRIG From last CKIN to LOS—750µs
PLL Performance
Output Clock Phase Change tP_STEP After clock switch
f3 128 kHz —200— ps
Closed Loop Jitter Peaking JPK — 0.05 0.1 dB
Jitter Tolerance JTOL BW determined by
BWSEL[1:0] 5000/
BW — — ns pk-
pk
Spurious Noise SPSPUR Max spur @ n x f3
(n > 1, n x f3 < 100 MHz) — –93 –70 dBc
Phase Change due to Temperature
Variation tTEMP Max phase changes fro m –
40 to +85 ºC — 300 500 ps
Si5322
Rev. 1.0 9
1.1. Three-Level (3L) Input Pins (No External Resistors)
Figure 3. Three-Level Input Pins
1.2. Three-Level Input Pins (Example with External Resistors)
Figure 4. Three-Level Input Pins
Table 4. Three-Level Input Pins1,2,3,4
Parameter Min Max
Input Low Current –30 µA —
Input Mid Current –11 µA –11 µA
Input High Current — –30 µA
Notes:
1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver using the
external resistor values indicate d in this example. In most designs, an external resistor voltage divider is
recommended.
2. Resistor packs are only needed if the leakage current o f the external driver exce eds the current specified in
Table 2, Iimm. Any resistor pack may be used (e.g., Panasonic EXB-D10C183J). PCB layout is not critical.
3. If a pin is tied to ground or VDD, no resistors are needed.
4. If a pin is left open (no connect), no resistors are needed.
External Driver
Si5322
Iimm 75 k
VDD
75 k
External Driver
Si5322
3L input current
18 k
VDD
18 k
75 k
VDD
75 k
One of eight resistors from a Panasonic EXB-D 10C183J
(or similar) resistor pack
Si5322
10 Rev. 1.0
Table 5. Performance Specifications1, 2, 3, 4
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Generation
fIN =f
OUT =622.08MHz,
LVPECL Output Format
BW = 877 Hz
JGEN 50 kHz–80 MHz — .47 — ps rms
12 kHz–20 MHz — .48 — ps rms
4MHz–80MHz — .23 — ps rms
Phase Noise
fIN =f
OUT = 622.08 MHz
LVPECL Output Format
CKOPN 1 kHz offset — –90 — dBc/Hz
10 kHz offset — –113 — dBc/Hz
100 kHz offset — –118 — dBc/Hz
1 MHz offset — –132 — dBc/Hz
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in by DSPLLsim.
2. VDD =3.3V
3. TA=85°C
4. Test condition: fIN =622.08MHz, f
OUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20-80%), LVPECL clock output.
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance
Junction to Ambient JA Still Air — 32 — ºC/W
Thermal Resistance
Junction to Case JC Still Air — 14 — ºC/W
Table 7. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage VDD –0.5 to 3.8 V
LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V
CKINn Voltage Level Limits CKNVIN 0 to VDD V
Operating Junction Temperature TJCT –55 to 150 C
Storage Temperature Range TSTG –55 to 150 C
ESD HBM Tolerance (100 pF, 1.5 k); All pins except
CKIN+/CKIN– 2kV
ESD MM Tolerance; All pins except CKIN+/CKIN– 150 V
ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN– 750 V
ESD MM Tolerance; CKIN+/CKIN– 100 V
Latch-Up Tolerance JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Si5322
Rev. 1.0 11
Figure 5. Typical Phase Noise Plot
Table 8. Typical Jitter Data
Jitter Bandwidth RMS Jitter (fs)
OC-48, 12 kHz to 20 MHz 374
OC-192, 20 k H z to 80 MHz 388
OC-192, 4 MHz to 80 MHz 181
OC-192, 50 k H z to 80 MHz 377
Broadband, 800 Hz to 80 MHz 420
622 M Hz I n, 622 M Hz O ut BW= 877 kHz
-170
-150
-130
-110
-90
-70
-50
1000 10000 100000 1000000 10000000 100000000
Offset Frequency (Hz)
P h ase Noise (d Bc/ Hz )
Si5322
12 Rev. 1.0
Figure 6. Si5322 Typical Application Circuit
Si5322
CS_CA3
C1B
C2B
FRQSEL[3:0]2
BWSEL[1:0]2
SFOUT[1:0]2
DBL2_BY2
RST
CKOUT1+
CKOUT1–
VDD
GND
Input Clock Select/
Active Clock Indicator
Frequency Select
Bandwidth Select
Signal Format Select
Clock Output 2 Disable/
Bypass Mode C ontrol
Reset
CKIN_1 Loss of Signal
CKIN_2 Loss of Signal
Clock
Outputs
FRQTBL2
Frequency Table Select
CKOUT2+
CKOUT2–
AUTOSEL2
Manual/Automatic Clock
Selection (L)
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
CKIN1+
CKIN1–
Input
Clock
Sources1
CKIN2+
CKIN2–
Notes:
3. Assumes m anual input clock selection.
1. Assumes differential LVEPEC L termination (3.3 V) on clock inputs.
Ferrite
Bead
System
Power
Supply
C3
C2
C1
C4
0.1 µF
0.1 µF
0.1 µF
1 µF
0.1 µF
100
0.1 µF +
–
0.1 µF
100
0.1 µF +
–
130 130
82 82
VDD = 3.3 V
130 130
82 82
VDD = 3.3 V
VDD
15 k
15 k
VDD
15 k
15 kVDD
15 k
15 k
VDD
15 k
15 kVDD
15 k
15 k
Si5322
Rev. 1.0 13
2. Functional Description
The Si5322 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, SDH STM-16/64 Ethernet, and Fibre
Channel. The Si5322 accepts dual clock inputs ranging
from 19.44 to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 19.44 to 1050
MHz. The two input clocks are at the same frequency
and the two output clocks are at the same frequency.
The input clock frequency and clock multiplication ratio
are selectable fr om a table of popular SONET, Ethernet,
and Fibre Channel rates. In addition to providing clock
multiplication in SONET and datacom applications, the
Si5322 supports SONET-to-datacom frequency
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5322 frequency translations. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
The Si5322 is recommended for applications in which
the input clock is relatively low jitter and only clock
multiplication is required. The Si5322 is based on
Silicon Laboratories' 3rd-generation DSPLL®
technology, which provides any-frequency synthesis in
a highly integrated PLL so lution that eliminates the nee d
for external VCXO and loop filter components. The
Si5322 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 150 kHz to
1.5 MHz. Th e DSPLLsim software utility can be used to
calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio. The Si5322
monitors all input clocks for loss of signal and provides
a LOS alarm when it detects a missing clock.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to th e last valid operating state.
The Si5322 has two differential clock outputs. The
electrical format of the clo ck output s is pr ogra mmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, the second clock output can be powered down
to minimize power consumption. For system-level
debugging, a bypass mode is available wh ich drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
2.1. Further Documentation
Consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed info rma tion a bou t the Si53 22. Add itio nal design
support is available from Silicon Laboratories through
your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
Si5322
14 Rev. 1.0
3. Pin Descriptions: Si5322
Table 9. Si5322 Pin Descriptions
Pin # Pin Name I/O Signal Level Description
1RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5322 will perform an internal self-calibration.
This pin has a weak pu ll-u p.
2 FRQTBL I 3-Level
Frequency Table Select.
Selects SONET/SDH, dat acom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH.
M=Datacom.
H = SONET/SDH to Datacom.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
3C1BOLVCMOS
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present.
1 = LOS on CKIN1.
4C2BOLVCMOS
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present.
1 = LOS on CKIN2.
Si5322
Rev. 1.0 15
5, 10, 11,
15, 32 VDD VDD Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply . Byp ass
capacitors should be associated with the following VDD pins:
5 0.1 µF
10 0.1 µF
32 0.1 µF
A 1.0 µF should be placed as close to device as is practical.
6, 8,19,
20, 31 GND GND Supply Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
9 AUTOSEL I 3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
selection to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
12
13 CKIN2+
CKIN2– IMulti
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency se lected from a table
of values. The same frequency must be ap plied to CKIN1
and CKIN2.
14 DBL2_BY I 3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled.
M = CKOUT2 disabled.
H = Bypass mode with CKOUT2 enabled.
CMOS outputs do not support Bypass Mode.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17 CKIN1+
CKIN1– IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency se lected from a table
of values. The same frequency must be ap plied to CKIN1
and CKIN2.
Table 9. Si5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
Si5322
16 Rev. 1.0
21 CS_CA I/O LVCMOS
Input Clock Select/Active Clock Indicator.
Input: If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS inpu t state.
0 = Select CKIN1.
1 = Select CKIN2.
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of
the two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the digital hold state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
23
22 BWSEL1
BWSEL0 I 3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. Detailed operations and timing characteristics for
these pins may be found in the Any-F requency Precision
Clock Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
I 3-Level
Multiplier Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting. Consult
the Any-Frequency Precision Clock Family Reference Man-
ual or DSPLLsim configuration software for settings, both
available for download at www.silabs.com/timing (click on
Documentation).
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Table 9. Si5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
Si5322
Rev. 1.0 17
33
30 SFOUT0
SFOUT1 I 3-Level
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2. Valid settings include LVPECL, LVDS, and
CML. Also includes selections for CMOS mode, tristate
mode, and tristate/sleep mode.
CMOS outputs do not support Bypass Mode.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
34
35 CKOUT2–
CKOUT2+ OMulti
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS fo rmat, both output pins drive
identical single-e nd e d cloc k ou tputs.
29
28 CKOUT1–
CKOUT1+ OMulti
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS fo rmat, both output pins drive
identical single-e nd e d cloc k ou tputs.
7, 18, 36 NC — — No Connect.
These pins must be left unconnected for normal operation.
GND PAD GND GND Supply Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a groun d plane.
Table 9. Si5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
SFOUT[1:0] Signal Format
HH Reserved
HM LVDS
HL CML
MH LVPECL
MM Reserved
ML LVDS—Low Swing
LH CMOS
LM Disabled
LL Reserved
Si5322
18 Rev. 1.0
4. Ordering Guide
Ordering Part Number Package ROHS6, Pb-Free Temperature Range
Si5322-C-GM* 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C
*Note: Not recommended for new designs. For alternatives, see the Si533x family.
Si5322
Rev. 1.0 19
5. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5322. Table 10 lists the values for the dimensions shown in the
illustration.
Figure 7. 36-Pin Quad Flat No-lead (QFN)
Table 10. Package Dimensions
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 L 0.50 0.60 0.70
A1 0.00 0.02 0.05 ——12º
b 0.18 0.25 0.30 aaa — — 0.10
D 6.00 BSC bbb — — 0.10
D2 3.95 4.10 4.25 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 6.00 BSC eee — — 0.05
E2 3.95 4.10 4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Si5322
20 Rev. 1.0
6. Land Pattern: 36-Pin QFN
Figure 8. 36-Pin QFN Land Pattern
Si5322
Rev. 1.0 21
Table 11. PCB Land Pattern Dimensions
Dimension MIN MAX
e 0.50 BSC.
E 5.42 REF.
D 5.42 REF.
E2 4.00 4.20
D2 4.00 4.20
GE 4.53 —
GD 4.53 —
X — 0.28
Y 0.89 REF.
ZE — 6.31
ZD — 6.31
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.0 5 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stenc i l th ickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Si5322
22 Rev. 1.0
7. Top Marking
7.1. Si5322 Top Marking (QFN)
7.2. Top Marking Explanation
Mark Method: Laser
Font Size: 0.80 mm
Right-Justified
Line 1 Marking: Si5322 Customer Part Number
See Ordering Guide for options
Line 2 Marking: C-GM C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
Line 3 Marking: YYWWRF YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking: Pin 1 Identifier Circle = 0.75 m m Diam et er
Lower-Left Justified
XXXX Internal Code
Si5322
Rev. 1.0 23
DOCUMENT CHANGE LIST
Revision 0.44 to Revision 0.45
Condensed format.
Revision 0.45 to Revision 0.46
Removed references to latency control, INC, and
DEC in figures and text.
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 5.
Added Figure 1, “T ypical Phase Noise Plot,” on page
4.
Updated “3. P in Descriptions: Si5322” .
Added “6. Land Pattern: 36-Pin QFN”.
Revision 0.46 to Revision 0.47
Removed Figure 1. “Typical Phase Noise Plot.”
Changed pins 11 and 15 from NC to VDD in “3. Pin
Descriptions: Si5322”.
Revision 0.47 to Revision 0.5
Changed 1.8 V operating range to ±5%.
Updated Ta ble 1 on page 4.
Updated Ta ble 2 on page 5.
Updated Figure 6 on page 12 to add pull-up/pull-
down resistors for 3-level inputs.
Added figure and table on page 11.
Updated "2. Functional Description" on page 13.
Clarified "3. Pin Descriptions: Si5322" on page 14.
Updated SFOU T value s.
Revision 0.5 to Revision 0.51
Changed “any-rate” to “any-frequency” throughout.
Expanded spec tables 1 through 7.
Updated Ta ble 5 on page 10.
Added "7. Top Marking" on page 22.
Added clarification that CMOS output format is not
available in PLL bypass mode.
Updated "4. Ordering Guide" on page 18.
Removed note from "3. Pin Descriptions: Si53 22" on
page 14.
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