83026BMI-01LF - IDT, Integrated Device Technology Inc

Low Skew, 1-to-2

Differential-to-LVCMOS/LVTTL Fanout Buffer 83026I-01

Data Sheet

GENERAL DESCRIPTION

The 83026I-01 is a low skew, 1-to-2 Differential-to-LVC-

MOS/LVTTL Fanout Buffer. The differential input can

accept most differential signal types (LVPECL, LVDS,

LVHSTL, HCSL and SSTL) and translate to two sin-

gle-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC

footprint makes this device ideal for use in applications with

limited board space.

FEATURES

• Two LVCMOS / LVTTL outputs

• Differential CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 350MHz

• Output skew: 15ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Additive phase jitter, RMS: 0.03ps (typical)

• Small 8 lead SOIC package saves board space

• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free RoHS (6) package

BLOCK DIAGRAM PIN ASSIGNMENT

83026I-01

8-Lead SOIC

3.8mm x 4.8mm, x 1.47mm package body

M Package

Top View

VDD

CLK

nCLK

CLK

nCLK

VDDO

GND

83026I-01

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VDD

CLK

nCLK

VDDO

GND

83026I-01 Data Sheet

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

Number Name Type Description

1VDD Power Positive supply pin.

2CLK Input Pulldown Non-inverting differential clock input.

3nCLK Input Pullup/

Pulldown Inverting differential clock input. VDD/2 default when left ﬂ oating.

4OE Input Pullup Output enable. When HIGH, outputs are enabled. When LOW, outputs are in

High Impedance State. LVCMOS / LVTTL interface levels.

5GND Power Power supply ground.

6Q1 Output Clock output. LVCMOS / LVTTL interface levels.

7Q0 Output Clock output. LVCMOS / LVTTL interface levels.

8VDDO Power Output supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Input Outputs

OE Q0, Q1

0 HiZ

1 Active

TABLE 3. CONTROL FUNCTION TABLE

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

CPD

Power Dissipation Capacitance

(per output)

VDD, VDDO = 3.465V 17 pF

VDD = 3.465V, VDDO = 2.625V 16 pF

VDD = 3.465V, VDDO = 1.95V 15 pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ROUT Output Impedance

VDD, VDDO = 3.3V 7 Ω

VDD = 3.3V, VDDO = 2.5V 8 Ω

VDD = 3.3V, VDDO = 1.8V 10 Ω

83026I-01 Data Sheet

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage

3.135 3.3 3.465 V

2.375 2.5 2.625 V

1.71 1.8 1.89 V

IDD Power Supply Current 10 mA

IDDO Output Supply Current 3mA

TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.375V TO 3.465V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage OE 2 VDD + 0.3 V

VIL Input Low Voltage OE -0.3 0.8 V

IIH Input High Current OE VDD = VIN = 3.465V 5 µA

IIL Input Low Current OE VDD = 3.465V, VIN = 0V -150 µA

VOH Output High Voltage; NOTE 1 VDDO = 3.135V 2.6 V

VDDO = 2.375V 1.8 V

VOL Output Low Voltage; NOTE 1 0.5 V

NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section,

“Output Load Test Circuit” diagrams.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI -0.5V to VDD + 0.5 V

Outputs, VO -0.5V to VDDO + 0.5V

Package Thermal Impedance, θ

8 Lead SOIC 112.7°C/W (0 lfpm)

8 Lead TSSOP 101.7°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁ cations only. Functional

operation of product at these conditions or any conditions

beyond those listed in the DC Characteristics or AC Charac-

teristics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage OE 2 VDD + 0.3 V

VIL Input Low Voltage OE -0.3 0.8 V

IIH Input High Current OE VDD = VIN = 3.465V 5 µA

IIL Input Low Current OE VDD = 3.465V, VIN = 0V -150 µA

VOH Output High Voltage IOH = -100µA VDDO - 0.2 V

IOH = -2mA VDDO - 0.45 V

VOL Output Low Voltage IOL = 100µA 0.2 V

IOL = 2mA 0.45 V

83026I-01 Data Sheet

TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 350 MHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 350MHz 1.3 1.9 2.5 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps

tjit Buffer Additive Phase Jitter, RMS, refer to

Additive Phase Jitter Section 0.03 ps

tR / tFOutput Rise/Fall Time 20% to 80% 150 800 ps

odc Output Duty Cycle

ƒ ≤ 66MHz 48 52 %

67MHz ≤ ƒ ≤ 166MHz 45 55 %

167MHz ≤ ƒ ≤ 350MHz 40 60 %

NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 6.

TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current nCLK VIN = VDD = 3.465V 150 µA

CLK VIN = VDD = 3.465V 150 µA

IIL Input Low Current nCLK VIN = 0V, VDD = 3.465V -150 µA

CLK VIN = 0V, VDD = 3.465V -5 µA

VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V

VCMR Common Mode Input Voltage; NOTE 2, 3 GND + 0.5 VDD - 0.85 V

NOTE 1: VPP can exceed 1.3V provided that there is sufﬁ cient offset level to keep VIL > 0V.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.

NOTE 3: Common mode voltage is deﬁ ned as VIH.

83026I-01 Data Sheet

TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 350 MHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 350MHz 1.5 2.0 2.6 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 750 ps

tjit

Buffer Additive Phase Jitter,

RMS, refer to Additive Phase

Jitter Section

0.03 ps

tR / tFOutput Rise/Fall Time 20% to 80% 150 800 ps

odc Output Duty Cycle

ƒ ≤ 66MHz 48 52 %

67MHz ≤ ƒ ≤ 166MHz 46 54 %

167MHz ≤ ƒ ≤ 350MHz 40 60 %

NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 350 MHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 350MHz 1.9 2.5 3.1 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 600 ps

tjit

Buffer Additive Phase Jitter,

RMS, refer to Additive Phase

Jitter Section

0.03 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 900 ps

odc Output Duty Cycle

ƒ ≤ 66MHz 48 52 %

67MHz ≤ ƒ ≤ 166MHz 43 57 %

167MHz ≤ ƒ ≤ 350MHz 40 60 %

NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

83026I-01 Data Sheet

ADDITIVE PHASE JITTER

Input/Output Additive

Phase Jitter at 155.52MHz

= 0.03ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k 10k 100k 1M 10M 100M

The spectral purity in a band at a speciﬁ c offset from the fun-

damental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using

a Phase noise plot and is most often the speciﬁ ed plot in many

applications. Phase noise is deﬁ ned as the ratio of the noise

power present in a 1Hz band at a speciﬁ ed offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in the

As with most timing speciﬁ cations, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise ﬂ oor of the equipment is higher

than the noise ﬂ oor of the device. This is illustrated above. The

1Hz band to the power in the fundamental. When the required

offset is speciﬁ ed, the phase noise is called a dBc value, which

simply means dBm at a speciﬁ ed offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

device meets the noise ﬂ oor of what is shown, but can actually

be lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

83026I-01 Data Sheet

PARAMETER MEASUREMENT INFORMATION

3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

OUTPUT SKEW PART-TO-PART SKEW

83026I-01 Data Sheet

PROPAGATION DELAY OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

83026I-01 Data Sheet

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF

in the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

OUTPUTS:

LVCMOS OUTPUTS

All unused LVCMOS output can be left ﬂ oating. We recommend

that there is no trace attached.

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

83026I-01 Data Sheet

FIGURE 2C. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2B. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2D. CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet

the VPP and VCMR input requirements. Figures 2A to 2E show

interface examples for the CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

FIGURE 2A. CLK/nCLK INPUT DRIVEN BY

LVHSTL DRIVER

examples only. Please consult with the vendor of the driver

component to conﬁ rm the driver termination requirements.

For example in Figure 2A, the input termination applies for

LVHSTL drivers. If you are using an LVHSTL driver from another

vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 2E. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL C1

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

83026I-01 Data Sheet

SCHEMATIC EXAMPLE

Figure 3 shows an application schematic example of 83026I-01.

The 83026I-01 CLK/nCLK input can directly accepts various

types of differential signal. In this example, the input is driven by

an LVDS driver. The 83026I-01 outputs are LVCMOS drivers. In

VDDO R1 43

LVDS

VDD

100

VDD=3.3V

LVCMOS

Zo = 50 Ohm

0.1u

3.3V

Zo = 50 Ohm

VDDO= 3.3V, 2.5V or 1.8V

Zo = 50 Ohm

U1 ICS83026I-01

VDD

CLK

nCLK

VDDO

GND

LVCMOS

R2 43

0.1u

VDD

Zo = 50 Ohm

FIGURE 3. 83026I-01 SCHEMATIC EXAMPLE

this example, series termination approach is shown. Additional

termination approaches are shown in the LVCMOS Termination

Application Note.

TRANSISTOR COUNT

The transistor count for ICS83026I-0I is: 260

TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

RELIABILITY INFORMATION

TABLE5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θJA by Velocity (Linear Feet per Minute)

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

83026I-01 Data Sheet

TABLE 6A. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-012

PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC

SYMBOL Millimeters

MINIMUM MAXIMUM

A 1.35 1.75

A1 0.10 0.25

B 0.33 0.51

C 0.19 0.25

D 4.80 5.00

E 3.80 4.00

e 1.27 BASIC

H 5.80 6.20

h 0.25 0.50

L 0.40 1.27

α0° 8°

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 6B. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

SYMBOL Millimeters

Minimum Maximum

A -- 1.20

A1 0.05 0.15

A2 0.80 1.05

b 0.19 0.30

c 0.09 0.20

D 2.90 3.10

E 6.40 BASIC

E1 4.30 4.50

e 0.65 BASIC

L 0.45 0.75

α0° 8°

aaa -- 0.10

83026I-01 Data Sheet

Part/Order Number Marking Package Shipping Packaging Temperature

83026BMI-01LF 026BI01L 8 lead “Lead Free” SOIC Tube -40°C to +85°C

83026BMI-01LFT 026BI01L 8 lead “Lead Free” SOIC Tape and Reel -40°C to +85°C

83026BGI-01LF BI01L 8 lead “Lead Free” TSSOP Tube -40°C to +85°C

83026BGI-01LFT BI01L 8 lead “Lead Free” TSSOP Tape and Reel -40°C to +85°C

TABLE 7. ORDERING INFORMATION

83026I-01 Data Sheet

REVISION HISTORY SHEET

Rev Table Page Description of Change Date

Added 8 Lead TSSOP package to Pin Assignment.

Absolute Maximum Ratings - added 8 Lead TSSOP to Package Thermal Imped-

ance.

Added 8 Lead TSSOP Reliability Information table.

Added 8 Lead TSSOP Package Outline and Package Dimensions.

Ordering Information Table - added 8 Lead TSSOP ordering information.

6/25/04

A 6 Additive Phase Jitter - corrected X axis on plot. 8/2/05

A T3C 3 LVCMOS DC Characteristics - corrected Test Conditions for IIH and IIL. 8/12/05

AT7

Features Section - added lead-free bullet

Added Recommendations for Unused Output Pins.

Ordering Information Table - added lead-free part number, marking, and note.

1/16/06

A T7 13 Ordering Information Table - added lead-free marking 10/22/07

AT7 13

Updated datasheet’s header/footer with IDT from ICS.

Removed ICS preﬁ x from Part/Order Number column.

Added Contact Page.

8/4/10

AT7

Removed the ICS preﬁ x on part numbers.

Features Section - removed reference to leaded packages.

Ordering Information - removed 2500 from Tape and Reel. Removed LF note

below the table.

Updated datasheet header and footer

12/15/15

83026I-01 Data Sheet

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operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided

without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-

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their respective third party owners.

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