2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
Rev. A
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FEATURES
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel
interface. CS selects the device and data is loaded into the
input registers on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF or
0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
1 Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
BUFFER
8-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5330
POWER-ON
RESET
RESET
10
9
7
6
13
20
8
1
312
4
11 5
0
6852-001
Figure 1. AD5330
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 17
Digital-to-Analog Section ......................................................... 17
Resistor String ............................................................................. 17
DAC Reference Input ................................................................. 17
Output Amplifier ........................................................................ 17
Parallel Interface ............................................................................. 18
Double-Buffered Interface ........................................................ 18
Clear Input (CLR) ...................................................................... 18
Chip Select Input (CS) ............................................................... 18
Write Input (WR) ....................................................................... 18
Load DAC Input (LDAC) .......................................................... 18
High-Byte Enable Input (HBEN) ............................................. 18
Power-On Reset .......................................................................... 18
Power-Down Mode ........................................................................ 19
Suggested Databus Formats .......................................................... 20
Applications Information .............................................................. 21
Typical Application Circuits ..................................................... 21
Driving VDD From the Reference Voltage ............................... 21
Bipolar Operation Using the AD5330/AD5331/
AD5340/AD5341 ......................................................................... 21
Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21
Programmable Current Source ................................................ 22
Power Supply Bypassing and Grounding ................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 4 .......................................................................... 16
Replaced Driving VDD from the Reference Voltage Section ..... 21
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
4/00—Revision 0: Initial Version
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 3 of 28
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
B Version2
Unit Conditions/Comments Min Typ Max
DC PERFORMANCE3, 4
AD5330
Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes
AD5331
Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes
AD5340/AD5341
Resolution 12 Bits
Relative Accuracy ±2 ±16 LSBs
Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes
Offset Error ±0.4 ±3 % of FSR
Gain Error ±0.15 ±1 % of FSR
Lower Deadband5 10 60 mV Lower deadband exists only if offset error is negative
Upper Deadband 10 60 mV VDD = 5 V; upper deadband exists only if VREF = VDD
Offset Error Drift6 −12 ppm of FSR/°C
Gain Error Drift6
−5 ppm of FSR/°C
DC Power Supply Rejection Ratio6 −60 dB ΔVDD = ±10%
DAC REFERENCE INPUT6
VREF Input Range 1 VDD V Buffered reference (AD5330, AD5340, and AD5341)
0.25 VDD V Unbuffered reference
VREF Input Impedance >10 MΩ Buffered reference (AD5330, AD5340, and AD5341)
180 kΩ Unbuffered reference; gain = 1, input impedance = RDAC
90 kΩ Unbuffered reference; gain = 2, input impedance = RDAC
Reference Feedthrough −90 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7 0.001 V min Rail-to-rail operation
Maximum Output Voltage4, 7
V
DD − 0.001 V max
DC Output Impedance 0.5 Ω
Short-Circuit Current 25 mA VDD = 5 V
15 mA VDD = 3 V
Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V
5 μs Coming out of power-down mode; VDD = 3 V
LOGIC INPUTS6
Input Current ±1 μA
Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%
0.6 V VDD = 3 V ± 10%
0.5 V VDD = 2.5 V
Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%
2.1 V VDD = 3 V ± 10%
2.0 V VDD = 2.5 V
Pin Capacitance 3 pF
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 4 of 28
Parameter1
B Version2
Unit Conditions/Comments Min Typ Max
POWER REQUIREMENTS
VDD 2.5 5.5 V
IDD (Normal Mode) DACs active and excluding load currents. Unbuffered
VDD = 4.5 V to 5.5 V 140 250 μA Reference, VIH = VDD, VIL = GND
VDD = 2.5 V to 3.6 V 115 200 μA IDD increases by 50 μA at VREF > VDD − 100 mV.
In buffered mode, extra current is (5 + VREF/RDAC) μA,
where RDAC is the resistance of the resistor string.
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V 0.2 1 μA
VDD = 2.5 V to 3.6 V 0.08 1 μA
1 See the Terminology section.
2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).
4 DC specifications tested with output unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
B Version3
Unit Conditions/Comments Min Typ Max
Output Voltage Settling Time VREF = 2 V; see Figure 29
AD5330 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0)
AD5331 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300)
AD5340 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
AD5341 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
Slew Rate 0.7 V/μs
Major Code Transition Glitch Energy 6 nV/s 1 LSB change around major carry
Digital Feedthrough 0.5 nV/s
Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p; unbuffered mode
Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 5 of 28
TIMING CHARACTERISTICS1, 2, 3
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Limit at TMIN, TMAX Unit Condition/Comments
t1 0 ns min CS to WR setup time.
t2 0 ns min CS to WR hold time.
t3 20 ns min WR pulse width.
t4 5 ns min Data, GAIN, BUF, HBEN setup time.
t5 4.5 ns min Data, GAIN, BUF, HBEN hold time.
t6 5 ns min Synchronous mode; WR falling to LDAC falling.
t7 5 ns min Synchronous mode; LDAC falling to WR rising.
t8 4.5 ns min Synchronous mode; WR rising to LDAC rising.
t9 5 ns min Asynchronous mode; LDAC rising to WR rising.
t10 4.5 ns min Asynchronous mode; WR rising to LDAC falling.
t11 20 ns min LDAC pulse width.
t12 20 ns min CLR pulse width.
t13 50 ns min Time between WR cycles.
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
NOTES:
1
SYNCHRONOUS LDAC UPDATE MODE
2
ASYNCHRONOUS LDAC UPDATE MODE
t
1
t
2
t
3
t
4
t
6
t
7
t
9
t
10
t
11
t
12
t
8
t
5
t
13
06852-002
Figure 2. Parallel Interface Timing Diagram
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
VOUT to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package
Power Dissipation (TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP)1 85°C/W
θJA Thermal Impedance (24-Lead TSSOP)1 80°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 Thermal resistance (JEDEC 4-layer (2S2P) board).
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BUFFER
8-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5330
POWER-ON
RESET
RESET
10
9
7
6
13
20
8
1
312
4
11 5
06852-003
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
BUF
V
REF
V
OUT
CLR
NC = NO CONNECT
NC
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
V
DD
PD
TOP VIEW
(Not to Scale)
AD5330
8-BIT
06852-004
Figure 3. AD5330 Functional Block Diagram Figure 4. AD5330 Pin Configuration
Table 5. AD5330 Pin Function Descriptions
Pin No. Mnemonic Description
1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
2 NC No Connect.
3 VREF Reference Input.
4 VOUT Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers.
11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 8 of 28
BUFFER
10-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
DB
8
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5331
POWER-ON
RESET
RESET
10
9
7
6
13
20
1
DB
92
GAIN
8
312
4
11 5
06852-005
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
V
REF
V
OUT
CLR
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
V
DD
PD
TOP VIEW
(Not to Scale)
AD5331
10-BIT
DB
8
DB
9
06852-006
Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration
Table 6. AD5331 Pin Function Descriptions
Pin No. Mnemonic Description
1 DB8 Parallel Data Input.
2 DB9 Most Significant Bit of Parallel Data Input.
3 VREF Unbuffered Reference Input.
4 VOUT Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9 CLR Active low control input that clears all input registers and DAC registers to zero.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers.
11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB0 to DB7 Eight Parallel Data Inputs.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 9 of 28
BUFFER
12-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
POWER-DOWN
LOGIC
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5340
POWER-ON
RESET
RESET
12
11
9
8
414
5
13 7
06852-007
DB
10
DB
9
DB
0
.
.
15
24
1
DB
11 2
BUF
3
GAIN
10
INTERFACE LOGIC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DB
10
PD
V
DD
DB
0
DB
1
DB
2
DB
7
DB
6
DB
3
DB
4
DB
5
12-BIT
AD5340
TOP VIEW
(Not to Scale)
DB
8
DB
9
DB
11
LDAC
GND
BUF
V
OUT
NC
V
REF
CS
WR
GAIN
CLR
06852-008
Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration
Table 7. AD5340 Pin Function Descriptions
Pin No. Mnemonic Description
1 DB10 Parallel Data Input.
2 DB11 Most Significant Bit of Parallel Data Input.
3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
4 VREF Reference Input.
5 VOUT Output of DAC. Buffered output with rail-to-rail operation.
6 NC No Connect.
7 GND Ground reference point for all circuitry on the part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
11 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero.
12 LDAC Active low control input that updates the DAC registers with the contents of the input registers.
13 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode.
14 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
15 to 24 DB0 to DB9 Ten Parallel Data Inputs.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 10 of 28
BUFFER
12-BIT
DAC
DAC
REGISTER
LOW BYTE
REGISTER
INTERFACE LOGIC
POWER-DOWN
LOGIC
BUF
DB
7
DB
0
.
.
HBEN
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD GND
AD5341
POWER-ON
RESET
RESET
9
7
6
1
13
20
2
GAIN
8
312
4
11 5
HIGH BYTE
REGISTER
10
06852-009
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
V
REF
V
OUT
CLR
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
V
DD
PD
TOP VIEW
(Not to Scale)
AD5341
10-BIT
HBEN
BUF
06852-010
Figure 9. AD5341 Functional Block Diagram Figure 10. AD5341 Pin Configuration
Table 8. AD5341 Pin Function Descriptions
Pin No. Mnemonic Description
1 HBEN High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high
byte register or the low byte register.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3 VREF Reference Input.
4 VOUT Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers.
11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 11 of 28
TERMINOLOGY
OUTPUT
VOLTAGE
DAC CODE
POSITIVE
OFFSET
GAIN ERROR
AND
OFFSET ERROR
ACTUAL
IDEAL
06852-012
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the actual endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 14, Figure 15,
and Figure 16.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono-
tonicity. This DAC is guaranteed monotonic by design. Typical
DNL vs. code plots can be seen in Figure 17, Figure 18, and
Figure 19.
Gain Error
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range. This is
illustrated in Figure 11.
Figure 12. Positive Offset Error and Gain Error
OUTPUT
VOLTAGE
DAC CODE
NEGATIVE
OFFSET
GAIN ERROR
AND
OFFSET ERROR
ACTUAL
IDEAL
AMPLIFIER
FOOTROOM
(~1mV)
NEGATIVE
OFFSET
DEADBAND CODES
0
6852-013
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage is still positive
at zero input code. This is shown in Figure 12. Because the
DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there is
a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code, there is a deadband over
which the output voltage does not change. This is illustrated in
Figure 13.
OUTPUT
V
OLTAGE
DAC CODE
POSITIVE
GAIN ERROR
ACTUAL
IDEAL
NEGATIVE
GAIN ERROR
06852-011
Figure 13. Negative Offset Error and Gain Error
Figure 11. Gain Error
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 12 of 28
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power-Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V and VDD is varied ±10%.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated (that is, LDAC is high). It is expressed in decibels.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the DAC changes state. It
is normally specified as the area of the glitch in nV/s and is
measured when the digital code is changed by 1 LSB at the
major carry transition (011 … 11 to 100 … 00 or 100 … 00
to 011 … 11).
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device; it is measured when the DAC is not being written to (CS
held high). It is specified in nV/s and is measured with a full-
scale change on the digital input pins, that is, from all 0s to all
1s and vice versa.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with a full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its atte-
nuated version using the DAC. The sine wave is used as the
reference for the DAC and THD is a measure of the harmonics
present on the DAC output. It is measured in decibels.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 13 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
0
–0.5
–1.0 0 50 100 150 200 250
INL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
06852-015
Figure 14. AD5330 Typical INL Plot
3
2
1
0
–1
–3
–2
0 200 400 500 800 1000
INL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
06852-016
Figure 15. AD5331 Typical INL Plot
12
8
4
0
–12
–8
–4
0 1000 2000 3000 4000
INL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
06852-017
Figure 16. AD5340/AD5341 Typical INL Plot
0.3
0.2
0.1
0
–0.1
–0.2
–0.3 0 50 100 150 200 250
DNL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
06852-018
Figure 17. AD5330 Typical DNL Plot
0.6
0.2
0.4
0
–0.2
–0.4
–0.6 0 200 400 600 800 1000
DNL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
0
6852-019
Figure 18. AD5331 Typical DNL Plot
1.0
0.5
0
–0.5
–1.0 0 1000 2000 3000 4000
DNL ERROR (LSBs)
CODE
T
A
= 25°C
V
DD
= 5V
06852-020
Figure 19. AD5340/AD5341 Typical DNL Plot
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 14 of 28
1.00
0.50
0.75
0
–0.50
0.25
–0.25
–0.75
–1.00 2345
ERROR (LSBs)
V
REF
(V)
MAX INL
MAX DNL
MIN DNL
MIN INL
T
A
= 25°C
V
DD
= 5V
06852-021
Figure 20. AD5330 INL and DNL Error vs. VREF
V
DD
= 5V
V
REF
= 3V
1.00
0.50
0.75
0
–0.50
0.25
–0.25
–0.75
–1.00
–40 0 40 80 120
ERROR (LSBs)
TEMPERATURE (°C)
MAX INLMAX DNL
MIN DNL
MIN INL
06852-022
Figure 21. AD5330 INL Error and DNL Error vs. Temperature
V
DD
= 5V
V
REF
= 2V
1.0
0.5
0
–0.5
–1.0
–40 0 40 80 120
ERROR (%)
TEMPERATURE (°C)
GAIN ERROR
OFFSET ERROR
0
6852-023
Figure 22. AD5330 Offset Error and Gain Error vs. Temperature
GAIN ERROR
OFFSET ERROR
–0.1
0
0.1
0.2
–0.2
–0.3
–0.4
–0.5
–0.6 0123456
ERROR (%)
VDD (V)
TA = 25°C
VREF = 2V
06852-024
Figure 23. Offset Error and Gain Error vs. VDD
5
0
1
2
3
4
0123456
V
OUT
(V)
SINK/SOURCE CURRENT (mA)
5V SOURCE
3V SOURCE
3V SINK
5V SINK
06852-025
Figure 24. VOUT Source and Sink Current Capability
300
0
50
100
150
200
250
ZERO-SCALE FULL-SCALE
I
DD
(µA)
DAC CODE
T
A
= 25°C
V
REF
= 2V
V
DD
= 5.5V
V
DD
= 3.6V
06852-026
Figure 25. Supply Current vs. DAC Code
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 15 of 28
300
T
A
= 25°C
200
100
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
I
DD
(µA)
V
DD
(V)
06852-027
Figure 26. Supply Current vs. Supply Voltage
0.5
T
A
= 25°C
0
0.1
0.2
0.3
0.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5
I
DD
(µA)
V
DD
(V)
06852-028
Figure 27. Power-Down Current vs. Supply Voltage
I
DD
(µA)
V
LOGIC
(V)
1800
T
A
= 25°C
0
200
400
600
800
1000
1200
1400
1600
012345
V
DD
= 5V
V
DD
= 3V
06852-029
Figure 28. Supply Current vs. Logic Input Voltage
CLK
CH1
1V
CH2
5V
TA = 25°C
VDD = 5V
VOUT
TIME BASE = 5µs/DIV
06852-030
Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change)
CH1
2V
CH2
2
00m
V
TIME BASE = 200µs/DIV
TA = 25°C
VDD = 5V
VREF = 2V
VDD
VOUTA
06852-031
Figure 30. Power-On Reset to 0 V
CH1
500mV
CH2
5V
TIME BASE = 1µs/DIV
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
V
OUT
A
PD
06852-032
Figure 31. Exiting Power-Down to Midscale
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 16 of 28
10
–60
–50
–40
–30
–20
–10
0
0.01 0.1 1 10010 10k1k
(dB)
FREQUENCY (kHz)
06852-035
80 90 100 110 120 130 140 150 160 170 190180 200
FREQUENCY
IDD (µA)
VDD = 3V
VDD = 5V
06852-033
Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response)
–0.2
0
0.2
0.4
012 435
FULL-SCALE ERROR (%FSR)
V
REF
(V)
T
A
= 25°C
V
DD
= 5V
06852-036
250ns/DIV
0.903
0.904
0.905
0.906
0.907
0.908
0.909
0.910
0.911
0.912
0.913
0.914
0.915
0.916
0.917
VOLTS
0
6852-034
Figure 33. AD5340 Major-Code Transition Glitch Energy Figure 35. Full-Scale Error vs. VREF
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 17 of 28
THEORY OF OPERATION
The AD5330/AD5331/AD5340/AD5341 are single resistor-
string DACs fabricated on a CMOS process with resolutions
of 8, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The AD5330, AD5340, and AD5341 have a reference
input that can be buffered to draw virtually no current from
the reference source. The reference input of the AD5331 is
unbuffered. The devices have a power-down feature that
reduces current consumption to only 80 nA @ 3 V.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 36 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
Gain
D
VV N
REF
OUT ××=
2
where:
D is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5330 (8 Bits)
0 to 1023 for AD5331 (10 Bits)
0 to 4095 for AD5340/AD5341 (12 Bits)
N is the DAC resolution.
Gain is the output amplifier gain (1 or 2).
GAIN
V
REF
VOUT
BUF
DAC
REGISTER
INPUT
REGISTER RESISTOR
STRING
OUTPUT
BUFF E R AMPLIFIER
REFERENCE
BUFFER
06852-037
Figure 36. Single DAC Channel Architecture
RESISTOR STRING
The resistor-string section is shown in Figure 37. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
TO OUTPUT
AMPLIFIER
R
R
R
R
R
V
REF
06852-038
Figure 37. Resistor String
DAC REFERENCE INPUT
There is a reference input pin for the DAC. The reference
input is buffered on the AD5330, AD5340, and AD5341 but
can be configured as unbuffered also. The reference input of
the AD5331 is unbuffered. The buffered/unbuffered option is
controlled by the BUF pin.
In buffered mode (BUF = 1), the current drawn from an
external reference voltage is virtually zero because the
impedance is at least 10 MΩ. The reference input range is
1 V to 5 V with a 5 V supply.
In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as VDD because there is no
restriction due to headroom and footroom of the reference
amplifier. The impedance is still large at typically 180 kΩ for
0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is
an external buffered reference (for example, REF192), there is
no need to use the on-chip buffer.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 × VREF. However, because of clamping, the maximum
output is limited to VDD – 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to
GND or 2 kΩ to VDD in parallel with 500 pF to GND or 500 pF
to VDD. The source and sink capabilities of the output amplifier
can be seen in Figure 24.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see
Figure 29).
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 18 of 28
PARALLEL INTERFACE
The AD5330, AD5331, and AD5340 load their data as a single
8-, 10-, or 12-bit word, while the AD5341 loads data as a low
byte of eight bits and a high byte containing four bits.
DOUBLE-BUFFERED INTERFACE
The AD5330/AD5331/AD5340/AD5341 DACs all have double-
buffered interfaces consisting of an input register and a DAC
register. DAC data, BUF, and GAIN inputs are written to the
input register under the control of chip select (CS) and write (WR).
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are only updated when LDAC is
taken low.
Double-buffering is also useful where the DAC data is loaded
in two bytes, as in the AD5341, because it allows the whole
data word to be assembled in parallel before updating the DAC
register. This prevents spurious outputs that can occur if the DAC
register is updated with only the high byte or the low byte.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC register is filled with the
contents of the input register. In the case of the AD5330/
AD5331/AD5340/AD5341, the parts only update the DAC
register if the input register has been changed since the last time
the DAC register was updated. This removes unnecessary crosstalk.
CLEAR INPUT (CLR)
CLR is an active low, asynchronous clear that resets the input
and DAC registers.
CHIP SELECT INPUT (CS)
CS is an active low input that selects the device.
WRITE INPUT (WR)
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising
edge of WR.
LOAD DAC INPUT (LDAC)
LDAC transfers data from the input register to the DAC register
(and therefore updates the outputs). Use of the LDAC function
enables double-buffering of the DAC data, GAIN, and BUF.
There are two LDAC modes: synchronous mode and
asynchronous mode.
In synchronous mode, the DAC register is updated after new
data is read in on the rising edge of the WR input. LDAC can
be tied permanently low or pulsed, as shown in . Figure 2
In asynchronous mode, the outputs are not updated at the same
time that the input register is written to. When LDAC goes low,
the DAC register is updated with the contents of the input
register.
HIGH BYTE ENABLE INPUT (HBEN)
High byte enable is a control input on the AD5341 only. It
determines if data is written to the high byte input register
or the low byte input register.
The low data byte of the AD5341 consists of Data Bits [0:7]
at the data inputs DB0 to DB7, whereas the high byte consists
of Data Bits [8:11] at the data inputs DB0 to DB3, as shown in
Figure 38. DB4 to DB7 are ignored during a high byte write, but
they can be used for data to set up the reference input as buffered/
unbuffered, and buffer amplifier gain (see Figure 42).
DB
8
DB
9
XX
HIGH BYTE
LOW BYTE
X
= UNUSED BIT
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
XX DB
10
DB
11
06852-039
Figure 38. Data Format for AD5341
POWER-ON RESET
The AD5330/AD5331/AD5340/AD5341 are provided with a
power-on reset function, so that they power up in a defined
state. The power-on state is
• Normal operation
• Reference input unbuffered
• 0 V to VREF output range
• Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
as such until a valid write sequence is made to the device. This
is particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 19 of 28
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power
consumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into power-
down mode, which is selected by taking Pin PD low.
When the PD pin is high, the DAC works normally with a
typical power consumption of 140 μA at 5 V (115 μA at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered down.
Not only does the supply current drop, but the output stage
is also internally switched from the output of the amplifier,
making it open-circuit. This has the advantage that the output
is three-state while the part is in power-down mode and provides
a defined input condition for whatever is connected to the
output of the DAC amplifier. The output stage is illustrated in
. Figure 39
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER V
OUT
06852-040
Figure 39. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
VDD = 3 V. This is the time from a rising edge on the PD pin to
when the output voltage deviates from its power-down voltage
(see ). Figure 31
Table 9. AD5330/AD5331/AD5340 Truth Table1
CLR LDAC CS WR Function
1 1 1 X No data transfer
1 1 X 1 No data transfer
0 X X X Clear all registers
1 1 0 0→1 Load input register
1 0 0 0→1 Load input register and DAC register
1 0 X X Update DAC register
1 X = don’t care.
Table 10. AD5341 Truth Table1
CLR LDAC CS WR HBEN Function
1 1 1 X X No data transfer
1 1 X 1 X No data transfer
0 X X X X Clear all registers
1 1 0 0→1 0 Load low byte input register
1 1 0 0→1 1 Load high byte input register
1 0 0 0→1 0 Load low byte input register and DAC register
1 0 0 0→1 1 Load high byte input register and DAC register
1 0 X X X Update DAC register
1 X = don’t care.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 20 of 28
SUGGESTED DATABUS FORMATS
In most applications, GAIN and BUF are hard-wired. However,
if more flexibility is required, they can be included in a databus.
This enables the user to software program GAIN, giving the
option of doubling the resolution in the lower half of the DAC
range. In a bused system, GAIN and BUF can be treated as data
inputs because they are written to the device during a write
operation and take effect when LDAC is taken low. This means
that the reference buffers and the output amplifier gain of
multiple DAC devices can be controlled using common GAIN
and BUF lines.
In the case of the AD5330, this means that the databus must be
wider than eight bits. The AD5331 and AD5340 databuses must
be at least 10 bits and 12 bits wide, respectively, and are best
suited to a 16-bit databus system.
Examples of data formats for putting GAIN and BUF on a
16-bit databus are shown in Figure 40. Note that any unused bits
above the actual DAC data can be used for BUF and GAIN. DAC
devices can be controlled using common GAIN and BUF lines.
AD5331
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
GAIN XXXX XXBUF
AD5330
AD5340
X = UNUSED BIT
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
GAIN XXXXBUF DB
9
DB
8
XX DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
GAINBUF DB
9
DB
8
DB
10
DB
11
06852-041
Figure 40. GAIN and BUF Data on a 16-Bit Bus
The AD5341 is a 12-bit device that uses byte load, so only four
bits of the high byte are actually used as data. Two of the unused
bits can be used for GAIN and BUF data by connecting them to
the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as
shown in Figure 41 and Figure 42.
DATA
INPUTS
BUF
GAIN
LDAC
CLR
CS
WR
HBEN
AD5341
DB
7
DB
6
8-BIT
DATA BUS
0
6852-042
Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data
on 8-Bit Bus
In this case, the low byte is written to first in a write operation
with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into
GAIN and BUF registers but have no effect. The high byte is
then written to. Only the lower four bits of data are written into
the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and
BUF data.
LDAC is used to update the DAC, GAIN, and BUF values.
DB
8
DB
9
HIGH BYTE
LOW BYTE
X = UNUSED BIT
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
XX DB
10
DB
11
BUF GAIN
06852-043
Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 21 of 28
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
The AD5330/AD5331/AD5340/AD5341 can be used with
a wide range of reference voltages, especially if the reference
inputs are configured to be unbuffered, in which case the
devices offer full, one-quadrant multiplying capability over a
reference range of 0.25 V to VDD. More typically, these devices
can be used with a fixed, precision reference voltage. Figure 43
shows a typical setup for the devices when using an external
reference connected to the unbuffered reference inputs. If the
reference inputs are unbuffered, the reference input range is
from 0.25 V to VDD, but if the on-chip reference buffers are
used, the reference range is reduced. Suitable references for 5 V
operation are the AD780 and REF192. For 2.5 V operation, a
suitable external reference is the AD589, a 1.23 V band gap
reference.
AD5330/AD5331/
AD5340/AD5341
V
OUT
V
DD
= 2.5V TO 5.5
V
V
DD
GND
V
REF
GND
EXT
REF
+
0.1µF 10µF
V
OUT
V
IN
AD780/REF192
WITH V
DD
= 5V
OR
A
D589 WITH V
DD
= 2.5V
06852-044
Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference
DRIVING VDD FROM THE REFERENCE VOLTAGE
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference inputs to VDD. Because this
supply may not be very accurate and may be noisy, the devices
can be powered from the reference voltage, for example using
a 5 V reference such as the ADP667, as shown in Figure 44.
AD5330/AD5331/
AD5340/AD5341
GND SHDN
V
OUT
ADP667
VSET
6V TO 16
V
V
OUT
V
DD
V
IN
GND
V
REF
+
0.1µF
0.1µF
10µF
06852-045
Figure 44. Using an ADP667 as Power and Reference to
AD5330/AD5331/AD5340/AD5341
BIPOLAR OPERATION USING THE AD5330/AD5331/
AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 are designed for
single-supply operation, but bipolar operation is achievable
using the circuit shown in Figure 45. The circuit shown has
been configured to achieve an output voltage range of –5 V <
VO < +5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as follows:
VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] –
R4 × VREF/R3
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
VREF is the reference voltage input.
with:
VREF = 2.5 V.
R1 = R3 = 10 kΩ.
R2 = R4 = 20 kΩ and VDD = 5 V.
VO = (10 × D/2N) − 5.
V
DD
= 5
V
+
0.1µF 10µF
R2
20kΩ
R1
10kΩ
R3
10kΩ
R4
20kΩ
GND
V
O
= ±5V
+5V
–5V
AD5330/AD5331/
AD5340/AD5341
V
REF
V
OUT
V
DD
GND
EXT
REF V
OUT
V
IN
AD780/REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 2.5V
0.1µF
06852-046
Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341
DECODING MULTIPLE AD5330/AD5331/
AD5340/AD5341
The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same data and WR pulses, but only CS to one
of the DACs is active at any one time, so data is only written to
the DAC whose CS is low. If multiple AD5341s are being used, a
common HBEN line is also required to determine if the data is
written to the high byte or low byte register of the selected DAC.
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 46 shows a
diagram of a typical setup for decoding multiple devices in a
system. Once data has been written sequentially to all DACs in
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 22 of 28
a system, all the DACs can be updated simultaneously using a
common LDAC line. A common CLR line can also be used to
reset all DAC outputs to zero.
ENABLE
CODED
A
DDRESS
G1
A1
B1
V
DD
V
CC
74HC139
DGND
1Y0
1Y1
1Y2
1Y3
DATA
INPUTS
DATA BUS
*AD5341 ONLY
LDAC
CLR
CS
HBEN*
AD5330/AD5331/
AD5340/AD5341
WR
LDAC
CLR
HBEN*
WR
DATA
INPUTS
LDAC
CLR
CS
HBEN*
AD5330/AD5331/
AD5340/AD5341
WR
DATA
INPUTS
LDAC
CLR
CS
HBEN*
AD5330/AD5331/
AD5340/AD5341
WR
DATA
INPUTS
LDAC
CLR
CS
HBEN*
AD5330/AD5331/
AD5340/AD5341
WR
06852-047
Figure 46. Decoding Multiple DAC Devices
PROGRAMMABLE CURRENT SOURCE
Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used
as the control element of a programmable current source. In
this example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment poten-
tiometer, which gives an adjustment of about ±5%. Suitable
transistors to place in the feedback loop of the amplifier include
the BC107 and the 2N3904, which enable the current source to
operate from a minimum VSOURCE of 6 V. The operating range is
determined by the operating characteristics of the transistor.
Suitable amplifiers include the AD820 and the OP295, both
having rail-to-rail operation on their outputs. The current for
any digital input code and resistor value can be calculated as
follows:
mA
)2( R
D
VGI N
REF ×
××=
where:
G is the gain of the buffer amplifier (1 or 2).
D is the digital equivalent of the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer
in kilo ohms.
AD5330/AD5331/
AD5340/AD5341
V
DD
= 5
V
4.7kΩ
5V
470Ω
LOAD
V
SOURCE
V
REF
V
DD
GND
V
OUT
AD820/
OP295
+
0.1µF 10µF
0.1µF
GND
EXT
REF V
OUT
V
IN
AD780/REF192
WITH V
DD
= 5V
06852-048
Figure 47. Programmable Current Source
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board on
which the AD5330/AD5331/AD5340/AD5341 are mounted
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. If the
device is in a system where multiple devices require an AGND-
to-DGND connection, the connection should be made at one
point only. The star ground point should be established as
closely as possible to the device. The AD5330/AD5331/
AD5340/AD5341 should have ample supply bypassing of
10 μF in parallel with 0.1 μF on the supply located as close to
the package as possible, ideally right up against the device.
The 10 μF capacitors are the tantalum bead type. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The power supply lines of the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by
far the best, but not always possible with a double-sided board.
In this technique, the component side of the board is dedicated to
the ground plane while signal traces are placed on the solder side.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 23 of 28
Table 11. Overview of AD53xx Parallel Devices
Part No. Resolution Bits DNL No. of VREF Pins Settling Time
Additional Pin Functions
Package No. of Pins BUF GAIN HBEN CLR
Singles
AD5330 8 ±0.25 1 6 μs BUF GAIN CLR TSSOP 20
AD5331 10 ±0.5 1 7 μs GAIN CLR TSSOP 20
AD5340 12 ±1.0 1 8 μs BUF GAIN CLR TSSOP 24
AD5341 12 ±1.0 1 8 μs BUF GAIN HBEN CLR TSSOP 20
Duals
AD5332 8 ±0.25 2 6 μs CLR TSSOP 20
AD5333 10 ±0.5 2 7 μs BUF GAIN CLR TSSOP 24
AD5342 12 ±1.0 2 8 μs BUF GAIN CLR TSSOP 28
AD5343 12 ±1.0 1 8 μs HBEN CLR TSSOP 20
Quads
AD5334 8 ±0.25 2 6 μs GAIN CLR TSSOP 24
AD5335 10 ±0.5 2 7 μs HBEN CLR TSSOP 24
AD5336 10 ±0.5 4 7 μs GAIN CLR TSSOP 28
AD5344 12 ±1.0 4 8 μs TSSOP 28
Table 12. Overview of AD53xx Serial Devices
Part No. Resolution Bits No. of DACs DNL Interface Settling Time Package No of Pins
Singles
AD5300 8 1 ±0.25 SPI 4 μs SOT-23, MSOP 6, 8
AD5310 10 1 ±0.5 SPI 6 μs SOT-23, MSOP 6, 8
AD5320 12 1 ±1.0 SPI 8 μs SOT-23, MSOP 6, 8
AD5301 8 1 ±0.25 2-Wire 6 μs SOT-23, MSOP 6, 8
AD5311 10 1 ±0.5 2-Wire 7 μs SOT-23, MSOP 6, 8
AD5321 12 1 ±1.0 2-Wire 8 μs SOT-23, MSOP 6, 8
Duals
AD5302 8 2 ±0.25 SPI 6 μs MSOP 10
AD5312 10 2 ±0.5 SPI 7 μs MSOP 10
AD5322 12 2 ±1.0 SPI 8 μs MSOP 10
AD5303 8 2 ±0.25 SPI 6 μs TSSOP 16
AD5313 10 2 ±0.5 SPI 7 μs TSSOP 16
AD5323 12 2 ±1.0 SPI 8 μs TSSOP 16
Quads
AD5304 8 4 ±0.25 SPI 6 μs MSOP, LFCSP 10
AD5314 10 4 ±0.5 SPI 7 μs MSOP, LFCSP 10
AD5324 12 4 ±1.0 SPI 8 μs MSOP, LFCSP 10
AD5305 8 4 ±0.25 2-Wire 6 μs MSOP 10
AD5315 10 4 ±0.5 2-Wire 7 μs MSOP 10
AD5325 12 4 ±1.0 2-Wire 8 μs MSOP 10
AD5306 8 4 ±0.25 2-Wire 6 μs TSSOP 16
AD5316 10 4 ±0.5 2-Wire 7 μs TSSOP 16
AD5326 12 4 ±1.0 2-Wire 8 μs TSSOP 16
AD5307 8 4 ±0.25 SPI 6 μs TSSOP 16
AD5317 10 4 ±0.5 SPI 7 μs TSSOP 16
AD5327 12 4 ±1.0 SPI 8 μs TSSOP 16
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 24 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARIT
Y
0.10
Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
24 13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC 1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 25 of 28
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD5330BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5330BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5330BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5330BRUZ1–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5330BRUZ-REEL1
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5330BRUZ-REEL71
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRUZ1
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRUZ-REEL1
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5331BRUZ-REEL71
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5340BRU –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5340BRU-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5340BRU-REEL7 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5340BRUZ1
–40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5340BRUZ-REEL1
–40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5340BRUZ-REEL71
–40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
AD5341BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5341BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5341BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5341BRUZ1
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5341BRUZ-REEL1
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5341BRUZ-REEL71
–40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
1 Z = RoHS Compliant Part.
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 26 of 28
NOTES
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 27 of 28
NOTES
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 28 of 28
NOTES
©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06852-0-2/08(A)
