7P160FLF1201C25 - Microsemi Corp.

PCMCIA Flash Memory Card

FLF1 Series

1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

March 2003

Rev. 5

High Density FLASH Memory Card

16, 32, 48, 64, 80 MEGABYTE

FEATURES

 Low cost, high density Linear Flash Card

 Universal 3V to 5V operating range providing full

“plug and play” exchangeability between different

systems

 Based on Intel 28F128J3A (MLC) and *28F640J3

(MLC) Components

 Fast Read Performance

• 250ns Maximum Access Time

• (200ns optional)

 PCMCIA compatible

• x8/ x16 Data Interface

 32-Byte Write Buffer (per Memory Device)

• 6μs per Byte Effective Write Time

 128-bit Protection Register (per Memory Device)

• 64-bit Unique Device Identiﬁ er

• 64-bit User Programmable OTP Cells

 Cross-Compatible Command Support

• Common Flash Interface (CFI)

• Intel Basic Command Set

• Scaleable Command Set

 Power-Down Mode

• Reset, Power Down Registers

 100,000 Erase Cycles per Block

 128K word symmetrical Block Architecture

 PC Card Standard Type I Form Factor

GENERAL DESCRIPTION

WEDC’s Flash memory cards — FLF1 Series — offer

high density linear Flash memory for code and data

storage, high performance disk emulation, mobile PC and

embedded applications.

The WEDC’s FLF1 series is based on Intel’s Multi Level

Cell (MLC) Flash memory technology, providing high

density Flash components at a signiﬁ cantly lower cost

per megabyte. MLC technology allows for two bits of

information to be stored in a single cell. This leads to

reduced die size and reduced cost per megabyte.

WEDC’s FLF1 series cards are built with Intel’s 128Mb

memory components, 28F128J3A, with a manufacturer/

device ID of 89/18H. The FLF1 series is available in

densities of 32, 64, 96, 128, 160, and 192MB. There are

also 16MB and 48MB cards available built with Intel’s

64Mb memory components 28F640J3 with 89/17H

manufacturer/device ID.

The cards up to the 64MB density operate in the regular

PCMCIA mode. The densities beyond the 64MB density

are implemented using a “paging scheme”, which is also

supported by the PCMCIA standard. By writing a page

address to the Conﬁ guration Option Register (address

4000H), an additional page of memory can be accessed.

The current FLF1 series supports densities up to 192MB:

total of 3 pages: page 0 := 64MB, page 1 := 64MB, and

page 2 := 64MB.

The FLF1 series card operates in a wide, universal

voltage range, from 3V to 5V, allowing full “plug and play”

functionality and upgrade solutions in all mobile, battery

powered applications.

Each memory component in the card also has a 128-

bit Protection Register, containing 64 bits of User

Programmable OTP (One Time Programmable) Cells.

These cells can be programmed with a numeric security

measure, such as an electronic signature.

To provide a 16 bit word wide access supported by

the PCMCIA standard, devices are paired on the card.

Therefore, the Flash array is structured in 128K word

(256kB) blocks. Write, read and block erase operations can

be performed as either a word or byte wide operation.

The FLF1 series cards conform to the PC Card 95 Standard

supported by PCMCIA and JEIDA, providing electrical and

physical compatibility. The PC Card form factor offers an

industry standard pinout and mechanical outline, allowing

density upgrades without system design changes.

WEDC’s standard cards are shipped with WEDC’s Flash

Logo. Cards are also available with blank housings

(no Logo). The blank housings are available in both, a

recessed (for label) or ﬂ at housing. Please contact your

WEDC sales representative for further information on

Custom artwork.

PCMCIA Flash Memory Card

FLF1 Series

2White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

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Rev. 5

BLOCK DIAGRAM

DATA

BUS

Q8-Q15

DATA

BUS

Q0-Q7

N x 28F128J3A

Device 0Device 1

Device 3 Device 2

Device (N-2)Device (N-1)

ADDRESS

BUFFER

A1-A25

B26, (B27..)

WRi

CL0

control

logic

RDi

(A1-A25)

(B26)

attrib. mem

CIS

E²PROM 2kB

Management

Registers

0000h

4000h

A24, A25, B26

At/Reg enable

Ctrl

Device Pair 0

Device Pair 1

Device Pair (N/2 - 1)

ADDRESS Register NAME

Configuration Option Register

4000h

4002h

4004h

4006h

4008h

Config. and Status Reg.

WE#

CE1#

CE2#

OE#

REG#

CHn

CH0

CLn

CL0

CLn

CL1

CH0

SR Clr

Reg Clr

D5-D0=Page Number (PN)

- Page Number (PN) -

D7 D5D6 D1D3 D2D4 D0

SRes LvReq

CH0

A1-A23 ADDRESS BUS

(A1-A25)

R/BUSY

R/B0

R/B(N-1)

R/B1

VS2

VS1

10k

N.C.

Vpp2

Vpp1

(3V-5V)

cVcc

GND

CD1

CD2

BVD1

BVD2

Vcc

OPEN

WAIT

OPEN

control

I/O buffer

DATA

BUS

D15

DATA

BUS

Q0-Q7

MRes Configuration Option Register: A=4000h (Read/Write)

MRes

SR Clr

Reg Clr

reset circuit

Configuration Option Register: ADRS=4000h

D6 LevelReq (not supported)

- Page Number (PN) -

D2D4D7 D6

D7 Soft Reset, active High

1=Reset State

0=End Reset State

D0D5 D1D3

SRes LvReq

D5-D0 Configuration index

D5-D1 reserved

D0 Page Number Config. (PN) Power On default =0

D7 D3 D0D6 D2D4 D1D5

Power Down; active High

1 = Place all memory devices in power down mode

0 = normal operation Power On default=0

PwrDwn reserved

reserved

Configuration Status Register: ADRS=4002h

Read/Write

D0 - D15

220k

Vcc

Reset

CE1#, CE2#, OE#, WE#, Reg#: pull up typ 100k

A0: pull down typ 100k

Reset: pull down typ 220k

R/Busy - Open Drain output pull up typ 100k

Manufacturer ID Intel 89H

Device ID 28F128J3A 18H

Device ID 28F640J3A 18H

FLF1 Flash Card

based on Strata Flash 28F128J3A and 28F640J3

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

MECHANICAL

PINOUT

Notes:

1. RDY/BSY# signal is an “Open drain” type output, pull-up resistors are required on

the host side.

2. VS1 is connected to GND.

3. Wait#, BVD1 and BVD2 are internally connected to VCC by resistors for

compatibility.

5.0mm MAX.

0.197”

1.6mm 0.05

0.063”

MIN.

10.0mm MIN.

0.400”

1.0mm 0.05

0.039’

85.6mm 0.20

3.370”

3.0mm

54.0mm 0.10

2.126”

1.0mm 0.05

0.039’

Substrate area

Interconnect area

Pin #1

Pin #35

3.3mm 0.05”

0.130”

Pin Signal name I/O Function Active

1 GND Ground

2 DQ3 I/O Data bit 3

3 DQ4 I/O Data bit 4

4 DQ5 I/O Data bit 5

5 DQ6 I/O Data bit 6

6 DQ7 I/O Data bit 7

7 CE1# I Card enable 1 LOW

8 A10 I Address bit 10

9 OE# I Output enable LOW

10 A11 I Address bit 11

11 A9 I Address bit 9

12 A8 I Address bit 8

13 A13 I Address bit 13

14 A14 I Address bit 14

15 WE# I Write Enable LOW

16 RDY/BSY# O Ready/Busy LOW (1)

17 VCC Supply Voltage

18 VPP1 Prog. Voltage N.C.

19 A16 I Address bit 16

20 A15 I Address bit 15

21 A12 I Address bit 12

22 A7 I Address bit 7

23 A6 I Address bit 6

24 A5 I Address bit 5

25 A4 I Address bit 4

26 A3 I Address bit 3

27 A2 I Address bit 2

28 A1 I Address bit 1

29 A0 I Address bit 0

30 DQ0 I/O Data bit 0

31 DQ1 I/O Data bit 1

32 DQ2 I/O Data bit 2

33 WP O Write Potect HIGH

34 GND Ground

Pin Signal name I/O Function Active

35 GND Ground

36 CD1# O Card Detect 1 LOW

37 DQ11 I/O Data bit 11

38 DQ12 I/O Data bit 12

39 DQ13 I/O Data bit 13

40 DQ14 I/O Data bit 14

41 DQ15 I Data bit 15

42 CE2# I Card Enable 2 LOW

43 VS1 O Voltage Sense 1 NC (2)

44 RFU Reserved

45 RFU Reserved

46 A17 I Address bit 17

47 A18 I Address bit 18

48 A19 I Address bit 19

49 A20 I Address bit 20

50 A21 I Address bit 21

51 VCC Supply Voltage

52 VPP2 Prog. Voltage NC

53 A22 I Address bit 22

54 A23 I Address bit 23

55 A24 I Address bit 24

56 A25 I Address bit 25

57 VS2 O Voltage Sense 2 NC

58 RST I Card Reset HIGH

59 Wait# O Extended Bus cycle LOW(3)

60 RFU Reserved

61 REG# I Attrib Mem Select

62 BVD2 O Bat. Volt. Detect 2 (2)

63 BVD1 O Bat. Volt. Detect 1 (3)

64 DQ8 I/O Data bit 8

65 DQ9 I/O Data bit 9

66 DQ10 O Data bit 10

67 CD2# O Card Detect 2 LOW

68 GND Ground

PCMCIA Flash Memory Card

FLF1 Series

4White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

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Rev. 5

Symbol Type Name and Function

A0 - A25 INPUT ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not

used in word access mode. A25 is the most signiﬁ cant bit

DQ0 - DQ15 INPUT/OUTPUT DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB.

CE1#, CE2# INPUT CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0,

CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7 (see truth table).

OE# INPUT OUTPUT ENABLE: Active low signal gating read data from the memory card.

WE# INPUT WRITE ENABLE: Active low signal gating write data to the memory card.

RDY/BSY# OUTPUT READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that

the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy

with internally timed erase or write activities.

CD1#, CD2# OUTPUT CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the

card. The host shall monitor these signals to detect card insertion (pulled-up on host side).

WP OUTPUT WRITE PROTECT: Write protect reﬂ ects the status of the Write Protect switch on the memory card. WP set to high =

write protected, providing internal hardware write lockout to the Flash array. If card dOE#s not include optional write

protect switch, this signal will be pulled low internally indicating write protect = “off”.

VPP1, VPP2 N.C. PROGRAMMING VOLTAGES: Not connected for 5V only card.

VCC CARD POWER SUPPLY: 5.0V for all internal circuitry

GND CARD GROUND

REG# INPUT ATTRIBUTE MEMORY SELECT : Active low signal, enables access to attribute memory space, occupied by the

Card Information Structure (CIS) and Card Registers.

RST INPUT RESET: Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down control for

the memory array.

WAIT# OUTPUT WAIT: This signal is pulled high internally for compatibility. No wait states are generated.

BVD1, BVD2 OUTPUT BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility.

VS1, VS2 OUTPUT VOLTAGE SENSE: Notiﬁ es the host socket of the card’s VCC requirements. VS1 and VS2 are

RFU RESERVED FOR FUTURE USE

NC NO INTERNAL CONNECTION TO CARD: pin may be driven or left ﬂ oating

Card Signal Description

READ function Common Memory Attribute Memory

Function Mode CE2#CE

1#A

0OE# WE# REG# D15-D8D7-D0REG# D15-D8D7-D0

Standby Mode H H X X X X High-Z High-Z X High-Z High-Z

Byte Access (8 bits) H L L L H H High-Z Even-Byte L High-Z Even-Byte

H L H L H H High-Z Odd-Byte L High-Z Not Valid

Word Access (16 bits) L L X L H H Odd-Byte Even-Byte L Not Valid Even-Byte

Odd-Byte Only Access L H X L H H Odd-Byte High-Z L Not Valid High-Z

WRITE function

Standby Mode H H X X X X X X X X X

Byte Access (8 bits) H L L H L H X Even-Byte L X Even-Byte

H L H H L H X Odd-Byte L X X

Word Access (16 bits) L L X H L H Odd-Byte Even-Byte L X Even-Byte

Odd-Byte Only Access L H X H L H Odd-Byte X L X X

Functional Truth Table

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

CARD INTERFACE

The FLF0 series ﬂ ash card complies with PC Card

standard (PCMCIA, March 1997). While maintaining

PCMCIA compatibility, the FLF0 series card has

integrated special features to extend functionality.

Card has built in 2 control registers:

• Conﬁ guration Option Register (COR)

Address = 4000h

• Conﬁ guration and Status Register (CSR)

Address = 4002h

COR register: provide a soft reset function (bit D7) and

additional page register (bit D0) to extend card capacity

beyond 64MB.

SReset

As deﬁ ned by PCMCIA, setting the SReset bit to 1,

places the card in the reset state. During this state

all memory devices are place in power down mode,

minimizing power consumption. Returning this bit to 0

leaves the reset cycle and place the card in the same

condition as following a power up or hardware reset.

This bit must be cleared to 0, to access any device on

the card.

Complete soft reset cycle must consist of a 2 step write

sequence to the SReset bit:

1. Initialization: write 1 to SReset

• reset cycle begin

• memory devices enters Power-Down mode

aborting all operations and clearing all registers.

2. Write 0 to SReset

• Reset cycle ends

• memory devices and registers enters power on

default state

Card can be place in Power Down mode by activating

Reset signal (pin58) or by controlling the bit D2 in CSR

LevlRequest

Not supported

Conﬁ guration Index

Conﬁ guration Index bits (D0 - D5) are deﬁ ned to provide

address extension bits -page address, to extend card

capacity beyond 64MB.

Only bit D0 is supported:

• D1D0 set to 00bin (0H) selects: page 0

• D1D0 set to 01bin (1H) selects: page 1

• D1D0 set to 10bin (2H) selects: page 2

• D1D0 set to 11bin (3H) selects: page 3 (No

Memory Access)

D1D0 is set to the value of 00bin (0H) during any

reset cycle (Power on Reset, Hardware Reset,

and SReset). Attempting to access page 3 will not

result in the writing or reading of data.

CSR register: provide a power control of memory array.

Only bit D2 is supported; all other bits are “don’t care”

PwrDwn

Writing 1 to PwrDwn bit (D2) forces each memory

device on the card into a reset/power down mode

by asserting all the devices RP# pins. Writing 0 to

the bit returns the array to stand by mode.

Card Information Structure (CIS) contains information

about Registers addressing and Memory structure.

Cards with memory capacity < 64MB do not support

Conﬁ guration Index bits.

Notes:

1. Reading from undeﬁ ned address location or unsupported bits will return random

data.

2. Writing to undeﬁ ned address location may result in card malfunctioning due to

limited address decoding.

3. See block diagram for more details about control registers.

Writing commands to the CUI enables reading of device data, query, identiﬁ er codes,

inspection and clearing of the status register, and, when VPEN = VPENH, block erasure,

program, and lock-bit conﬁ guration.

The Block Erase command requires appropriate command data and an address within

the block to be erased. The Byte/Word Program command requires the command

and address of the location to be written. Set Block Lock-Bit commands require the

command and block within the device to be locked. The Clear Block Lock-Bits command

requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device

is enabled and WE# is active. The address and data needed to execute a command are

latched on the rising edge of WE# or the ﬁ rst edge of CE0, CE1, or CE2 that disables the

device. Standard microprocessor write timings are used.

For information regarding modes of operation,

commands, and programming details for the memory

components, please consult the Intel 28F128J3A

(28F640J3) data sheet.

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

Note:

Stress greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation

at these or any other conditions greater than those indicated in the operational sections

of this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

ABSOLUTE MAXIMUM RATINGS (2)

Operating Temperature TA (ambient)

Commercial 0°C to +60°C

Industrial -40°C to +85°C

Storage Temperature -65°C to +125°C

Voltage on any pin relative to VSS -0.5V to VCC+0.5V

VCC supply Voltage relative to VSS -0.5V to +7.0V

DC CHARACTERISTICS (1)

Symbol Parameter Density (Mbytes) Notes Typ(3) Max Units Test Conditions

ICCR VCC Read Current 32,64, 96, 128, 160, 192 70 110 mA VCC = VCC max tcycle = 200ns

ICCW VCC Program Current 32,64, 96, 128, 160, 192 70 120 mA 2 memory devices

ICCE VCC Erase Current 32,64, 96, 128, 160, 192 70 140 mA 2 memory devices

ICCD VPP Power-down Current 32 2 100 200 μAVCC = VCC max

Control Signals = VCC

Reset = VCC (active)

64 200 400

96 300 600

128 400 800

160 500 1000

192 600 1200

ICCS

(CMOS)

VCC Standby Current 32 2 0.1 0.2 mA VCC = VCC max

Control Signals = VCC

Reset = 0V (not active)

64 0.2 0.4

96 0.3 0.6

128 0.4 0.8

160 0.5 1.0

192 0.6 1.2

CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V

Notes:

1. All currents are RMS values unless otherwise speciﬁ ed. ICCR, ICCW and ICCE are based on Word wide operations (2 memory devices activated).

2. Control Signals: CE1#, CE2#, OE#, WE#.

3. Typical: VCC = 5V or VCC = 3V, T = +25°C.

VCC Tolerance

3.3V ± 0.3V

5.0V ± 0.5V

RECOMMENDED SUPPLY VOLTAGE

Note: The FLF1 Series Card will

function at either 3.3V or 5.0V

VCC = 3.3V or 5V

Symbol Parameter Notes Min Max Units Test Conditions

ILI Input Leakage Current 1, 2 ±20 μAVCC = VCCMAX

VIN =VCC or GND

ILO Output Leakage Current 1 ±20 μAVCC = VCCMAX

VIN =VCC or GND

VIL Input Low Voltage 1 0 0.8 V

VIH Input High Voltage 1 2.0V VCC+0.5 V

VOL Output Low Voltage 1 0.4 V IOL = 3.2mA

VOH Output High Voltage 1 2.4V V IOH = -2.0mA

VLKO VCC Erase/Program Lock Voltage 1 2.0 V

Notes:

1. Values are the same for byte and word wide modes for all card densities.

2. Exception: Leakage current on control signals with internal pull up resistors (see block diag) will be <500 μA when VIN = GND.

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

AC CHARACTERISTICS – READ TIMING PARAMETERS

VCC = 3.3V or 5V

SYMBOL (PCMCIA) Parameter 200ns 250ns Unit

Min Max Min Max

tC(R) Read Cycle Time 200 250 ns

tA(A) Address Access Time 200 250 ns

tA(CE) Card Enable Access Time 200 250 ns

tA(OE#) Output Enable Access Time 90 100 ns

tSU(A) Address Setup Time 20 30 ns

tSU(CE) Card Enable Setup Time 0 0 ns

tH(A) Address Hold Time 20 20 ns

tH(CE) Card Enable Hold Time 20 20 ns

tV(A) Output Hold from Address Change 0 0 ns

tDIS(CE) Output Disable Time from CE 90 100 ns

tDIS(OE#) Output Disable Time from OE# 90 100 ns

tEN(CE) Output Enable Time from CE 5 5 ns

tEN(OE#) Output Enable Time from OE# 5 5 ns

tREC(RST) Power Down recovery to Output

Delay. VCC = 5V

500 500 ns

Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 speciﬁ cations.

READ TIMING DIAGRAM

NOTE 1

[25::0], REG#

, CE

NOTE 1

D[15::0]

OE#

(R)

(A) t

(A)

(CE) t

(A)

(CE)

DIS

(OE)

DIS

(CE)

DATA VALID

(CE)

(A) t

(OE)

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

AC CHARACTERISTICS – WRITE TIMING PARAMETERS

VCC = 3.3V or 5V

SYMBOL (PCMCIA) Parameter 200ns 250ns Unit

Min Max Min Max

tCW Write Cycle Time 200 250 ns

tW(WE) Write Pulse Width 120 150 ns

tSU(A) Address Setup Time 20 30 ns

tSU(A-WEH) Address Setup Time for WE# 140 180 ns

tSU(CE-WEH) Card Enable Setup Time for WE# 140 180 ns

tSU(D-WEH) Data Setup Time for WE# 60 80 ns

tH(D) Data Hold Time 30 30 ns

tREC(WE) Write Recover Time 30 30 ns

tDIS(WE) Output Disable Time from WE# 90 100 ns

tDIS(OE) Output Disable Time from OE# 90 100 ns

tEN(WE) Output Enable Time from WE# 5 5 ns

tEN(OE) Output Enable Time from OE# 5 5 ns

tSU(OE-WE) Output Enable Setup from WE# 10 10 ns

tH(OE-WE) Output Enable Hold from WE# 50 50 ns

tSU(CE) Card Enable Setup Time from OE# 0 0 ns

tH(CE) Card Enable Hold Time 20 20 ns

tREC(WEL) Reset recovery to WE# going low 1 1 μs

Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 speciﬁ cations.

WRITE TIMING DIAGRAM

[25::0], REG#

tC(W)

CE1#, CE2#

OE#

D[15::0](DIN)

tW(WE)

tSU(A)

NOTE 1

DATA INPUT

tSU(A-WEH)

tSU(CE) NOTE 1

tREC(WE)

tH(CE)

tSU(OE-WE)

tH(D)

tEN(WE)

D[15::0](DOUT)

WE#

tSU(CE-WEH)

tH(OE-WE)

tDIS(OE)

tDIS(WE)

NOTE 2

tSU(D-WEH)

tEN(OE)

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

DATA WRITE AND ERASE PERFORMANCE (1,3)

Vcc = 5V ± 5%, 0°C to ≤ TA ≤ 70°C

Symbol Parameter Notes Min Typ(1) Max Units Test Conditions

tWHQV1Word/Byte Program time 2,4 6.3 μs Effective time per Byte

(using Write Buffer)

tWHQV3Block Program Time (using Byte program command) 180 μs

Block Program Time (usingwrite to buffer command) 2 0.8 sec Word Program Mode

tWHQV4Block Erase Time 2 0.7 sec

tWHRH Erase Suspend Latency Time to Read 26 35 μs

Notes:

1. Typical: Nominal voltages and TA = 25C.

2. Excludes system overhead.

3. Valid for all speed options.

4. To maximize system performance RDY/BSY# signal should be polled.

WAVEFORMS FOR RESET OPERATION

tW(RST) P2

RDY/BSY#

RST

Valid Output

tREC(RST)

WE#

Read Operation

tWHQV

tREC(WEL)

Write Operation

tWHRH

tWHRL

SYMBOL Parameter Min Max Unit

tW(RST) Reset pulse High time 35 μs

P2 RST Low to reset during Erase/Program/Lock-bit 100 ns

tREC(RST) Reset Low to output delay 500 ns

tREC(WEL) Reset Recovery to WEgoing Low 1 μs

tWHRL WEHigh to RDY/BSY# going low 100 ns

PCMCIA Flash Memory Card

FLF1 Series

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Rev. 5

CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A

Address Value Description

00H 01H CISTPL_DEVICE

02H 03H TPL_LINK

04H 51H FLASH = 250ns (device writable)

06H 7EH CARD SIZE: 32MB

FEH 64MB

08H FFH END OF DEVICE

0AH 1CH CISTPL_DEVICE_OC

0CH 04H TPL_LINK

0EH 02H 3 VOLT OPERATION

10H 51H FLASH = 250ns (device writable)

12H 7EH CARD SIZE:32MB

FEH 64MB

14H FFH END OF DEVICE

16H 18H CISTPL_JEDEC_C

18H 03H TPL_LINK

1AH 89H Manufacturer ID -INTEL

1CH 18H Device ID - 28F0128J3A

1EH FFH END OF DEVICE

20H 17H CISTPL_DEVICE_A

22H 03H TPL_LINK

24H 42H EEPROM - 200ns

26H 01H Device Size = 2KBytes

28H FFH END OF TUPLE

2AH 1DH CISTPL_DEVICE_OA

2CH 03H TPL_LINK

2EH 02H 3 VOLT OPERATION

30H 11H ROM - 250ns

32H FFH END OF DEVICE

34H 1EH CISTPL_DEVICEGEO

36H 07H TPL_LINK

38H 02H DGTPL_BUS

3AH 12H DGTPL_EBS

3CH 01H DGTPL_RBS

3EH 01H DGTPL_WBS

40H 01H DGTPL_PART

42H 01H FLASH DEVICE

NON-INTERLEAVED

44H FFH END OF TUPLE

46H 20H CISTPL_MANFID

48H 05H TPL_LINK(05H)

4AH F6H EDI TPLMID_MANF: LSB

4CH 01H EDI TPLMID_MANF: MSB

4EH 00H LSB: Number Not Assigned

50H 00H MSB: Number Not Assigned

52H FFH END OF TUPLE

54H 1AH CISTPL_CONF

56H 06H TPL_LINK

58H 01H TPCC_SZ

Address Value Description

5AH 00H TPCC_LAST

5CH 00H TPCC_RADR

5EH 40H TPCC_RADR

60H 00H TPCC_RMSK

62H FFH END OF TUPLE

64H 1BH CISTPL_CFTABLE_ENTRY

66H 03H TPL_LINK

68H 00H TPCE_INDEX

6AH 00H TPCE_FS (no selection)

6CH FFH END OF TUPLE

6EH 15H CISTPL_VERS1

70H 7FH TPL_LINK

72H 04H TPLLV1_MAJOR

74H 01H TPLLV1_MINOR

76H 37H 7

78H 50H P

7AH 30H 0

7CH 33H 3

7EH 32H 2

80H 46H F

82H 4CH L

84H 46H F

86H 31H 1

88H 32H 2

8AH 2DH -

8CH 2DH -

8EH 2DH -

90H 32H 2

92H 35H 5

94H 20H SPACE

96H 00H END TEXT

98H 43H C

9AH 4FH O

9CH 50H P

9EH 59H Y

A0H 52H R

A2H 49H I

A4H 47H G

A6H 48H H

A8H 54H T

AAH 20H SPACE

ACH 57H W

AEH 48H H

B0H 49H I

B2H 54H T

B4H 45H E

B6H 20H SPACE

Address Value Description

B8H 45H E

BAH 4CH L

BCH 45H E

BEH 43H C

C0H 54H T

C2H 52H R

C4H 4FH O

C6H 4EH N

C8H 49H I

CAH 43H C

CCH 20H SPACE

CEH 44H D

D0H 45H E

D2H 53H S

D4H 49H I

D6H 47H G

D8H 4EH N

DAH 53H S

DCH 20H SPACE

DEH 43H C

E0H 4FH O

E2H 52H R

E4H 50H P

E6H 4FH O

E8H 52H R

EAH 41H A

ECH 54H T

EEH 49H I

F0H 4FH O

F2H 4EH N

F4H 20H SPACE

F6H 00H END TEXT

F8H 31H 1

FAH 39H 9

FCH 39H 9

FEH 39H 9

100H 00H END TEXT

102H 00H NULL

104H FFH END OF LIST

PCMCIA Flash Memory Card

FLF1 Series

11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

March 2003

Rev. 5

CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A

Address Value Description

00H 01H CISTPL_DEVICE

02H 03H TPL_LINK

04H 51H FLASH = 250ns (device writable)

06H FEH CARD SIZE: 64MB (1st page)

08H FFH END OF DEVICE

0AH 1CH CISTPL_DEVICE_OC

0CH 04H TPL_LINK

0EH 02H 3 VOLT OPERATION

10H 51H FLASH = 250ns (device writable)

12H FEH CARD SIZE:64MB (1st page)

14H FFH END OF DEVICE

16H 09H CISTPL_EXTDEVICE

18H 06H TPL_LINK

1AH 0CH Mem Paging Info:2bit/COR/64MB

1CH 51H Flash = 250 ns

1EH 07H Device Size Extender

20H 01H 1x64MB (for 96MB and 128MB)

02H 2x64MB (for 160MB and 192MB)

22H 7DH +32MB (for 96MB and 160MB)

FEH +64MB (for 128MB and 192 MB)

24H FFH END OF TUPLE

26H 18H CISTPL_JEDEC_C

28H 03H TPL_LINK

2AH 89H Manufacturer ID - INTEL

2CH 18H Device ID - 28F0128J3A

2EH FFH END OF DEVICE

30H 17H CISTPL_DEVICE_A

32H 03H TPL_LINK

34H 42H EEPROM - 200ns

36H 01H Device Size = 2Kbytes

38H FFH END OF TUPLE

3AH 1DH CISTPL_DEVICE_OA

3CH 03H TPL_LINK

3EH 02H 3 VOLT OPERATION

40H 11H ROM - 250ns

42H FFH END OF DEVICE

44H 1EH CISTPL_DEVICEGEO

46H 07H TPL_LINK

48H 02H DGTPL_BUS

4AH 12H DGTPL_EBS

4CH 01H DGTPL_RBS

4EH 01H DGTPL_WBS

50H 01H DGTPL_PART

52H 01H FLASH DEVICE

NON-INTERLEAVED

54H FFH END OF TUPLE

56H 20H CISTPL_MANFID

58H 05H TPL_LINK(05H)

5AH F6H EDI TPLMID_MANF: LSB

Address Value Description

5CH 01H EDI TPLMID_MANF: MSB

5EH 00H LSB: Number Not Assigned

60H 00H MSB: Number Not Assigned

62H FFH END OF TUPLE

64H 1AH CISTPL_CONF

66H 06H TPL_LINK

68H 01H TPCC_SZ

6AH 00H TPCC_LAST

6CH 00H TPCC_RADR

6EH 40H TPCC_RADR

70H 03H TPCC_RMSK

72H FFH END OF TUPLE

74H 15H CISTPL_VERS1

76H 7FH TPL_LINK

78H 04H TPLLV1_MAJOR

7AH 01H TPLLV1_MINOR

7CH 37H 7

7EH 50H P

80H 30H 0

82H 39H 9

84H 36H 6

86H 46H F

88H 4CH L

8AH 46H F

8CH 31H 1

8EH 32H 2

90H 2DH -

92H 2DH -

94H 2DH -

96H 32H 2

98H 35H 5

9AH 20H SPACE

9CH 00H END TEXT

9EH 43H C

A0H 4FH O

A2H 50H P

A4H 59H Y

A6H 52H R

A8H 49H I

AAH 47H G

ACH 48H H

AEH 54H T

B0H 20H SPACE

B2H 57H W

B4H 48H H

B6H 49H I

B8H 54H T

BAH 45H E

BCH 20H SPACE

Address Value Description

BEH 45H E

C0H 4CH L

C2H 45H E

C4H 43H C

C6H 54H T

C8H 52H R

CAH 4FH O

CCH 4EH N

CEH 49H I

D0H 43H C

D2H 20H SPACE

D4H 44H D

D6H 45H E

D8H 53H S

DAH 49H I

DCH 47H G

DEH 4EH N

E0H 53H S

E2H 20H SPACE

E4H 43H C

E6H 4FH O

E8H 52H R

EAH 50H P

ECH 4FH O

EEH 52H R

F0H 41H A

F2H 54H T

F4H 49H I

F6H 4FH O

F8H 4EH N

FAH 20H SPACE

FCH 00H END TEXT

FEH 31H 1

100H 39H 9

102H 39H 9

104H 39H 9

106H 00H END TEXT

108H 00H NULL

10AH FFH END OF LIST

PCMCIA Flash Memory Card

FLF1 Series

12 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

March 2003

Rev. 5

PART NUMBERING

PRODUCT MARKING

Note:

Some products are currently marked with our pre-merger company name/acronym (EDI). During our

transition period, some products will also be marked with our new company name/acronym (WED).

Starting October 2000 all PCMCIA products will be marked only with the WED preﬁ x.

Company Name

Part Number

Lot Code/Trace Number

Date Code

EDI

WED 7P032FLF1200C20 C995 9915

7 P 032 FLF12 00 C 25

CARD TECHNOLOGY

7 FLASH

8 SRAM

PC CARD

P Standard PCMCIA

R Ruggedized PCMCIA

CARD CAPACITY

032 32MB

CARD FAMILY AND VERSION

- See Card Family and Version Info.

for details (next page)

PACKAGING OPTION

00 Standard, type I

TEMPERATURE RANGE

C = Commercial 0°C to +70°C

I = Industrial -40°C to +85°C

CARD ACCESS TIME

20 200ns

25 250ns

PCMCIA Flash Memory Card

FLF1 Series

13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

March 2003

Rev. 5

ORDERING INFORMATION

XXX

016* 16MB

032 32MB

048* 48MB

064 64MB

096 96MB

128 128MB

160 160MB

192 192MB

12 Based on 28F128J3A (*28F640J3)

with Attribute Memory

14 Based on 28F128J3A (*28F640J5)

with Attribute Memory and

Write Protect Switch (optional)

00 WEDC Logo Type I

01 Blank Housing Type I

02 Blank Housing Type I Recessed

C Commercial

I Industrial

20 200ns

25 250ns

7P XXX FLF YY SS T ZZ

PCMCIA Flash Memory Card

FLF1 Series

14 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

March 2003

Rev. 5

Document Title

High Density FLASH Memory Card

16, 32, 48, 64, 80 MEGABYTE

Revision History

Rev # History Release Date Status

Rev 0 Initial release 7-22-99

Rev 1 Added page 16 5-3-01

Rev 2 Corrected Timing Errors, pages 9 and 10 8-1-00

Rev 3 Corrected CIS Errors, page 14

Added Memory Chip Info, page 16

10-17-00

Rev 4 Corrected VIH, VOH, page 8

CIS for 96-192MB, in Adr 12h: 7E->FE

3-18-01

Rev 5 64Mb component, Industrial temp. added 3-18-03