PCMCIA Flash Memory Card FLF1 Series White Electronic Designs High Density FLASH Memory Card 16, 32, 48, 64, 80 MEGABYTE information to be stored in a single cell. This leads to reduced die size and reduced cost per megabyte. FEATURES Low cost, high density Linear Flash Card Universal 3V to 5V operating range providing full "plug and play" exchangeability between different systems Based on Intel 28F128J3A (MLC) and *28F640J3 (MLC) Components Fast Read Performance WEDC's FLF1 series cards are built with Intel's 128Mb memory components, 28F128J3A, with a manufacturer/ device ID of 89/18H. The FLF1 series is available in densities of 32, 64, 96, 128, 160, and 192MB. There are also 16MB and 48MB cards available built with Intel's 64Mb memory components 28F640J3 with 89/17H manufacturer/device ID. The cards up to the 64MB density operate in the regular PCMCIA mode. The densities beyond the 64MB density are implemented using a "paging scheme", which is also supported by the PCMCIA standard. By writing a page address to the Configuration Option Register (address 4000H), an additional page of memory can be accessed. The current FLF1 series supports densities up to 192MB: total of 3 pages: page 0 := 64MB, page 1 := 64MB, and page 2 := 64MB. * 250ns Maximum Access Time * (200ns optional) PCMCIA compatible * x8/ x16 Data Interface 32-Byte Write Buffer (per Memory Device) * 6s per Byte Effective Write Time 128-bit Protection Register (per Memory Device) The FLF1 series card operates in a wide, universal voltage range, from 3V to 5V, allowing full "plug and play" functionality and upgrade solutions in all mobile, battery powered applications. * 64-bit Unique Device Identifier * 64-bit User Programmable OTP Cells Cross-Compatible Command Support * Common Flash Interface (CFI) Each memory component in the card also has a 128bit Protection Register, containing 64 bits of User Programmable OTP (One Time Programmable) Cells. These cells can be programmed with a numeric security measure, such as an electronic signature. * Intel Basic Command Set * Scaleable Command Set Power-Down Mode * Reset, Power Down Registers 100,000 Erase Cycles per Block 128K word symmetrical Block Architecture PC Card Standard Type I Form Factor To provide a 16 bit word wide access supported by the PCMCIA standard, devices are paired on the card. Therefore, the Flash array is structured in 128K word (256kB) blocks. Write, read and block erase operations can be performed as either a word or byte wide operation. The FLF1 series cards conform to the PC Card 95 Standard supported by PCMCIA and JEIDA, providing electrical and physical compatibility. The PC Card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. GENERAL DESCRIPTION WEDC's Flash memory cards -- FLF1 Series -- offer high density linear Flash memory for code and data storage, high performance disk emulation, mobile PC and embedded applications. WEDC's standard cards are shipped with WEDC's Flash Logo. Cards are also available with blank housings (no Logo). The blank housings are available in both, a recessed (for label) or flat housing. Please contact your WEDC sales representative for further information on Custom artwork. The WEDC's FLF1 series is based on Intel's Multi Level Cell (MLC) Flash memory technology, providing high density Flash components at a significantly lower cost per megabyte. MLC technology allows for two bits of March 2003 Rev. 5 1 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs BLOCK DIAGRAM N x 28F128J3A Device Pair (N/2 - 1) CLn Device (N-1) CH0 Device (N-2) (B26) + ADDRESS BUS (A1-A25) (A1-A25) A1-A23 ADDRESS BUFFER A1-A25 A24, A25, B26 B26, (B27..) D5-D0=Page Number (PN) SRes D7 Ai WRi RDi M Res CH0 CLn Device 3 CH0 Device 2 CL1 D5 Q2 Q0 Ctrl control logic CL0 Device 1 D2 D1 D0 SR Clr Reg Clr REG# At/Reg enable Management 4000h Device 0 DATA BUS Q8-Q15 D3 CE2# CE1# Device Pair 0 CH0 D4 WE# OE# Qn CL0 D6 Configuration Option Register: A=4000h (Read/Write) CHn Device Pair 1 - Page Number (PN) - LvReq Registers 0000h DATA BUS Q0-Q7 ADDRESS Register NAME 4008h 4006h 4004h 4002h Config. and Status Reg. 4000h Configuration Option Register attrib. mem CIS EPROM 2kB control Q0-Q7 A0 I/O buffer DATA BUS D0-D7 DATA BUS D8-D15 Reset 220k M Res SR Clr Reg Clr reset circuit C R Vcc D0 - D15 Configuration Option Register: ADRS=4000h Read/Write CD1 CD2 SRes (3V-5V) Vcc D7 Vcc D7 GND WAIT OPEN R/B(N-1) R/BUSY VS1 VS2 R/B1 R/B0 OPEN OPEN Vpp2 Vpp1 - Page Number (PN) D2 D6 LevelReq (not supported) D5-D0 Configuration index D5-D1 reserved D0 Page Number Config. (PN) D1 D0 Power On default =0 Configuration Status Register: ADRS=4002h Read/Write reserved PwrDwn reserved D7 D6 D5 D4 D3 D2 D1 D0 10k BVD1 BVD2 LvReq D6 D5 D4 D3 Soft Reset, active High 1=Reset State 0=End Reset State Vcc N.C. N.C. D2 CE1#, CE2#, OE#, WE#, Reg#: pull up typ 100k A0: pull down typ 100k Reset: pull down typ 220k R/Busy - Open Drain output pull up typ 100k Power Down; active High 1 = Place all memory devices in power down mode 0 = normal operation Power On default=0 Intel 89H Device ID Manufacturer ID 28F128J3A 18H Device ID 28F640J3A 18H FLF1 Flash Card based on Strata Flash 28F128J3A and 28F640J3 March 2003 Rev. 5 2 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs PINOUT Pin Signal name 1 GND 2 DQ3 3 DQ4 4 5 I/O Function Active Pin Signal name Ground 35 GND I/O Data bit 3 36 CD1# O Card Detect 1 I/O Data bit 4 37 DQ11 I/O Data bit 11 DQ5 I/O Data bit 5 38 DQ12 I/O Data bit 12 DQ6 I/O Data bit 6 39 DQ13 I/O Data bit 13 6 DQ7 I/O Data bit 7 40 DQ14 I/O Data bit 14 7 CE1# I Card enable 1 41 DQ15 I Data bit 15 8 A10 I Address bit 10 42 CE2# I Card Enable 2 LOW 9 OE# I Output enable 43 VS1 O Voltage Sense 1 NC (2) 10 A11 I Address bit 11 44 RFU 11 A9 I Address bit 9 45 RFU 12 A8 I Address bit 8 46 A17 I Address bit 17 13 A13 I Address bit 13 47 A18 I Address bit 18 14 A14 I Address bit 14 48 A19 I Address bit 19 15 WE# I Write Enable LOW 49 A20 I Address bit 20 16 RDY/BSY# O Ready/Busy LOW (1) 50 A21 I 17 VCC 51 VCC 18 VPP1 52 VPP2 19 A16 I Address bit 16 53 A22 I Address bit 22 20 A15 I Address bit 15 54 A23 I Address bit 23 21 A12 I Address bit 12 55 A24 I Address bit 24 22 A7 I Address bit 7 56 A25 I Address bit 25 23 A6 I Address bit 6 57 VS2 O Voltage Sense 2 NC 24 A5 I Address bit 5 58 RST I Card Reset HIGH 25 A4 I Address bit 4 59 Wait# O Extended Bus cycle LOW(3) 26 A3 I Address bit 3 60 RFU 27 A2 I Address bit 2 61 REG# I Attrib Mem Select 28 A1 I Address bit 1 62 BVD2 O Bat. Volt. Detect 2 (2) 29 A0 I Address bit 0 63 BVD1 O Bat. Volt. Detect 1 (3) 30 DQ0 I/O Data bit 0 64 DQ8 I/O Data bit 8 31 DQ1 I/O Data bit 1 65 DQ9 I/O Data bit 9 32 DQ2 I/O Data bit 2 66 DQ10 O Data bit 10 33 WP O Write Potect 67 CD2# O Card Detect 2 34 GND 68 GND LOW LOW Supply Voltage Prog. Voltage N.C. HIGH Ground Notes: 1. RDY/BSY# signal is an "Open drain" type output, pull-up resistors are required on the host side. 2. VS1 is connected to GND. 3. Wait#, BVD1 and BVD2 are internally connected to VCC by resistors for compatibility. I/O Function Active Ground LOW Reserved Reserved Address bit 21 Supply Voltage Prog. Voltage NC Reserved LOW Ground MECHANICAL 1.6mm 0.063" 0.05 85.6mm 0.20 3.370" 1.0mm 0.05 0.039' 3.0mm MIN. Substrate area 54.0mm 2.126" 0.10 Pin #35 1.0mm 0.05 0.039' Pin #1 10.0mm MIN. 0.400" Interconnect area 3.3mm 0.130" March 2003 Rev. 5 3 0.05" 5.0mm MAX. 0.197" White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs Card Signal Description Symbol A0 - A25 Type INPUT Name and Function DQ0 - DQ15 INPUT/OUTPUT CE1#, CE2# INPUT CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7 (see truth table). OE# INPUT OUTPUT ENABLE: Active low signal gating read data from the memory card. WE# INPUT WRITE ENABLE: Active low signal gating write data to the memory card. RDY/BSY# OUTPUT READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy with internally timed erase or write activities. CD1#, CD2# OUTPUT CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the card. The host shall monitor these signals to detect card insertion (pulled-up on host side). WP OUTPUT WRITE PROTECT: Write protect reflects the status of the Write Protect switch on the memory card. WP set to high = write protected, providing internal hardware write lockout to the Flash array. If card dOE#s not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". VPP1, VPP2 N.C. ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not used in word access mode. A25 is the most significant bit DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB. PROGRAMMING VOLTAGES: Not connected for 5V only card. VCC CARD POWER SUPPLY: 5.0V for all internal circuitry GND CARD GROUND REG# INPUT ATTRIBUTE MEMORY SELECT : Active low signal, enables access to attribute memory space, occupied by the Card Information Structure (CIS) and Card Registers. RST INPUT RESET: Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down control for the memory array. WAIT# OUTPUT BVD1, BVD2 OUTPUT BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility. VS1, VS2 OUTPUT VOLTAGE SENSE: Notifies the host socket of the card's VCC requirements. VS1 and VS2 are RESERVED FOR FUTURE USE WAIT: This signal is pulled high internally for compatibility. No wait states are generated. RFU NC NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating Functional Truth Table READ function Function Mode Common Memory Attribute Memory CE2# CE1# A0 OE# WE# REG# D15-D8 D7-D0 REG# D15-D8 D7-D0 H H H L L H L L L H X L H X X X L L L L X H H H H X H H H H High-Z High-Z High-Z Odd-Byte Odd-Byte High-Z Even-Byte Odd-Byte Even-Byte High-Z X L L L L High-Z High-Z High-Z Not Valid Not Valid High-Z Even-Byte Not Valid Even-Byte High-Z Word Access (16 bits) H H H L H L L L X L H X X H H H X L L L X H H H X X X Odd-Byte X Even-Byte Odd-Byte Even-Byte X L L L X X X X X Even-Byte X Even-Byte Odd-Byte Only Access L H X H L H Odd-Byte X L X X Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte Only Access WRITE function Standby Mode Byte Access (8 bits) March 2003 Rev. 5 4 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs CARD INTERFACE The FLF0 series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining PCMCIA compatibility, the FLF0 series card has integrated special features to extend functionality. Only bit D0 is supported: * D1D0 set to 00bin (0H) selects: page 0 * D1D0 set to 01bin (1H) selects: page 1 * D1D0 set to 10bin (2H) selects: page 2 Card has built in 2 control registers: * D1D0 set to 11bin (3H) selects: page 3 (No Memory Access) * Configuration Option Register (COR) Address = 4000h D1D0 is set to the value of 00bin (0H) during any reset cycle (Power on Reset, Hardware Reset, and SReset). Attempting to access page 3 will not result in the writing or reading of data. * Configuration and Status Register (CSR) Address = 4002h COR register: provide a soft reset function (bit D7) and additional page register (bit D0) to extend card capacity beyond 64MB. CSR register: provide a power control of memory array. Only bit D2 is supported; all other bits are "don't care" SReset PwrDwn As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state all memory devices are place in power down mode, minimizing power consumption. Returning this bit to 0 leaves the reset cycle and place the card in the same condition as following a power up or hardware reset. This bit must be cleared to 0, to access any device on the card. Card Information Structure (CIS) contains information about Registers addressing and Memory structure. Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit: Cards with memory capacity < 64MB do not support Configuration Index bits. Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode. 1. Initialization: write 1 to SReset Notes: 1. Reading from undefined address location or unsupported bits will return random data. 2. Writing to undefined address location may result in card malfunctioning due to limited address decoding. 3. See block diagram for more details about control registers. * reset cycle begin * memory devices enters Power-Down mode aborting all operations and clearing all registers. 2. Write 0 to SReset Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. * Reset cycle ends * memory devices and registers enters power on default state The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device. Card can be place in Power Down mode by activating Reset signal (pin58) or by controlling the bit D2 in CSR register. LevlRequest The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device. Standard microprocessor write timings are used. Not supported Configuration Index Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend card capacity beyond 64MB. March 2003 Rev. 5 For information regarding modes of operation, commands, and programming details for the memory components, please consult the Intel 28F128J3A (28F640J3) data sheet. 5 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs ABSOLUTE MAXIMUM RATINGS (2) Operating Temperature TA (ambient) Commercial Industrial Storage Temperature Voltage on any pin relative to VSS VCC supply Voltage relative to VSS Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 0C to +60C -40C to +85C -65C to +125C -0.5V to VCC+0.5V -0.5V to +7.0V RECOMMENDED SUPPLY VOLTAGE VCC 3.3V 5.0V Tolerance 0.3V 0.5V Note: The FLF1 Series Card will function at either 3.3V or 5.0V DC CHARACTERISTICS (1) Symbol ICCR ICCW ICCE ICCD Parameter VCC Read Current VCC Program Current VCC Erase Current VPP Power-down Current ICCS (CMOS) VCC Standby Current Density (Mbytes) 32,64, 96, 128, 160, 192 32,64, 96, 128, 160, 192 32,64, 96, 128, 160, 192 32 64 96 128 160 192 32 64 96 128 160 192 Notes Typ(3) 70 70 70 100 200 300 400 500 600 0.1 0.2 0.3 0.4 0.5 0.6 2 2 Max 110 120 140 200 400 600 800 1000 1200 0.2 0.4 0.6 0.8 1.0 1.2 Units mA mA mA A mA Test Conditions VCC = VCC max tcycle = 200ns 2 memory devices 2 memory devices VCC = VCC max Control Signals = VCC Reset = VCC (active) VCC = VCC max Control Signals = VCC Reset = 0V (not active) CMOS Test Conditions: VCC = 5V 5%, VIL = VSS 0.2V, VIH = VCC 0.2V Notes: 1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Word wide operations (2 memory devices activated). 2. Control Signals: CE1#, CE2#, OE#, WE#. 3. Typical: VCC = 5V or VCC = 3V, T = +25C. VCC = 3.3V or 5V Symbol ILI ILO VIL VIH VOL VOH VLKO Parameter Input Leakage Current Notes 1, 2 Output Leakage Current 1 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC Erase/Program Lock Voltage 1 1 1 1 1 Min 0 2.0V Max 20 Units A 20 A 0.8 VCC+0.5 0.4 V V V V V 2.4V 2.0 Test Conditions VCC = VCCMAX VIN =VCC or GND VCC = VCCMAX VIN =VCC or GND IOL = 3.2mA IOH = -2.0mA Notes: 1. Values are the same for byte and word wide modes for all card densities. 2. Exception: Leakage current on control signals with internal pull up resistors (see block diag) will be <500 A when VIN = GND. March 2003 Rev. 5 6 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs AC CHARACTERISTICS - READ TIMING PARAMETERS VCC = 3.3V or 5V SYMBOL (PCMCIA) tC(R) tA(A) tA(CE) tA(OE#) tSU(A) tSU(CE) tH(A) tH(CE) tV(A) tDIS(CE) tDIS(OE#) tEN(CE) tEN(OE#) tREC(RST) 200ns Parameter Min 200 Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Address Setup Time Card Enable Setup Time Address Hold Time Card Enable Hold Time Output Hold from Address Change Output Disable Time from CE Output Disable Time from OE# Output Enable Time from CE Output Enable Time from OE# Power Down recovery to Output Delay. VCC = 5V 250ns Max Min 250 200 200 90 20 0 20 20 0 90 90 5 5 Unit Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns 250 250 100 30 0 20 20 0 100 100 5 5 500 500 Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. READ TIMING DIAGRAM tC(R) tA(A) tH(A) A[25::0], REG# tV(A) tA(CE) tSU(CE) CE1#, CE2# NOTE 1 NOTE 1 tSU(A) tA(OE) tH(CE) tDIS(CE) OE# tDIS(OE) tEN(OE) D[15::0] March 2003 Rev. 5 DATA VALID 7 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs AC CHARACTERISTICS - WRITE TIMING PARAMETERS VCC = 3.3V or 5V SYMBOL (PCMCIA) tCW tW(WE) tSU(A) tSU(A-WEH) tSU(CE-WEH) tSU(D-WEH) tH(D) tREC(WE) tDIS(WE) tDIS(OE) tEN(WE) tEN(OE) tSU(OE-WE) tH(OE-WE) tSU(CE) tH(CE) tREC(WEL) 200ns Parameter Min 200 120 20 140 140 60 30 30 Write Cycle Time Write Pulse Width Address Setup Time Address Setup Time for WE# Card Enable Setup Time for WE# Data Setup Time for WE# Data Hold Time Write Recover Time Output Disable Time from WE# Output Disable Time from OE# Output Enable Time from WE# Output Enable Time from OE# Output Enable Setup from WE# Output Enable Hold from WE# Card Enable Setup Time from OE# Card Enable Hold Time Reset recovery to WE# going low 250ns Max Min 250 150 30 180 180 80 30 30 Max 90 90 100 100 5 5 10 50 0 20 1 5 5 10 50 0 20 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. WRITE TIMING DIAGRAM tC(W) A[25::0], REG# tSU(A-WEH) CE1#, CE2# tREC(WE) tH(CE) tSU(CE-WEH) tSU(CE) NOTE 1 NOTE 1 OE# tH(OE-WE) tSU(A) tW(WE) WE# tH(D) tSU(OE-WE) D[15::0](DIN) tSU(D-WEH) NOTE 2 DATA INPUT tDIS(WE) tEN(OE) tDIS(OE) tEN(WE) D[15::0](DOUT) March 2003 Rev. 5 NOTE 2 8 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs DATA WRITE AND ERASE PERFORMANCE (1,3) Vcc = 5V 5%, 0C to TA 70C Symbol Parameter Notes tWHQV1 Word/Byte Program time tWHQV3 Block Program Time (using Byte program command) Min 2,4 Typ(1) Max Units 6.3 180 s Block Program Time (usingwrite to buffer command) 2 0.8 sec tWHQV4 Block Erase Time 2 0.7 sec tWHRH Erase Suspend Latency Time to Read 26 Test Conditions s 35 Effective time per Byte (using Write Buffer) Word Program Mode s Notes: 1. Typical: Nominal voltages and TA = 25C. 2. Excludes system overhead. 3. Valid for all speed options. 4. To maximize system performance RDY/BSY# signal should be polled. WAVEFORMS FOR RESET OPERATION Write Operation Read Operation WE# Valid Output tREC(RST) tWHQV tWHRH tREC(WEL) RST tWHRL tW(RST) P2 RDY/BSY# SYMBOL tW(RST) P2 tREC(RST) tREC(WEL) tWHRL March 2003 Rev. 5 Parameter Reset pulse High time RST Low to reset during Erase/Program/Lock-bit Reset Low to output delay Reset Recovery to WEgoing Low WEHigh to RDY/BSY# going low Min 35 Max 100 500 1 100 9 Unit s ns ns s ns White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A Address 00H 02H 04H 06H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H Value 01H 03H 51H 7EH FEH FFH 1CH 04H 02H 51H 7EH FEH FFH 18H 03H 89H 18H FFH 17H 03H 42H 01H FFH 1DH 03H 02H 11H FFH 1EH 07H 02H 12H 01H 01H 01H 01H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H FFH 20H 05H F6H 01H 00H 00H FFH 1AH 06H 01H 08H 0AH 0CH 0EH 10H 12H March 2003 Rev. 5 Description CISTPL_DEVICE TPL_LINK FLASH = 250ns (device writable) CARD SIZE: 32MB 64MB END OF DEVICE CISTPL_DEVICE_OC TPL_LINK 3 VOLT OPERATION FLASH = 250ns (device writable) CARD SIZE:32MB 64MB END OF DEVICE CISTPL_JEDEC_C TPL_LINK Manufacturer ID -INTEL Device ID - 28F0128J3A END OF DEVICE CISTPL_DEVICE_A TPL_LINK EEPROM - 200ns Device Size = 2KBytes END OF TUPLE CISTPL_DEVICE_OA TPL_LINK 3 VOLT OPERATION ROM - 250ns END OF DEVICE CISTPL_DEVICEGEO TPL_LINK DGTPL_BUS DGTPL_EBS DGTPL_RBS DGTPL_WBS DGTPL_PART FLASH DEVICE NON-INTERLEAVED END OF TUPLE CISTPL_MANFID TPL_LINK(05H) EDI TPLMID_MANF: LSB EDI TPLMID_MANF: MSB LSB: Number Not Assigned MSB: Number Not Assigned END OF TUPLE CISTPL_CONF TPL_LINK TPCC_SZ Address 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H Value 00H 00H 40H 00H FFH 1BH 03H 00H 00H FFH 15H 7FH 04H 01H 37H 50H 30H 33H 32H 46H 4CH 46H 31H 32H 2DH 2DH 2DH 32H 35H 20H 00H 43H 4FH 50H 59H 52H 49H 47H 48H 54H 20H 57H 48H 49H 54H 45H 20H Description TPCC_LAST TPCC_RADR TPCC_RADR TPCC_RMSK END OF TUPLE CISTPL_CFTABLE_ENTRY TPL_LINK TPCE_INDEX TPCE_FS (no selection) END OF TUPLE CISTPL_VERS1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR 7 P 0 3 2 F L F 1 2 2 5 SPACE END TEXT C O P Y R I G H T SPACE W H I T E SPACE 10 Address B8H BAH BCH BEH C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH 100H 102H 104H Value 45H 4CH 45H 43H 54H 52H 4FH 4EH 49H 43H 20H 44H 45H 53H 49H 47H 4EH 53H 20H 43H 4FH 52H 50H 4FH 52H 41H 54H 49H 4FH 4EH 20H 00H 31H 39H 39H 39H 00H 00H FFH Description E L E C T R O N I C SPACE D E S I G N S SPACE C O R P O R A T I O N SPACE END TEXT 1 9 9 9 END TEXT NULL END OF LIST White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A Address 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H Value 01H 03H 51H FEH FFH 1CH 04H 02H 51H FEH FFH 09H 06H 0CH 51H 07H 01H 02H 7DH FEH FFH 18H 03H 89H 18H FFH 17H 03H 42H 01H FFH 1DH 03H 02H 11H FFH 1EH 07H 02H 12H 01H 01H 01H 01H 54H 56H 58H 5AH FFH 20H 05H F6H 22H March 2003 Rev. 5 Description CISTPL_DEVICE TPL_LINK FLASH = 250ns (device writable) CARD SIZE: 64MB (1st page) END OF DEVICE CISTPL_DEVICE_OC TPL_LINK 3 VOLT OPERATION FLASH = 250ns (device writable) CARD SIZE:64MB (1st page) END OF DEVICE CISTPL_EXTDEVICE TPL_LINK Mem Paging Info:2bit/COR/64MB Flash = 250 ns Device Size Extender 1x64MB (for 96MB and 128MB) 2x64MB (for 160MB and 192MB) +32MB (for 96MB and 160MB) +64MB (for 128MB and 192 MB) END OF TUPLE CISTPL_JEDEC_C TPL_LINK Manufacturer ID - INTEL Device ID - 28F0128J3A END OF DEVICE CISTPL_DEVICE_A TPL_LINK EEPROM - 200ns Device Size = 2Kbytes END OF TUPLE CISTPL_DEVICE_OA TPL_LINK 3 VOLT OPERATION ROM - 250ns END OF DEVICE CISTPL_DEVICEGEO TPL_LINK DGTPL_BUS DGTPL_EBS DGTPL_RBS DGTPL_WBS DGTPL_PART FLASH DEVICE NON-INTERLEAVED END OF TUPLE CISTPL_MANFID TPL_LINK(05H) EDI TPLMID_MANF: LSB Address 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH Value 01H 00H 00H FFH 1AH 06H 01H 00H 00H 40H 03H FFH 15H 7FH 04H 01H 37H 50H 30H 39H 36H 46H 4CH 46H 31H 32H 2DH 2DH 2DH 32H 35H 20H 00H 43H 4FH 50H 59H 52H 49H 47H 48H 54H 20H 57H 48H 49H 54H 45H 20H Description EDI TPLMID_MANF: MSB LSB: Number Not Assigned MSB: Number Not Assigned END OF TUPLE CISTPL_CONF TPL_LINK TPCC_SZ TPCC_LAST TPCC_RADR TPCC_RADR TPCC_RMSK END OF TUPLE CISTPL_VERS1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR 7 P 0 9 6 F L F 1 2 2 5 SPACE END TEXT C O P Y R I G H T SPACE W H I T E SPACE 11 Address BEH C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH 100H 102H 104H 106H 108H 10AH Value 45H 4CH 45H 43H 54H 52H 4FH 4EH 49H 43H 20H 44H 45H 53H 49H 47H 4EH 53H 20H 43H 4FH 52H 50H 4FH 52H 41H 54H 49H 4FH 4EH 20H 00H 31H 39H 39H 39H 00H 00H FFH Description E L E C T R O N I C SPACE D E S I G N S SPACE C O R P O R A T I O N SPACE END TEXT 1 9 9 9 END TEXT NULL END OF LIST White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs PRODUCT MARKING EDI WED 7P032FLF1200C20 C995 9915 Company Name Part Number Lot Code/Trace Number Date Code Note: Some products are currently marked with our pre-merger company name/acronym (EDI). During our transition period, some products will also be marked with our new company name/acronym (WED). Starting October 2000 all PCMCIA products will be marked only with the WED prefix. PART NUMBERING 7 P 032 FLF12 00 C 25 CARD TECHNOLOGY 7 FLASH 8 SRAM PC CARD P Standard PCMCIA R Ruggedized PCMCIA CARD CAPACITY 032 32MB CARD FAMILY AND VERSION - See Card Family and Version Info. for details (next page) PACKAGING OPTION 00 Standard, type I TEMPERATURE RANGE C = Commercial 0C to +70C I = Industrial -40C to +85C CARD ACCESS TIME 20 200ns 25 250ns March 2003 Rev. 5 12 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs ORDERING INFORMATION 7P XXX FLF YY SS T ZZ XXX 016* 032 048* 064 096 128 160 192 16MB 32MB 48MB 64MB 96MB 128MB 160MB 192MB YY 12 Based on 28F128J3A (*28F640J3) with Attribute Memory 14 Based on 28F128J3A (*28F640J5) with Attribute Memory and Write Protect Switch (optional) 00 01 02 WEDC Logo Type I Blank Housing Type I Blank Housing Type I Recessed SS T C Commercial I Industrial ZZ 20 25 March 2003 Rev. 5 200ns 250ns 13 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com PCMCIA Flash Memory Card FLF1 Series White Electronic Designs Document Title High Density FLASH Memory Card 16, 32, 48, 64, 80 MEGABYTE Revision History Rev # History Release Date Rev 0 Initial release 7-22-99 Rev 1 Added page 16 5-3-01 Rev 2 Corrected Timing Errors, pages 9 and 10 8-1-00 Rev 3 Corrected CIS Errors, page 14 10-17-00 Status Added Memory Chip Info, page 16 Rev 4 Corrected VIH, VOH, page 8 3-18-01 CIS for 96-192MB, in Adr 12h: 7E->FE Rev 5 March 2003 Rev. 5 64Mb component, Industrial temp. added 3-18-03 14 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com