256 Kb (256K x 1) Static RAM
CY7C197BN
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06447 Rev. ** Revised March 21, 2007
Features
• Fast access time: 12 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed and power
• TTL compatible inputs and outputs
• Available in 24-lead DIP and 24-lead SOJ
General Description [1]
The CY7C197BN is a high performance CMOS Asynchronous
SRAM organized as 256K × 1 bits that supports an
asynchronous memory interface. The device features an
automatic power down feature that significantly reduces power
consumption when deselected.
See the “Truth Table” on page 7 for a complete description of
Read and Write modes.
The CY7C197BN is available in 24-lead DIP and 24-lead SOJ
package(s).
Notes
1. For best practice recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Logic Block Diagram
Row Decoder
Column
Decoder
Input
Buffer
Sense Amps
Ax
x
Dout
WE
CE
Din
Power
Down
Circuit
RAM Array
Product Portfolio
-12 -15 -25 Unit
Maximum Access Time 12 15 25 ns
Maximum Operating Current 150 150 95 mA
Maximum CMOS Standby Current 10 10 10 mA
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CY7C197BN
Document #: 001-06447 Rev. ** Page 2 of 9
Pin Layout and Specification
Pin Description
Pin Type Description DIP SOJ
AXInput Address Inputs 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17,
18, 19, 20, 21, 22, 23
1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17,
18, 19, 20, 21, 22, 23
CE Control Chip Enable 13 13
Din Input Data Input Pins 14 14
Dout Output Data Output Pins 10 10
VCC Supply Power (5.0V) 24 24
WE Control Write Enable 11 11
A0
A1
A2
A3
A4
A5
A6
A7
A8
Dout
WE
GND CE
Din
A9
A10
A11
A12
A13
A14
A15
A16
A17
VCC 1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
24-lead DIP (6.6 × 31.8 × 3.5 mm)
A0
A1
A2
A3
A4
A5
A6
A7
A8
Dout
WE
GND CE
Din
A9
A10
A11
A12
A13
A14
A15
A16
A17
VCC 1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
24-lead SOJ (8 × 15 × 3.5 mm)
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CY7C197BN
Document #: 001-06447 Rev. ** Page 3 of 9
Maximum Ratings
Exceeding the maximum rating may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[2] .....................................–0.5V to VCC +0.5V
DC Input Voltage[2]..................................–0.5V to VCC +0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature[3] VCC
Commercial 0°C to 70°C 5.0V ± 10%
DC Electrical Characteristics[2]
Parameter Description Condition 12 and 15 ns 25 ns Unit
Min Max Min Max
VIH Input HIGH Voltage 2.2 VCC+0.3 2.2 VCC+0.3 V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V
VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 – 2.4 – V
VOL Output LOW Voltage VCC = Min, lol = 8.0 mA – 0.4 – 0.4 V
IOZ Output Leakage Current GND ≤ Vi ≤ VCC, Output
Disabled
–5 +5 –5 +5 µA
IIX Input Leakage Current GND ≤ Vi ≤ VCC –5 +5 –5 +5 µA
ICC VCC Operating Supply
Current
VCC = Max, IOUT = 0 mA,
f = FMAX = 1/tRC
–150– 95mA
ISB1 Automatic CE Power
Down Current TTL Inputs
VCC = Max,
CE ≥ VIH, VIN ≥ VIH or
VIN ≤ VIL, f = FMAX
–30–30mA
ISB2 Automatic CE Power
Down Current CMOS
Inputs
VCC = Max,
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V or
VIN < 0.3V, f = 0
–10–10mA
Capacitance[4]
Parameter Description Conditions Max (ALL – PACKAGES) Unit
CIN Input Capacitance TA = 25C, f = 1 MHz,
VCC = 5.0V
8pF
COUT Output Capacitance 10
Thermal Resistance[4]
Parameter Description Conditions 24 DIP 24 SOJ Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5
square inches, two-layer
printed circuit board
75.69 84.15 °C/W
ΘJC Thermal Resistance
(Junction to Case)
33.80 37.56
Notes
2. VIL(min) = –2.0V for pulse durations of less than 20 ns.
3. TA is the “instant on” case temperature
4. Tested initially and after any design or process change that may affect these parameters
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CY7C197BN
Document #: 001-06447 Rev. ** Page 4 of 9
AC Test Loads[5]
Note
5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
V
CC
VSS
Rise Time
1 V/ns
Fall Time
1 V/ns
All Input Pulses
90%
10%
90%
10%
V
Output
R1
R2C1
CC V
Output
R3
C2
CC
R4
Output Loads Output Loads
tHZCE & t
HZWE
* including scope and jig capacitance
(B)*
(A)*
RTH
TH
V
Thevenin Equivalent
for
AC Test Conditions
Parameter Description Nom. Unit
C1 Capacitor 1 30 pF
C2 Capacitor 2 5
R1 Resistor 1 480 Ω
R2 Resistor 2 255
R3 Resistor 3 480
R4 Resistor 4 255
RTH Resistor Thevenin 167
VTH Voltage Thevenin 1.73 V
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Document #: 001-06447 Rev. ** Page 5 of 9
AC Electrical Characteristics[4, 6, 7, 8]
Parameter Description 12 ns 15 ns 25 ns Unit
MinMaxMinMaxMinMax
tRC Read Cycle Time 12 – 15 – 25 – ns
tAA Address to Data Valid –12–15–25ns
tOHA Data Hold from Address Change 3 – 3 – 3 – ns
tACE CE to Data Valid –12–15–25ns
tLZCE CE to Low Z 3 – 3 – 3 – ns
tHZCE CE to High Z – 5 – 5 – 11 ns
tPU CE to Power-up 0 – 0 – 0 – ns
tPD CE to Power-down –12–15–20ns
tWC Write Cycle Time 12 – 15 – 25 – ns
tSCE CE to Write End 9 – 9 – 20 – ns
tAW Address Set-up to Write End 9 – 10 – 20 – ns
tHA Address Hold from Write End 0 – 0 – 0 – ns
tSA Address Set-up to Write Start 0 – 0 – 0 – ns
tPWE WE Pulse Width 8 – 9 – 20 – ns
tSD Data Set-Up to Write End 8 – 9 – 15 – ns
tHD Data Hold from Write End 0 – 0 – 0 – ns
tHZWE WE LOW to High Z – 7 – 7 – 11 ns
tLZWE WE HIGH to Low Z 2 – 2 – 3 – ns
Notes
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device.
7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. tHZCE, tHZWE are specified as in part (b) of the “AC Test Loads[5]” on page 4. Transitions are measured ±200 mV from steady state voltage.
9. Device is continuously selected. CE = VIL.
10. WE is HIGH for Read Cycle.
Timing Waveforms
Read Cycle No. 1[9, 10]
Address
Data Out Previous Data Valid Data Valid
tRC
tAA
tOHA
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CY7C197BN
Document #: 001-06447 Rev. ** Page 6 of 9
Read Cycle No. 2[4, 11, 12]
Write Cycle No. 1 (WE Controlled)[4, 13]
Notes
11. WE is HIGH in read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. The minimum write cycle time is the sum of tHZWE and tSD.
Timing Waveforms (continued)
Address
CE
Data Out Data Valid
tRC
High Z
tACE tHZCE
ICC
ISB
tPU
50% 50%
tPD
High Z
Vcc Supply Current
tLZCE
Address
Data In
tWC
Data
Valid
tSCE
tSA
tAW
tPWE
tHA
tHD
tSD
Data Out Data
Undefined
High Impedance
tHZWE tLZWE
CE
WE
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CY7C197BN
Document #: 001-06447 Rev. ** Page 7 of 9
Write Cycle No. 2 (CE Controlled)[14, 15]
Timing Waveforms (continued)
Address
CE
WE
Data In
tWC
Data Valid
tSCE
tSA
tAW
tPWE
tHA
tHD
tSD
Data Out High Z
Notes
14. This cycle is CE controlled.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Truth Table
CE WE I/Ox Mode Power
H X High Z Deselect/Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L Data In Write Active (ICC)
Ordering Information
Speed (ns) Ordering Code Package
Diagram Package Type Operating
Range
12 CY7C197BN-12VC 51-85030 24-lead SOJ (8 x 15 x 3.5 mm) Commercial
15 CY7C197BN-15VC 51-85030 24-lead SOJ (8 x 15 x 3.5 mm) Commercial
25 CY7C197BN-25PC 51-85013 24-lead DIP (6.6 x 31.8 x 3.5 mm) Commercial
Please contact local sales representative regarding availability of these parts.
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CY7C197BN
Document #: 001-06447 Rev. ** Page 8 of 9
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
Figure 1. 24-lead (300-mil) SOJ (51-85030)
Figure 2. 24-lead DIP (6.6 x 31.8 x 3.5 mm) (51-85013)
DIMENSIONS IN INCHES[MM] MIN.
MAX.
PIN 1 ID
0.291[7.39]
0.300[7.62]
0.050[1.27]
TYP.
0.007[0.17]
0.013[0.33]
0.013[0.33]
0.019[0.48]
0.330[8.38]
0.350[8.89]
0.120[3.05]
0.140[3.55]
0.025[0.63] MIN.
0.262[6.65]
0.272[6.91]
0.597[15.16]
0.613[15.57]
112
13 24
SEATING PLANE
0.004[0.10]
REFERENCE JEDEC MO-088
PART #
V24.3 STANDARD PKG.
VZ24.3 LEAD FREE PKG.
PACKAGE WEIGHT 0.75gms
51-85030-*B
51-85013-*B
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