Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Description
The Atmel® | SMART SAM4N series is a member of a family of Flash
microcontrollers based on the high performance 32-bit ARM® Cortex®-M4 RISC
processor. It operates at a maximum speed of 100 MHz and features up to 1024
Kbytes of Flash and up to 80 Kbytes of SRAM. The peripheral set includes 3
USARTs, 4 UARTs, 3 TWIs, 1 SPI, as well as 1 PWM timer, 2 three-channel
general-purpose 16-bit timers (with stepper motor and quadrature decoder logic
support), a low-power RTC, a low-power RTT, 256-bit general purpose backup
registers, a 10-bit ADC (up to 12-bit with digital averaging) and a 10-bit DAC with
an internal voltage reference.
The SAM4N devices have three software-selectable low-power modes: Sleep,
Wait and Backup. In Sleep mode, the processor is stopped while all other
functions can be kept running. In Wait mode, all clocks and functions are stopped
but some peripherals can be configured to wake up the system based on
predefined conditions. In Backup mode, only the RTC, RTT, and wake-up logic
are running.
The Real-time Event Managment allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM4N device is a medium range general purpose microcontroller with the
best ratio in terms of reduced power consumption, processing power and
peripheral set. This enab les the SAM4N to sustain a wide range of applications
including industrial automation and M2M (machine-to-machine), energy metering,
consumer and appliance, building and home control.
It operates from 1.62V to 3.6 V and is available in 48, 64, and 10 0-pin QFP, 48 and
64-pin QFN, and 100-ball BGA packages.
The SAM4N series offers pin-to-pin compatibility with Atmel SAM4S, SAM3S,
SAM3N and SAM7S devices, facilitating easy migration within the portfolio.
The SAM4N series is the ideal migration path from the SAM4S for applications
that require a reduced BOM cost.
SAM4N8 / SAM4N16
Atmel | SMART ARM-based MCU
DATASHEET
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
2
1. Features
Core
ARM Cortex-M4 running at up to 100 MHz
Memory Protection Unit (MPU)
Thumb®-2 instruction Set
Pin-to-pin compatible with SAM3N, SAM3S products (48/64/100-pin versions), SAM4S (64/100-pin versions)
and SAM7S legacy products (64-pin version)
Memories
Up to 1024 Kbytes embedded Flash
Up to 80 Kbytes embedded SRAM
8 Kbytes ROM with embedded boot loader routines (UART) and IAP routines, single-cycle access at maximum
speed
System
Embedded voltage regulator for single supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power
32.768 kHz for RTC or device clock
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup.
In-application trimming access for frequency adjustment
Slow Clock Internal RC oscillator as permanent low-power mode device clock
PLL up to 240 MHz for device clock
Temperature Sensor
Up to 23 peripheral DMA (PDC) channels
Low-power Modes
Sleep, Wait, and Backup modes, down to 0.7 µA in Backup mode with RTC, RTT, and GPBR
Peripherals
Up to 3 USARTs with ISO7816, IrDA (only USART0), RS-485, and SPI Mode
Up to 4 two-wire UARTs
Up to 3 Two-wire Interfaces (TWI)
1 SPI
2 Three-channel 16-bit Timer Counter blocks with capture, waveform, compare and PWM mode, Quadrature
Decoder Logic and 2-bit Gray Up/Down for Stepper Motor
1 Four-channel 16-bit PWM
32-bit low-power Real-time T imer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features
256-bit General Purpose Backup Registers (GPBR)
I/Os
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-
die Series Resistor Termination. Individually Programmable Open-drain, Pull-up and Pull-down resistor and
Synchronous Output
Three 32-bit Parallel Input/Output Controllers
Analog
One 10-bit ADC up to 510 ksps, with Digital Averaging Function providing Enhanced Resolution Mode up to 12-
bit, up to 16-channels
One 10-bit DAC up to 1 msps
Internal voltage reference, 3V typ
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Packages
100-lead LQFP – 14 x 14 mm, pitch 0.5 mm
100-ball TFBGA – 9 x 9 mm, pitch 0.8 mm
100-ball VFBGA – 7 x 7 mm, pitch 0.65 mm
64-lead LQFP – 10 x 10 mm, pitch 0.5 mm
64-pad QFN – 9 x 9 mm, pitch 0.5 mm
48-lead LQFP – 7 x7 mm, pitch 0.5 mm
48-pad QFN – 7 x 7 mm, pitch 0.5 mm
1.1 Configuration Summary
The SAM4N series devices differ in memory size, package and features. Table 1-1 summarizes the configurations
of the device family.
Notes: 1. Includes Temperature Sensor
2. Only 3 channels output
3. USARTs with SPI mode are taken into account.
4. Ti mer Counter in PWM mode is taken into account
5. Only 2 channels output
Table 1-1. Configuration Summary
Feature SAM4N16C SAM4N16B SAM4N8C SAM4N8B SAM4N8A
Flash 1024 Kbytes 1024 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes
SRAM 80 Kbytes 80 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Package LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64 LQFP48
QFN48
Number of PIOs 79 47 79 47 34
10-bit ADC 17 ch (1) 11 ch (1) 17 ch (1) 11 ch (1) 9 ch (1)
10-bit DAC 1 ch 1 ch 1 ch 1 ch –
16-bit Timer 6 6(2) 66
(2) 6(5)
PDC Channels 23 23 23 23 23
USART/UART 3/4 2/4 3/4 2/4 1/4
SPI 4(3) 3(3) 4(3) 3(3) 2(3)
TWI33333
PWM 7(4) 4(4) 7(4) 4(4) 4(4)
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4
2. Block Diagram
See Table 1-1 for detailed configurations of memory size, package and features of the SAM4N devices.
Figure 2-1. SAM4N 100-pin Version Block Diagram
3-layer Bus Matrix
f
MAX
100 MHz
PCK[2:0]
XIN32
XOUT32
VDDCORE
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIN
VDDOUT
JTAG and Serial Wire
Voltage
Regulator
TST
In-Circuit Emulator
Cortex-M4 Processor
f
MAX
100 MHz
WKUP[15:0]
24-bit SysTick Counter
VDDIO
XIN
XOUT
VDDPLL
SSMM
System Controller
NVIC
MPU
I/D
S
S
S M
PDC
UART3
URXD3
UTXD3
NRST
PIO A/B/C
TMS/SWDIO
SRAM
80 Kbytes
64 Kbytes
Flash
1024 Kbytes
512 Kbytes
Flash
Unique ID
3 x
TWI PWM
Peripheral Bridge
PWM0..3
TWD0..2
TWCK0..2
UART0
UART1
UART2
URXD0..2
UTXD0..2
PDCPDC
3 x
USART
10-bit
ADC
10-bit
DACC
PIO SPI
PDC
RXD0..2
SCK0..2
RTS0..2
TXD0..2
CTS0..2
PIODCCLK
PIODCEN1..2
PIOD0..7
NPCS0..3
MISO
MOSI
SPCK
ADTRG
AD0..15
DAC0
DATRG
Temp.
Sensor
TIOB0..2
TCLK0..2
TIOA0..2
PDC PDCPDCPDC
ADVREFP
Timer
Counter
0
ROM
8 Kbytes
PMC
RC Oscillator
4/8/12 MHz
RSTC
SM
POR
32K Osc
32K RC
SUPC
RTT
RTC
WDT
PLL
3–20 MHz
Oscillator
8 GPBR
Tamper Detection
Timer
Counter
1
PDC
TIOB3..5
TCLK3..5
TIOA3..5
RTCOUT0
ERASE
5
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
3. Signals Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Voltage
Reference Comments
Power Supplies
VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V
VDDIN Voltage Regulator, ADC and DAC Power
Supply Power 1.6V to 3.6V
VDDOUT Voltage Regulator Output Power 1.2V Output
VDDPLL Oscillator Power Supply Power 1.08V to 1.32V
VDDCORE Core Chip Power Supply Power 1.08V to 1.32V
Connected externally to
VDDOUT
GND Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input VDDIO
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input VDDIO
XOUT32 Slow Clock Oscillator Output Output
PCK0–PCK2 Programmable Clock Output Output
ICE and JTAG
TCK Test Clock Input VDDIO No pull-up resistor
TDI Test Data In Input VDDIO No pull-up resistor
TDO Test Data Out Output VDDIO
TRACESWO Trace Asynchronous Data Out Output VDDIO
SWDIO Serial Wire Input/Output I/O VDDIO
SWCLK Serial Wire Clock Input VDDIO
TMS Test Mode Select Input VDDIO No pull-up resistor
JTAGSEL JTAG Selection Input High VDDIO Pull-down resistor
Flash Memory
ERASE Flash and NVM Configuration Bits Erase
Command Input High VDDIO Pull-down (15 kΩ) resistor
Reset/Test
NRST Microcontroller Reset I/O Low VDDIO Pull-up resistor
TST Test Mode Select Input VDDIO Pull-down resistor
Universal Asynchronous Receiver Transmitter - UARTx
URXDx UART Receive Data Input
UTXDx UART Transmit Data Output
SAM4N8/SAM4N16 [DATASHEET]
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PIO Controller - PIOA - PIOB - PIOC
PA0–PA31 Parallel IO Controller A I/O VDDIO Pulled-up input at reset
PB0–PB14 Parallel IO Controller B I/O VDDIO Pulled-up input at reset
PC0–PC31 Parallel IO Controller C I/O VDDIO Pulled-up input at reset
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
Timer Counter - TCx
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Pulse Width Modulation Controller - PWMC
PWM PWM Waveform Output for channel Output
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
NPCS0 SPI Peripheral Chip Select 0 I/O Low
NPCS1–NPCS3 SPI Peripheral Chip Select Output Low
Two-wire Interface - TWIx
TWDx TWIx Two-wire Serial Data I/O
TWCKx TWIx Two-wire Serial Clock I/O
Analog
ADVREFP(1) ADC and DAC Reference Analog
10-bit Analog-to-Digital Converter - ADC
AD0–AD15 Analog Inputs Analog
ADTRG ADC Trigger Input
Digital-to-Analog Converter - DAC
DAC0 DAC Channel Analog Output Analog
DACTRG DAC Trigger Input
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Note: 1. “ADVREFP” is named “ADVREF” in Section 17. “Supply Controller (SUPC)” and in Section 34. “Analog-to-Digital Converter
(ADC)”.
Fast Flash Programming Interface - FFPI
PGMEN0–PGMEN2 Programming Enabling Input VDDIO
PGMM0–PGMM3 Programming Mode Input VDDIO
PGMD0–PGMD15 Programming Data I/O VDDIO
PGMRDY Programming Ready Output High VDDIO
PGMNVALID Data Direction Output Low VDDIO
PGMNOE Programming Read Input Low VDDIO
PGMCK Programming Clock Input VDDIO
PGMNCMD Programming Command Input Low VDDIO
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
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4. Package and Pinout
SAM4N devices are pin-to-pin compatible with SAM3N4.
4.1 Overview of the 100-lead LQFP Package
Figure 4-1. Orientation of the 100-lead LQFP Pack ag e
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.2 Overview of the 100-ball TFBGA Package
The 100-ball TFBGA package respects the Green Standards.
Figure 4-2. Orientation of the 100-ball TFBGA Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
Table 4-1. SAM4N Packages
Device 100 Pins/Balls 64 Pins/Balls 48 Pins/Balls
SAM4N16 LQFP, TFBGA and VFBGA LQFP and QFN –
SAM4N8 LQFP, TFBGA and VFBGA LQFP and QFN LQFP and QFN
125
26
50
5175
76
100
1
3
4
5
6
7
8
9
10
2
ABCDEFGHJK
TOP VIEW
BALL A1
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.3 Overview of the 100-ball VFBGA Package (7 x 7 x 1 mm - 0.65 mm ball pitch)
The 100-ball VFBGA package respects the Green Standards.
Figure 4-3. Orientation of the 100-ball VFBGA Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
Top View
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
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4.4 100-lead LQFP, TFBGA and VFBGA Pinout
Table 4-2. SAM4N8/16 100-lead LQFP Pinout
1 ADVREFP 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27 82 PC20
8 PC31/AD15 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25 63 PA29 88 PB10
14 PA18/PGMD6/AD1 39 PA26 64 PA30 89 PB11
15 PA21/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/PGMM0 73 PC16 98 VDDIO
24 PA20/AD3 49 PA7/XIN32/PGMNVALID 74 PA0/PGMEN0 99 PB14
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 4-3. SAM4N8/16 100-ball TFBGA Pinout
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4
A2 PC29/AD13 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27 J1 PC15/AD11
A7 PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24
B1 PC30 D6 GND G1 PA21/AD8 J6 PA25
B2 ADVREFP D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GND D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1 PA17/PGMD5/
AD0 G6 PA26 K1 PA22/AD9
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/AD3
B10 TDO/TRACESWO/
PB5 E5 GND G10 PA5/PGMRDY K5 PC5
C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/
AD2 K6 PC3
C2 VDDPLL E7 PA29 H2 PA23 K7 PC2
C3 PC25 E8 PA30/AD14 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/
PGMM0
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/
PGMNVALID
SAM4N8/SAM4N16 [DATASHEET]
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Table 4-4. SAM4N8/16 100-ball VFBGA Pinout
A1 ADVREFP C6 PC9 F1 VDDOUT H6 PA12/PGMD0
A2 VDDPLL C7 TMS/SWDIO/PB6 F2 PA18/PGMD6/AD1 H7 PA9/PGMM1
A3 PB9/PGMCK/XIN C8 PA1/PGMEN1 F3 PA17/PGMD5/AD0 H8 VDDCORE
A4 PB8/XOUT C9 PA0/PGMEN0 F4 GND H9 PA6/PGMNOE
A5 JTAGSEL C10 PC16 F5 GND H10 PA5/PGMRDY
A6 PB11 D1 PB1/AD5 F6 PC26 J1 PA20/AD3
A7 PB10 D2 PC30 F7 PA4/PGMNCMD J2 PC12/AD12
A8 PC20 D3 PC31 F8 PA28 J3 PA16/PGMD4
A9 PC19 D4 PC22 F9 TST J4 PC6
A10 TDO/TRACESWO/
PB5 D5 PC5 F10 PC8 J5 PA24
B1 GND D6 PA29 G1 PC15/AD11 J6 PA25
B2 PC25 D7 PA30/AD14 G2 PA19/PGMD7/AD2 J7 PA11/PGMM3
B3 PB14 D8 GND G3 PA21/PGMD9/AD8 J8 VDDCORE
B4 PB13/DAC0 D9 PC14 G4 PA15/PGMD3 J9 VDDCORE
B5 PC23 D10 PC11 G5 PC3 J10 TDI/PB4
B6 PC21 E1 VDDIN G6 PA10/PGMM2 K1 PA23
B7 TCK/SWCLK/PB7 E2 PB3/AD7 G7 PC1 K2 PC0
B8 PA31 E3 PB2/AD6 G8 PC28 K3 PC7
B9 PC18 E4 GND G9 NRST K4 PA13/PGMD1
B10 PC17 E5 GND G10 PA27 K5 PA26
C1 PB0/AD4 E6 GND H1 PC13/AD10 K6 PC2
C2 PC29/AD13 E7 VDDIO H2 PA22/AD9 K7 VDDIO
C3 PC24 E8 PC10 H3 PC27 K8 VDDIO
C4 ERASE/PB12 E9 PA2/PGMEN2 H4 PA14/PGMD2 K9 PA8/XOUT32/
PGMM0
C5 VDDCORE E10 PA3 H5 PC4 K10 PA7/XIN32/
PGMNVALID
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.5 Overview of the 64-lead LQFP Package
Figure 4-4. Orientation of the 64-lead LQFP Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.6 Overview of the 64-lead QFN Package
Figure 4-5. Orientation of the 64-lead QFN Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
33
49
48
32
17
16
1
64
1
16
17 32
33
48
4964
TOP VIEW
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
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4.7 64-lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-5. 64-pin SAM4N8/16 Pinout
1 ADVREFP 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 PB10
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 PB11
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA8/XOUT32/PGMM0 47 PA1/PGMEN1 63 PB14
16 PA20/PGMD8/AD3 32 PA7/XIN32/XOUT32/
PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
15
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.8 Overview of the 48-lead LQFP Package
Figure 4-6. Orientation of the 48-lead LQFP Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.9 Overview of the 48-lead QFN Package
Figure 4-7. Orientation of the 48-lead QFN Package
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
25
37
36
24
13
12
1
48
1
12
13 24
25
36
3748
TOP VIEW
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
16
4.10 48-lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-6. 48-pin SAM4N8 Pinout
1 ADVREFP 13 VDDIO 25 TDI/PB4 37 TDO/TRACESWO/PB5
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6
4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7
5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12
7 VDDIN 19 PA12/PGMD0 31 PA3 43 PB10
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 PB11
9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8
10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/P/PB9/GMCK
11 PA19/PGMD7/AD2 23 PA8/XOUT32/PGMM0 35 PA1/PGMEN1 47 VDDIO
12 PA20/AD3 24 PA7/XIN32/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL
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SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
5. Power Considerations
5.1 Power Supplies
The SAM4N8/16 product has several types of power supply pins:
VDDCORE pins: power the core, including the processor, the embedded memo ries and the peripherals;
voltage ranges from 1.08V to 1.32V.
VDDIO pins: power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V.
VDDIN pin: Voltag e Regulator, ADC and DAC power supply; voltage ranges from 1.6V to 3.6V for Voltage
Regulator, ADC and DAC.
VDDPLL pin: powers the Main Oscillator; voltage ranges from 1.08V to 1.32V.
5.2 Power-up Considerations
5.2.1 VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCORE(min). The minimum
slope for VDDCORE is define d by (V DDCORE(min) - VT+) / tRST.
If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 8.8 V/ms.
If VDDCORE is powered by the internal regulator, all power-up considerations are met
Figure 5-1. VDDCORE and VDDIO Constraints at Startup
5.2.2 VDDIO Versus VDDIN
At power-up, VDDIO needs to reach 0.6 V before VDDIN reac he s 1.0 V .
VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V).
Supply (V)
Time (t)
t
RST
VDDIO
VT+
VDDCORE
VDDIO(min)
VDDCORE(min)
Core supply POR output
SLCK
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5.3 Voltage Regulator
The SAM4N embeds a core voltage regulator that is managed by the Supply Controller and that supplies the
Cortex-M4 core, internal memories (SRAM, ROM and Flash logic) and the peripherals. An internal adaptive
biasing adjusts the regulator quiescent current depending on the required load current.
For adequate input an d output power supply decoupling/bypassing, ref er to Table 36-3, “1.2V Voltage Regulator
Characteristics,” on page 795.
5.4 Typical Powering Schematics
The SAM4N8/16 supports a 1.62–3.6 V single supply mode. The internal regulator input connected to the source
and its output feeds VDDCORE. Figure 5-2 shows the powe r sch em a tics.
As VDDIN powers voltage regulator and ADC/DAC, when the user does not want to use the embedded voltage
regulator, he can disable it by software via the SUPC (note that it is different from backup mode).
Figure 5-2. Single Supply
Note: For temperature sensor, VDDIO needs to be greater than 2.4 V.
VDDIN
Voltage
Regulator
VDDOUT
Main Supply (1.62–3.6 V)
VDDCORE
VDDIO
VDDPLL
19
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Figure 5-3. Core Externally Supp lied
Note: For temperature sensor, VDDIO needs to be greater than 2.4 V.
Figure 5-4 provides an example of the powering scheme when using a backup battery. Since the PIO state is
preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the
PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake- up of the system can be from
a push button or any signal, see Se ctio n 5. 7 “Wa ke -up Source s” for further details.
Figure 5-4. Core Externally Supp lied (Backup Battery)
Note: For temperature sensor, VDDIO needs to be greater than 2.4 V.
VDDIN
Voltage
Regulator
VDDOUT
Main Supply (1.62–3.6 V)
VDDCORE
VDDCORE Supply (1.08–1.32 V)
ADC/DAC Supply (1.62–3.6 V)
VDDIO
VDDPLL
ADC, DAC,
Analog Comp.
Note: The two diodes provide a “switchover circuit (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
3.3V LDO
Main Supply
External wakeup signal
Backup battery
Voltage
Regulator
IOs
VDDIN
VDDOUT
VDDCORE
VDDIO
VDDPLL
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5.5 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLL. The power management controll er can be used to adapt the frequency and to disable the
peripheral clocks.
5.6 Low-power Modes
The SAM4N has the follo win g low -p ow er mod es: Backup, Wait, and Sleep .
Note: The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes,
however, this may add complexity in the design of application state machines. This is due to the fact that the WFE
instruction goes along with an event flag of the Cortex core (cannot be managed by the software application). The
event flag can be set by interrupts, a debug event or an event signal from another processor. Since it is possible for an
interrupt to occur just before the execution of WFE, WFE takes into account events that happened in the past. As a
result, WFE prevents the device from entering Wait mode if an interrupt event has occurred.
Atmel has made provisions to avoid using the WFE instruction. The workarounds to ease ap plication design are as
follows:
- For Backup mode, switch off the voltage regulator and configure the VROFF bit in the Supply Controller Control
Register (SUPC_CR).
- For Wait mode, configure the WAITMODE bit in the PMC Clock Generator Main Oscillator Register of the Power
Management Controller (PMC)
- For Sleep mode, use the Wait for Interrupt (WFI) instruction.
Complete information is available in Table 5-1 “Low Power Mode Configuration Summary”.
5.6.1 Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is
performing pe riodic wake-ups to pe rform tasks but not req uiring fast startup time . Total current consum ption is
1 µA typical (VDDIO = 1.8V at 25°C).
The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or
crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are
off.
The SAM4N can be awakened from this mode using the pins WKUP0–15, the supply monitor (SM), the RTT or
RTC wake-up event.
Backup mode can be entered by using the VROFF bit in the Supply Controller Control Register (SUPC_CR) or by
using the WFE instruction. The corresponding procedures are described below.
The procedure to enter Backup mode using the VROFF bit is the following:
Write a 1 to the VROFF bit in SUPC_CR (SUPC_CR.KEY field value must be configured correctly; refer to
Section 17.5.3 “Supply Controller Control Register”).
The procedure to enter Backup mode using the WFE instruction is the following:
1. Write a 1 to the SLEEPDEEP bit in the Cortex-M4 processor System Control Register (SBC_SCR) (refer to
Section 11.9.1.6 “System Control Register”).
2. Execute the WFE instruction of the processor.
In both cases, exit from Backup mode happens if one of the following enable wake-up events occurs:
Level transition, configurable debouncing on pins WKUPEN0–15
Supply Monitor alarm
RTC alarm
RTT alarm
21
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5.6.2 Wait Mode
The purpose of the Wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a startup time of less than 10 µs. Curr ent consumption in wait mode is typically 32 µA (total
current consumption) if the internal voltage regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast startup is available.
This mode is entered by setting the WAITMODE bit in the PMC Clock Generator Main Oscillator Register
(CKGR_MOR) in conjunction with configuring the Flash Low Power Mode field (FLPM = 00 or 01) in the PMC Fast
Startup Mode Register (PMC_FSMR) or by the WFE instruction.
The Cortex-M4 is able to han dle external events or internal events in order to wake up the core. This is done by
configuring the exte rnal lines WKUP0–1 5 as fast startup wa ke-u p pins (refe r to Se ction 5.8 “Fast Startup ”). RTC or
RTT alarm can be used to wake up the CPU.
The procedure to enter Wait mode using the WAITMODE bit is the following:
1. Select the 4/8/12 MHz fast RC oscillator as source of MCK Clock
2. Configure the FLPM field in PMC_FSMR
3. Set Flash wait state to 0
4. Set the WAITMODE bit in CKGR_MOR
5. Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR)
The procedure to enter Wait mode using the WFE instruction is the following:
1. Select the 4/8/12 MHz fast RC oscillator as Main Clock.
2. Set the FLPM field in the PMC_FSMR.
3. Set Flash wait state to 0.
4. Set the LPM bit in the PMC_FSMR.
5. Execute the WFE instruction of the processor.
In both cases, depending on the value of the field FLPM, the Flash enters one of three different modes:
FLPM = 0 in Standby mode (low consumption)
FLPM = 1 in Deep power-down mode (extra low consumption)
FLPM = 2 in Idle mode. Memory ready for Read access
Table 5-1 summarizes the power consumption, wake-up time and system state in Wait mode.
5.6.3 Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stoppe d. The peripheral clocks can be e nabled. The current consump tion in this mode is
application dependent.
This mode is entered via WFI or WFE instructions with bit LPM = 0 in PMC_FSMR.
The processor can be awak ened from an interrupt if the WFI instruction of the Cortex-M4 is used or from an event
if the WFE instruction is used.
5.6.4 Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake-
up sources can be individually configured. Table 5-1 shows a summary of the configurations of the low power
modes.
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22
Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC
oscillator. The user has to add the PLL startup time if it is needed in the system. The wake-up time is defined as the time taken for wake-up until the first
instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. BOD current consumption is not included.
4. Total consumption 0.9 µA typ at 1.8V on VDDIO at 25°C.
5. Total consumption (VDDIO + VDDIN)
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
Table 5-1. Low Power Mode Configuration Summary
Mode
SUPC, 32 kHz Osc.,
RTC, RTT, GPBR,
POR
(VDDBU Region) Regulator Core Memory
Peripherals Mode Entry Potential Wake-up Sources Core at
Wake-up
PIO State
while in Low-
power Mode PIO State at
Wake-up Consumption
(2) (3) Wake-up
Time(1)
Backup Mode ON OFF OFF
(Not powered)
VROFF = 1
or
WFE
+ SLEEPDEEP = 1
Pins WKUP0–15
SM alarm
RTC alarm
RTT alarm
Reset Previous state
saved
PIOA &
PIOB &
PIOC
Inputs with
pull-ups
0.9 µA typ(4) < 1 ms
Wait Mode
w/Flash in
Standby Mode ON ON Powered
(Not clocked)
WA ITMODE = 1
+ FLPM = 0
or
WFE
+ SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 0
Any event from:
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
Clocked
back Previous state
saved Unchanged 28.4 µA(5) < 10 µs
Wait Mode
w/Flash in
Deep Power
Down Mode
ON ON Powered
(Not clocked)
WA ITMODE = 1
+ FLPM = 1
or
WFE
+ SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 1
Any event from:
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
Clocked
back Previous state
saved Unchanged 23.9 µA(5) < 100 µs
Sleep Mode ON ON Powered(7)
(Not clocked)
WFE
or
WFI
+ SLEEPDEEP = 0
+ LPM = 0
Entry mode = WFI
Interrupt only; any enabled
interrupt
Entry mode = WFE
Any enabled interrupt and/or
any event from:
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
Clocked
back Previous state
saved Unchanged (6) (6)
23
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5.7 Wake-up Sources
The wake-up events allow the device to exit the Backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically reenables the core power supply and the SRAM power
supply, if they are not already enabled. See Figure 17-4, "Wake-up Sources" on page 311.
5.8 Fast Startup
The SAM4N8/16 allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast
startup can occur upon detection of a low level on one of the 18 wake-up inputs (WKUP0 to 15 + RTC + RTT).
The fast re start circuit ry (shown in Figure 25-3, "Fast Start-up Circuitry" on page 401) is fully asynchronous and
provides a fast startup signal to the Power Management Controller. As soon as the fast star tup signal is as serted ,
the PMC automatically restarts the embedded 4/18/12 MHz fast RC oscillator, switches the master clock on this 4
MHz clock by default and reenables the processor clock.
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6. Input/Output Lines
The SAM4N8/16 has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system
I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO
line can be used whether in I/O mode or by the multiplexed peripher al. System I/Os include pins such as test pins,
oscillators, erase or analog inputs.
6.1 General Purpose I/O Lines
GPIO lines are manag ed by PIO controllers. All I/Os have several input or ou tput modes such as pull-up or pull-
down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt.
Programming of these modes is performed independently for each I/O line through the PIO controller user
interface. For more details, refer to Section 27. “Parallel Input/Output (PIO) Controller”.
Some GPIOs can have alternate function as analog input. When the GPIO is set in analog mode, all digital
features of the I/O are disabled.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4N8/16 embeds high-speed pads. See Section 36.10 “AC Characteristics” for more details.
Each I/O line also embeds an ODT (On-Die Termination) (see Figure 6-1). It consists of an internal series resistor
termination scheme fo r impedance m atching between the driver output (SAM4N) and the PCB track imped ance,
preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in
turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion, ODT helps diminish signal integrity issues.
Figure 6-1. On-die Termination
PCB Track
Z0 ~ 50 Ω
Receiver
SAM4 Driver with
R
ODT
Z
O
~ 10 Ω
Z0 ~ Z
O
+ R
ODT
ODT
36 Ω Typ.
25
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6.2 System I/O Lines
Table 6-1 lists the SAM4N system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup, the default function of
these pins is always used.
Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode.
2. Refer to Section 17.4.2 “Slow Clock Generator”.
3. Refer to Section 24.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-ba sed Oscillator”.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard
20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table
3-1 on page 5.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer
to Section 12. “Debug and Test Features”.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port
is not needed in the end application. Mode selection between SWJ-DP mode (system IO mode) and general IO
mode is performed through the AHB Matrix Special Function Registers (MATRIX_ SFR). Configuration of the pad
for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a
permanent pull-down re sistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is a ctive. If the debugger host wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and T CK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to
Section 12. “Debug and Test Features”.
6.3 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programm ing mode of the SAM4N
series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left
unconnected for normal operations. To enter fast p rogramming mode, see Section 20. “Fast Flash Programming
Interface (F F P I) ”. For more on the ma nufacturing and test mode, refer to Section 12. “Debug and Test Features”.
Table 6-1. System I/O Configuration
CCFG_SYSIO
Bit No. Default Function
after Reset Other Function Constraints for
Normal St art Configuration
12 ERASE PB12 Low leve l at startup(1)
In Matrix User Interface Registers (Refer
to System I/O Configuration Register in
Section 22. “Bus Matrix (MATRIX)”.)
7 TCK/SWCLK PB7 –
6 TMS/SWDIO PB6 –
5 TDO/TRACESWO PB5 –
4 TDI PB4 –
–PA7 XIN32 –
(2)
– PA8 XOUT32 –
– PB9 XIN – (3)
– PB8 XOUT –
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6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components or asserted low externally to reset the microcontroller. It will reset the core and
the peripherals except the backup region (RTC, RTT and Supply Controller). There is no constraint on the length
of the reset pulse and the reset controller can guarante e a minimum pulse length. The NRST pin integrates a
permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read
as logic level 1). The ERASE pin and the ROM code ensure an in-situ re-programmability of the Flash content
without the use of a debug tool. When the security bit is activated, the ERASE pin provides a capability to
reprogram the Flash array. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left
unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a
minimum ERASE pin assertion time is required. This time is defined in Table 36-46 "AC Flash Characteristics".
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured
as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted
erasing. Refer to Section 10.2 “Peripherals Signals Multiplexing on I/O Lines” on page 36. Also, if the ERASE pin
is used as a standard I/O output, asserting the pin to low does not erase the Flash.
6.6 Anti-ta mper Pins/Low-power Tamper Detection
WKUP0 and WKUP1 generic wake-up pins can be used as anti-tamper pins. Anti-tamper pins detect intrusion, for
example, into a housing box. Upon detection through a tamper switch, automatic, asynchronous and immediate
clear of registers in the backup area will be performed. Anti-tamper pins can be used in all power modes
(Backup/Wait/Sleep/Active). Anti-tampering events can be programmed so that half of the General Purpose
Backup Registers (GPBR) are erased automatically. See Section 17. “Supply Controller (SUPC)” for further
description.
27
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7. Memories
7.1 Product Mapping
Figure 7-1. SAM4N8/16 Product Mapping
Address memory space
Code
0x00000000
Internal SRAM
0x20000000
Peripherals
0x40000000
Reserved
0x60000000
System
0xE0000000
0xFFFFFFFF
Code
Boot Memory
0x00000000
Internal Flash
0x00400000
Internal ROM
0x00800000
Reserved
0x00C00000
0x1FFFFFFF
Internal SRAM
SRAM
0x20000000
Undefined (Abort)
0x20080000
0x40000000
Peripherals
Reserved
0x40000000
Reserved
0x40004000
SPI
21
0x40008000
Reserved
0x4000C000
TC0 TC0
0x40010000
23
TC0 TC1
+0x40
24
TC0 TC2
+0x80
25
TC1 TC3
0x40014000
26
TC1 TC4
+0x40
27
TC1 TC5
+0x80
28
TWI0
19
0x40018000
TWI1
20
0x4001C000
PWM
31
0x40020000
USART0
14
0x40024000
USART1
15
0x40028000
USART2
17
0x4002C000
Reserved
0x40030000
Reserved
0x40034000
ADC
29
0x40038000
DACC
30
0x4003C000
TWI2
22
0x40040000
UART2
10
0x40044000
UART3
16
0x40048000
Reserved
0x4004C000
System Controller
0x400E0000
Reserved
0x400E2600
0x60000000
System Controller
Reserved
0x400E0000
MATRIX
0x400E0200
PMC
5
0x400E0400
UART0
8
0x400E0600
CHIPID
0x400E0740
UART1
9
0x400E0800
EFC
6
0x400E0A00
Reserved
0x400E0C00
PIOA
11
0x400E0E00
PIOB
12
0x400E1000
PIOC
13
0x400E1200
SYSC RSTC
0x400E1400
1
SYSC SUPC
+0x10
SYSC RTT
+0x30
3
SYSC WDT
+0x50
4
SYSC RTC
+0x60
2
SYSC GPBR
+0x90
Reserved
0x400E1600
0x4007FFFF
offset
ID
(+ : wired-or)
peripheral
block
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7.2 Embedded Memories
7.2.1 Internal SRAM
The SAM4N8 product embeds a total of 64-Kbytes high-speed SRAM.
The SAM4N16 product embeds a total of 80-Kbytes high-speed SRAM.
The SRAM is accessible over system Cortex-M4 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF FFFF.
RAM size must be configurable by calibration fuses.
7.2.2 Internal ROM
The SAM4N8/16 product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA®), In
Application Programming (IAP) routines and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
7.2.3 Embedded Flash
7.2.3.1 Flash Overview
The memory is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is divided
into three smaller sectors.
The three smalle r sectors are org anized to co nsist of two sector s of 8 Kbytes and one sector of 48 Kbytes. Refer to
Figure 7-2 “Global Flash O r ga niz ation”.
Figure 7-2. Global Flash Orga nization
Flash Organization
Small sector 0
8 Kbytes
Small sector 1
8 Kbytes
Larger sector
48 Kbytes
Sector 1
64 Kbytes
64 Kbytes Sector n
Sector 0
Sector size Sector name
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Each sector is organized in pages of 512 bytes.
For sector 0:
The smaller sector 0 has 16 pages of 512 bytes
The smaller sector 1 has 16 pages of 512 bytes
The larger sector ha s 96 pages of 512 bytes
From sector 1 to n:
The rest of the arra y i s composed of 64 Kbytes se cto rs ea ch of 12 8 p ages of 512 bytes. Re fe r to Figure 7-3 “Flash
Sector Organization”.
Figure 7-3. Flash Sector Organization
Flash size varies by product:
SAM4N16 the Flash size is 1024 Kbytes
SAM4N8 the Flash size is 512 Kbytes
Figure 7-4 “Flash Size” illustrates the Flash organization by size.
Figure 7-4. Flash Size
Erasing the memory can be performed as follows:
On a 512-byte page inside a sector of 8 Kbytes
Note: EWP and EWPL commands can be only used in 8 Kbytes sectors.
Sector 0
Sector n
Smaller sector 0
Smaller sector 1
Larger sector
Flash Sector Organization
A sector size is 64 Kbytes
16 pages of 512 bytes
16 pages of 512
16 pages of 512 bytes
96 pages of 512 bytes
128 pages of 512 bytes
2 * 8 Kbytes
1 * 48 Kbytes
15 * 64 Kbytes
Flash 1 Mbyte Flash 512 Kbytes
2 * 8 Kbytes
1 * 48 Kbytes
7 * 64 Kbytes
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On a 4-Kbyte bloc k insid e a sec to r of 8 Kbytes/48 Kbytes/64 Kbytes
Note: Erase Page commands can be only used with FARG[1:0] = 1
On a sector of 8 Kbytes/48 Kbytes/64 Kbytes
Note: Erase Page commands can be only used with FARG[1:0] = 2
On chip
The memory has one additional reprogrammable page that can be used as page signature by the user. It is
accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the
User Signature page.
7.2.3.2 Enhanced Embedded Flash Controller
The Enhanced Em bedded Flash Co ntroller m anage s accesses performed by the masters of th e system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
7.2.3.3 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to Section 36.10 “AC Characteristics”.
7.2.3.4 Lock Regions
Several lock bits are used to protect write and erase operat ions on lock regions. A lock region is compos ed of
several consecutive pages, and each lock region has its associated lock bit.
If a locked-region’s erase or pr ogram command occurs, the command is aborted and the EEFC triggers an
interrupt.
The lock bits ar e software pro grammable through the EEFC User Interface. The “Set Lock Bit” command enables
the protection. The “Clear Lock Bit” command unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
7.2.3.5 Security Bit Feature
The SAM4N8/16 features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the
security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the
ICE interface or through the Fast Flash Programming Interface (FFPI), is forbidden. This ensures the
confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the “Set General Purpose NVM Bit 0” command of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the secur ity bit is deactivated, all accesses to the Flash, SRAM, Cor e Registers, In ternal
Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
Table 7-1. Lock Bit Number
Product Number of Lock Bits Lock Region Size
SAM4N8 64 8 Kbytes
SAM4N16 128 8 Kbytes
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As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.
However, it is safer to connect it directly to GND for the final application.
7.2.3.6 Calibration Bits
NVM bits ar e used to calib rate the brow nout detect or and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
7.2.3.7 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed
by the user. The ERASE pin has no effect on the unique identifier.
7.2.3.8 Fast Flash Programming Interface (FFPI)
The FFPI allo ws programming th e device through either a serial JTAG in terface or throug h a multiplexed fully-
handshaked parallel port. It allows gang programming with market-standard industria l programmers.
The FFPI suppo rts read, page progr am , pa ge erase , fu ll er ase, lock, unlock and pr ot ec t com m an d s.
The FFPI is enabled and the Fast Programming mode is entered when TST and PA0 and PA1 are tied low.
7.2.3.9 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-s itu the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
7.2.3.10GPNVM Bits
The SAM4N feat ures two G PNVM b its that can be c leare d or set respectively through the “Clear GPNVM Bit” and
“Set GPNVM Bit” commands of the EEFC User Interface.
7.2.4 Boot Strategies
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory lay out can be
changed via GPNVM.
A General Purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the "Clear General-purpose NVM Bit" and "Set
General-purpose NVM Bit" commands of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it select s the boot fr om the ROM. As serting
ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Table 7-2. General-purpose Non-volatile Memory Bits
GPNVM Bit[#] Function
0 Security bit
1 Boot mode selecti o n
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32
8. Real-time Event Management
The events generated by peripherals are designed to be directly routed to peripherals managing/using these
events without processor intervention. Peripherals receiving events contain logic by which to determine and
perform the action required.
8.1 Embedded Characteristics
Timers, IO peripherals generate event triggers which are directly routed to event managers such as ADC,
DACC, for example, to start measurement/conversion without processor intervention.
UART, USART, SPI, TWI, ADC, DACC, PIO also generate event triggers directly connected to Peripheral
DMA Controller (PDC) for data transfer without processor interventio n.
PMC security event (clock failure detection) can be programmed to switch the MCK on reliable main RC
internal clock withou t pr oc essor interventio n.
8.2 Real-time Event Mapping List
Table 8-1. Real-time Event Mappin g List
Event Generator Event Manager F unction
IO (WKUP0/1) General Purpose Backup Register
(GPBR) Security / Immediate GPBR clear (asynchronous)
on tamper detection through WKUP0/1 IO pins
Power Management Controller
(PMC) PMC Safety / Automatic switch to reliable main RC
oscillator in case of main crystal clock failure
IO (ADTRG) Analog-to-Digital Converter (ADC) Trigger for measurement. Selection in ADC module
TC Output 0 ADC Tr igger for measurement. Selection in ADC module
TC Output 1 ADC Tr igger for measurement. Selection in ADC module
TC Output 2 ADC Tr igger for measurement. Selection in ADC module
IO (DATRG) Digital-Analog Converter Controller
(DACC) Trig ger for conversion. Selection in DAC module
TC Output 0 DACC Trigger for conversion. Selection in DAC module
TC Output 1 DACC Trigger for conversion. Selection in DAC module
TC Output 2 DACC Trigger for conversion. Selection in DAC module
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9. System Controller
The System Contr oller is a set of peripherals which allow handling of key elements of the system, such as but not
limited to power, resets, clocks, time, interrupts, and watchdog.
9.1 System Controller and Peripherals Mapping
Please refer to Figure 7-1 “SAM4N8/16 Product Mapping”.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
9.2 Power-on-Reset, Brownout and Supply Monitor
The SAM4N embeds three features to monitor, warn and/or reset the chip:
Power-on-Reset on VDDIO
Brownout Detector on VDDCORE
Supply Monitor on VDDIO
9.2.1 Power-on-Reset on VDDIO
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at startup but also during power
down. If VDDIO goes below the threshold voltage, the entire chip is reset.
For more information, refer to Section 36. “SAM4N Electrical Characteristics”.
9.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the
Supply Controller Mode Register (SUPC_MR). It is especially recommended to disable it during low-power modes
such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For m ore information, refer to
Section 17. “Supply Controller (SUPC)” and Section 36. “SAM4N Electrical Characteristics”.
9.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully
programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller
(SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to
2048.
For more information, refer to Section 17. “Supply Controller (SUPC)” and Section 36. “SAM4N Electrical
Characteristics”.
9.3 SysTick Timer
24-bit down counter
Self-reload capability
Flexible system timer
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34
10. Peripherals
10.1 Peripheral Identifiers
Table 10-1 defines the peripheral identifiers of the SAM4N8/16. A peripheral identifier is required for the control of
the peripheral interru pt with the Nested Vectored Interrupt Co ntroller and for the control of the peripheral clock with
the Power Management Controller.
Table 10-1 . Peripheral Identifiers
Instance ID Instance Name NVIC
Interrupt PMC
Clock Control Instance Description
0 SUPC X Supply Controller
1 RSTC X Reset Contro ller
2 RTC X Real-time Clock
3 RTT X Real-time Timer
4 WDT X Watchdog Timer
5 PMC X Power Management Controller
6 EFC X Enhanced Flash Controller
7– – –Reserved
8 UART0 X X Universal Asynchronous Receiver Transmitter 0
9 UART1 X X Universal Asynchronous Receiver Transmitter 1
10 UART2 X X Universal Asynchronous Receiver Transmitter 2
11 PIOA X X Para llel I/O Controller A
12 PIOB X X Parallel I/O Controller B
13 PIOC X X Parallel I/O Controller C
14 USART0 X X Universal Synchronous Asynchronous Receiver Transmi tter 0
15 USART1 X X Universal Synchronous Asynchronous Receiver Transmi tter 1
16 UART3 X X Universal Asynchronous Receiver Transmitter 3
17 USART2 X X Universal Synchronous Asynchronous Receiver Transmi tter 2
18 – – – Reserved
19 TWI0 X X Two-wire Interface 0
20 TWI1 X X Two-wire Interface 1
21 SPI X X Serial Periph eral Interface
22 TWI2 X X Two-wire Interface 2
23 TC0 X X Timer Counter Channel 0
24 TC1 X X Timer Counter Channel 1
25 TC2 X X Timer Counter Channel 2
26 TC3 X X Timer Counter Channel 3
27 TC4 X X Timer Counter Channel 4
28 TC5 X X Timer Counter Channel 5
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29 ADC X X Analog-to-Digital Converter
30 DACC X X Digital-to-Analog Converter Controller
31 PWM X X Pulse Width Modulation
Table 10-1 . Peripheral Identifiers (Co ntinu ed)
Instance ID Instance Name NVIC
Interrupt PMC
Clock Control Instance Description
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36
10.2 Peripherals Signals Multiplexing on I/O Lines
The SAM4N8/16 product features two PIO (48-pin and 64-pin version) or three PIO (100-pin version) controllers,
PIOA, PIOB and PIOC, which multiplex the I/O lines of the peripheral set.
Each PIO Controller co ntrols up to 32 lines. Each lin e can be assigned to one of three periph eral function s: A, B or
C. The following multiplexing tables define how the I/O lines of the peripherals A, B and C are multiplexed on the
PIO controllers.
Note that some output-only peripheral functions might be duplicated within the tables.
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10.2.1 PIO Controller A Multiplexing
Notes: 1. WKUPx can be used if PIO controller defines the I/O li ne as "input".
2. Refer to Section 6.2 “System I/O Lines”.
3. To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
4. Analog input has priority over WKUPx pin.
Table 10-2. Multiplexing on PIO Controller A (PIOA)
I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments
PA0 PWM0 TIOA0 WKUP0(1) High Drive
PA1 PWM1 TIOB0 WKUP1(1) High Drive
PA2 PWM2 SCK0 DATRG WKUP2(1) High Drive
PA3 TWD0 NPCS3 High Drive
PA4 TWCK0 TCLK0 WKUP3(1)
PA5 RXD0 NPCS3 WKUP4(1)
PA6 TXD0 PCK0
PA7 RTS0 PWM3 XIN32(2)
PA8 CTS0 ADTRG WKUP5(1) XOUT32(2)
PA9 URXD0 NPCS1 WKUP6(1)
PA10 UTXD0 NPCS2
PA11 NPCS0 PWM0 WKUP7(1)
PA12 MISO PWM1
PA13 MOSI PWM2
PA14 SPCK PWM3 WKUP8(1)
PA15 UTXD2 TIOA1 WKUP14(1)
PA16 URXD2 TIOB1 WKUP15(1)
PA17 PCK1 AD0(3)
PA18 PCK2 AD1(3)
PA19 AD2/WKUP9(4)
PA20 AD3/WKUP10(4)
PA21 RXD1 PCK1 AD8(3) 64/100 pins versions
PA22 TXD1 NPCS3 AD9(3) 64/100 pins versions
PA23 SCK1 PWM0 64/100 pins versions
PA24 RTS1 PWM1 64/100 pins versions
PA25 CTS1 PWM2 64/100 pins versions
PA26 TIOA2 64/100 pins versions
PA27 TIOB2 64/100 pins versions
PA28 TCLK1 64/100 pins versions
PA29 TCLK2 64/100 pins versions
PA30 NPCS2 WKUP11(1) 64/100 pins versions
PA31 NPCS1 PCK2 64/100 pins versions
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38
10.2.2 PIO Controller B Multiplexing
Notes: 1. To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
2. Analog input has priority over WKUPx pin.
3. Refer to Section 6.2 “System I/O Lines”.
4. WKUPx can be used if PIO controller defines the I/O line as "input".
5. DAC0 is enabled when DACC_MR.DACEN is set. See Section 35.7. 2 “DAC C Mo de Re g i ste r”.
Table 10-3. Multiplexing on PIO Controller B (PIOB)
I/O Line Peripheral A Peripheral B Periph eral C E xtra Function System Function Comments
PB0 PWM0 TWD2 AD4(1)
PB1 PWM1 TWCK2 AD5(1)
PB2 URXD1 NPCS2 AD6/WKUP12(2)
PB3 UTXD1 PCK2 AD7(1)
PB4 TWD1 PWM2 TDI(3)
PB5 TWCK1 WKUP13(4) TDO/TRACESWO(3)
PB6 TMS/SWDIO(3)
PB7 TCK/SWCLK(3)
PB8 XOUT(3)
PB9 XIN(3)
PB10 URXD3
PB11 UTXD3
PB12 ERASE(3)
PB13 PCK0 DAC0(5) 64/100 pins versions
PB14 NPCS1 PWM3 64/100 pins versions
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10.2.3 PIO Controller C Multiplexing
Notes: 1. To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
Table 10-4. Multiplexing on PIO Controller C (PIOC)
I/O Line Peripheral A Peripheral B Peripheral C Extra Fu nc tio n System Function Comments
PC0 100 pins version
PC1 100 pins version
PC2 100 pins version
PC3 100 pins version
PC4 NPCS1 100 pins version
PC5 100 pins version
PC6 100 pins version
PC7 NPCS2 100 pins version
PC8 PWM0 100 pins version
PC9 RXD2 PWM1 100 pins version
PC10 TXD2 PWM2 100 pins version
PC11 PWM3 100 pins version
PC12 AD12(1) 100 pins version
PC13 AD10(1) 100 pins version
PC14 SCK2 PCK2 100 pins version
PC15 AD11(1) 100 pins version
PC16 RTS2 PCK0 100 pins version
PC17 CTS2 PCK1 100 pins version
PC18 PWM0 100 pins version
PC19 PWM1 100 pins version
PC20 PWM2 100 pins version
PC21 PWM3 100 pins version
PC22 PWM0 100 pins version
PC23 TIOA3 100 pins version
PC24 TIOB3 100 pins version
PC25 TCLK3 100 pins version
PC26 TIOA4 100 pins version
PC27 TIOB4 100 pins version
PC28 TCLK4 100 pins version
PC29 TIOA5 AD13(1) 100 pins version
PC30 TIOB5 AD14(1) 100 pins version
PC31 TCLK5 AD15(1) 100 pins version
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40
10.3 Embedded Peripherals Overview
10.3.1 Analog Mux
The Analog Mux is used to enable any of the 16 ADC analog inputs and the temperature sensor by means of the
ADC Channel Enable Register (ADC_CHER).
The tempera tu re sens or is inter na lly con n ec te d to the 17 th inpu t of th e an alo g mux .
10.3.2 Voltage Reference Block
The ADC/DAC cell features one internal voltage reference block
3V typ., 2V to 3.6V supply voltage operation
Power by analog power supply voltage
20 µA typ. current consumption
4 bits trimmable output value from 1.6V to 3.4V, 121 mV steps
3 bits trimmable temperature compensation
Low noise in the 10 Hz–100 kHz bandwidth (-74 dBV typ.), usable for a 10-bit ADC reference
PSRR DC higher than 60 dB typ.
3.6 kΩ/100 nF load availability
Sense pin for VREF output
Only one external component needed (100 nF decoupling)
Direct reference connection to the supply voltage possible using force control pin
Level shifters with reset included (for digital supply detection flat)
Five output currents available (one 1 µA, three 2 µA and one 10 µA PTAT sourced form analog power
supply) and can be activated independently from the VREF buffer
10.3.3 Peripheral DMA Controller (PDC)
Handles data transfer between peripherals and memories
Twenty-three channels
Six for USART0/1/2
Six for the UART0/1/2
Six for Two-wire Interface (TWI0/1/2)
Two for Serial Peripheral Interface (SPI)
One for Timer Counter 0
One for Analog-to-Digital Converter
One for the Digital-to-Analog Converter
Low bus arbitration overhead
One Master Clock cycle needed for a transfer from memory to peripheral
Two Master Clock cycles needed for a transfer from peripheral to memory
Next pointer management for reducing interrupt latency requirement
The PDC handles transfe r requests from the channe l according to the priorities (low to high prio rities) defined in
Table 10-5.
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Table 10-5. Peripheral DMA Controller
Instance Name Channel T/R
TWI0 Transmit
TWI1 Transmit
TWI2 Transmit
UART0 Transmit
UART1 Transmit
UART2 Transmit
USART0 Transmit
USART1 Transmit
USART2 Transmit
DACC Transmit
SPI Transmit
TC0–TC2 Receive
TWI0 Receive
TWI1 Receive
TWI2 Receive
UART0 Receive
UART1 Receive
UART2 Receive
USART0 Receive
USART1 Receive
USART2 Receive
ADC Receive
SPI Receive
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42
11. ARM Cortex-M4
11.1 Description
The Cortex-M4 processor is a high performance 32-bit processor des igned fo r the microc ontr oller m arke t. It offers
significant benefits to developers, including outstanding processing performance combined with fast interrupt
handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core,
system and memories, ultra-low power consumption with integrated sleep modes, and platform security
robustness, with integrated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded a pplications. The processor delivers exceptional power
efficiency through an e fficient instruction set and extensively optimized d esign, providing high-end processing
hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities,
saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system
components that reduce processor area while significantly improving interrupt handling and system debug
capabilities. The Cortex-M4 processor implements a version of th e Thumb® instruction set based on Thumb-2
technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction
set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of
8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt
performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs),
dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the
ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in
assembler code, removing any code over head from the ISRs. A tail-chain optimization also significantly re duces
the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that
enables the entire device to be rapidly powered down while still retaining program state.
11.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high spee d, low latency
memory acces ses. It supports unaligned data accesses and implements atomic bit manipulation that enables
faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task
basis. Such requirements are becoming critical in many embe dd e d ap plic at ion s such as automotive .
11.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of
the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is
ideal for microcontrollers and other small package devices.
For system trace the processor integrates an In strumentation Trace Macrocell (ITM) a longside data wa tchpoints
and a profiling unit. T o enable simple and cost-ef fective profiling of the system eve nts these generate, a Serial
Wire Viewer (SWV) can export a stream of software-ge nerated messages, data trace, and profiling inform ation
through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides up to 8 hard ware breakpo int comparato rs that debuggers ca n
use. The c om p arators in the FPB a lso p ro vid e r ema p f un ctions of up to 8 words in the program code in the CODE
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memory region. This enables app lications sto red on a non-eras able, ROM-based mi crocontrolle r to be patched if a
small programmable memory, for example flash, is available in the device. During initialization , the application in
ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application
programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are
redirected to a remap table specified in the FPB confi guration, which means the program in the non-mod ifiable
ROM can be patched.
11.2 Embedded Characteristics
Tigh t int eg ra tio n of syste m peri ph er al s reduces area and develo pm e nt co sts
Thumb instruction set combines high code density with 32-bit performance
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing,
and code profiling.
11.3 Block Diagram
Figure 11-1. TTypical Cortex-M4 Implementation
NVIC
Debug
Access
Port Memory
Protection Unit
Serial
Wire
Viewer
Bus Matrix
Code
Interface SRAM and
Peripheral Interface
Data
Watchpoints
Flash
Patch
Cortex-M4
Processor
Processor
Core
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44
11.4 Cortex-M4 Models
11.4.1 Programmers Model
This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it
contains information about the processor modes and privilege levels for software execution and stacks.
11.4.1.1 Processor Modes and Privilege Levels for Software Execution
The processor modes are:
Thread mode
Used to execute application software. The processor enters the Thread mode when it comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to the Thread mode when it has finished exception
processing.
The privilege levels for software execution are:
Unprivileged
The software:
Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
Cannot access the System Timer, NVIC, or System Control Block
Might have a restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged
The software can use all the instructions and has access to all resources. Privileged software execute s at
the privileged level.
In Thread mode , t he CON TROL register co nt ro ls wh et he r the software execution is privileged or unprivileged, see
“CONTROL Register” . In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software execution in
Thread mode. Unprivile ged software can use the SVC inst ruction to make a supervisor call to transfer c ontrol to
privileged software.
11.4.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked
item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then
writes the item to the new memory lo cation. The pr ocessor implements two stacks, the main stack and the process
stack, with a pointer for each held in independent registers, see “Stack Pointer” .
In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack,
see “CONTROL Register” .
In Handler mode, the processor always uses the ma in stack.
The options for processor operations are:
Note: 1. See “CONTROL Register” .
Table 1 1-1. Summary of processor mode, execution privilege level, and stack use options
Processor Mode Used to Execute Privilege Level for
Software Execution Stack Used
Thread Applications Pri v ileged or unprivileged(1) Main stack or process stack(1)
Handler Exception handlers Always privileged Main stack
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11.4.1.3 Core Registers
Figure 11-2. Process or Core Registers
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP‡
PSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
Table 11-2. Core Processor Registers
Register Name Access(1) Required
Privilege(2) Reset
General-purpose registers R0-R12 Read-write Either Unknown
Stack Pointer MSP Read-write Privileged See description
Stack Pointer PSP Read-write Either Unknown
Link Register LR Read-write Eithe r 0xFFFFFFFF
Program Counter PC Read-write Either See description
Program Status Register PSR Read-write Privileged
0x01000000
Application Program Status Register APSR Read-write Either 0x00000000
Interrupt Program Status Register IPSR Read-only Privileged 0x00000000
Execution Program Status Register EPSR Read-only Privileged 0x01000000
Priority Mask Register PRIMASK Read-write Privileged 0x00000000
Fault Mask Register FAULTMASK Read-write Privileged 0x00000000
Base Priority Mask Register BASEPRI Read-write Privileged 0x00000000
CONTROL register CONTROL Read-write Privileged 0x00000000
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11.4.1.4 General-purpose Registers
R0-R12 are 32-bit general-purpose registers for data operations.
11.4.1.5 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, b it[1] of the CONTROL regis ter indi cates the st ack point er
to use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value fro m add re ss
0x00000000
.
11.4.1.6 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and
exceptions. On reset, the processor loads the LR value
0xFFFFFFFF
.
11.4.1.7 Program Counter
The Progra m Coun te r ( PC) is r eg ister R15. It con tains th e cur rent pro gr am addr ess. On r eset, the pr ocesso r lo ads
the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loa ded into the
EPSR T-bit at reset and must be 1.
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11.4.1.8 Program Status Register
Name: PSR
Access: Read-write
Reset: 0x000000000
The Program Status Register (PSR) combines:
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR.
The PSR register accesses these registers individually or as a combination of any two or all three registers, using the reg-
ister name as an argument to the MSR or MRS instructions. For example:
Read of all the regis te rs us ing PSR with the MRS instruction
Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
Notes: 1. The processor ignores wri tes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits
See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers.
31 30 29 28 27 26 25 24
NZCVQ ICI/IT T
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT – ISR_NUMBER
76543210
ISR_NUMBER
Name Access Combination
PSR Read-write(1)(2) APSR, EPSR, and IPSR
IEPSR Read-only EPSR and IPSR
IAPSR Read-write(1) APSR and IPSR
EAPSR Read-write(2) APSR and EPSR
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11.4.1.9 Application Program Status Register
Name: APSR
Access: Read-write
Reset: 0x000000000
The APSR contains the current state of the condition flags from previous instruction executions.
• N: Negative Flag
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
• Z: Zero Flag
0: Operation result was not zero
1: Operation result was zero.
• C: Carry or Borrow Flag
Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag
Sticky saturation flag:
0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1: Indicates when an
SSAT
or
USAT
instruction results in saturation.
This bit is cleared to zero by software using an
MRS
instruction.
• GE[19:16] : Gre at er Tha n or Eq ua l Fl ags
See “SEL” for more information.
31 30 29 28 27 26 25 24
NZCVQ –
23 22 21 20 19 18 17 16
– GE[3:0]
15 14 13 12 11 10 9 8
–
76543210
–
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11.4.1.10 Interrupt Program Status Register
Name: IPSR
Access: Read-write
Reset: 0x000000000
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
• ISR_NUMBER: Number of the Current Exception
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
45 = IRQ29
See “Exception Types” for more informatio n.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– ISR_NUMBER
76543210
ISR_NUMBER
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11.4.1.11 Execution Program Status Register
Name: EPSR
Access: Read-write
Reset: 0x000000000
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interrupt-
ible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return ze ro. Attempts to
write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR
value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return”
• ICI: Interruptible-continuable Instruction
When an interrup t occ ur s du rin g th e exe cu tio n of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH,
or VPOP instruction, the processor:
–Stops the load multiple or store multiple instruction operation temporarily
–Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
– Returns to the register pointed to by bits[15:12]
– Resumes the execution of the mult iple load or store instruction.
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the
IT
instruction.
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional.
The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more
information.
• T: Thumb S tate
The Cortex-M4 processor only supp or ts the execution of instructions in Thumb state. The following can clear the T b it to 0:
– Instructions BLX, BX and POP{PC}
– Restorat ion from the stacked xPSR value on an except ion return
– Bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information.
31 30 29 28 27 26 25 24
–ICI/ITT
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT –
76543210
–
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11.4.1.12 Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they
might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the
value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
11.4.1.13 Priority Mask Register
Name: PRIMASK
Access: Read-write
Reset: 0x000000000
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
•PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– PRIMASK
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11.4.1.14 Fault Mask Register
Name: FAULTMASK
Access: Read-write
Reset: 0x000000000
The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI).
• FAULTMASK
0: No effect.
1: Prevents the activation of all exceptions except for NMI.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– FAULTMASK
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11.4.1.15 Base Priority Mask Register
Name: BASEPRI
Access: Read-write
Reset: 0x000000000
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it
prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
• BASEPRI
Priority mask bits:
0x0000
= No effect.
Nonzero = Defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this
field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that
higher priority field values correspond to lower exception prioritie s.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
BASEPRI
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11.4.1.16 CONTROL Register
Name: CONTROL
Access: Read-write
Reset: 0x000000000
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in
Thread mode.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception
return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CON-
TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register based
on the EXC_RETURN value.
In an OS environment, ARM recommen ds that threa ds running in Thr ead mode use the proce ss stack, and the kernel and
exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
•Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” , or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 11-10.
Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures
that instructions after the ISB execute using the new stack pointer. See “ISB” .
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– – SPSEL nPRIV
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11.4.1.17 Exceptions and Interrupts
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software
control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry”
and “Exception Return” for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more
information.
11.4.1.18 Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
The process or ma nage s all da ta memor y acc es se s as little-e nd ian . In str uc tio n me m or y an d Private
Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for
more information.
11.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
A common way to:
Access peripheral registers
Define exception vectors
The names of :
The registe rs of the co re per iph e ra ls
The core exception vectors
A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the combination of
CMSIS-compliant software components from various middleware vendors. Software vendors can expand the
CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, an d gives short descriptions of the CMSIS
functions that address the processor core and the core peripherals.
Note: This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural
short names that might be used in other documents.
The following sections give more information about the CMSIS:
Section 11.5.3 “Power Management Programming Hints”
Section 11.6.2 “CMSIS Functions”
Section 11.8.2.1 “NVIC Programming Hints”.
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11.4.2 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding
features. The processor has a fixed memory map that provides up to 4GB of addressable memory.
Figure 11-3. Memory Map
The regions for SRAM and peripherals include bit-band r egions. Bit-banding provides atomic operatio ns to bit
data, see “Bit-banding” .
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.
This memory mapping is gen eric to ARM Cortex-M 4 products. To get the sp ecific memory map ping of this product,
refer to the Memories section of the datasheet.
Vendor-specific
memory
External device
External RAM
Peripheral
SRAM
Code
0xFFFFFFFF
Private peripheral
bus
0xE0100000
0xE00FFFFF
0x9FFFFFFF
0xA0000000
0x5FFFFFFF
0x60000000
0x3FFFFFFF
0x40000000
0x1FFFFFFF
0x20000000
0x00000000
0x40000000
32 MB Bit band alias
0x400FFFFF
0x42000000
0x43FFFFFF
1 MB Bit Band region
32 MB Bit band alias
0x20000000
0x200FFFFF
0x22000000
0x23FFFFFF
1.0GB
1.0GB
0.5GB
0.5GB
0.5GB
0xDFFFFFFF
0xE0000000
1.0MB
511MB
1 MB Bit Band region
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11.4.2.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a d efined
memory type, and some regions have additional memo ry attributes. The memory type and attributes determin e the
behavior of accesses to the region.
Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
memory.
Strongly-ordered
The processor preserves transaction order relative to all othe r transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can
buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memor y region, the memory system pr ovides data synchronizatio n between bus masters in
a system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data
coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
11.4.2.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions, providing
this does not affect the behavior of the instruction sequence. Normally, if correct progr am execution depends on
two memory accesses completing in program order, the software must in sert a me mory barrier instructi on betwee n
the memory access instructions, see “Software Ordering of Memory Accesses” .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered
memory. F or t wo m e mo ry a ccess instructio n s A1 and A2, if A1 occurs before A2 in program order, the ordering of
the memory accesses is described below.
Where:
– Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses ar e observed in program order, that is, A1 is always observed
before A2.
Table 11-3. Ordering of the Memory Accesses Caused by Two Instructions
A2
Normal Access
Device Access Strongly-ordered
AccessA1 Non-shareable Shareable
Normal Access – – – –
Device access, non-shareable – < – <
Device access, shareable – – < <
Strongly-ordered access – < < <
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11.4.2.3 Behavior of Memory Accesses
The behavior of acce sses to each region in the memory map is:
Note: 1. See “Memory Regions, Types an d Attributes” for more information.
The Code, SRAM, and externa l RAM regions can hold progr ams. However, ARM recommends that programs
always use the Code region. This is beca use the processor has separ ate buses that enable instruction fetches and
data accesses to occur simultaneously.
The MPU can overr ide the default memory acce ss behavior described in this section. For more in formation, see
“Memory Protection Unit (MPU)” .
Additional Memory Access Constraints For Shared Memory
When a system includes shared m emory, some memory regions have additional access constraints, and some
regions are subd ivid ed , as Table 11-5 shows:
Notes: 1. See “Memory Regions, Types and Attributes” for more information.
2. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the “Glossary” for more
information.
Table 11-4 . Memory Ac cess Behavior
Address Range Memory Region Memory
Type XN Description
0x00000000 - 0x1FFFFFFF Code Normal(1) -Executable region for program code. Data can also be
put here.
0x20000000 - 0x3FFFFFFF SRAM Normal(1) -Executable region for data. Code can also be put here .
This region includes bit band and bit band alias areas,
see Table 11-6.
0x40000000 - 0x5FFFFFFF Peripheral Device(1) XN This region includes bit band and bit band alias areas,
see Table 11-6.
0x60000000 - 0x9FFFFF FF External RAM Normal(1) - Executable region for da ta.
0xA0000000 - 0xDFFFFFFF External device Device(1) XN External Device memory
0xE0000000 - 0xE00FFFFF Private Peripheral Bus Strongly-
ordered(1) XN This region includes the NVIC, System timer, and
system control block.
0xE0100000 - 0xFFFFFFFF Reserved Device(1) XN Reserved
Table 11-5. Memory Region Shareability Policies
Address Range Memory Region Memory Type Shareability
0x00000000
-
0x1FFFFFFF
Code Normal(1) -(2)
0x20000000
-
0x3FFFFFFF
SRAM Normal(1) -(2)
0x40000000
-
0x5FFFFFFF
Peripheral Device(1) -
0x60000000
-
0x7FFFFFFF
External RAM Normal(1) -WBWA(2)
0x80000000
-
0x9FFFFFFF
WT(2)
0xA0000000
-
0xBFFFFFFF
External device Device(1) Shareable(1) -
0xC0000000
-
0xDFFFFFFF
Non-shareable(1)
0xE0000000
-
0xE00FFFFF
Private Peripheral Bus Strongly- ordered(1) Shareable(1) -
0xE0100000
-
0xFFFFFFFF
Vendor-specific device Device(1) --
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Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
11.4.2.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Acce sses” desc ribes the cases where the memory system guarantees t he
order of memory accesses. Otherwise, if the order o f memory accesses is critical, the software must include
memory barrier instructions to force that ordering. The processor provides the following memory barrier
instructions:
DMB
The Data Memory Bar rier (DMB) instruction ensures that outstanding memory transactions complete before
subsequent memory transactions. See “DMB” .
DSB
The Data Synchronization Barrier (DSB) instruction ensur es that outstanding memory transactions complete
before subsequent instructions execute. See “DSB” .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB” .
MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions
11.4.2.5 Bit-banding
A bit-band re gion maps each word in a bit-band alia s region to a sing le bit in the bit-band region. T he bit-band
regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band regi on, as shown in Table 11-6.
Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in
Table 11-7.
Table 11-6. SRAM Memory Bit-banding Regions
Address Range Memory Region Instruction and Data Accesses
0x20000000-
0x200FFFFF SRAM bit-ba nd region Direct accesses to this memory range behave as SRAM memory
accesses, but this region is also bit-addressable through bit-band alias.
0x22000000-
0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instructi on accesses are not
remapped.
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Notes: 1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-
band region.
2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size
of the instruction making the bit-band access.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
Bit_word_offset
is the position of the target bit in the bit-band memory region.
Bit_word_addr
is the address of the word in the alias memory region that maps to the targeted bit.
Bit_band_base
is the starting address of the alias region.
Byte_offset
is the number of the byte in the bit-band region that contains the targeted bit.
Bit_number
is the bit position, 0-7, of the targeted bit.
Figure 11-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-
band region:
The alias word at
0x23FFFFE0
maps to bit[0] of the bit-band byte at
0x200FFFFF
:
0x23FFFFE0
=
0x22000000
+
(
0xFFFFF
*32) + (0*4).
The alias word at
0x23FFFFFC
maps to bit[7] of the bit-band byte at
0x200FFFFF
:
0x23FFFFFC
=
0x22000000
+
(
0xFFFFF
*32) + (7*4).
The alias word at
0x22000000
maps to bit[0] of the bit-band byte at
0x20000000
:
0x22000000
=
0x22000000
+
(0*32) + (0 *4).
The alias word at
0x2200001C
maps to bit[7] of the bit-band byte at
0x20000000
:
0x2200001C
=
0x22000000
+
(0*32) + (7*4).
Table 11-7. Peripheral Memory Bit-banding Regions
Address Range Memory Region Instruction and Data Accesses
0x40000000-
0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory
accesses, but this region is also bit-addressable through bit-band alias.
0x42000000-
0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write
operation i s per fo rme d as read-modify-write. Instruction accesses are
not permitted.
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Figure 11-4. Bit-band Mapping
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-
band region . Writin g a va lue wit h bit[ 0] se t to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0
writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing
0x01
has the same effect as writing
0xFF
.
Writing
0x00
has the same effect as writing
0x0E
.
Reading a word in the alias region:
0x00000000
indicates that the targeted bit in the bit-band region is set to 0
0x00000001
indicates that the targeted bit in the bit-band region is set to 1
Directly Accessing a Bit-band Region
“Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band
regions.
11.4.2.6 Memory Endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example,
bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. “Little-endian Format” describes
how words of data are stored in memory.
Figure 11-5.
Little-endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-nu mbered byte, and
the most significant byte at the highest-numbered byte. For example:
0x23FFFFE4
0x22000004
0x23FFFFE00x23FFFFE80x23FFFFEC0x23FFFFF00x23FFFFF40x23FFFFF80x23FFFFFC
0x220000000x220000140x220000180x2200001C 0x220000080x22000010 0x2200000C
32 MB alias region
0
7 0
07
0x200000000x200000010x200000020x20000003
6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1
07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1
0x200FFFFC0x200FFFFD0x200FFFFE0x200FFFFF
1 MB SRAM bit-band region
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Figure 11-6. Little-endian Format
11.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking
mechanism that a thread or process can use to obta in exclusive access to a memory location. The software can
use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did no t gain exclusive access to the memory, and no write is
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software mu st use a Load-Exclusive instr uc tio n with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location
4. Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The
software must retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the
software has claimed the se ma p ho re . How ev er, if the Store-Exclusive instruction failed, another process
might have claimed the semaphore after the software performed the first step.
Memory Register
Address
A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
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The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-
Exclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whethe r the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different
threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all
global exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” .
11.4.2.8 Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for
generation of these instructions:
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic
function. For example, the following C code generates the required LDREXB operation:
__ldrex((volatile char *) 0xFF);
Table 11-8. CMSIS Functions for Exclusive Access Instructions
Instruction CMSIS Function
LDREX uint32_t __LDREXW (uint32_t *addr)
LDREXH ui nt16_t __LDREXH (uint16_t *addr)
LDREXB uint8_t __LDREXB (uint8_t *addr)
STREX uint32_t __STREXW (uint32_t value, uint32_t *addr)
STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr)
STREXB uint32_t __STREXB (uint8_t value, uint8_ t *addr)
CLREX void __CLREX (void)
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11.4.3 Exception Model
This section describes the exception model.
11.4.3.1 Exception States
Each exception is in one of the following states:
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to
pending.
Active
An exception is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another ex ception handler. In this case, both exceptions are in
the active state.
Active and Pending
The exception is being serviced by the processor and there is a pending exception from the same source.
11.4.3.2 Exception Types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception mode l treats reset as a special form of exce ption.
When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset
is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution
restarts as privileged execution in Thread mode.
Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest
priority exception other than reset. It is permanently ena bled and has a fixed priority of -2.
NMIs cannot be:
Masked or prevented from activation by any other exception.
Preempted by an y exception other th an Rese t.
Hard Fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception
cannot be managed by any othe r except ion me chanism . Hard Faults have a fixed priority of -1 , meani ng they have
higher priority than any exception with configurable priority.
Memory Management Fault (MemManage)
A Memory Ma nagem ent Fau lt is an ex cept ion that o ccurs becaus e of a m emo ry pr otec tion re late d fau lt. The MPU
or the fixed memory protection constraints determ ines this fault, fo r both instru ction and data m emory transactions.
This fault is used to a bort instruction accesses to Execute Never (XN) memory regions, even if the MPU is
disabled.
Bus Fault
A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory
transaction. This might be from an error detected on a bus in the memory system.
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Usage Fault
A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:
An undefined instruction
An illegal unaligned access
An invalid state on instruction exec ut ion
An error on exception return.
The following can cause a Usage Fault when the core is configured to report them:
An unaligned address on word and halfword memory access
A division by zero.
SVCall
A superviso r call (SVC) is an exception that is triggered by the SVC instru ction. In an OS environment, applications
can use SVC instructions to access OS kernel functions and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context
switching when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also gener ate
a SysTick exception. In an OS environment, the processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are
asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the
processor.
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Notes: 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions oth er
than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” .
2. See “Vector Table” for more information
3. See “System Handler Priority Registers”
4. See “Interrupt Priority Registers”
5. Increasing in steps of 4.
For an asynchronous excep tion, other than re set, the processor can execute another instruction between wh en the
exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 11-9 shows as having configurable priority, see:
“System Handler Control and State Register”
“Interrupt Clear-enable Registers” .
For more information about hard faults, memory ma nagement faults, bus faults, and usage faults, see “Fault
Handling” .
11.4.3.3 Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ29 are the exceptions handled by ISRs.
Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exce ptions handled by the fault
handlers.
System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by
system handlers.
Table 11-9. Properties of the Different Exception Types
Exception
Number(1) Irq Number(1) Exception Type Priority Vector Address or Offset(2) Activation
1 - Reset -3, the highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 Hard fault -1 0x0000000C -
4 -12 Memory
management fault Configurable(3) 0x00000010 Synchronous
5 -11 Bus fault Configurable(3) 0x00000014
Synchronous when
precise,
asynchronous when
imprecise
6 -10 Usage fault Configurable(3) 0x00000018 Synchronous
7-10 - - - Reserved -
11 -5 SVCall Configurable(3) 0x0000002C Synchronous
12-13 - - - Reserved -
14 -2 PendSV Configurable(3) 0x00000038 Asynchronous
15 -1 SysTick Configurable(3) 0x0000003C Asynchronous
16 and above 0 and abo ve Interrupt (IRQ) Configurable(4) 0x00000040 and above(5) Asynchronous
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11.4.3.4 Vector Table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception
vectors, for all exception handlers. Figure 11-7 shows the order of the exception vectors in the ve ctor table. The
least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 11-7. Vector Table
On system reset, the vector table is fixed at address
0x00000000
. Privileged software can write to the SCB_VTOR
register to relocate the vector table start address to a different memory location, in the range
0x00000080
to
0x3FFFFF80
, see “Vector Table Offset Register” .
11.4.3.5 Exception Priorities
As Table 11-9 shows, all exceptions have an associated priority, with:
A lower priority value indicating a higher priority
Configurable priorities for all except ions except Reset, Hard fault and NMI.
If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
For information about configuring exception priorities see “System Handler Prio rity Registers” , and “Interrupt
Priority Registers” .
Note: Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with
fixed negative priority values, always have higher priority than any other exception.
For example, assigning a hig her prior ity value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has
higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
SysTick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ239
17
0x0048
0x004C
255
.
.
.
.
.
.
0x03FC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
239
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If multiple pending exceptio ns have the same priority, the pending excep tion with the lowest exception number
takes preced ence. For examp le, if both IRQ[0] and IRQ [1] are pending and have the same priority, then IRQ[0] is
processed before IRQ[1].
When the processor is executing an ex ception handler, the exception handler is preempted if a higher priority
exception occurs. If an exception occurs with the same priority as the except ion being handled, the handler is not
preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.
11.4.3.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each
interrupt priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt ex ception ha ndler, an other int errupt with t he same gr oup priori ty as the inte rrupt be ing handled does no t
preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they
are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the
lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application
Interrupt and Reset Control Register” .
11.4.3.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its
priority is higher than the priority of the exception being handled. See “Interrupt Priority Groupin g” for more
information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more
information.
Return
This occurs when the exception handler is completed, and:
There is no pending exception with sufficient priority to be serviced
The completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
See “Exception Return” for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending
exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the
new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occu rs during state s aving for a previou s
exception, the processor switches to handle the higher pr iority exception and initiates the vector fetch for that
exception. State saving is not affe cted by late arrival because the state save d is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the execute stage o f the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.
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Exception Entry
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in
Thread mode, or the new exception is of a higher priority than the exception being ha ndled, in which case the new
exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means that the exception has more priority than any limits set by the mask registers, see
“Exception Mask Registers” . An exception with less priority than this is pending but is not handled by the
processor.
When the processor takes a n exception, un less the except ion is a tail-chained or a late-arriving exception, the
processor pushes information onto the current stack. This operation is referred as stacking and the structure of
eight data words is referred to as stack frame.
Figure 11-8. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the
stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the interrupted program.
This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler sta rt
address from the vector table. When stacking is comple te, th e processor star ts executing the exce ption handler. At
the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer
corresponds to the stack frame and what operation mode the processor was in before the entry occurred.
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
Decreasing
memory
address
xPSR
PC
LR
R12
R3
R2
R1
R0
S7
S6
S5
S4
S3
S2
S1
S0
S9
S8
FPSCR
S15
S14
S13
S12
S11
S10
{aligner}
IRQ top of stack
...
Exception frame with
floating-point storage Exception frame without
floating-point storage
Pre-IRQ top of stack
...
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If no higher priority exception occurs during the exceptio n entry, the processor starts exec uting the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during the exception entry, the processor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival
case.
Exception Return
An Exception return occurs when the processor is in Handler mode an d executes one of the following instructions
to load the EXC_RETURN value into the PC:
An LDM or POP instruction that loads the PC
An LDR instruction with the PC as the destination.
A BX instruction using any register.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value
to detect when the processor has completed an exception handler. The lowest five bits of this value provide
information on the return stack and processor mode. Table 11-10 shows the EXC_RETURN values with a
description of the exception return behavior.
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the
processor that the exception is complete, and the processor initiates the appropriate exception return sequence.
11.4.3.8 Fault Handling
Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault:
A bus error on:
An instruction fetch or vector table load
A data access
An internally-detected error such as an undefined instruction
An attempt to execute an instruction from a memory region marked as Non-Executable (XN).
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
Table 11-11 shows th e types of fault, the h andler used for the f ault, the corr esponding fau lt status registe r, and th e
register bit that indicates that the fault has occurred. See “Con figurable Fault Sta tus Register” for more information
about the fault status registers.
Table 11-10. Exception Return Behavior
EXC_RETURN[31:0] Description
0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state
from the MSP and execution uses MSP after return.
0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from
MSP and execution uses MSP after return.
0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from
the PSP and execution uses PSP after return.
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Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
Fault Escalation an d Ha rd Faul ts
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority
Registers” . The software can disable the execution of the handlers for these faults, see “Syste m Handle r Control
and State Register” .
Usually, the exception prio rity, together with the values of the exception mask registers, determ ines whether the
processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in
“Exception Model” .
Table 11-11. Faults
Fault Handler Bit Name Fault Status Register
Bus error on a vector read Hard fault VECTTBL “Hard Fault Status Register”
Fault escalated to a hard fault FORCED
MPU or default memory map mismatch:
Memory
management
fault
--
on instruction access IACCVIOL
“MMFSR: Memory Management Fault
Status Subregister”
on data access DACCVIOL(2)
during exception stacking MSTKERR
during exception unstacking MUNSKERR
during lazy floating-point state preservation MLSPERR
Bus error:
Bus fault
--
during exception stacking STKERR
“BFSR: Bus Fault Status Subregister”
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
during lazy floating-point state preservation LSPERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
Attempt to access a coprocessor
Usage fault
NOCP
“UFSR: Usage Fault Status Subregister”
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction set state(1) INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
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In some situations, a fault with conf igurable priority is treated as a hard fault. This is called priority escalation, and
the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs
because a fault handler cannot preempt itself; it must have the same priority as the current priority level.
A fault handler caus es a fa ult with the sam e or lower pr ior ity as the fault it is servicing. This is because the
handler for the new fault cannot preempt the currently executing fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a
hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt an y exce p ti o n other than
Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory managem ent faults, the fault
address register indicates the address accessed by the oper ation that caused the fault, as shown in Table 11-12.
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the
processor is in lockup state, it does not execute an y instructions. The processor remains in lockup state until
either:
It is reset
An NMI occurs
It is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup
state.
Table 11-12. Fault Status and Fault Address Registers
Handler Status Register
Name Address
Register Name Register Description
Hard fault SCB_HFSR - “Hard Fault Status Register”
Memory
management fault MMFSR SCB_MMFAR “MMFSR: Memory Management Fault Status Subregister”
“MemManage Fault Address Register”
Bus fault BFSR SCB_BFAR “BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register”
Usage fault UFSR - “UFSR: Usage Fau lt Status Subregister”
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11.5 Power Management
The Cortex-M4 processor sleep modes reduce the power con sumption:
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep
mode.
11.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor.
Therefore, the software mu st be able to put the processor back into sleep mode after such an event. A program
might have an idle loop to put the processor back to sleep mode.
11.5.1.1 Wait for Interrupt
The wait for interrupt instruction , WFI, causes immediate entry to sleep mo de. When the processor executes a
WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
11.5.1.2 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an e xception
handler, it retu rns to Thread mode and im mediately enters sleep mo de. Use this mechanism in app lications that
only require the processor to run when an exception occurs.
11.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
11.5.2.1 Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception
entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an
interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes
up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information
about PRIMASK and FAULTMASK, see “Exception Mask Registers” .
11.5.3 Power Management Programming Hints
ISO/IEC C cannot directly generate the WFI instructions. The CMSIS provides the following functions for these
instructions:
void __WFI(void) // Wait for Interrupt
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11.6 Cortex-M4 Instruction Set
11.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 11-13 lists the supported instructions.
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 11-13. Cortex-M4 Instructions
Mnemonic Operands Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V
ADD, ADDS {Rd,} Rn, Op2 Ad d N,Z,C,V
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V
ADR Rd, label Load PC-relative address -
AND, ANDS {Rd,} Rn, Op2 L ogical AND N,Z,C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C
B label Branch -
BFC Rd, #lsb, #width Bit Field Clear -
BFI Rd, Rn, #lsb, #width Bit Field Insert -
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C
BKPT #imm Breakpoint -
BL label Branch with Link -
BLX Rm Branch indirect with Link -
BX Rm Branch indirect -
CBNZ Rn, label Compare and Branch if Non Zero -
CBZ Rn, label Compare and Branch if Zero -
CLREX - Clear Exclusive -
CLZ Rd, Rm Count leading zeros -
CMN Rn, Op2 Compare Negative N,Z,C,V
CMP Rn, Op2 Compare N,Z,C,V
CPSID i Change Processor St ate, Disable Interrupts -
CPSIE i Change Processor S tate, Enable Interrupts -
DMB - Data Memory Barrier -
DSB - Data Synchronization Barrier -
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB - Instruction Synchronization Barrier -
IT - If-Then condition block -
LDM Rn{!}, reglist Load Multiple registers, increment after -
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LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before -
LDMFD, LDMI A Rn{!}, reglist Load Multiple registers, increment after -
LDR Rt, [Rn, #offset] Load Register with word -
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte -
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes -
LDREX Rt, [Rn, #offset] Load Register Exclusive -
LDREXB Rt, [Rn] Load Register Exclusive with byte -
LDREXH Rt, [Rn] Load Register Exclusive with halfword -
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword -
LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte -
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword -
LDRT Rt, [Rn, #of fset] Load Register with word -
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result -
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result -
MOV, MOVS Rd, Op2 Move N,Z,C
MOVT Rd, #imm16 Move Top -
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C
MRS Rd, spec_reg Move from special register to general register -
MSR spec_reg, Rm Move from general register to special register N,Z,C,V
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP - No Operation -
ORN, ORNS {Rd ,} Rn, Op 2 Logical OR NOT N,Z,C
ORR, ORRS {Rd ,} Rn, Op 2 Logical OR N,Z,C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword -
POP reglist Po p re gisters from stack -
PUSH reglist Push register s on to stack -
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16 -
QADD8 {Rd,} Rn, Rm Saturating Add 8 -
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange -
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q
QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange -
QSUB {Rd,} Rn, Rm Saturating Subtract Q
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 -
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 -
RBIT Rd, Rn Reverse Bits -
REV Rd, Rn Reverse byte order in a word -
REV16 Rd , Rn Reverse byte order in each halfword -
REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend -
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V
SADD16 {Rd,} Rn, Rm Signed Add 16 GE
SADD8 {Rd,} Rn, Rm Signed Add 8 and Subtract with Exchange GE
SASX {Rd,} Rn, Rm Signed Add GE
SBC, SBCS {Rd,} Rn, Op 2 Subtract with Carry N,Z,C,V
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract -
SDIV {Rd,} Rn, Rm Signed Divide -
SEL {Rd,} Rn, Rm Select bytes -
SEV - Send Event -
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 -
SHADD8 {Rd,} Rn, Rm Si gned Halving Add 8 -
SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange -
SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange -
SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 -
SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 -
SMLABB, SMLABT,
SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dua l Q
SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result -
SMLALBB, SMLALBT,
SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords -
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual -
SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q
SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q
SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual
SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate -
SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract -
SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply -
SMUAD {Rd ,} Rn, Rm Signed dual Multiply Add Q
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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SMULBB, SMULBT
SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) -
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result -
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword -
SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract -
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q
SSAT16 Rd, #n, Rm Signed Saturate 16 Q
SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE
SSUB16 {Rd ,} Rn, Rm Si gned Subtract 16 -
SSUB8 {Rd,} Rn, Rm Signed Subtract 8 -
STM Rn{!}, reglist Store Multiple registers, increment after -
STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before -
STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after -
STR Rt, [Rn, #offset] Store Register word -
STRB, STRBT Rt, [Rn, #offset] Store Register byte -
STRD Rt, Rt2, [Rn, #offset] Store Register two words -
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive -
STREXB Rd, Rt, [Rn] Store Registe r Exclusive by te -
STREXH Rd, Rt, [Rn] Store Reg ister Exclusive halfword -
STRH, STRHT Rt, [Rn, #offset] Store Register halfword -
STRT Rt, [Rn, #offset] Store Register word -
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V
SVC #imm Supervisor Call -
SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add -
SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add -
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add -
SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16 -
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte -
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword -
TBB [Rn, Rm] Table Branch Byte -
TBH [Rn, Rm, LSL #1] Table Branch Halfword -
TEQ Rn, Op2 Test Equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE
UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE
USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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UHADD16 {Rd,} Rn, Rm Unsigned Halvi ng Add 16 -
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 -
UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchan ge -
UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange -
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 -
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 -
UBFX Rd , Rn, #lsb, #width Unsigned Bit Field Extract -
UDIV {Rd,} Rn, Rm Unsigned Divide -
UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 x 32 + 32 +32),
64-bit result -
UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result -
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result -
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 -
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 -
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange -
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange -
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 -
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 -
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences -
USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate -
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add -
UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add -
UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword -
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte -
UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 -
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword -
VABS.F32 Sd, Sm Floating-point Absolute -
VADD.F32 {Sd,} Sn, Sm Floating-point Add -
VCMP.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero FPSCR
VCMPE.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check FPSCR
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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VCVT.S32.F32 Sd, Sm Convert between floating-point and integer -
VCVT.S16.F32 Sd, Sd, #fbits Convert between floati ng-point and fixed point -
VCVTR.S32.F32 Sd, Sm Convert between floating-point and inte ger with rounding -
VCVT<B|H>.F32.F16 Sd, Sm C onverts half-precision value to single-precision -
VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to half-precision -
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide -
VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate -
VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate -
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract -
VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract -
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers -
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory -
VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate -
VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract -
VMOV.F32 Sd, #imm Floating-point Move immediate -
VMOV Sd, Sm Floating-point Move register -
VMOV Sn, Rt Copy ARM core register to single precision -
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single precision -
VMOV Dd[x], Rt Copy ARM core register to scalar -
VMOV Rt, Dn[x] Copy scalar to ARM core register -
VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR N,Z,C,V
VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply -
VNEG.F32 Sd, Sm Floating-point Negate -
VNMLA.F32 Sd, Sn, Sm Floati ng-point Multiply and Add -
VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract -
VNMUL {Sd,} Sn, Sm Floating-point Multiply -
VPOP list Pop extension registers -
VPUSH list Push extension re gisters -
VSQRT.F32 Sd, Sm Calculates floating-point Sq uare Root -
VSTM Rn{!}, list Floating-point register Store Multip le -
VSTR.F<32|64> Sd, [Rn] Stores an extensi on register to memory -
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract -
WFI - Wait For Interrupt -
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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11.6.2 CMSIS Functions
ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can
generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler
does not support an appropriate intrinsic function , the user might have to use inline assembler to access some
instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly
access:
The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR
instructions:
Table 11-14. CMSIS Functions to Generate some Cortex-M4 Instructions
Instruction CMSIS Function
CPSIE I void __enable_irq(void)
CPSID I void __disable_irq(void)
CPSIE F void __enable_fault_irq(void)
CPSID F void __disable_fault_irq (void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB void __DMB(void)
REV uint32_t __REV(ui nt32_t int value)
REV16 uint32_t __REV16( uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
RBIT uint32_t __RBIT(uint32_t int value)
SEV void __SEV(void)
WFI voi d __ WFI(void)
Table 11-15. CMSIS Intrinsic Functions to Access the Special Registers
Special Register Access CMSIS Function
PRIMASK Read uint32_t __get_PRIMASK (void)
Write void __set_PRIMASK (uint32_t value)
FAULTMASK Read uint32_t __get_FAULTMASK (void)
Write void __set_FAULTMASK (uint32_t value)
BASEPRI Read uint32_t __get_BASEPRI (void)
Write void __set_ BASEPRI (uint32_t value)
CONTROL Read uint32_t __get_CONTROL (void)
Write void __set_ CONTROL (uint32_t value)
MSP Read uint32_t __get_MSP (void)
Write void __set_ MSP (uint32_t TopOfMainStack)
PSP Read uint32_t __get_PSP (void)
Write void __set_ PSP (uint32_t TopOfProcStack)
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11.6.3 Instruction Descriptions
11.6.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction- specific p aramete r. Instru ctions
act on the operands and often store the result in a destination register. When there is a destination register in the
instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” .
11.6.3.2 Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands
or destination register can be used. See instruction descriptions for more information.
Note: Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution,
because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions.
11.6.3.3 Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
“Constant”
“Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
Any constant of the form 0x00XY00XY
Any constant of the form 0xXY00XY00
Any constant of the form 0xXYXYXYXY.
Note: In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in
the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other
constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant
that is not permitted. For example, an assembler might assemble th e instruction CMP
Rd
, #0xFFFFFFFE as the
equivalent instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
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ASR #narithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #nlogical shift left n bits, 1 ≤ n ≤ 31.
LSR #nlogical shift right n bits, 1 ≤ n ≤ 32.
ROR #nrotate right n bits, 1 ≤ n ≤ 31.
RRX rotate right one bit, with extend.
- if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the re sulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also
updates the carry flag when used with certain instructions. For information on the shift operations and how they
affect the carry flag, see “Flexible Second Operand”
11.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified numb er of bits, th e shift length.
Register shift can be performed:
Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the re sult is written to a destination register
During the calculation of Operand2 by the instructions that specify the second operand as a register with
shift. See “Flexible Second Operand” . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The following sub-
sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the
register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the
result. See Figure 11-9.
The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded
towards negative-infinity.
When the instruction is ASRS or wh en ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1] , of the
register Rm.
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 11-9. ASR #3
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-
hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 11-10.
&DUU\
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The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an
unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 11-10. LSR #3
LSL
Logical shift left by n bits moves the right-hand 32- n bits of the register Rm, to the left by n places, into the left-hand
32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 11-11.
The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarde d as an
unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32-
n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 11-11. LSL #3
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand
32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See
Figure 11-12.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register
Rm.
If n is 32, then the value of the re sult is same as the value in Rm, and if th e carry flag is updated, it is updated
to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
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Figure 11-12. ROR #3
RRX
Rotate right with extend moves the bits of the register Rm to the r ight by one bit; an d it copies the carry fla g into
bit[31] of the result. See Figure 11-13.
When the instruction is RRXS or when RRX is used in Operand2 with the instruct ions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 11-13. RRX
11.6.3.5 Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word
access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions gene rate a usage fault exception if they perform an unaligned access, and
therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling” .
Unaligned accesses ar e usually slower than a ligned accesses. In addition, some memory regions might not
support unaligned accesses. Therefore, ARM re commends that prog rammers ensure that accesses are aligned.
To avoid accidental gene ration of unalig ned accesses, use the UNALIGN_TRP bit in the Configuration a nd Control
Register to trap all unalig ne d accesses, see “Configuration and Control Register” .
11.6.3.6 PC-relative Expressions
A PC-relative expression or label is a symbol that repres ents the address of an instruct ion or literal data. It is
represented in the instruction as the PC value plus or minus a numeric offset. Th e assembler calculates the
required offset from the label and the address of the current instruction. If the offset is too big, the assembler
produces an error.
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4
bytes.
For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4
bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
&DUU\
)ODJ
&DUU\
)ODJ
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Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a
number, or an expression of the form [PC, #number].
11.6.3.7 Conditional Execution
Most data proc essing instructions can optionally upda te the condition flags in the Application Program Status
Register (APSR) according to the result of the operation, see “Application Program Status Register” . Some
instructions update all flags, and some only update a subset. If a flag is not updated, the original value is
preserved. See the instruction descriptions for the flags they affect.
An instruction can be exe cu ted con d ition a lly, ba se d on the condition flags set in another instruction, either:
Immediately after the instruction that updated the flags
After any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code suffixes to
instructions. See Table 11-16 for a list of the suffixes to add to instructions to make them conditional instructions.
The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a
conditional instruction fails, the instruction:
Does not execute
Does not write any value to its destination register
Does not affect any of the flags
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for
more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might
automatically insert an IT instruction if there are conditional instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare th e value of a register again st zero and branch on the re sult.
This section describes:
“Condition Flags”
“Condition Code Suffixes” .
Condition Flags
The APSR contains the following condition flags:
N Set to 1 when the result of th e op e ration was negative, cleared to 0 otherwise.
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR, see “Program Status Register” .
A carry occurs:
If the result of an addition is greater than or equal to 232
If the result of a subtraction is positive or zero
As the result of an inline barrel shifter operation in a move or logical instruction.
An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation
been performed at infinite precision, for example:
If adding two negative values results in a positive value
If adding two positive values results in a negative value
If subtracting a positive value from a negative value generates a positive value
If subtracting a negative value from a positive value generates a negative value.
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The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is
discarded. See the instruction descriptions for more information.
Note: Most instructions update the status flags only if the S suffix is specified. Se e the instruction descriptions for more
information.
Condition Code Suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}.
Conditional execution req uires a preceding IT instruction. An instruction with a conditio n code is only executed if
the condition code flags in the APSR meet the specified condition. Table 11-16 shows the condition codes to use.
A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code.
Table 11-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Absolute Value
The example below shows the use of a conditional instru ction to find the absolute value of a number. R0 =
ABS(R1). MOVS R0, R1 ; R0 = R1, setting flags
IT MI ; IT instruction for the negative condition
RSBMI R0, R1, #0 ; If negative, R0 = -R1
Compare and Up da te Value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is
greater than R1 and R2 is greater than R3.
CMP R0, R1 ; Compare R0 and R1, setting flags
ITT GT ; IT instruction for the two GT conditions
CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags
MOVGT R4, R5 ; If still 'greater than', do R4 = R5
Table 11-16. Condition Code Suffixes
Suffix Flags Meaning
EQ Z = 1 Equal
NE Z = 0 Not equal
CS or
HS C = 1 Higher or same, unsigned ≥
CC or
LO C = 0 Lower, unsigne d <
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N = V Greater than or equal, signed ≥
LT N != V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N != V Less than or equal, signed ≤
AL Can have any value Always. This is the default when no suffix is specified.
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11.6.3.8 Instruction Width Selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the
operands and destination register specified. For some of these instructions, the user can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix
forces a 16-bit instruction encoding.
If the user specifie s an instruction width suffix and th e assembler cannot generate an instruction encoding of the
requested width, it generates an error.
Note: In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or
literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the
right size encoding.
To use an instruction width suffix, place it im mediately after the instruction m nemonic and condition cod e, if any.
The example below shows instructions with the instruction width suffix.
BCS.W label ; creates a 32-bit instruction even for a short
; branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
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11.6.4 Memory Access Instructions
The table below shows the memory access instructions:
Table 11-17. Memory Access Instructions
Mnemonic Description
ADR Load PC-relative address
CLREX Clear Exclusive
LDM{mode} Lo ad Multiple registers
LDR{type} Lo ad Register using immediate offset
LDR{type} Load Register using register offset
LDR{type}T Lo ad Register with unprivileged access
LDR Load Register using PC-relative address
LDRD Load Register Dual
LDREX{type} Load Register Exclusive
POP Pop registers from stack
PUSH Push registers onto stack
STM{mode} Store Multiple registers
STR{type} Store Register using immediate offset
STR{type} Store Register using register offset
STR{type}T Store Register with unprivileged access
STREX{type} S tore Register Exclusive
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11.6.4.1 ADR
Load PC-relative address.
Syntax ADR{cond} Rd, label
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er .
label is a PC-relative expres sio n. See “PC-relative Expressions” .
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination
register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a targ et address for a BX or BLX in struction, ensu re that bit[0 ] of the addre ss gene rated
is set to 1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Note: The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-
aligned. See “Instruction Width Selection” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
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11.6.4.2 LDR and STR, Immediate Offset
Load and Store with imm edi at e of fse t, pr e- in de xe d imm ediate offset, or post-indexed immediate offset.
Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
op is one of:
LDR Load Register .
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on load s.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the regist er to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an offset from Rn. If offset is omitted, the address is th e contents of Rn.
Rt2 is the additional register to load or store for two-word operations.
Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset Addressing
The offset value is ad ded to or subtracted from the address o btained from the r egister Rn. The result is used as the
address for the memory access. The register Rn is unaltered. The assembly languag e syntax for this mode is:
[Rn, #offset]
Pre-indexed Addressing
The offset value is ad ded to or subtracted from the address o btained from the r egister Rn. The result is used as the
address for the me mory access and written b ack into the re gister Rn. The assembly language syn tax for this mode
is: [Rn, #offset]!
Post-indexed Addressing
The address obtained from the register Rn is used as the address for the memory access. The offset value is
added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for
this mode is:
[Rn], #offset
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The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed
or unsigned. See “Address Alignment” .
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
Table 11-18. Offset Ranges
Instruction Type Immedia te Offset Pre-indexed Post-indexed
Word, halfword, signed
halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255
Two words multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to 1020
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11.6.4.3 LDR and STR, Register Offset
Load and Store with register offset.
Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
LDR Load Register .
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on load s.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the regist er to lo a d or stor e.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #nis an optional shift, with n in the range 0 to 3 .
Operation
LDR instructions load a register with a value from me m or y.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the
register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
Restrictions
In these instructions:
Rn must not be PC
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
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; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
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11.6.4.4 LDR and STR, Unprivileged
Load and Store with unprivileged access.
Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
LDR Load Register .
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on load s.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the regist er to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
Operation
These load and store instructions perform the same function as the memory access instructions with immediate
offset, see “LDR and STR, Immediate Offset” . The difference is that these instructions have only unprivileged
access even when used in privileged software.
When used in unprivileged so ftware, these instruction s behave in exactly the same way as normal memory access
instructions with immediate offset.
Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
Condition Flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
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11.6.4.5 LDR, PC-relative
Load register from memory.
Syntax LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label ; Load two words
where:
type is one of:
B unsigned byte, zero extend to 32 bits.
SB signed byte, sign extend to 32 bits.
H unsigned halfword, zero extend to 32 bits.
SH signed halfword, sign extend to 32 bits.
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the regist er to lo a d or stor e.
Rt2 is the second register to load or store.
label is a PC-relative expres sio n. See “PC-relative Expressions” .
Operation
LDR loads a register with a value from a PC-relative me mory address. The mem ory address is sp ecified by a label
or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
label must be within a limited range of the current instruction. The table below shows the possible offsets between
label and the PC.
The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection” .
Restrictions
In these instructions:
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Table 11-19. Offset Ranges
Instruction Type Offset Range
Word, halfword, signed halfword, byte, signed byte -4095 to 4095
Two words -1020 to 1020
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Condition Flags
These instructions do not change the flags.
Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable
LDRSB R7, localdata ; Load a byte value from an address labelled
; as localdata, sign extend it to a word
; value, and put it in R7
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11.6.4.6 LDM and STM
Load and Store Multiple registers.
Syntax op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
LDM Load Multiple registers.
STM Store Multiple registers.
addr_mode is any one of the follow i ng :
IA Increment address After each access. This is the default.
DB Decrement address Before each access.
cond is an optional condition code, see “Conditional Execution” .
Rn is the register on which the memory addresses are based.
! is an optional writeback suffix.
If ! is present, the final address, that is loaded from or stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains mo re
than one register or register range, see “Examples” .
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending
stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending
stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks
Operation
LDM instructions load the registers in reglist with word values from memory addresses based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on Rn.
For LDM, LDM IA, LDMFD, STM, STMIA, and STME A the m emory add resses use d for the acce sses are at 4-byte
intervals rang ing fro m Rn to Rn + 4 * (n-1), where n is the number of register s in reglist. The accesses happens in
order of increasing register numbers, with the lowest numbered register using the lowest memory address and the
highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4
* (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals
ranging from Rn to Rn - 4 * (n-1), where n is the nu mber of registers in reglist. The accesses ha ppen in order of
decreasing register numbers, with the highest nu mbered register using the highest memory address and the
lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 *
(n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
Restrictions
In these instructions:
Rn must not be PC
reglist must not contain SP
In any STM instruction, reglist must not contain PC
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In any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if the writeback suffix is specified.
When PC is in reglist in an LDM instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-
aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM
STMDB R1!,{R3-R6,R11,R12}
Incorrect Examples
STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
LDM R2, {} ; There must be at least one register in the list
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11.6.4.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
Syntax PUSH{cond} reglist
POP{cond} reglist
where:
cond is an optional condition code, see “Conditional Execution” .
reglist is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based
on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred
mnemonics in these cases.
Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered
register using the highest memory address and the lowest numbered register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register
using the lowest memo ry ad d re ss an d th e hig he st numbered register using the highest memory address.
See “LDM and STM” for more information.
Restrictions
In these instructions:
reglist must not contain SP
For the PUSH instruction, reglist must not contain PC
For the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-
aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples PUSH {R0,R4-R7}
PUSH {R2,LR}
POP {R0,R10,PC}
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11.6.4.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register for the returned status.
Rt is the regist er to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and ha lfword respective ly from a me m or y ad dr e ss.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address.
The address used in any Store-Exclusive instruction must be the same as the address in the most recently
executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same
data size as the value loaded by the preceding Loa d-exclusive instruction. This means software must always use a
Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see
“Synchronization Primitives” .
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the
store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is
guaranteed that no other p rocess in the system has accessed the memory location between the Load-exclusive
and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions betwe en corresponding Load-Exclusive and Store-
Exclusive instruction to a minimum.
The result of exe cu tin g a S tor e -Exc lus ive instr u ctio n to an ad dr es s th at is diffe r en t fr om th at u se d in the pr ece d ing
Load-Exclusive instruction is unpredictable.
Restrictions
In these instructions:
Do not use PC
Do not use SP for Rd and Rt
For STREX, Rd must be diffe rent from both Rt and Rn
The value of offset must be a multiple of four in the range 0-1020.
Condition Flags
These instructions do not change the flags.
Examples MOV R1, #0x1 ; Initialize the ‘lock taken’ value try
LDREX R0, [LockAddr] ; Load the lock value
CMP R0, #0 ; Is the lock free?
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ITT EQ ; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr] ; Try and claim the lock
CMPEQ R0, #0 ; Did this succeed?
BNE try ; No – try again
.... ; Yes – we have the lock
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11.6.4.9 CLREX
Clear Exclusive.
Syntax CLREX{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to
perform the store. It is usefu l in exception handler co de to force the failure of the store exclusive if the exception
occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization
operation.
See “Synchronization Primitives” for more information.
Condition Flags
These instructions do not change the flags.
Examples
CLREX
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11.6.5 General Data Processing Instructions
The table below shows the data pr ocessing instructions:
Table 11-20. Data Processing Instructions
Mnemonic Description
ADC Add with Carry
ADD Add
ADDW Add
AND Logical AND
ASR Arithmetic Shift Right
BIC Bit Clear
CLZ Count leading zeros
CMN Compare Negative
CMP Compare
EOR Exclusive OR
LSL Logical Shift Left
LSR Logical Shift Right
MOV Move
MOVT Move Top
MOVW Move 16-bit constant
MVN Move NOT
ORN Logical OR NOT
ORR Logical OR
RBIT Reverse Bits
REV Reverse byte order in a word
REV16 Re verse byte order in each halfword
REVSH Reverse byte order in bottom halfword and sign extend
ROR Rotate Right
RRX Rotate Right with Extend
RSB Reverse Subtract
SADD16 Signed Add 16
SADD8 Signed Add 8
SASX Signed Add and Subtract with Exchange
SSAX Signed Subtract and Add with Exchange
SBC Subtract with Carry
SHADD16 Signed Halving Add 16
SHADD8 Signed Halving Add 8
SHASX Signed Halving Add and Subtract with Exchange
SHSAX Signed Halving Subtract and Add with Exchange
SHSUB16 Signed Halving Subtract 16
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SHSUB8 Signed Halving Subtract 8
SSUB16 Signed Subtract 16
SSUB8 Signed Subtract 8
SUB Subtract
SUBW Subtract
TEQ Test Equivalence
TST Test
UADD16 Unsigned Add 16
UADD8 Unsigned Add 8
UASX Unsigned Add and Subtract with Exchange
USAX Unsigned Subtract and Add with Exchange
UHADD16 Unsigned Halving Add 16
UHADD8 Unsigned Halving Add 8
UHASX Unsigned Halving Add and Subtract with Exchange
UHSAX Unsigned Halving Subtract and Add with Exchange
UHSUB16 Unsigned Halving Subtract 16
UHSUB8 Unsigned Halving Subtract 8
USAD8 Unsigne d Sum of Absol ute Differences
USADA8 Unsigne d Sum of Absolute Differences and Accumulate
USUB16 Unsigned Subtract 16
USUB8 Unsigned Subtract 8
Table 11-2 0. Data Processing In structions (Continued)
Mnemonic Description
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11.6.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er. I f Rd is omitted, the destination register is Rn.
Rn is the re gis ter ho ldin g th e firs t ope r an d.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm12 is any value in the range 0-4095.
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is
reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide
range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on.
See also “ADR” .
Note: ADDW is equiva lent to the A DD syntax th at uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses
the imm12 operand.
Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
Rn must also be SP
Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
The user must not specify the S suffix
Rm must not be PC and must not be SP
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If the instruction is conditional, it must be the last instruction in the IT block
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only
with the addit ion a l rest rict ion s :
The user must not specify the S suffix
The second operand must be a constant in the range 0 to 4095.
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00
before performing the calculation, making the base address for the calculation word-aligned.
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the
PC, because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples ADD R2, R1, R3 ; Sets the flags on the result
SUBS R8, R6, #240 ; Subtracts contents of R4 from 1280
RSB R4, R4, #1280 ; Only executed if C flag set and Z
ADCHI R11, R0, R3 ; flag clear.
Multiword Arithmetic Examples
The example below shows two instruction s that add a 64-bit integer contained in R2 and R3 to another 64-bit
integer contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a
96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the
result in R6, R9, and R2.
96-bit Subtraction Example
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBC R2, R8, R11 ; subtract the most significant words with carry
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11.6.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
AND logical AND.
ORR
logical OR, or bit set.
EOR
logical Exclusive OR.
BIC
logical AND NOT, or bit clear.
ORN
logical OR NOT.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the re gis ter ho ldin g th e firs t ope r an d.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn
and Operand2.
The BIC instruction per forms an AND operation on the bits in Rn with the com plements of the correspond ing bits in
the value of Operand2.
The ORN instruction performs an OR ope ration on the bits in Rn with the comple ments of the corresp onding bits in
the value of Operand2.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
S
is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples AND R9, R2, #0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BIC R0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
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11.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rm is the register holding the value to be shifted.
Rs is the register ho ldi ng th e shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shif t length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number o f places specified by
constant n or register Rs.
RRX moves the bits in register Rm to the ri ght by 1.
In all these instructions, the result is written to Rd, but the value in r eg ist er Rm remains unchanged. For details on
what result is generated by the different instructions, see “Shift Operations” .
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
S
is specified:
These instructions update the N and Z flags according to the result
The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” .
Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits
SLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend.
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11.6.5.4 CLZ
Count Leading Zeros.
Syntax CLZ{cond} Rd, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rm is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the re su lt in Rd. The result
value is 32 if no bits are set and zero if bit[31] is set.
Restrictions
Do not use SP and do not use PC.
Condition Flags
This instruction does not change the flags.
Examples CLZ R4,R9
CLZNE R2,R3
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11.6.5.5 CMP and CMN
Compare an d Co mp a re Neg ativ e.
Syntax CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the re gis ter ho ldin g th e firs t ope r an d.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions compare the value in a register with Operand2. They update the condition flags on the result,
but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction,
except that the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2 must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
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11.6.5.6 MOV and MVN
Move and Move NOT.
Syntax MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
imm16 is any value in the range 0-65535.
Operation
The MOV instructio n co pie s the v alue of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n!= 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX” .
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and
places the result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 opera nd .
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When Rd is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is p ossible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX
instruction to branch for software portability to the ARM instruction set.
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Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples MOVS R11, #0x000B ; Write value of 0x000B to
R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to
R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10,
flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
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11.6.5.7 MOVT
Move Top.
Syntax MOVT{cond} Rd, #imm16
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
imm16 is a 16-bit immediate con stant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write
does not affect Rd[15:0].
The MOV, MOVT instr u ction pair enables to generate any 32-bit constant.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
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11.6.5.8 REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax op{cond} Rd, Rn
where:
op is any of:
REV Reverse byte or de r in a wor d .
REV16 Reverse byte order in each halfword independently.
REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT Reverse the bit order in a 32-bit word.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn is the re gis ter holding the oper an d .
Operation
Use these instructions to change endianness of data:
REV converts either:
32-bit big-endian data into little-endian data
32-bit little-endian data into big-endian data.
REV16 converts either:
16-bit big-endian data into little-endian data
16-bit little-endian data into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
REV R3, R7; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5; Reverse Signed Halfword
REVHS R3, R7; Reverse with Higher or Same condition
RBIT R7, R8; Reverse bit order of value in R8 and write the result to R7.
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11.6.5.9 SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SADD16 Performs two 16-bit signed integer additions.
SADD8 Performs four 8-bit signed integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R1, R0 ; Adds the halfwords in R0 to the corresponding
; halfwords of R1 and writes to corresponding halfword
; of R1.
SADD8 R4, R0, R5 ; Adds bytes of R0 to the corresponding byte in R5 and
; writes to the corresponding byte in R4.
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11.6.5.10 SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHADD16 Signed Halving Add 16.
SHADD8 Signed Halving Add 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The SHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halfword results in the destination register.
The SHADDB8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1
; and writes halved result to corresponding halfword in
; R1
SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
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11.6.5.11 SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
3. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Writes the ha lfword result of th e addition to the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
3. Adds the bottom halfword of the first operand with the top halfword of the second operand.
4. Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SHASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4 and writes halved result to bottom halfword of R7
SHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword
; of R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
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11.6.5.12 SHSUB16 and SHSUB8
Signed Halving Subtract 16 and Signed Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHSUB16 Signed Halving Subtract 16.
SHSUB8 Signed Halving Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The SHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halved halfword results in the destination register.
The SHSUBB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand,
2. Shuffles the result by one bit to the right, halving the data,
3. Writes the corresponding signed byte results in the destin a tio n re gis ter.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SHSUB8 R4, R0, R5 ; Subtracts bytes of R0 from corresponding byte in R5,
; and writes to corresponding byte in R4.
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11.6.5.13 SSUB16 and SSUB8
Signed Subtract 16 and Signed Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SSUB16 Performs two 16-bit signed integer subtractions.
SSUB8 Performs four 8-bit signed integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Operation
Use these instructions to change endianness of data:
The SSUB16 instruction:
1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand
2. Writes the difference result of two signed halfwo rds in th e cor res ponding ha lfwo rd of th e destin ation re gister.
The SSUB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand
2. Writes the difference result of four signed bytes in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in
; R0, and writes to corresponding byte of R4.
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11.6.5.14 SASX and SSAX
Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is any of:
SASX Signed Add and Subtract with Exchange.
SSAX Signed Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SASX instruction:
1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
2. Writes the signed result of the addition to the top halfword of th e destination regis ter.
3. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first
operand.
4. Writes the signed result of the subtraction to the bottom halfword of the destination register.
The SSAX instruction:
1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand.
2. Writes the signed result of the addition to the bottom halfword of the destinatio n register.
3. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
4. Writes the signed result of the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R4
; and writes to bottom halfword of R0
SSAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 with bottom halfword of R2 and
; writes to top halfword of R7.
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11.6.5.15 TST and TEQ
Test bits and Test Equivalence.
Syntax TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where
cond is an optional condition code, see “Conditional Execution” .
Rn is the re gis ter ho ldin g th e firs t ope r an d.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions te st the value in a register against Operand2. They update the cond ition flags based on the
result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the
same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1
and all other bits cleared to 0.
The TEQ instr uction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2.
This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testin g the sign of a value. After th e compar ison, the N flag is th e logical Exclusive OR o f the
sign bits of the two ope r an ds .
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded.
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11.6.5.16 UADD16 and UADD8
Unsigned Add 16 and Unsigned Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to add 16- and 8-bit unsigned data:
The UADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the unsigned result in the corresponding halfword s of the destination register.
The UADD16 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Writes the unsigned result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1,
; writes to corresponding halfword of R1
UADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes to corresponding byte in R4.
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11.6.5.17 UASX and USAX
Add and Subtract with Exchange and Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UASX Add and Subtract with Exchange.
USAX Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The UASX instruction:
1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
2. Writes the unsigned result from the subtraction to the bottom halfword of the destination re gister.
3. Adds the top halfword of the first operand with the bottom halfword of the second operand.
4. Writes the unsigned result of the addition to the top halfword of the destination register.
The USAX instruction:
1. Adds the bottom halfword of the first operand with the top halfword of the second operand.
2. Writes the unsigned result of the addition to the bottom halfword of the destination register.
3. Subtracts the bottom halfword of the second operand from the top halfword of the first operand.
4. Writes the unsigned result from the subtraction to the top halfword of the destin a tion re gist er.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R0
; and writes to bottom halfword of R0
USAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 to bottom halfword of R2 and
; writes to top halfword of R7.
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11.6.5.18 UHADD16 and UHADD8
Unsigned Halving Add 16 and Unsigned Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHADD16 Unsigned Halving Add 16.
UHADD8 Unsigned Halving Add 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the re gis ter ho ldin g th e firs t ope r an d.
Rm is the register holding the second operand.
Operation
Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the halfword result by one bit to the right, halving the data.
3. Writes the unsigned results to the corresponding halfword in the destination register.
The UHADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the byte result by one bit to the right, halving the data.
3. Writes the unsigned results in the correspond ing byte in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHADD16 R7, R3 ; Adds halfwords in R7 to corresponding halfword of R3
; and writes halved result to corresponding halfword
; in R7
UHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
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11.6.5.19 UHASX and UHSAX
Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UHASX Add and Subtract with Exchange and Halving.
UHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The UHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the addition to the top halfword of the destination register.
4. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the division in the bottom halfword of the destination register.
The UHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the subtraction in the top halfword of the destination register.
4. Adds the bottom halfword of the first operand with the top halfword of the second operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the addition to the bottom halfword of the destination r egister.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UHASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R7 and writes halved result to bottom halfword of R7
UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
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11.6.5.20 UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHSUB16 Performs two unsigned 16-bit integer additions, halves the results,
and writes the results to the de st ina tio n re gis te r.
UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and
writes the results to the destination register.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand.
2. Shuffles each halfword result to the right by one bit, halving the data.
3. Writes each unsigned halfword result to the corresponding halfwo rd s in the des tin at ion regi st er.
The UHSUB8 instruction:
1. Subtracts each byte of second operand from the corresponding byte of the first operand.
2. Shuffles each byte result by one bit to the right, halving the data.
3. Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of
; R1 and writes halved result to corresponding halfword in R1
UHSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and
; writes halved result to corresponding byte in R4.
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11.6.5.21 SEL
Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the
values of the GE flags.
Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
where:
c, q are standard assembler syntax fields.
Rd is the de stin a tio n regist er.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
The
SEL
instruction:
1. Reads the value of each bit of APSR.GE.
2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second
operand re gister.
Restrictions
None.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R0, R1, R2 ; Set GE bits based on result
SEL R0, R0, R3 ; Select bytes from R0 or R3, based on GE.
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11.6.5.22 USAD8
Unsigned Sum of Absolute Differences
Syntax USAD8{cond}{Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Operation
The USAD8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the absolute values of the differences together.
3. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USAD8 R1, R4, R0 ; Subtracts each byte in R0 from corresponding byte of R4
; adds the differences and writes to R1
USAD8 R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0,
; adds the differences and writes to R0.
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11.6.5.23 USADA8
Unsigned Sum of Absolute Differences and Accumulate
Syntax USADA8{cond}{Rd,} Rn, Rm, Ra
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Ra is the re gis ter tha t con tains the ac cum u lat ion v alue.
Operation
The USADA8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the unsigned absolute differences together.
3. Adds the accumulation value to the sum of the absolute differences.
4. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USADA8 R1, R0, R6 ; Subtracts bytes in R0 from corresponding halfword of R1
; adds differences, adds value of R6, writes to R1
USADA8 R4, R0, R5, R2 ; Subtracts bytes of R5 from corresponding byte in R0
; adds differences, adds value of R2 writes to R4.
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11.6.5.24 USUB16 and USUB8
Unsigned Subtract 16 and Unsigned Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where
op is any of:
USUB16 Unsigned Subtract 16.
USUB8 Unsigned Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r.
Rm is the second operand register.
Operation
Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register:
The USUB16 instruction:
1. Subtracts each halfword from the second operand register from the corresponding halfword of the first operand
register.
2. Writes the unsigned result in the corresponding halfword s of the destination register.
The USUB8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Writes the unsigned byte result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of R1
; and writes to corresponding halfword in R1USUB8 R4, R0, R5
; Subtracts bytes of R5 from corresponding byte in R0 and
; writes to the corresponding byte in R4.
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11.6.6 Multiply and Divide Instructions
The table below shows the multiply and divide instructions:
Table 11-21. Multiply an d Divide Instructions
Mnemonic Description
MLA Multiply with Accumulate, 32-bit result
MLS Multiply and Subtract, 32-bit result
MUL Multiply, 32-bit result
SDIV Signed Divide
SMLA[B,T] Signed Multiply Accu mulate (halfwords)
SMLAD
,
SMLADX
Signed Multiply Accumulate Dual
SMLAL Signed Multiply with Accumulate (32x32+64), 64-bit result
SMLAL[B,T]
Signed Multiply Accumulate Long (halfwords)
SMLALD
,
SMLALDX
Signed Multiply Accumu late Long Dual
SMLAW[B|T] Signed Multiply Accumu late (word by halfword)
SMLSD Signed Multiply Subtract Dual
SMLSLD Signed Multiply Subtract Long Dual
SMMLA Signed Most Significant Word Multiply Accumulate
SMMLS
,
SMMLSR
Signed Most Significant Word Multiply Subtract
SMUAD, SMUADX Signed Dual Multiply Add
SMUL[B,T] Signed Multiply (word by halfword)
SMMUL
,
SMMULR
Signed Most Significant Word Multiply
SMULL Signed Multiply (32x32), 64-bit result
SMULWB, SMULWT Signed Multiply (word by halfword)
SMUSD, SMUSDX Signed Dual Multiply Subtract
UDIV Unsigned Divide
UMAAL Unsigned Multiply Accumulate Accumulate Long
(32x32+32+32), 64-bit result
UMLAL Unsigned Multiply with Accumulate (32x32+64), 64-bit result
UMULL Unsigned Multiply (32x32), 64-bit result
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11.6.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, an d pro ducing a 32 -bit result.
Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see “Conditional Execution” .
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
Rd is the de stin a tion re gist er. I f Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in
Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least
significant 32 bits of the result in Rd.
The MLS instruction multiplies the v alues from Rn and Rm, subtracts the product from the value from Ra, and
places the least significant 32 bits of the result in Rd.
The results of thes e inst ru ctio n s do no t de pe n d on whether the operands are signed or unsigned.
Restrictions
In these instructions, do not use SP and do not use PC.
If the S suffix is used with the MUL instruction:
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
The cond suffix must not be used.
Condition Flags
If S is specified, the MUL instruction:
Updates the N and Z flags according to the result
Does not affect the C and V flags.
Examples MUL R10, R2, R5 ; Multiply, R10 = R2 x R5
MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2
MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2
MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6)
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11.6.6.2 UMULL, UMAAL, UMLAL
Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro ducing a 64-bit result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMAAL Unsigned Long Multiply with Accumulate Accumulate.
UMLAL Unsigned Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold
the accumulating value.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions interpret the values from Rn and Rm as unsigned 32-bit integers.
The UMULL instruction:
Multiplies the two unsigned integers in the first and second operands.
Writes the least significant 32 bits of the result in RdLo.
Writes the most significant 32 bits of the result in RdHi.
The UMAAL instruction:
Multiplies the two unsigned 32-bit integers in the first and second operands.
Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.
Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.
Writes the top 32-bits of the result to RdHi.
Writes the lower 32-bits of the result to RdLo.
The UMLAL instruction:
Multiplies the two unsigned integers in the first and second operands.
Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.
Writes the result back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Multiplies R5 and R6, writes the top 32 bits to R4
; and the bottom 32 bits to R0
UMAAL R3, R6, R2, R7 ; Multiplies R2 and R7, adds R6, adds R3, writes the
; top 32 bits to R6, and the bottom 32 bits to R3
UMLAL R2, R1, R3, R5 ; Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
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11.6.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLA Signed Multiply Accumulate Long (halfwords).
X and Y specifies which half of the source registers Rn and Rm are used as the
first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used
SMLAW Signed Multiply Accumulate (word by halfword).
Y specifies which half of the source register Rm is used as the second multiply
operand.
If Y is T, then the top halfword, bits [31:16] of Rm is used.
If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er. I f Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.
Adds the value in Ra to the resulting 32-bit produc t.
Writes the result of the multiplication and addition in Rd.
The non-specified halfwords of the so ur ce regi ste rs are igno re d .
The SMLAWB and SMLAWT instructions:
Multiply the 32-bit signed values in Rn with:
The top signe d ha lfwo rd of Rm, T instruction suffix.
The bottom signed halfword of Rm, B instruction suffix.
Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product
Writes the result of the multiplication and addition in Rd.
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No
overflow can occur during the multiplication.
Restrictions
In these instructions, do not use SP and do not use PC.
Condition Flags
If an overflow is detected, the
Q
flag is set.
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Examples
SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds
; R1 and writes to R5
SMLATB R5, R6, R4, R1 ; Multiplies top halfword of R6 with bottom halfword
; of R4, adds R1 and writes to R5
SMLATT R5, R6, R4, R1 ; Multiplies top halfwords of R6 and R4, adds
; R1 and writes the sum to R5
SMLABT R5, R6, R4, R1 ; Multiplies bottom halfword of R6 with top halfword
; of R4, adds R1 and writes to R5
SMLABT R4, R3, R2 ; Multiplies bottom halfword of R4 with top halfword of
; R3, adds R2 and writes to R4
SMLAWB R10, R2, R5, R3 ; Multiplies R2 with bottom halfword of R5, adds
; R3 to the result and writes top 32-bits to R10
SMLAWT R10, R2, R1, R5 ; Multiplies R2 with top halfword of R1, adds R5
; and writes top 32-bits to R10.
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11.6.6.4 SMLAD
Signed Multiply Accumulate Lo ng Dua l
Syntax op{X}{cond} Rd, Rn, Rm, Ra ;
where:
op is one of:
SMLAD Signed Multiply Accumulate Dual.
SMLADX Signed Multiply Accumulate Dual Reverse.
X specifies which halfword of the source register Rn is used as the multiply
operand.
If X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the first operand register holding the values to be multiplied.
Rm the second operand register.
Ra is the accumulate value.
Operation
The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and
SMLADX instructions:
If X is not present, multiply t he top signed halfword value in Rn with the top signed halfword of Rm and the
bottom signed halfword values in Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and
the bottom signed halfword values in Rn with the top signed halfword of Rm.
Add both multiplication results to the signed 32-bit value in Ra.
Writes the 32-bit signed result of the multiplication and addition to Rd.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SMLAD R10, R2, R1, R5 ; Multiplies two halfword values in R2 with
; corresponding halfwords in R1, adds R5 and
; writes to R10
SMLALDX R0, R2, R4, R6 ; Multiplies top halfword of R2 with bottom
; halfword of R4, multiplies bottom halfword of R2
; with top halfword of R4, adds R6 and writes to
; R0.
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11.6.6.5 SMLAL and SMLALD
Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate
Long Dual.
Syntax op{cond} RdLo, RdHi, Rn, Rm
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
MLAL Signed Multiply Accumulate Long.
SMLAL Signed Multiply Accumu late Long (halfwords, X and Y).
X and Y specify which halfword of the source registers Rn and Rm are used as
the first and second multiply operand:
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLALD Signed Multiply Accumulate Long Dual.
SMLALDX Signed Multiply Accumulate Long Dual Reversed.
If the X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers.
RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer.
For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA
LDX, they also hold the ac cu mu la ting valu e .
Rn, Rm are registers holding the first and second operands.
Operation
The SMLAL instruction:
Multiplies the two’s complement signed word values from Rn and Rm.
Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The non-specified halfwords of the so ur ce regi ste rs are igno re d .
The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement
signed 16-bit integers. These instructions:
If X is not present, multiply t he top signed halfword value of Rn with the top signed halfword of Rm and the
bottom signed halfword values of Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and
the bottom signed halfword values of Rn with the top signed halfword of Rm.
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Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit
product.
Write the 64-bit product in RdLo and RdHi.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMLAL R4, R5, R3, R8 ; Multiplies R3 and R8, adds R5:R4 and writes to
; R5:R4
SMLALBT R2, R1, R6, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R7, sign extends to 32-bit, adds
; R1:R2 and writes to R1:R2
SMLALTB R2, R1, R6, R7 ; Multiplies top halfword of R6 with bottom
; halfword of R7,sign extends to 32-bit, adds R1:R2
; and writes to R1:R2
SMLALD R6, R8, R5, R1 ; Multiplies top halfwords in R5 and R1 and bottom
; halfwords of R5 and R1, adds R8:R6 and writes to
; R8:R6
SMLALDX R6, R8, R5, R1 ; Multiplies top halfword in R5 with bottom
; halfword of R1, and bottom halfword of R5 with
; top halfword of R1, adds R8:R6 and writes to
; R8:R6.
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11.6.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax op{X}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Ra is the re gis ter ho ldin g th e acc um u lat e valu e .
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-b it halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwo rds.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-b it halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the resul t of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplicat ion s or subt ra ctio n .
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom
; halfword of R5, multiplies top halfword of R4
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; with top halfword of R5, subtracts second from
; first, adds R6, writes to R0
SMLSDX R1, R3, R2, R0 ; Multiplies bottom halfword of R3 with top
; halfword of R2, multiplies top halfword of R3
; with bottom halfword of R2, subtracts second from
; first, adds R0, writes to R1
SMLSLD R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with bottom
; halfword of R2, multiplies top halfword of R6
; with top halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3
SMLSLDX R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R2, multiplies top halfword of R6
; with bottom halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3.
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11.6.6.7 SMMLA and SMMLS
Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract
Syntax op{R}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMMLA Signed Most Significant Word Multiply Accumulate.
SMMLS Signed Most Significant Word Multiply Subtract.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second multiply operands.
Ra is the re gis ter ho ldin g th e acc um u lat e valu e .
Operation
The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLA instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Adds the value of Ra to the signed extracted value.
Writes the result of the addition in Rd.
The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLS instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Subtracts the extract ed valu e of the resu lt fro m th e va lue in Ra.
Writes the result of the subtraction in Rd.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMMLA R0, R4, R5, R6 ; Multiplies R4 and R5, extracts top 32 bits, adds
; R6, truncates and writes to R0
SMMLAR R6, R2, R1, R4 ; Multiplies R2 and R1, extracts top 32 bits, adds
; R4, rounds and writes to R6
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SMMLSR R3, R6, R2, R7 ; Multiplies R6 and R2, extracts top 32 bits,
; subtracts R7, rounds and writes to R3
SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
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11.6.6.8 SMMUL
Signed Most Significant Word Multiply
Syntax op{R}{cond} Rd, Rn, Rm
where:
op is one of:
SMMUL Signed Most Significant Word Multiply.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The
SMMUL instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL R0, R4, R5 ; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0
SMULLR R6, R2 ; Multiplies R6 and R2, rounds the top 32 bits
; and writes to R6.
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11.6.6.9 SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax op{X}{cond} Rd, Rn, Rm
where:
op is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
SMUSDX Signed Dual Multiply Subtract Reversed.
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in ea ch
operand. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Adds the two multiplication results together.
Writes the result of the addition to the destination register.
The SMUSD instruction interprets the va lues from the first and second operands as two’s complement signed
integers. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.
Writes the result of the subtraction to the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
Examples
SMUAD R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom
; halfword of R5, adds multiplication of top halfword
; of R4 with top halfword of R5, writes to R0
SMUADX R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword
; of R4, adds multiplication of top halfword of R7
; with bottom halfword of R4, writes to R3
SMUSD R3, R6, R2 ; Multiplies bottom halfword of R4 with bottom halfword
; of R6, subtracts multiplication of top halfword of R6
; with top halfword of R3, writes to R3
SMUSDX R4, R5, R3 ; Multiplies bottom halfword of R5 with top halfword of
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; R3, subtracts multiplication of top halfword of R5
; with bottom halfword of R3, writes to R4.
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11.6.6.10 SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword)
Syntax op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op is one of:
SMUL{XY} Signed Multiply (halfwords).
X and Y specify which halfword of the source registers Rn and Rm is used as
the first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0] of Rn is used.
If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot
tom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMULW{Y} Signed Multiply (word by halfword).
Y specifies which halfword of the source register Rm is used as the second mul
tiply operand.
If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
If Y is T, then the top halfword (bits [31:16]) of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions inter prets th e va lues fr om Rn and Rm as four signed
16-bit integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Writes the 32-bit result of the multiplication in Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Examples
SMULBT R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; top halfword of R5, multiplies results and
; writes to R0
SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; bottom halfword of R5, multiplies results and
; writes to R0
SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top
; halfword of R5, multiplies results and writes
; to R0
SMULTB R0, R4, R5 ; Multiplies the top halfword of R4 with the
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; bottom halfword of R5, multiplies results and
; and writes to R0
SMULWT R4, R5, R3 ; Multiplies R5 with the top halfword of R3,
; extracts top 32 bits and writes to R4
SMULWB R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,
; extracts top 32 bits and writes to R4.
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11.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long M ultiply, with optional Accumulate, using 32-bit operands and producing a 64-bit
result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Lo ng Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accu
mulating value.
Rn, Rm are registers holding the operands.
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers,
adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to
RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers and plac es the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the
result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result
back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
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11.6.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er. I f Rd is omitted, the destination register is Rn.
Rn is the re gis ter ho ldin g th e valu e to be div ide d.
Rm is a re gis te r ho ldin g the divisor.
Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1
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11.6.7 Saturating Instructions
The table below shows the saturating instructions:
For signed n-bit saturation, this means that:
If the value to be saturated is less than -2n-1, the result returned is -2n-1
If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1
Otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation, this means that:
If the value to be saturated is less than 0, the result returned is 0
If the value to be saturated is greater than 2n-1, the result returned is 2n-1
Otherwise, the result returned is the same as the value to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the
MSR
instruction must be used; see “MSR” .
To read the state of the Q flag, the
MRS
instruction must be used; see “MRS” .
Table 11-22. Saturating Instructions
Mnemonic Description
SSAT Signed Saturate
SSAT16 Signed Saturate Halfword
USAT Unsi gned Saturate
USAT16 Unsigned Saturate Halfword
QADD Saturating Add
QSUB Saturating Subtract
QSUB16 Saturating Subtract 16
QASX Saturating Add and Subtract with Exchange
QSAX Saturating Subtract and Add with Exchange
QDADD Saturating Double and Add
QDSUB Saturating Double and Subtract
UQADD16 Unsigned Saturating Add 16
UQADD8 Unsigned Saturating Add 8
UQASX Unsigned Saturati ng Add and Subtract with Exchange
UQSAX Unsigned Saturati ng Subtract and Add with Exchange
UQSUB16 Unsigned Saturating Subtract 16
UQSUB8 Unsigned Saturating Subtract 8
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11.6.7.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
Syntax op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination re gist er.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 31 for USAT.
to 32 for SSAT
Rm is the register containing the value to saturate.
shift #s is an optional shift applied to Rm before saturating. It must be one of the
following:
ASR #s where s is in the range 1 to 31.
LSL #s where s is in the range 0 to 31.
Operation
These instructions saturate to a signed or unsigned n-bit value.
The
SSAT
instruction applies the specified shift, then saturates to the signed range -2n–1 £x£2
n–1-1.
The
USAT
instruction applies the specified shift, then saturates to the unsigned range 0 £ x£2
n-1.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
; saturate it as a signed 16-bit value and
; write it back to R7
USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0.
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11.6.7.2 SSAT16 and USAT16
Signed Saturate and Unsigned Saturate to any bit position for two halfwords.
Syntax op{cond} Rd, #n, Rm
where:
op is one of:
SSAT16 Saturates a signed halfword value to a signed range.
USAT16 Saturates a signed halfword value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination re gist er.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 15 for USAT.
to 16 for SSAT
Rm is the register containing the value to saturate.
Operation
The SSAT16 instruction:
Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two signed 16-bit halfwords to the destination register.
The USAT16 instruction:
Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two unsigned halfwords in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT16 R7, #9, R2 ; Saturates the top and bottom highwords of R2
; as 9-bit values, writes to corresponding halfword
; of R7
USAT16NE R0, #13, R5 ; Conditionally saturates the top and bottom
; halfwords of R5 as 13-bit values, writes to
; corresponding halfword of R0.
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11.6.7.3 QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a
signed saturated value in the destination register.
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed
range -2n–1 £x£2
n–1-1, where x is given by the number of bits applied in the instr uction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit
and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see “MSR” .
To read the state of the Q flag, the MRS instruction must be used; see “MRS” .
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
QADD16 R7, R4, R2 ; Adds halfwords of R4 with corresponding halfword of
; R2, saturates to 16 bits and writes to
; corresponding halfword of R7
QADD8 R3, R1, R6 ; Adds bytes of R1 to the corresponding bytes of R6,
; saturates to 8 bits and writes to corresponding
; byte of R3
QSUB16 R4, R2, R3 ; Subtracts halfwords of R3 from corresponding
; halfword of R2, saturates to 16 bits, writes to
; corresponding halfword of R4
QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte
; in R2, saturates to 8 bits, writes to corresponding
; byte of R4.
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11.6.7.4 QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QASX Add and Subtract with Exchange and Saturate.
QSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The QASX instruction:
1. Adds the top halfword of the source operand with the bottom halfword of the second operand.
2. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
3. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where x equals 16, to the bottom halfword of the destination register.
4. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the source operand with the top halfword of the second operan d.
3. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where
x
equals 16, to the bottom halfword of the destination register.
4. Saturates the result of the subtraction and wr ites a 16-bit signed inte ger in the range –2 15 ≤ x ≤ 215 – 1, where
x
equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
QASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top highword of R2 from bottom halfword of
; R4, saturates to 16 bits and writes to bottom halfword
; of R7
QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3, saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R3 to top halfword of R5,
; saturates to 16 bits, writes to bottom halfword of R0.
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11.6.7.5 QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QDADD Saturatin g Dou b le an d Ad d.
QDSUB Saturating Double and Subtract.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rm, Rn are registers holding the firs t and second operands.
Operation
The QDADD instruction:
Doubles the second operand value.
Adds the result of the doubling to the signed saturated value in the first operand.
Writes the result to the destination register.
The QDSUB instruction:
Doubles the second operand value.
Subtracts the doubled value from the signed saturated value in the first operand.
Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –
231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD R7, R4, R2 ; Doubles and saturates R4 to 32 bits, adds R2,
; saturates to 32 bits, writes to R7
QDSUB R0, R3, R5 ; Subtracts R3 doubled and saturated to 32 bits
; from R5, saturates to 32 bits, writes to R0.
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11.6.7.6 UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax op{cond} {Rd}, Rm, Rn
where:
type is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn, Rm are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with the top halfword of the second operand.
2. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range
0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4. Saturates the result of the subtra ction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the first operand with the top halfword of the second operand.
3. Saturates the result of the subtraction and writes a 16-bit un signed intege r in the range 0 ≤ x ≤ 216 – 1, where
x
equals 16, to the top halfword of the destination register.
4. Saturates the results of th e additio n and wr ites a 16-b it unsigned integ er in the range 0 ≤ x ≤ 216 – 1, where
x
equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4, saturates to 16 bits, writes to bottom halfword of R7
UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of R3,
; saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R4 to top halfword of R5
; saturates to 16 bits, writes to bottom halfword of R0.
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11.6.7.7 UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op is one of:
UQADD8 Saturating four unsigned 8-bit integer additions.
UQADD16 Saturating two unsigned 16 -bit integer additions.
UDSUB8 Saturating four unsigned 8-bit integer subtractions.
UQSUB16 Saturating two unsigned 16-bit integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the
destination register.
The UQADD16 instruction:
Adds the respective top and bottom halfwords of the first and second operands.
Saturates the result of the additions for each halfword in the destination register to the unsigned range
0£x£2
16-1, where x is 16.
The UQADD8 instruction:
Adds each respective byte of the first and second operands.
Saturates the result of the addition for each byte in the destination register to the unsigned range 0 £ x£2
8-
1, where x is 8.
The UQSUB16 instruction:
Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
Saturates the result of the dif ference s in the destin ation register to the unsigned r ange 0 £ x£2
16-1, where x
is 16.
The UQSUB8 instructions:
Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
Saturates the results of the differences for each byte in the destination register to the unsigned range
0£x£2
8-1, where x is 8.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQADD16 R7, R4, R2 ; Adds halfwords in R4 to corresponding halfword in R2,
; saturates to 16 bits, writes to corresponding halfword of R7
UQADD8 R4, R2, R5 ; Adds bytes of R2 to corresponding byte of R5, saturates
; to 8 bits, writes to corresponding bytes of R4
UQSUB16 R6, R3, R0 ; Subtracts halfwords in R0 from corresponding halfword
; in R3, saturates to 16 bits, writes to corresponding
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; halfword in R6
UQSUB8 R1, R5, R6 ; Subtracts bytes in R6 from corresponding byte of R5,
; saturates to 8 bits, writes to corresponding byte of R1.
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11.6.8 Packing and Unpacking Instructions
The table below shows the instructions that operate on packing and unpacking data:
Table 1 1-23. Packing and Unpacking Instructions
Mnemonic Description
PKH Pack Halfword
SXTAB Extend 8 bits to 32 and add
SXTAB16 Dual extend 8 bits to 16 and add
SXTAH Extend 16 bits to 32 and add
SXTB Sign extend a byte
SXTB16 Dual extend 8 bits to 16 and add
SXTH Sign extend a halfword
UXTAB Extend 8 bits to 32 and add
UXTAB16 Dual extend 8 bits to 16 and add
UXTAH Extend 16 bits to 32 and add
UXTB Zero extend a byte
UXTB16 Dual zero extend 8 bits to 16 and add
UXTH Zero extend a halfword
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11.6.8.1 PKHBT and PKHTB
Pack Halfword
Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the firs t ope r an d re gis te r
Rm is the second operand register holding the value to be optionally shifted.
imm is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.
2. If shifted, the shifted value of the second operand is written to the top halfword of the de stin a tio n re gist er.
The PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfword of the destination register.
2. If shifted, the shifted value of the second op erand is written to the bottom halfword of the destination register.
Restrictions
Rd
must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
PKHBT R3, R4, R5 LSL #0 ; Writes bottom halfword of R4 to bottom halfword of
; R3, writes top halfword of R5, unshifted, to top
; halfword of R3
PKHTB R4, R0, R2 ASR #1 ; Writes R2 shifted right by 1 bit to bottom halfword
; of R4, and writes top halfword of R0 to top
; halfword of R4.
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11.6.8.2 SXT and UXT
Sign extend and Zero extend.
Syntax op{cond} {Rd,} Rm {, ROR #n}
op{cond} {Rd}, Rm {, ROR #n}
where:
op is one of:
SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH Sign extends a 16-bit value to a 32-bit value.
SXTB16 Sign extends two 8-bit values to two 16-bit values.
UXTB Zero extend s an 8-bit valu e to a 32 -b it va lue .
UXTH Zero extends a 16-bit value to a 32-bit value.
UXTB16 Zero extends two 8-bit values to two 16-bit values.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
SXTB16 extracts bits[7:0] and sign extends to 16 bits,
and extracts bits [23:16] and sign extends to 16 bits.
UXTB16 extracts bits[7:0] and zero extends to 16 bits,
and extracts bits [23:16] and zero extends to 16 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH R4, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom halfword of
; of result, sign extends to 32 bits and writes to R4
UXTB R3, R10 ; Extracts lowest byte of value in R10, zero extends, and
; writes to R3.
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11.6.8.3 SXTA and UXTA
Signed and Unsigned Extend and Add
Syntax op{cond} {Rd,} Rn, Rm {, ROR #n}
op{cond} {Rd,} Rn, Rm {, ROR #n}
where:
op is one of:
SXTAB Sign extends an 8-bit value to a 32-bit value and add.
SXTAH Sign extends a 16-bit value to a 32-bit value and add.
SXTAB16 Sign extends two 8-bit values to two 16-bit values and add.
UXTAB Zero extends an 8-bit value to a 32-bit value and add.
UXTAH Zero extends a 16-bit value to a 32-bit value and add.
UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tio n regist er.
Rn is the firs t ope r an d re gis te r.
Rm is the register holding the value to rotate and extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.
UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.
SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.
UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.
SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits,
and extracts bits [23:16] from Rm and sign extends to 16 bits.
UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits,
and extracts bits [23:16] from Rm and zero extends to 16 bits.
3. Adds the signed or zero extended value to th e wo rd or corre sponding halfwo rd o f Rn and writes the result in
Rd.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
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SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom
; halfword, sign extends to 32 bits, adds
; R8,and writes to R4
UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends
; to 32 bits, adds R4, and writes to R3.
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11.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields:
Table 1 1-24. Packing and Unpacking Instructions
Mnemonic Description
BFC Bit Field Clear
BFI Bit Field Insert
SBFX Signed Bit Field Extract
SXTB Sign extend a byte
SXTH Sign extend a halfword
UBFX Unsigned Bit Field Extract
UXTB Zero extend a byte
UXTH Zero extend a halfword
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11.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are
unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit
position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
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11.6.9.2 SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
Syntax SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
SBFX extracts a bitfield from one register , sign extends it to 32 bits, and writes the r esult to the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destin ation
register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the flags.
Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8.
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11.6.9.3 SXT and UXT
Sign extend and Zero extend.
Syntax SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower
; halfword of the result and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3.
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11.6.10 Branch and Control Instructions
The table below shows the branch and control instructions:
Table 11-25. Branch and Control Instr uction s
Mnemonic Description
BBranch
BL Branch with Link
BLX Branch indire ct with Link
BX Branch indirect
CBNZ Compare and Branch if Non Zero
CBZ Compare and Branch if Zero
IT If-Then
TBB Table Branch Byte
TBH Table Branch Halfword
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11.6.10.1 B, BL, BX, and BLX
Branch instructions.
Syntax B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (imm e dia te ).
BL is branch with link (imme dia te ).
BX is branch indirect (register).
BLX is bran ch indire ct with link (register).
cond is an optional condition code, see “Conditional Execution” .
label is a PC-relative expres sio n. See “PC-relative Expressions” .
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm
must be 1, but the address to branch to is created by changing bit[0] to 0.
Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instruc tion s writ e th e ad dr es s of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch
instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” .
The table below shows the ranges fo r the various branch instructions.
The .W suffix might be used to get the ma ximum branch range. See “Instruction Width Selection” .
Restrictions
The restrictions are:
Do not use PC in the BLX instruction
For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address
created by changing bit[0] to 0
When any of thes e inst ru ctio n s is inside an IT bl oc k, it must be the last instruction of the IT block.
B
cond is the only conditional instruction that is not re quired to be inside an IT block. However, it has a longer
branch range when it is inside an IT block.
Table 11-26. Branch Ranges
Instruction Branch Ran ge
B label −16 MB to +16 MB
Bcond label
(outside IT block) −1 MB to +1 MB
Bcond label
(inside IT block) −16 MB to +16 MB
BL{cond} label −16 MB to +16 MB
BX{cond} Rm Any value in register
BLX{cond} Rm Any value in register
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Condition Flags
These instructions do not change the flags.
Examples
B loopA ; Branch to loopA
BLE ng ; Conditionally branch to label ng
B.W target ; Branch to target within 16MB range
BEQ target ; Conditionally branch to target
BEQ.W target ; Conditionally branch to target within 1MB
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX LR ; Return from function call
BXNE R0 ; Conditionally branch to address stored in R0
BLX R0 ; Branch with link and exchange (Call) to a address stored in R0.
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11.6.10.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
Syntax CBZ Rn, label
CBNZ Rn, label
where:
Rn is the re gis ter ho ldi n g the op erand.
label is the branch destinatio n .
Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of
instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BEQ label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BNE label
Restrictions
The restrictions are:
Rn must be in the range of R0 to R7
The branch destination must be within 4 to 130 bytes after the instruction
These instructions must not be used inside an IT block.
Condition Flags
These instructions do not change the flags.
Examples CBZ R5, target ; Forward branch if R5 is zero
CBNZ R0, target ; Forward branch if R0 is not zero
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11.6.10.3 IT
If-Then condition instruction.
Syntax IT{x{y{z}}} cond
where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruc tion in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be eith er:
T Then. Applies the condition cond to the instruction.
E Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in
the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some
of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT
block.
The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their
syntax.
The asse mbler mig ht be able to gener ate the required I T instructions for conditional instructions automatically, so
that the user does not have to write them. See the assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an
exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked
PSR.
Instructions designed for use for exception re turns can be used as normal to return from the exception, and
execution of the IT block resumes corre ctly. This is the only way that a PC-modifying instruction is permitted to
branch to an instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
IT
CBZ and CBNZ
CPSID and CPSIE.
Other restric tio ns wh en usin g an IT block ar e:
A branch or any instruction that modifies the PC must either be outside an IT block or must be the last
instruction inside the IT block. These are:
ADD PC, PC, Rm
MOV PC, Rm
B, BL, BX, BLX
Any LDM, LDR, or POP instruction that writes to the PC
TBB and TBH
Do not branch to any instruction inside an IT block, except when returning from an exception handler
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All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside
an IT block but has a larger branch range if it is inside one
Each instruction inside the IT block must specify a condition code suffix that is either the same or logical
inverse as for the other instructions in the block.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler
directives within them.
Condition Flags
This instruction does not change the flags.
Example ITTE NE ; Next 3 instructions are conditional
ANDNE R0, R0, R1 ; ANDNE does not update condition flags
ADDSNE R2, R2, #1 ; ADDSNE updates condition flags
MOVEQ R2, R3 ; Conditional move
CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
ITE GT ; Next 2 instructions are conditional
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLE R1, R0, #48 ; Convert 0x0 -> '0'
IT GT ; IT block with only one conditional instruction
ADDGT R1, R1, #1 ; Increment R1 conditionally
ITTEE EQ ; Next 4 instructions are conditional
MOVEQ R0, R1 ; Conditional move
ADDEQ R2, R2, #10 ; Conditional add
ANDNE R3, R3, #1 ; Conditional AND
BNE.W dloop ; Branch instruction can only be used in the last
; instruction of an IT block
IT NE ; Next instruction is conditional
ADD R0, R0, R1 ; Syntax error: no condition code used in IT block
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11.6.10.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword
offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch
offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the
unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
Restrictions
The restrictions are:
Rn must not be SP
Rm must not be SP and must not be PC
When any of thes e inst ru ctio n s is used inside an IT bl ock, it must be the last instruction of the IT block.
Condition Flags
These instructions do not change the flags.
Examples ADR.W R0, BranchTable_Byte
TBB [R0, R1] ; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB 0 ; Case1 offset calculation
DCB ((Case2-Case1)/2) ; Case2 offset calculation
DCB ((Case3-Case1)/2) ; Case3 offset calculation
TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation
DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation
DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation
CaseA
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; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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11.6.11 Miscellaneous Instructions
The table below shows the remaining Cortex-M4 instructions:
Table 11-27. Miscellaneous Instructions
Mnemonic Description
BKPT Breakpoint
CPSID Change Processor State, Disable Interrupts
CPSIE Change Processor State, Enable Interrupts
DMB Data Memory Barrier
DSB Data Synchronization Barrier
ISB Instruction Synchronization Barrier
MRS Move from special register to register
MSR Move from register to special register
NOP No Operation
SEV Send Event
SVC Supervisor Call
WFI Wait For Interrupt
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11.6.11.1 BKPT
Breakpoint.
Syntax BKPT #imm
where:
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system
state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional information a bout the
breakpoint.
The BKPT instruction can be placed inside an IT b lock, bu t it executes unconditionally, unaffected by the condition
specified by the IT instruction.
Condition Flags
This instruction does not change the flags.
Examples
BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
Note: ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other
than Semi-hosting.
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11.6.11.2 CPS
Change Processor State.
Syntax CPSeffect iflags
where:
effect is one of:
IE Clears the special purpose register.
ID Sets the specia l pu rpos e re gis ter .
iflags is a sequ en ce of on e or mor e flags :
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more
information about these registers.
Restrictions
The restrictions are:
Use CPS only from privileged software, it has no effect if used in unprivileged software
CPS cannot be conditional and so must not be used inside an IT block.
Condition Flags
This instruction does not change the condition flags.
Examples
CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)
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11.6.11.3 DMB
Data Memory Barrier.
Syntax DMB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order,
before the DMB instruction are completed before any explicit memory accesses that appear, in program order ,
after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access
memory.
Condition Flags
This instruction does not change the flags.
Examples DMB ; Data Memory Barrier
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11.6.11.4 DSB
Data Synchronization Barrier.
Syntax DSB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DSB acts as a special data synchro nization memory barrier. Instructions that come after the DSB, in program
order, do not execute until the DSB instru ction completes. The DSB instruction completes when all explicit memory
accesses before it complete.
Condition Flags
This instruction does not change the flags.
Examples DSB ; Data Synchronisation Barrier
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11.6.11.5 ISB
Instruction Synchronization Barrier.
Syntax ISB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
ISB acts as an instruction synchr onization barrier. It flushes the pipeline o f the processor, so that all instruction s
following the ISB are fetched from memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples ISB ; Instruction Synchronisation Barrier
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11.6.11.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax MRS{cond} Rd, spec_reg
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the de stin a tion re gist er .
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to
clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These
operations use MRS in the state-sa ving instruction sequence and MSR in the state-restoring in struction sequence.
Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
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11.6.11.7 MSR
Move the contents of a general-purpose register into the specified special register.
Syntax MSR{cond} spec_reg, Rn
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the source register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can only access the
APSR. See “Application Program Status Register” . Privileged software can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note: W hen the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
See “MRS” .
Restrictions
Rn must not be SP and must not be PC.
Condition Flags
This instruction up da te s th e flag s ex plicit ly ba sed on the va lue in Rn.
Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
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11.6.11.8 NOP
No Operation.
Syntax NOP{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the
pipeline befo re it reac he s th e exe cu tio n sta g e.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Condition Flags
This instruction does not change the flags.
Examples NOP ; No operation
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11.6.11.9 SEV
Send Event.
Syntax SEV{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register to 1, see “Power Management” .
Condition Flags
This instruction does not change the flags.
Examples SEV ; Send Event
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11.6.11.10 SVC
Supervisor Call.
Syntax SVC{cond} #imm
where:
cond is an optional condition code, see “Conditional Execution” .
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the proce ssor. If r equired, it can be retrieve d by th e except ion han dler to deter mine what service
is being requested.
Condition Flags
This instruction does not change the flags.
Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
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11.6.11.11 WFI
Wait for Interrupt.
Syntax WFI{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
An exception
A Debug Entry request, regardless of whether Debug is enabled.
Condition Flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
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11.7 Cortex-M4 Core Peripherals
11.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interr up t pr oc es sing . See Section 11.8 “Nested Vectored Interrupt Contr oller (NVIC)”
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See Section 11.9 “System Control Block (SCB)”
System Timer (SysTick)
The System Timer , SysT ick , is a 24-b it co un t- down time r. Use this as a Real Tim e Opera tin g Syste m
(RTOS) tick timer or as a simple counter. See Section 11.10 “System Timer ( S ysTick)”
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See Section 11.11 “Memory Protection Unit (MPU)”
11.7.2 Address Map
The addre ss ma p of the Priv at e pe rip her al bu s (PPB) is:
In register descriptions:
The required privilege gives the privilege level required to access the register, as follows:
Privileged: Only privileged software can access the register.
Unprivileged: Both unprivileged and privileged software can access the register.
Table 11-28. Core Peripheral Register Regions
Address Core Peripheral
0xE000E008-0xE000E00F System Control Block
0xE000E010-0xE000E01F System Timer
0xE000E100-0xE000E4EF Nested Vectored Interrupt Controlle r
0xE000ED00-0xE000ED3F System control block
0xE000ED90-0xE000EDB8Memory Protection Unit
0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller
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11.8 Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
1 to 30 interrupts.
A programmab le pr ior ity level of 0-15 for each int er rupt . A high er level co rr es po nd s to a lower priorit y, so
level 0 is the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NM I)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction ov er he a d. This pr ov id es low latency ex ception handling.
11.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request.
When the processor enters the ISR, it au tomatically removes the pendin g state fr om the inte rrupt (se e “Hardware
and Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the
processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR
again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
11.8.1.1 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending
Registers” , or to the NVIC_STIR register to make an interrupt pending, see “Softw ar e Tr ig ge r Int er ru p t
Register” .
A pending interrupt remains pending until one of the following :
The processor enters th e ISR for the inte rrupt. This changes the sta te of the interrup t from pendin g to active.
Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to
inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not
change. Otherwise, the state of the interrupt changes to inactive.
11.8.2 NVIC Design Hints and Tips
Ensure that the software uses corre ctly aligned register accesses. The processor does n ot support unaligned
accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from
taking that interrupt.
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Before programming SCB_VTOR to relocate the vector table, ensure th at the vector table entries of the new vector
table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the
“Vector Table Offset Register” .
11.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS prov ides
the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
The array ISER[0] corresponds to the registers ISER0
The array ICER[0] corresponds to the registers ICER0
The array ISPR[0] corresponds to the registers ISPR0
The array ICPR[ 0] cor re sp o nd s to the re gisters ICPR0
The array IABR[0]corresponds to the registers IABR0
The 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to
IP[29] corres po nd s to the re gis te rs IPR0 - IPR7 , an d the ar ra y en try IP[ n] holds the interrupt priority for
interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 11-30
shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables
that have one bit per interrupt.
Notes: 1. Each array element corresponds to a single NVIC register, for example the
ICER[0]
element corresponds to the ICER0
register.
Table 11-29. CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn _t IRQn) Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn
void NVIC_SystemReset (void) Reset the system
Table 11-30. Mapping of Interrupts to the Interrupt Variables
Interrupts
CMSIS Array Elements(1)
Set-enable Clear-enable Set-pending Clear-pending Active Bit
0-29 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0]
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11.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface
Table 11-31. Nested Vectored Interrup t Contr oller (NVIC) Register Mapping
Offset Register Name Access Reset
0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read-write 0x00000000
... ... ... ... ...
0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read-write 0x00000000
0XE000E180 Interrupt Clear-enable Register0 NVIC_ICER0 Read-write 0x0000 0000
... ... ... ... ...
0xE000E19C Interrupt Clear-enable Register 7 NVIC_ICER7 Read-write 0 x00000000
0XE000E200 Interrupt Set-pending Register 0 NVIC_ISPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E21C Interrupt Set-pending Register 7 NVIC_ISPR7 Read-write 0x00000000
0XE000E280 Interrupt Clear-pending Register 0 NVIC_ICPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E29C Interrupt Clear-pending Register 7 NVIC_ICPR7 Read-write 0x0000000 0
0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read-write 0x00000000
... ... ... ... ...
0xE000E31C Interrupt Active Bit Register 7 NVIC_IABR7 Read-write 0x00000000
0xE000E400 Interrupt Priority Register 0 NVIC_IPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E41C Interrupt Priority Register 7 NVIC_IPR7 Read-write 0x00000000
0xE000EF00 S oftware Trigger Interrupt Register NVIC_STIR Write-only 0x0000 0000
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11.8.3.1 Interrupt Set-enable Registers
Name: NVIC_ISERx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates
the interrupt, regardless of its priority.
31 30 29 28 27 26 25 24
SETENA
23 22 21 20 19 18 17 16
SETENA
15 14 13 12 11 10 9 8
SETENA
76543210
SETENA
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11.8.3.2 Interrupt Clear-enable Registers
Name: NVIC_ICERx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers disable interrupts, and show which interrup ts are enabled.
• CLRENA: Interrupt Clear-enable
Write:
0: No effect.
1: Disables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
31 30 29 28 27 26 25 24
CLRENA
23 22 21 20 19 18 17 16
CLRENA
15 14 13 12 11 10 9 8
CLRENA
76543210
CLRENA
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11.8.3.3 Interrupt Set-pending Registers
Name: NVIC_ISPRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers force interrupts into the pending state, and show which interrupts are pending.
• SETPEND: Interrupt Set-pending
Write:
0: No effect.
1: Changes the interrupt state to pending.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Notes: 1. Writing 1 to an ISPR bit corresponding to an interrupt that is pending has no effect.
2. Writing 1 to an ISPR bit corresponding to a disabled in terrupt sets the state of that interrupt to pending.
31 30 29 28 27 26 25 24
SETPEND
23 22 21 20 19 18 17 16
SETPEND
15 14 13 12 11 10 9 8
SETPEND
76543210
SETPEND
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11.8.3.4 Interrupt Clear-pending Registers
Name: NVIC_ICPRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers remove the pending state from interrupts, and show which interrupts are pending.
• CLRPEND: Interrupt Clear-pending
Write:
0: No effect.
1: Removes the pending state from an interrupt.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
31 30 29 28 27 26 25 24
CLRPEND
23 22 21 20 19 18 17 16
CLRPEND
15 14 13 12 11 10 9 8
CLRPEND
76543210
CLRPEND
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11.8.3.5 Interrupt Active Bit Registers
Name: NVIC_IABRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers indicate which interrupts are active.
• ACTIVE: Interrupt Active Flags
0: Interrupt is not active.
1: Interrupt is active.
Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
31 30 29 28 27 26 25 24
ACTIVE
23 22 21 20 19 18 17 16
ACTIVE
15 14 13 12 11 10 9 8
ACTIVE
76543210
ACTIVE
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11.8.3.6 Interrupt Priority Registers
Name: NVIC_IPRx [x=0..7]
Access: Read-write
Reset: 0x000000000
The NVIC_IP R0- NVI C_IPR7 registers pro vid e a 4- bit prio rity field fo r ea ch inter ru pt. Th e s e reg is te rs ar e by te -a cce ss ib le .
Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array
IP[0]
to
IP[29]
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes: 1. Each priority field holds a priority value, 0-
15
. The lower the value, the greater the priority of the corresponding interrupt. The
processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes.
2. for more information about the IP[0] to IP[
29
] interrupt priority array, that provides the software view of the interrupt priorities,
see Table 11-29, “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
31 30 29 28 27 26 25 24
PRI3
23 22 21 20 19 18 17 16
PRI2
15 14 13 12 11 10 9 8
PRI1
76543210
PRI0
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11.8.3.7 Software Trigger Interrupt Register
Name: NVIC_STIR
Access: Write-only
Reset: 0x000000000
Write to this register to generate an interrupt from the software.
• INTID: Interrupt ID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of
0x03
specifies interrupt IRQ3.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––INTID
76543210
INTID
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11.9 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:
Except for the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it must use aligned word accesses
For the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
1. Read and save the MMFAR or SCB_BFAR value.
2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The
SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
The software must follow this seque nce because anothe r higher prior ity exception might change the SCB_MMFAR
or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault
might change the SCB_MMFAR or SCB_BFAR value.
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11.9.1 System Control Block (SCB) User Interface
Notes: 1. See the register descriptio n for more information.
2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits),
“BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16
bits).
Table 11-32. System Control Block (SCB) Register Mapping
Offset Register Name Access Reset
0xE000E008 Auxiliary Control Register SCB_ACTLR Read-write 0x00000000
0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240
0xE000ED04 Interrupt Control and State Register SCB_ICSR Read-write(1) 0x00000000
0xE000ED08 Vector Table Offset Register SCB_VTOR Read-write 0x00000000
0xE000ED0C Application Interrupt and Reset Control Register SCB_AIRCR Read-write 0xFA050000
0xE000ED10 System Control Register SCB_SCR Read-write 0x00000000
0xE000ED14 Configuration and Control Register SCB_CCR Read-write 0x00000200
0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read-write 0x00000000
0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read-write 0x00000000
0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read-write 0x00000000
0xE000ED24 System Handler Control and State Register SCB_SHCSR Read-write 0x00000000
0xE000ED28 Configurable Fault Status Register SCB_CFSR(2) Read-write 0x00000000
0xE000ED2C HardFault Status Register SCB_HFSR Read-write 0x00000000
0xE000ED34 MemManage Fault Address Register SCB_MMFAR Read-write Unknown
0xE000ED38 BusFault Address Register SCB_BF AR Read-write Unknown
0xE000ED3C Auxiliary Fault Status Register SCB_AFSR Read-write 0x00000000
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11.9.1.1 Auxiliary Control Register
Name: SCB_ACTLR
Access: Read-write
Reset: 0x000000000
The SCB_ACTLR register provides disable bits for the following processor functions:
IT folding
Write buffer use for accesses to the default memory map
Interruption of multi-cycle instructions.
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally
require modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must
avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise
but decreases the performance, as any store to mem ory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the in terrupt
latency of the processor, as any LDM or STM must complete before th e processor can stack the curren t state and enter the
interrupt hand le r.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– DISOOFP DISFPCA
76543210
–DISFOLD DISDEFWBUF DISMCYCINT
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11.9.1.2 CPUID Base Register
Name: SCB_CPUID
Access: Read-write
Reset: 0x000000000
The SCB_CPUID register contains the processor part number, version, and implementation information.
• Implementer: Implementer Code
0x41: ARM.
• Variant: Variant Number
It is the r value in the rnpn pro d uct revis ion iden tif ier :
0x0: Revision 0.
• Constant
Reads as 0xF.
• PartNo: Part Number of the Processor
0xC24 = Cortex-M4.
• Revision: Revision Number
It is the p value in the rnpn product revision identifier:
0x0: Patch 0.
31 30 29 28 27 26 25 24
Implementer
23 22 21 20 19 18 17 16
Variant Constant
15 14 13 12 11 10 9 8
PartNo
76543210
PartNo Revision
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11.9.1.3 Interrupt Control and State Register
Name: SCB_ICSR
Access: Read-write
Reset: 0x000000000
The SCB_ICSR register provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions.
It indicates:
The exception number of the exception being processed, and whether there are preempted active
exceptions,
The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the p rocessor nor mally ente rs the NMI except ion handler as soon as it register s a
write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if
the NMI signal is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
31 30 29 28 27 26 25 24
NMIPENDSET – PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR –
23 22 21 20 19 18 17 16
– ISRPENDING VECTPENDING
15 14 13 12 11 10 9 8
VECTPENDING RETTOBASE – VECTACTIVE
76543210
VECTACTIVE
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• PENDSVCLR: PendSV Clear-pending
Write:
0: No effect.
1: Removes the pending state from the PendSV exception.
• PENDSTSET: SysTick Exception Set-pending
Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick except ion is not pe nd in g.
1: SysTick exception is pending.
• PENDSTCLR: SysTick Exception Clear-pending
Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.
• ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults)
0: Interrupt not pending.
1: Interrupt pending.
• VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception
0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
• RETTOBASE: Preempted Active Exceptions Present or Not
0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE: Active Exception Number Contained
0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt
Program Status Register” .
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-
Pending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” .
Note: When the user writes to the SCB_ICSR register, the effect is unpredictable if:
- Writing 1 to the PENDSVSET bit and writing 1 to the PENDSVCLR bit
- Writing 1 to the PENDSTSET bit and writing 1 to the PENDSTCLR bit.
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11.9.1.4 Vector Table Offset Register
Name: SCB_VTOR
Access: Read-write
Reset: 0x000000000
The SCB_VTOR register indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Off se t
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next
statement to give the information required for your implementation; the statement reminds the user of how to determine th e
alignment requirement. The minimum alignment is 32 words, enough fo r up to 16 interrupts. For more interrupts, adjust the
alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word
boundary because the required table size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
31 30 29 28 27 26 25 24
TBLOFF
23 22 21 20 19 18 17 16
TBLOFF
15 14 13 12 11 10 9 8
TBLOFF
76543210
TBLOFF –
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11.9.1.5 Application Interrupt and Reset Control Register
Name: SCB_AIRCR
Access: Read-write
Reset: 0x000000000
The SCB_AIRCR register provides priority grouping control for the exception model, endian statu s for data accesses, and
reset control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores
the write.
• VECTKEYSTAT: Register Key
Read:
Reads as 0xFA05.
• VECTKEY: Register Key
Write:
Writes 0x5FA to VECTKEY, otherwise the writ e is ignored.
• ENDIANNESS: Data Endianness
0: Little-endian.
1: Big-endian.
31 30 29 28 27 26 25 24
VECTKEYSTAT/VECTKEY
23 22 21 20 19 18 17 16
VECTKEYSTAT/VECTKEY
15 14 13 12 11 10 9 8
ENDIANNESS – PRIGROUP
76543210
– SYSRESETREQ VECTCLRACTI
VE VECTRESET
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• PRIGROUP: Interrupt Priority Grouping
This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n
fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the
PRIGROUP value controls this split:
Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Determining preemption of an exception uses only the group priority field.
• SYSRESETREQ: System Reset Request
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
• VECTRESET
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
Interrupt Priority Level Value, PRI_N[7:0] Number of
PRIGROUP Binary Point(1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities
0b000 bxxxxxxx.y [7:1] None 128 2
0b001 bxxxxxx.yy [7:2] [4:0] 64 4
0b010 bxxxxx.yyy [7:3] [4:0] 32 8
0b011 bxxxx.yyyy [7:4] [4:0] 16 16
0b100 bxxx.yyyyy [7:5] [4:0] 8 32
0b101 bxx.yyyyyy [7:6] [5:0] 4 64
0b110 bx.yyyyyyy [7] [6:0] 2 128
0b111 b.yyyyyyy None [7:0] 1 256
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11.9.1.6 System Control Register
Name: SCB_SCR
Access: Read-write
Reset: 0x000000000
• SEVONPEND: Send Event on Pending Bit
0: Only enabled interrupts or events can wake up the processor ; disabled interrupts are excluded.
1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
The processor also wakes up on execution of an
SEV
instruction or an external event.
• SLEEPDEEP: Sleep or Deep Sleep
Controls whether the processor uses sleep or deep sleep as its low power mode:
0: Sleep.
1: Deep sleep.
• SLEEPONEXIT: Sleep-on-exit
Indicates sleep-on-exit when returning from the Handler mode to the Thread mode:
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– SEVONPEND – SLEEPDEEP SLEEPONEXIT –
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11.9.1.7 Configuration and Control Register
Name: SCB_CCR
Access: Read-write
Reset: 0x000000000
The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults
escalated by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the
access to the NVIC_STIR register by unprivileged software (see “Software Trigger Interrupt Register” ).
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stac k alignment. On return from the
exception, it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: Data bus faults caused by load and store instructions cause a lock-up.
1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe sys-
tem devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0.
1: Trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– STKALIGN BFHFNMIGN
76543210
– DIV_0_TRP UNALIGN_TRP – USERSETMPE
ND NONBASETHR
DENA
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• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses.
1: Trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND
Enables unprivile ge d so ftw ar e access to the NVIC_ST IR re gis te r, se e “Software Trigger Interrupt Register” :
0: Disable.
1: Enable.
• NONEBASETHRDENA: Thread Mode Enable
Indicates how the processor enters Thread mode:
0: The processor can enter the Thread mode only when no exception is active.
1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception
Return” .
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11.9.1.8 System Handler Priority Registers
The SCB_SHPR1-SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable pri-
ority. They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and
ignore writes.
Table 11-33. System Fault Handler Priority Fields
Handler Field Register Description
Memory management fault (MemManage) PRI_4
“System Handler Priority Register 1” Bus fault (BusFault) PRI_5
Usage fault (Usa geFault) PRI_6
SVCall PRI_11 “System Handler Priority Register 2”
PendSV PRI_14 “System Handler Priority Register 3”
SysTick PRI_15
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11.9.1.9 System Handler Priority Register 1
Name: SCB_SHPR1
Access: Read-write
Reset: 0x000000000
• PRI_6: Priority
Priority of system handler 6, UsageFault.
• PRI_5: Priority
Priority of system handler 5, BusFault.
• PRI_4: Priority
Priority of system handler 4, MemManage.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
PRI_6
15 14 13 12 11 10 9 8
PRI_5
76543210
PRI_4
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11.9.1.10 System Handler Priority Register 2
Name: SCB_SHPR2
Access: Read-write
Reset: 0x000000000
• PRI_11: Priority
Priority of system handler 11, SVCall.
31 30 29 28 27 26 25 24
PRI_11
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
–
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11.9.1.11 System Handler Priority Register 3
Name: SCB_SHPR3
Access: Read-write
Reset: 0x000000000
• PRI_15: Priority
Priority of system handler 15, SysTick exception.
• PRI_14: Priority
Priority of system handler 14, PendSV.
31 30 29 28 27 26 25 24
PRI_15
23 22 21 20 19 18 17 16
PRI_14
15 14 13 12 11 10 9 8
–
76543210
–
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11.9.1.12 System Handler Control and State Register
Name: SCB_SHCSR
Access: Read-write
Reset: 0x000000000
The SHCSR register enab les the system handlers, and indicates the pending status of the b us fault, memory managemen t
fault, and SVC exceptions; it also indicates the active status of the system handlers.
• USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
• BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
• MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
• SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
– USGFAULTENA BUSFAULTENA MEMFAULTENA
15 14 13 12 11 10 9 8
SVCALLPENDE
DBUSFAULTPEN
DED MEMFAULTPEN
DED USGFAULTPEN
DED SYSTICKACT PENDSVACT – MONITORACT
76543210
SVCALLAVCT – USGFAULTACT – BUSFAULTACT MEMFAULTACT
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• MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• USGFAULTPENDED: Usage Fault Exce ption Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• SYSTICKACT: SysTick Exception Active
Read:
0: The exception is not active.
1: The exception is active.
Note: The user can write to these bits to change the active status of the exceptions.
- Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content
can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequent ly
restores the current active status.
- Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write
procedure to ensure that only the required bit is changed.
• PENDSVACT: PendSV Exception Active
0: The exception is not active.
1: The exception is active.
• MONITORACT: Debug Monitor Active
0: Debug monitor is not active.
1: Debug monitor is active.
• SVCALLACT: SVC Call Active
0: SVC call is not active.
1: SVC call is active.
• USGFAULTACT: Usage Fault Exception Active
0: Usage fault exception is not active.
1: Usage fault exception is active.
• BUSFAULTACT: Bus Fault Exception Active
0: Bus fault exception is not active.
1: Bus fault exception is active.
• MEMFAULTACT: Memory Management Fault Exception Active
0: Memory management fault exception is not active.
1: Memory management fault exception is active.
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If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault.
The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to
the active bits to perform a context switch that changes the current exception type.
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11.9.1.13 Configurable Fault Status Register
Name: SCB_CFSR
Access: Read-write
Reset: 0x000000000
• IACCVIOL: Instruction Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No instruction access violation fault.
1: The processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruc tio n. T he pro ce sso r ha s not
written a fault address to the SCB_MMFAR register.
• DACCVIOL: Data Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No data access violation fault.
1: The processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked fo r the exception retu rn points to the faul ting instruction. The processor has loaded
the SCB_MMFAR register with the address of the attempted access.
• MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The proces-
sor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the SCB_MMFAR register.
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR register.
31 30 29 28 27 26 25 24
– DIVBYZERO UNALIGNED
23 22 21 20 19 18 17 16
– NOCP INVPC INVSTATE UNDEFINSTR
15 14 13 12 11 10 9 8
BFRVALID – STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR
76543210
MMARVALID – MLSPERR MSTKERR MUNSTKERR – DACCVIOL IACCVIOL
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• MLSPERR: MemManage during Lazy State Preservation
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy stat e preservation.
• MMARVALID: Memory Management Fault Address Register ( S CB_MMFAR) Valid Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR re gister holds a valid fault ad dr e ss.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents prob lems on return to a stacked active memory man agement fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No instruction bus error.
1: Instruction bus error.
The process or det ec ts the inst ru ction bu s er ro r on pre fe tch in g an instruc tio n, but it sets the IBUSERR flag to 1 only if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR register.
• PRECISERR: Precise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR register.
• IMPRECISERR: Imprecise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No imprecise data bus error.
1: A data bus error has occurred, but the return addr ess in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR register.
This is an asynchronous fault. Therefor e, if it is detected when the pr iority of the current process is higher than the b us fault
priority, the bus fault becomes pending and becomes active only when the processo r returns from all higher priori ty pro-
cesses. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects
that both this bit and one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exc eption
This is part of “BFSR: Bus Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
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This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still
present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write
a fault address to the BFAR.
• STKERR: Bus Fault on Stacking for Exception Entry
This is part of “BFSR: Bus Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incor-
rect. The proc es so r do es not write a fault address to the SCB_BF AR re gist er .
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of “BFSR: Bus Fault Status Subregister” .
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known . Ot he r fa ults can set this bit to 0, such as a
memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of pr iority, the hard fault handler must set this bit to 0. This
prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No undefined instruction usage fault.
1: The processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the e xception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No invalid state usa g e fa ult.
1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal
use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
• INVPC: Invalid PC Load Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the ille-
gal load of the PC.
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• NOCP: No Coprocessor Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions:
0: No usage fault caus ed by att em p tin g to ac ce ss a cop ro ce ss or .
1: The processor has attempted to access a coprocessor.
• UNALIGNED: Unaligned Access Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned acce sses by setting the UNALIGN_TRP bit in the SCB_CCR register to 1. See “Configuration
and Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, th e PC value stacked for the exception return points to th e instruction that performed
the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR register to 1. See
“Configuration and Control Register” .
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11.9.1.14 Configurable Fault Status Register (Byte Access)
Name: SCB_CFSR (BYTE)
Access: Read-write
Reset: 0x000000000
• MMFSR: Memory Management Fault Status Subregister
The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section
11.9.1.13.
• BFSR: Bus Fault Status Subregister
The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section
11.9.1.13.
• UFSR: Usage Fault Status Subregister
The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 11 .9.1.13.
Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
The SCB_CFSR register indicates the cause of a memory manage ment fault, bus fault, or usage fault. It is byte accessible.
The user can access the SCB_CFSR register or its subregisters as follows:
Access complete SCB_CFSR with a word access to 0xE000ED28
Access MMFSR with a byte access to 0xE000ED28
Access MMFSR and BFSR with a halfword access to 0xE000ED28
Access BFSR with a byte access to 0xE000ED29
Access UFSR with a halfword access to 0xE000ED2A.
31 30 29 28 27 26 25 24
UFSR
23 22 21 20 19 18 17 16
UFSR
15 14 13 12 11 10 9 8
BFSR
76543210
MMFSR
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11.9.1.15 Hard Fault Status Register
Name: SCB_HFSR
Access: Read-write
Reset: 0x000000000
The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear.
This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
Note: The HFSR bits are sticky. Th is means th at, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
31 30 29 28 27 26 25 24
DEBUGEVT FORCED –
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– VECTTBL –
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11.9.1.16 MemManage Fault Address Register
Name: SCB_MMFAR
Access: Read-write
Reset: 0x000000000
The MMFAR re gis ter con ta i ns the ad d ress of the lo cation that generated a memory management fau lt.
• ADDRESS
When the MMARVALID bit of the MMF SR su bregister is set to 1, this field hold s the add ress of the location that generated
the memory management fault.
Notes: 1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction
can be split into multiple aligned accesses, the fault address can be any add ress in the range of the requested access size.
2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR register is valid.
See “MMFSR: Memory Management Fault Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
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11.9.1.17 Bus Fault Address Register
Name: SCB_BFAR
Access: Read-write
Reset: 0x000000000
The BFAR register contains the address of the location that generated a bus fault.
• ADDRESS
When the BFARVALID bit of the BFSR subreg ister is se t to 1, this fie ld holds th e address of the lo cation that ge nerated the
bus fault.
Notes: 1. When an unaligned access faults, the address in the SCB_BF AR register is the one requested by the instruction, even if it is
not the address of the fault.
2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BF AR register is valid. See “BFSR: Bus
Fault Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
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11.10 System Timer (SysTick)
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps
to) the value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks.
When the processor is halted for debugging, the counter does not decrement.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick
counter stops.
Ensure that the software uses aligned word accesses to access the SysTick registers.
The SysTick counter relo ad and current value are undefined at re set; the correct initialization sequence fo r the
SysTick counter is:
1. Program the reload value.
2. Clear the current value.
3. Program the Control and Status register.
11.10.1 System Timer (SysTick) User Interface
Table 11-34. System Timer (SYST) Register Mapping
Offset Register Name Access Reset
0xE000E010 SysTick Control and Status Register SYST_CSR Read-write 0x0000 0004
0xE000E014 SysTick Reload Value Register SYST_RVR Read-write Unknown
0xE000E018 SysTick Current Value Register SYST_CVR Read-write Unknown
0xE000E01C SysTick Calibration Value Register SYST_CALIB Read-only 0xC0000000
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11.10.1.1 SysTick Control and Status
Name: SYST_CSR
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CSR register enables the SysTick features.
• COUNTFLAG: Count Flag
Returns 1 if the timer counted to 0 since the last time this was read.
• CLKSOURCE: Clock Source
Indicates the clock source:
0: External Clock.
1: Processor Clock.
• TICKINT
Enables a SysTick exception request:
0: Counting down to zero does not assert the SysTick exception request.
1: Counting down to zero asserts the SysTick exception request.
The software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE
Enables the counter:
0: Counter disabled.
1: Counter enabled.
When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down. On
reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then
loads the RELOAD value again, and begins counting.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
– COUNTFLAG
15 14 13 12 11 10 9 8
–
76543210
CLKSOURCE TICKINT ENABLE
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11.10.1.2 SysTick Reload Value Registers
Name: SYST_RVR
Access: Read-write
Reset: 0x000000000
The SYST_RVR register specifies the start value to load into the SYST_CVR register.
•RELOAD
Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0.
The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no
effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N pro-
cessor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clo ck pulse s, set RELOAD
to 99.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
RELOAD
15 14 13 12 11 10 9 8
RELOAD
76543210
RELOAD
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11.10.1.3 SysTick Current Value Register
Name: SYST_CVR
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CVR register contains the current value of the SysTick counter.
• CURRENT
Reads return the current value of the SysTick counter.
A write of any value clears th e field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
CURRENT
15 14 13 12 11 10 9 8
CURRENT
76543210
CURRENT
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11.10.1.4 SysTick Calibration Value Register
Name: SYST_CALIB
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CSR register indicates the SysTick calibration properties.
• NOREF: No Reference Clock
It indicates whether the device provides a reference clock to the processor:
0: Reference clock provided.
1: No reference clock provided.
If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.
•SKEW
It indicates whether the TENMS value is exact:
0: TENMS value is exact.
1: TENMS value is inexact, or not given.
An inexact TENMS value can affect the suitability of SysTick as a software real time clock.
• TENMS: Ten Milliseconds
The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibra-
tion value is not known.
Read as 0x000030D4 . The SysTick calibration value is fixed at 0x0 00030D4 (12500), wh ich allows the generation of a time
base of 1 ms with SysTick clock at 12.5 MHz (100/8 = 12.5 MHz).
31 30 29 28 27 26 25 24
NOREF SKEW –
23 22 21 20 19 18 17 16
TENMS
15 14 13 12 11 10 9 8
TENMS
76543210
TENMS
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11.11 Memory Protection Unit (MPU)
The MPU divides the mem ory map into a number of reg ions, and defines the location, size , access permissions,
and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlappin g re gio ns
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:
Eight separate memory regions, 0-7
A background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest
number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps
region 7.
The background region has the same memory access attributes as the default memory map, but is accessible
from privileged softw ar e on ly.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the
same region settings.
If a program accesses a memory location that is prohibited by the MPU, the proc essor generates a memory
management fault. This causes a fault exception, and might cause the termination of the process in an OS
environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be
executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” ).
Table 11-35 shows the possible MPU region attributes. These in clude Share ability and cache beh avior attributes
that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for
guidelines for programming such an implementation.
Table 11-35. Memory Attributes Summary
Memory Type Shareability Other Attributes Description
Strongly- ordered - - All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Device Shared - Memory-mapped peripherals that several processors share.
Non-shared - Memory-mapped peripherals that only a single processor uses.
Normal Shared Normal memory that is shar ed between several processors.
Non-shared Normal memory that only a single processor uses.
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11.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permiss ion bits (TEX, C, B, S, AP, and
XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of
memory without the required permissions, then the MPU generates a permission fault.
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Note: 1. The MPU ignores the value of this bit.
Table 11-37 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7.
Table 11-36. TEX, C, B, and S Encoding
TEX C B S Memory Type Shareability Other Attributes
b000
0
0 x(1) Strongly-
ordered Shareable -
1 x(1) Device Shareable -
1
0 0Normal Not
shareable Outer an d inner write-through. No
write allocate.
1 Shareable
1 0Normal Not
shareable Outer an d inner write-back. No write
allocate.
1 Shareable
b001
0
0 0Normal Not
shareable
1 Shareable
1 x(1) Reserved encoding -
1
0 x(1) Implementation defined
attributes. -
1 0Normal Not
shareable Outer an d inner write-back. Write and
read allocate.
1 Shareable
b010 00 x(1) Device Not
shareable Nonshared Device.
1 x(1) Reserved encoding -
1x
(1) x(1) Reserved encoding -
b1B
BAA0Normal Not
shareable
1Shareable
Table 11-37. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate
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Table 11-38 shows th e A P enc od i ngs th at de fin e the ac cess permissions for privileged and unprivileged software.
11.11.1.1 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault, see
“Exceptions and Interrupts” . The MMFSR indicate s the caus e of the fault. Se e “MMFSR: Memory Management
Fault Status Subregister” for more information.
11.11.1.2 Updating an MPU Region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASR registers. Each
register can be programed separately, or a multiple-word write can be used to program all of these registers.
MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM
instruction.
11.11.1.3 Updating an MPU Region Using Separate Words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU, if the region being changed was previously
enabled . Fo r ex am ple:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
Table 11-38. AP Encoding
AP[2:0] Privileged
Permissions Unprivileged
Permissions Description
000 No access No access All accesses generate a permission fault
001 RW No access Access from privileged software only
010 RW RO Writes by unprivileged software generate a permission fault
011 RW RW Full access
100 Unpredictable Unpredictable Reserved
101 RO No access Reads by privileged software only
110 RO RO Read only, by privileged or unprivileged software
111 RO RO Read only, by privileged or unprivileg ed software
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The software must use memory barrier instructions:
Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might
be affected by the change in MPU settings
After the MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception
handler, or is fo llowed by an exception return, because the exception entry and exception return mechanisms
cause memory barrier behavior.
The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU
through the PPB, which is a Strongly-Ordered memory region.
For example, if the user wants all of the memory access behavior to take effect immediately after the programming
sequence, a DSB instructio n and an ISB instru ction m ust be used . A DSB is requir ed after chan ging MPU setting s,
such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is
entered using a branch or call. If the programming sequence is enter ed using a return from exception, or by taking
an exception, then an ISB is not required.
11.11.1.4 Updating an MPU Region Using Multi-word Writes
The user can program directly using multi-word writes, depending on how the information is divided. Cons ider the
following reprog ra m m i ng :
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region Number, address, attribute, size and enable
This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required
region number and had th e VALID bit set to 1. See “MPU Region Ba se Ad dre ss Register ” . Use this when the data
is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and
; region number combined with VALID (bit 4) set to 1
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
11.11.1.5 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subre gions. Set the co rrespo nding b it in the SRD
field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least
significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
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a subregion means another region overlapping the disabled range matches instead. If no other enabled region
overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not suppor t subregions. With regions of these sizes, the SRD field must be
set to 0x00, otherwise the MPU behavior is unpredictable.
11.11.1.6 Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the
attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the
first two subregions, as in Figure 11-14 below :
Figure 11-14. SRD Use
11.11.1.7 MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt
handlers might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU_RASR register, it must use aligned word accesses
For the MPU_RASR register, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU h as previously been prog rammed, disable unu sed regions to preven t
any previous region settings from affecting the new MPU setup.
MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU
as follows:
In most microcontroller implementations, the shareability and cache policy attributes do not affect the system
behavior. However, using these settings for the MPU regions can make the application code more portable. The
values given are for typical situations. In special systems, such as multiprocessor designs or designs with a
separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations
of the memory device manufacturer.
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
Table 11-39. Memory Region Attributes for a Microcontroller
Memory Region TEX C B S Memory Type and Attributes
Flash memory b000 1 0 0 Normal memo ry, non-shareable, write - through
Internal SRAM b000 1 0 1 Normal memory, shareable, write-through
External SRAM b000 1 1 1 Normal memory, shareable, write-back, write-allocate
Peripherals b000 0 1 1 Device memory, shareable
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11.11.2 Memory Protection Unit (MPU) User Interface
Table 11-40. Memory Protection Unit (MPU) Register Mapping
Offset Register Name Access Reset
0xE000ED90 MPU Type Register MPU_TYPE Read-only 0x0000080 0
0xE000ED94 MPU Control Register MPU_CTRL Read-write 0x00000000
0xE000ED98 MPU Region Number Register MPU_RNR Read-write 0x00000000
0xE000ED9C MPU Region Base Address Register MPU_RBAR Read-write 0x00000000
0xE000EDA0 MPU Region Attribute and Size Register MPU_RASR Read-write 0x00000000
0xE000EDA4 Alias of RBAR, see MPU Region Base Address Register MPU_RBAR_A1 Read-write 0x00000000
0xE000EDA8 Alias of RASR, see MPU Region Attribute and Size Register MPU_RASR_A1 Read-write 0x00000000
0xE000EDAC Alias of RBAR, see MPU Region Base Address Register MPU_RBAR_A2 Read-write 0x00000000
0xE000EDB0 Alias of RASR, see MPU Region Attribute and Size Register MPU_RASR_A2 Read-write 0x00000000
0xE000EDB4 Alias of RBAR, see MPU Region Base Address Register MPU_RBAR_A3 Read-write 0x00000000
0xE000EDB8 Alias of RASR, see MPU Region Attribute and Size Register MPU_RASR_A3 Read-write 0x00000000
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11.11.2.1 MPU Type Register
Name: MPU_TYPE
Access: Read-write
Reset: 0x00000800
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports.
• IREGION: Instruction Region
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION: Data Region
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
• SEPARATE: Separate Instruction
Indicates support for unified or separate instruction and date memory maps:
0: Unified.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
IREGION
15 14 13 12 11 10 9 8
DREGION
76543210
– SEPARATE
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11.11.2.2 MPU Control Register
Name: MPU_CTRL
Access: Read-write
Reset: 0x00000800
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of
the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enabled
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by
any enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software
accesses.
When enabled, the backgrou nd region acts as a regio n number -1. Any region that is defined and enabled has priority over
this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enabled
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default me m ory map is as described in “Memory Model” . Any access by privileged
software that does not address an enabled memory region behaves as defined by the def ault memory map.
• Any access b y unprivileged so ftw are th at does n ot address an enab le d memory region causes a m emory management
fault.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– PRIVDEFENA HFNMIENA ENABLE
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XN and Strongly-ordered rules always apply to the System Control Space rega rd le ss of th e va lu e of the ENABLE bit .
When the ENABLE bit is set to 1, at least one region of the memor y map must be enabled for the syste m to function unless
the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged soft-
ware can operate.
When the ENABLE bit is set to 0 , the system uses th e defa ult memory map. This has the same memory attributes as if the
MPU is not implemented. The default memory map applies to accesses fro m both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Con trol Space and vector table ar e always per mitted. Other areas are
accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with
priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is
enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
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11.11.2.3 MPU Region Number Register
Name: MPU_RNR
Access: Read-write
Reset: 0x00000800
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers.
•REGION
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. How-
ever, the region number can be chan ged by writing to the MPU_ RBAR with th e VALID bit set to 1; see “MPU Region Base
Address Register” . This write update s the value of the REGION field.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
REGION
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11.11.2.4 MPU Region Base Address Register
Name: MPU_RBAR
Access: Read-write
Reset: 0x00000000
Note: If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field .
The MPU_RBAR defines th e base address o f the MPU region sele cted by the MPU_RNR, and can upda te the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligne d to the size of the reg ion. For exam ple, a 64 KB region must be align ed on a mul tiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, a nd updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 N
ADDR
N-16543210
– VALID REGION
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11.11.2.5 MPU Region Attribute and Size Register
Name: MPU_RASR
Access: Read-write
Reset: 0x00000000
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
The most significant halfword holds the region attributes.
The least signif ic an t ha lfwo r d hol ds the re gio n size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 11-38 .
• TEX, C, B: Memory Access Attributes
See Table 11-36 .
• S: Shareable
See Table 11-36 .
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding sub-region is enabled.
1: Corresponding sub-region is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes an d less do not support subregion s. When writing the attribu tes for such a region, write the SRD
field as 0x00.
31 30 29 28 27 26 25 24
–XN–AP
23 22 21 20 19 18 17 16
–TEXSCB
15 14 13 12 11 10 9 8
SRD
76543210
–SIZEENABLE
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZ E valu e of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR, see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N(1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 -
b10011 (19) 1 MB 20 -
b11101 (29) 1 GB 30 -
b11111 (31) 4 GB b01100 Maximum possible size
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11.12 Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid.
An abort can be caused by the external or internal memory system as a result of attempting to acces s
invalid instruction or data memory.
Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is
said to be aligned. Aligned words and ha lfwords have addresses that are divisible by four and two
respectively. The terms word-aligned and halfword -aligned therefore stipulate addresses that are
divisible by four and two respectively.
Banked register A register that has multiple physical copies, where the state of the processor determines which copy is
used. The Stack Pointer, SP (R13) is a banked register.
Base register In instruction descriptions, a register specified by a load or store instruction that is used t o ho l d the
base value for the instruction’s address calculation. Depending on the instru ction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the address that is
sent to memory.
See also “Index register”
Big-endian (BE) Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
increasing addresses in memory.
See also “Byte-invariant” , “Endianness” , “Little-endian (LE)” .
Big-endian memory Memory in which:
a byte or halfword at a word-aligned address is the most significant byt e or halfword within the word at
that address,
a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
See also “Little-endian memory” .
Breakpoint A breakpoint is a mechanism provided by debuggers to iden tify an instruction at which program
execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register
contents, memory locations, variable values at fixed points in the program execution to test that the
program is operating correctly. Breakp oints are removed after the program is successfully tested.
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Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged whe n switching
between little-endian and big-endian operation. When a data item larger than a byte is loaded from or
stored to memory, the bytes making up that data item are arranged into the correct order depending
on the endianness of the memory access.
An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses.
It expects multi-word accesses to be word-aligned.
Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute.
Conditional execution If th e condition code flags indicate that the corresp onding condition is true when the instruction starts
executing, it executes normally. Otherwise, the instruction does nothing.
Context The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and the
associated memory access permissions.
Coprocessor A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.
Debugger A debugging system that includes a program, use d to dete ct, locate, and correct software faults,
together with custom hardware that supports software debugging.
Direct Memory Access
(DMA) An operation that accesses main memory directly, without the processor performing any accesses to
the data concerned.
Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
Doubleword-aligned A data item having a memory address that is divisible by eight.
Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored
in memory. An aspect of the system’s memory mapping.
See also “Little-endian (LE)” and “Big-endian (BE)”
Exception
An event that interrupts program execution. When an exception occurs, the processor suspends the
normal program flow and starts execution at the address indicated by the corresponding exception
vector. The indicated address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults
include attempting an invalid memory access, attempting to execute an instructio n in an invalid
processor state, and attempting to execute an undefined instruction.
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Exception service routine See “Interrupt handler” .
Exception vector See “Interrupt vector” .
Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as
the corresponding virtual address.
Halfword A 16-bit data item.
Illegal instruction An instruction that is archi tecturally Undefined.
Implementation-defined The behavior is not architecturally defined, but is defined and documented by indivi dual
implementations.
Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the option
chosen does not affect software compatibility.
Index register In some load and store instruction descriptions, the value of this register is used as an offset to be
added to or subtracted from the base register value to form the address that is sent to memory. Some
addressing modes optiona lly enable the index register value to be shifted prior to the addition or
subtraction.
See also “Base register” .
Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline.
Interrupt handler A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured,
that contains the first instruction of the corresponding interrupt handler.
Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
addresses in memory.
See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” .
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Little-endian memory Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also “Big-endian memory” .
Load/store architecture A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Memory Protection Unit
(MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an i nstruction does not mean that the
instruction has to be executed.
Preserved Preserved by writing the same value back that has been previously read from the same field on the
same processor.
Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb
instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region A p artition of memory space.
Reserved A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These fields
are reserved for use in future extensions of the architecture or are implementation-specific. All
reserved bits not used by the implementation must be written as 0 and read as 0.
Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing
shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be
halfword-aligned.
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size
is said to be unaligned. For example, a word stor ed at an address that is not divisible by four.
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Undefined Indicates an instruction that generates an Undefined instructio n exception.
Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes.
Unpredictable behavior must not halt or hang the processor, or any parts of the system.
Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and
debug logic. This type of reset is useful if debugging features of a processor.
Word A 32-bit data item.
Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb
instructions STM, STR, STRH, STRB, and PUSH.
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12. Debug and Test Features
12.1 Description
The SAM4N Se ries microcontrolle rs feature a number of complementary debug and test capabilities. The Serial
Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug Port (JTAG-
DP) is used for standard de bugging functions, such as do wnloading code and sin gle-stepping throu gh programs. It
also embeds a serial wire trace.
12.2 Embedded Characteristics
Debug access to all memories an d registers in the system, including Cort ex-M4 register bank when the core
is running, halted, or held in reset
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakp oin ts and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
IEEE1149.1 JTAG Boundary-scan on all digital pins
Figure 12-1 . Debu g and Test Block Diagram
TST
TMS
TCK/SWCLK
TDI
JTAGSEL
TDO/TRACESWO
Boundary
TAP SWJ-DP
Reset
and
Test
POR
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12.3 Application Examples
12.3.1 Debug Environment
Figure 12-2 shows a complete debug environment example. The SWJ-DP interface is used for standard
debugging functions, such as downloading code and single-stepping through the program, and viewing core and
peripheral registers.
Figure 12-2. Application Debug Environment Example
12.3.2 Test Environment
Figure 12-3 shows a te st environment example (JTAG boundary scan). Test vectors are sent and interpreted by
the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These
devices can be connected to form a single scan chain.
SAM4
Host Debugger
PC
SAM4-based Application Board
SWJ-DP
Connector
SWJ-DP
Emulator/Probe
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Figure 12-3. Application Test Environme nt Examp le
12.4 Debug and Test Pin Description
Note: 1. TDO pin is set in input mode when the Cortex-M4 Core is no t in debug mode. Thus the internal pull-up
corresponding to this PIO line must be enabled to avoid current consumption due to floating input.
Chip 2
Chip n
Chip 1
SAM4
SAM4-based Application Board In Test
JTAG
Connector
Tes t e r
Test Adaptor
JTAG
Probe
Table 12-1. Debug and Test Signal List
Signal Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Inpu t/Output Low
TST Test Select Input
SWD/JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output (1)
TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input
JTAGSEL JTAG Selection Input High
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12.5 Functional Description
12.5.1 Test Pin
One dedic ated pin, T ST, is used to define the de vice operating mode. When this pin is at low level during power-
up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST
pin integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal
operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state
during the duration of the whole operation.
12.5.2 Debug Architecture
Figure 12-4 shows the Deb ug Architecture used in the SAM4. The Cortex-M 4 embeds five functional units for
debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP emulators/probes
and debugging tool vendors for Cortex M4-based microcontrollers. For further details on SWJ-DP see the Cortex
M4 technical refe re nce manual.
Figure 12-4. Debug Architecture
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU
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12.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)
The Cortex-M4 embeds a SWJ-DP debug port which is the standard CoreSight™ debug port. It combines Serial
Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG Debug Port(JTAG-DP), 5 pins.
By default, the JTAG Debug Port is a ctive. If the host debugger wa nts to switch to the Serial Wire Debug Port, it
must provide a ded icated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and
enables SW-DP.
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE
output (TRACESWO) is multiplexed with TDO. The asynchronous trace can only be used with SW-DP, not JTAG-
DP.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
12.5.3.1SW-DP and JTAG-DP Selection Mechanism
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by
default after reset.
Switch from JTAG-DP to SW-DP. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Switch from SWD to JTAG. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
12.5.4 FPB (Flash Patch Breakpoint)
The FPB:
Implements hardware breakpoints.
Patches code and data from code space to system space.
The FPB unit cont ain s:
Two literal comparators for matching against literal loads from code space, and remapping to a
corresponding area in system space.
Six instruction comparators for matching against instruction fetches from code space and remapping to a
corresponding area in system space.
Alternatively, comparators ca n also be co nfigured to generate a breakpoint instruction to the p roce ssor cor e
on a match.
Table 12-2. SWJ-DP Pin List
Pin Name JTAG Port Serial Wire Debug Port
TMS/SWDIO TMS SWDIO
TCK/SWCLK TCK SWCLK
TDI TDI –
TDO/TRACESWO T DO TRACESWO (optional: trace)
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12.5.5 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
PC sampling packets at set intervals
PC or data watchpoint packets
Watchpoint event to ha lt cor e
The DWT contains counters for the items that follow:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead
12.5.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application drive n trace source that supports printf style debugging to trace Op erat ing Syste m (OS)
and application events, and emits diagnostic system information. The ITM emits trace information as packets
which can be generated by three different sources with several priority levels:
Software trace: Soft ware can write directly to ITM stimulus registers. This can be done us ing the printf
function. For more informa tio n, re fe r to Section 12.5.6.1 “How to Configure the ITM”.
Hardware trace: The ITM emits packets generated by the DWT.
Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate
the timestamp.
12.5.6.1How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
Configure the TPIU for asynchronous trace mode (refer to Section 12.5.6.3 “How to Configure the TPIU”).
Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register
(address: 0xE0000FB0).
Write 0x00010015 into the Trace Control Register:
Enable ITM.
Enable synchronization packets.
Enable SWO behavior.
Fix the ATB ID to 1.
Write 0x1 into the Trace Enable Register:
Enable the stimulus port 0.
Write 0x1 into the Trace Privilege Register:
Stimulus port 0 only accessed in privileged mode (clearing a bit in this register will result in the
corresponding stimulus port being accessible in user mode).
Write into the Stimulus Port 0 Register: TPIU (Trace Port Interface Unit).
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
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12.5.6.2Asynchronous Mode
The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Po rt. As a con sequence, asynchr onous
trace mode is only available when the serial wire debug mode is selected since TDO signal is used in JTAG debug
mode.
Two encoding formats are available for the single pin output:
Manchester encoded stream. This is the reset value.
NRZ-based UART byte structure
12.5.6.3How to Configure the TPIU
This example only concerns the asynchronous trace mode.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of
trace and debug blocks.
Write 0x2 into the Selected Pin Protocol Register.
Select the Serial Wire Output – NRZ.
Write 0x100 into the Formatter and Flush Control Register.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
12.5.7 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during pow er-up
and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS
functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID
that identifies the processor. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset
must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file to set up the
test is provided on www.atmel.com.
12.5.7.1JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains a number of bits which corresponds to active pins and associated
control signals.
Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects
the direction of the pad.
For more information, please refer to BSDL files available for the SAM4 Series.
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12.5.8 ID Code Register
Access: Read-only
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1
Set to 0x1.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER MANUFACTURER IDENTITY
76543210
MANUFACTURER IDENTITY 1
Chip Name Chip ID
SAM4N 0x05B2E
Chip Name JTAG ID Code
SAM4N 0x05B3_603F
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13. Reset Controller (RSTC)
13.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and
processor resets.
13.2 Embedded Characteristics
Manages all Resets of the System, Including
External Devices through the NRST Pin
Processor Reset
Peripheral Set Reset
Based on Embedded Power-on Cell
Reset Source Status
Status of the Last Rese t
Either Software Reset, User Reset, Watchdog Reset
External Reset Signal Shaping
13.3 Block Diagram
Figure 13-1. Reset Contr olle r Block Diagram
NRST
proc_nreset
wd_fault
periph_nreset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager exter_nreset
nrst_out
core_backup_reset
WDRPROC
user_reset
vddcore_nreset
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13.4 Functional Description
13.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and
generates the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer
periph_nreset: Affects the whole set of embedded peripherals
nrst_out: Drives the NRST pin
These reset signals are asserted by the Reset Controller, either on external events or on software action. The
Reset State Manager controls the gener ation o f reset signals and provid es a signal to the NRST Manag er when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The Reset Controller Mode Register (RST C_MR), allowing the con figuration of the Rese t Controller, is power ed
with VDDIO, so that its configuration is saved as long as VDDIO is on.
13.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has
elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external
signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State
Manager. Figure 13-2 shows the block diagram of the NRST Manager.
Figure 13-2. NRST Manager
13.4.2.1NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs.
Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller ca n also be pr ogrammed to gen erate an in terrup t inste ad of gene ratin g a reset. To do so, th e
bit URSTIEN in RSTC_MR must be written at 1.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
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13.4.2.2NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven lo w by the NRST Manager for a time prog ramme d by the field ERSTL in RSTC_ MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-u p
reset for devices requiring a longer startup time than the Slow Clock Oscillator.
13.4.3 Brownout Manager
The Brownout manager is embedded within the Supply Controller, please refer to the product Supply Controller
section for a detailed description.
13.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal rese t signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is
performed when the processor reset is released.
13.4.4.1General Reset
A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation loss is detected by
the Supply contro ller. The vddcore_nr eset signal is asserted by the Supply Controller when a general re set occurs.
All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR
is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.
Figure 13-3 shows how the General Reset affects the reset signals.
Figure 13-3. General Reset State
SLCK
periph_nreset
proc_nreset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
MCK
Processor Startup
= 2 cycles
backup_nreset
Any
Freq.
RSTTYP XXX 0x0 = General Reset XXX
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13.4.4.2Backup Reset
A Backup reset occurs when the chip returns from Backup Mode. The core _backup_r eset signal is assert ed by the
Supply Controller when a Backup reset occurs.
The field RSTTYP in RSTC_SR is updated to report a Backup Reset.
13.4.4.3User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral
Reset are asser te d .
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with
the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock
cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH
because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.
Figure 13-4. User Reset State
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 2 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
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13.4.4.4Software Reset
The Reset Controller offers several commands used to assert the different reset signals. Th ese commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writin g PROCRST at 1 resets the processor and the watchdog timer
PERRST: Writing PERRST at 1 resets all the embedded peripherals including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously).
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time define d by the field ERST L in the
Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a softw are operatio n is detected , the bit SRCMP (Software Reset Command in Progress) is set in the
Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be
performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Figure 13-5. Software Reset
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1 EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
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13.4.4.5Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by
default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 13-6. Watchdog Reset
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
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13.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in
descending order:
General Reset
Backup Reset
Watchdog Reset
Software Reset
User Reset
Particular cases are listed below:
When in User Reset:
A watchdog event is impossible because the W atchdog T imer is being reset by the proc_nrese t signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
A watchdog event ha s pr ior ity over the current state.
The NRST has no effect.
When in Watchdog Reset:
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
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13.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software
reset should be p er fo rmed u ntil th e e nd o f the cu rr en t o ne. This b it is a utoma tical ly clea re d at the end of th e
current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK
rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This
transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-7). If the User Reset is
disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the
interrupt.
Figure 13-7. Reset Contro ller Status and Interrupt
MCK
NRST
NRSTL
2 cycle
resynchronization 2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
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13.5 Reset Controller (RSTC) User Interface
Table 13-1 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register RSTC_CR Write-only -
0x04 Status Register RSTC_SR Read-only 0x0000_0000
0x08 Mode Register RSTC_MR Read-write 0x0000 0001
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13.5.1 Reset Controller Control Register
Name: RSTC_CR
Address: 0x400E1400
Access: Write-only
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin and resets the processor and the peripherals.
• KEY: System Reset Key
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––EXTRSTPERRST–PROCRST
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
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13.5.2 Reset Controller Status Register
Name: RSTC_SR
Address: 0x400E1404
Access: Read-only
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is being p erformed by the reset cont roller. The reset controller is re ady for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
–––––––URSTS
Value Name Description
0 General Reset First power-up Reset
1 Backup Reset Return from Backup Mode
2 Watchdog Reset Watch dog fault occurred
3 Software Reset Processor reset required by the software
4 User Reset NRST pin detected low
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13.5.3 Reset Controller Mode Register
Name: RSTC_MR
Address: 0x400E1408
Access: Read-write
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc _irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: Exte rna l Re se t Le n g th
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles .
This allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Write Access Password
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– ERSTL
76543210
– – URSTIEN – – – URSTEN
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
Always reads as 0.
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14. Real-time Timer (RTT)
14.1 Description
The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit
prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic
interrupt and/or triggers an alarm on a programmed value.
It can be configured to be driven by the 1 Hz signal generated by the RTC, thus taking advantage of a calibrated 1
Hz clock.
The slow clock source can be fully disabled to reduce power consumption when RTT is not required.
14.2 Embedded Characteristics
32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1 Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm
14.3 Block Diagram
Figure 14-1. Real-time Timer
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
RTT_MR
RTTDIS
10
RTT_MR
RTC1HZ
RTC 1Hz
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14.4 Functional Description
The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock
divided by a programm able 16-bit value. The value can be programmed in the field RTPRES o f the Real-time
Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 correspon ds to feeding the real -time counter with a 1 Hz sign al (if the Slow
Clock is 32.768 kHz). The 32 -bit cou nter can count up to 232 second s, corre sponding to more than 1 36 years, then
roll over to 0.
The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC
1Hz is calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism
between RTC and RTT counters.
Setting the RTC 1HZ clock to 1 in RTT_MR r egister allo ws to d rive th e 32-bit RTT counter with the RTC 1Hz clock.
In this mode, RTPRES field has no effect on 32-bit counter but RTTINC is still triggered by RTPRES.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is
achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status
events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to
trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several
executions of the interrupt handler, the inter rupt must be disab led in the interrupt han dler and re-e nabled when th e
status register is clear.
The Real-time Timer value (CRTV) can be read at any time in the regi ster RTT_ VR (R eal-time Value Register). As
this value can be updated a synchronously from the Master Clock, it is advisable to read this register twice at the
same value to improve accuracy of the returned value.
The current value of the co unter is compar ed with the value written in the a larm r egister RTT_ AR (Rea l-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR register) when writing a new ALMV
value in Real-time Alarm Register.
The bit RTTINC in RTT_SR is set each time there is a prescaler roll-over, so each time the Real-time Timer
counter is incremented if RTC1HZ=0 else if RTC1HZ=1 the RTTINC bit can be triggered according to RTPRES
value, in a fully independent way from the 32-bit counter increment. This bit can be used to start a periodic
interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
The RTTINCIEN field must be cleared prior to write a new RTPRES value in RTT_MR register.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this
module. This can be achieved by setting the RTTDIS field to 1 in RTT_MR register.
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Figure 14-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
SCLK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
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14.5 Real-time Timer (RTT) User Interface
Table 14-1 . Register Mapping
Offset Register Name Access Reset
0x00 Mode Register RTT_MR Read-write 0x0000_8000
0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF
0x08 Value Register RT T_VR Read-only 0x0000_0000
0x0C Status Register RTT_SR Read-only 0x0000_0000
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14.5.1 Real-time Timer Mode Register
Name: RTT_MR
Address: 0x400E1430
Access: Read-write
• RTPRES: Real- ti me Timer Prescale r Value
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
RTPRES ≠ 0: The prescaler per iod is equal to RT PRES * SCL K per iod .
Note: The RTTINCIEN field must be cleared prior to write a new RTPRES value.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effect on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR has no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
0 = No effect.
1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
• RTTDIS: Real-time Timer Disable
0 = The real-time timer is enabled.
1 = The real-time timer is disabled (no dyn amic power consumption).
• RTC1HZ: Real-Time Clock 1Hz Clock Selection
0 = The RTT 32-bit counter is driven by the 16-bit prescaler roll-over ev en ts.
1 = The RTT 32-bit counter is driven by the RTC 1 Hz clock.
31 30 29 28 27 26 25 24
–––––––RTC1HZ
23 22 21 20 19 18 17 16
– – – RTTDIS – RTTRST RTTINCIEN ALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
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14.5.2 Real-time Timer Alarm Register
Name: RTT_AR
Address: 0x400E1434
Access: Read-write
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
Note: The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR register) when writing a new ALMV
value.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
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14.5.3 Real-time Timer Value Register
Name: RTT_VR
Address: 0x400E1438
Access: Read-only
• CRTV: Current Real-time Value
Returns the curre n t valu e of the Real- tim e Time r.
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
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14.5.4 Real-time Timer Status Register
Name: RTT_SR
Address: 0x400E143C
Access: Read-only
• ALMS: Real-time Alarm Status
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Re al -ti me Timer Increm e nt
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––RTTINCALMS
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15. Real-time Clock (RTC)
15.1 Description
The Real-time Clock (RTC) peripheral is designed for very low power consumption.
It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar,
complemented by a programmable perio dic interrupt. The alarm an d calendar registers are accessed by a 32-bit
data bus.
The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24 -hour
mode or 12-hour mode with an AM/PM indicator.
Updating time a nd calendar fields and configuring the alar m fields are performed by a parallel captur e on the 32-bit
data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an
incompatible da te acco rd in g to th e cur ren t mo nt h/ yea r /ce nt ur y.
A clock divider calibration circuitry enables to compensate crystal oscillator frequency inaccuracy.
15.2 Embedded Characteristics
Ultra Low Power Consumption
Full Asynchronous Design
Gregorian Calendar up to 2099 or Persian Calendar
Programmable Periodic Interrupt
Safety/security features:
Valid Time and Date Programmation Check
On-The-Fly Time and Date Validity Check
Crystal Oscillator Clock Calibration
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15.3 Block Diagram
Figure 15-1. RTC Block Dia gr am
15.4 Product Dependencies
15.4.1 Power Management
The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on
RTC behavior.
15.4.2 Interrupt
RTC interrup t line is con ne cted on o ne of the in tern al sour ce s of the interrupt controller. RTC interrupt requires the
interrupt controller to be programmed first.
User Interface
32768 Divider Time
Slow Clock: SLCK
APB
Date
RTC Interrupt
Entry
Control Interrupt
Control
Clock Calibration
Alarm
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15.5 Functional Description
The RTC provid es a full binary-c oded decimal (BC D) clock that inclu des century (1 9/20), year (with le ap years),
month, date , da y, ho urs, mi nu te s and se con d s.
The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar(or 1300 to 1499 in Persian
mode).
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year
2099.
15.5.1 Reference Clock
The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal.
During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal
selection has to take into account the current consumption for power saving and the frequency drift due to
temperat ur e ef fec t on the cir cuit for tim e ac cu ra cy.
15.5.2 Timing
The RTC is updated in real time at one-second intervals in normal mode for the counters o f seconds, at one-
minute intervals for the counter of minutes and so on.
Due to the asynchronous op eration of the RTC with respect to the rest of the chip, to be certain that the value read
in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is
necessary to read these reg isters twice. If the data is the same both times, then it is valid. Therefore , a minimum of
two and a maximum of three accesses are required.
15.5.3 Alarm
The RTC has five prog ra m ma b le fie lds: mo nth, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the al arm condition:
If all the fields are enabled, an alarm flag is generated (the cor responding flag is asserted and an interrupt
generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the combination of fields enabled, a large num ber of possibilities are available to the user ranging
from minutes to 365/366 days.
Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC,
MIN, HOUR fields.
Note: To change one of the SEC, MIN, HOUR, DA TE, MONTH fields, it is recommended to disable the field before changing
the value and re-enable it after the value has been changed. Th is requires up to 3 accesses to the RTC_TIMALR or
RTC_CALALR registers. First access to only clear the enable corresponding to the field to change (SECEN, MINEN,
HOUREN, DATEEN, MTHEN), this access is not required if the field is already cleared. The second access performs
the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by
writing 1 in SECEN, MINEN, HOUREN, DATEEN, MTHEN fields.
15.5.4 Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours,
minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with
regard to the year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity
register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids
any further side effects in the hardware. The same procedure is done for the alarm.
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The following checks are performe d :
1. Century (check if it is in range 19 - 20 or 13-14 in Persian mode)
2. Year (BCD entry check)
3. Date (check range 01 - 31)
4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”)
5. Day (check range 1 - 7)
6. Hour (BCD checks: in 24-hour mode, check r ange 00 - 23 a nd check that AM/PM flag is not set if RTC is set
in 24-hour mode; in 12-hour mode check range 01 - 12)
7. Minute (check BCD and range 00 - 59)
8. Second (check BCD and range 00 - 59)
Note: If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the
returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the
AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked.
15.5.5 RTC Internal Free Running Counter Error Checking
To improve the reliability and security of the RTC, a permanent ch eck is per formed on the internal free running
counters to report non-BCD or invalid date/time values.
An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The
flag can be cleared by programming the TDERRCLR in the RTC status clear control register (RTC_SCCR).
Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the
TDERR flag. The clearing of the source of such error can be done either by reprogramm ing a correct value on
RTC_CALR and/or RTC_TIMR registers.
The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e.
every 10 seconds for SECONDS[3:0] bitfield in RTC_TIMR register). In this case the TDERR is held high until a
clear command is asserted by TDERRCLR bit in RTC_SCCR register.
15.5.6 Updating Time/Calendar
To update any of the time/calendar fie lds, the user must first stop the RTC by setting the cor responding field in the
Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be
set to update calendar fields (century, year, month, date, day).
Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit
reads 1, it is mandatory to cle ar this flag by writing the corresponding bit in RTC_SCCR. The user can now write to
the appropriate Time and Calendar register .
Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control
When entering programm ing mode of the calendar fields, the time fields remain enabled. When entering the
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the
calendar logic circuity (downstream for low-power considerations). It is highly recomm ended to prepare all the
fields to be updated before entering programmin g mode. In successive up date operations, the user mu st wait at
least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these
bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit.
After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.
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Figure 15-2. Update Sequence
Prepare TIme or Calendar Fields
Set UPDTIM and/or UPDCAL
bit(s) in RTC_CR
Read RTC_SR
ACKUPD
= 1 ?
Clear ACKUPD bit in RTC_SCCR
Update Time and/or Calendar values in
RTC_TIMR/RTC_CALR
Clear UPDTIM and/or UPDCAL bit in
RTC_CR
No
Yes
Begin
End
Polling or
IRQ (if enabled)
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15.5.7 RTC Accurate Clock Calibration
The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation.
The RTC is equipped with circuitry able to correct slow clock crystal drift.
To compensate fo r possible temperature varia tions over time, this accurate clock ca libration circuitry can be
programmed on-the-fly and also programmed during application manufac turing, in order to correct the cr ystal
frequency accuracy at ro om temper atur e (20-25°C). The typical clock drift range at room temperature is ±20 ppm.
In a temperature range of -40°C to +85°C, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200
ppm.
The RTC clock calibr ation cir cuitry allow s positive o r negative co rrectio n in a range o f 1.5 ppm to 1950 ppm . After
correction, the remaining crystal drift is as follows:
Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 90 ppm
Below 2 ppm, for an initial crystal drift between 90 ppm up to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm
The calibration circuitry acts by slightly modifying the 1 Hz clock period from time to time. When the period is
modified, depending on the sign of the correction, the 1 Hz clock period increa ses o r reduces by ar ound 4 ms. The
period interval between 2 correction events is programmable in order to cover the po ssible crystal oscillator clock
variations.
The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20-25 deg rees Celsius) can be
compensated if a reference clock/signal is use d to measure such inaccuracy. This kin d of calibration operation can
be set up during the final product manufacturing by means of measurement equipment embedding such a
reference clock. The correction of value must be programmed into the RTC Mode Register (RTC_MR), and this
value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this
calibration. This room temperature calibration can be furt her processed by means of the networking capability o f
the target application.
In any event, this adjustment does not take into account the temperature variation.
The frequency drift (u p to -200 ppm) due to temperature variation can be compensated using a reference tim e if
the application c an access such a refe rence. If a reference time cannot be used, a temperature sensor can be
placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once
obtained, the temper ature may be converte d using a loo kup table (describ ing the accuracy/temper ature curve of
the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This
adjustment method is not base d on a measurement of t he crystal fre quency/drift and the refore can be improved by
means of the networking capability of the target application.
If no crystal frequency a djustment has been done durin g manufacturing, it is still possible to do it. In the case
where a reference tim e of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of
the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and
programming the HIGHPPM and CORRECTION bitfields on RTC_MR according to the difference measured
between the reference time and those of RTC_TIMR.
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15.6 Real-time Clock (RTC) User Interface
Note: If an offset is not listed in the table it must be considered as reserved.
Table 15-1. Register Mapping
Offset Register Name Access Reset
0x00 C ontrol Register RTC_CR Read-write 0x0
0x04 Mode Register RTC_MR Read-write 0x0
0x08 Time Register RTC_TIMR Read-write 0x0
0x0C Calendar Register RTC_CALR Read-write 0x01A11020
0x10 T im e Al arm Register RTC_ TIMALR Read-write 0 x0
0x14 C alendar Alarm Register RTC_CALALR Read-write 0x01010000
0x18 St atus Register RTC_SR Read-only 0x0
0x1C Status Clear Command Register RTC_SCCR Write-only –
0x20 Interrupt Enable Register RTC_IER Write-only –
0x24 Interrupt Disab le Register RTC_IDR Write-only –
0x28 Interrupt Mask Register RTC_IMR Read-only 0x0
0x2C Valid Entry Register RTC_VER Read -only 0x0
0x30–0xC4 Reserved Register – – –
0xC8–0xF8 Reserved Register – – –
0xFC Reserved Register – – –
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15.6.1 RTC Control Register
Name: RTC_CR
Address: 0x400E1460
Access: Read-write
• UPDTIM: Update Request Time Register
0 = No effect.
1 = Stops the RTC time counting.
Time counting co nsis ts of seco nd , min u te an d hou r coun te rs. Tim e cou n te rs can be pro gr amm e d on ce this bit is set and
acknowledged by the bit ACKUPD of the Status Register.
• UPDCAL: Update Request Calendar Register
0 = No effect.
1 = Stops the RTC calendar counting.
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once
this bit is set.
• TIMEVSEL: Time Event Selection
The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.
• CALEVSEL: Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
–––––– CALEVSEL
15 14 1312 11 10 9 8
–––––– TIMEVSEL
76543210
––––––UPDCALUPDTIM
Value Name Description
0 MINUTE Minute change
1 HOUR Hour change
2 MIDNIGHT Every day at midnight
3 NOON Every day at noon
Value Name Description
0 WEEK Week change (every Monday at time 00:00 :00)
1 MONTH Month change (every 01 of each month at time 00:00:00)
2 YEAR Year change (every January 1 at time 00:00:00)
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15.6.2 RTC Mode Register
Name: RTC_MR
Address: 0x400E1464
Access: Read-write
• HRMOD: 12-/24-hour Mode
0 = 24-hour mode is selected.
1 = 12-hour mode is selected.
• PERSIAN: PERSIAN Calendar
0 = Gregorian Calendar.
1 = Persian Calendar.
• NEGPPM: NEGative PPM Correction
0 = positive correction (the divider will be slightly lower than 32768).
1 = negative correction (the divider will be slightly higher than 32768).
Refer to CORRECTION and HIGHPPM field descriptions.
• CORRECTION: Slow Clock Correction
0 = No correction
1..127 = The slow clock will be corrected according to the formula given below in HIGHPPM description.
• HIGHPPM: HIGH PPM Correction
0 = lower range ppm correction with accurate correction.
1 = higher range ppm correction with accurate correction.
If the absolute valu e of the correction to b e applied is lower than 30ppm, it is re commended to clear HIGHPPM. HIGHPPM
set to 1 is recommended for 30 ppm correction and above.
Formula:
If HIGHPPM = 0, then the clock freque ncy correction range is from 1.5 ppm up to 9 8 ppm. The RTC accuracy is less
than 1 ppm for a rang e corr ection from 1.5 ppm up to 30 ppm..
The correction fi eld must be programmed according to the required correction in ppm, the formula is as follows:
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
HIGHPPM CORRECTION
76543210
– – – NEGPPM – – PERSIAN HRMOD
CORRECTION 3906
20 ppm×
-----------------------1–=
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286
The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field.
If HIGHPPM = 1, then the clock fre quency correctio n range is from 30.5 pp m up to 1950 ppm. Th e RTC accuracy is less
than 1 ppm for a rang e corr ection from 30.5 ppm up to 90 ppm.
The correction fi eld must be programmed according to the required correction in ppm, the formula is as follows:
The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field.
If NEGPPM is set to 1, the ppm correction is negative.
CORRECTION 3906
ppm
------------1–=
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15.6.3 RTC Time Register
Name: RTC_TIMR
Address: 0x400E1468
Access: Read-write
• SEC: Current Second
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour
The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
0 = AM.
1 = PM.
All non-significant bits read zero.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
–AMPM HOUR
15 14 1312 11 10 9 8
–MIN
76543210
–SEC
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15.6.4 RTC Calendar Register
Name: RTC_CALR
Address: 0x400E146C
Access: Read-write
• CENT: Current Century
The range that can be set is 19 - 20 (gregorian) or 13-14 (persian) (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year
The range that can be set is 00 - 99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Cu rre n t Mon th
The range that can be set is 01 - 12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week
The range that can be set is 1 - 7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month
The range that can be set is 01 - 31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
All non-significant bits read zero.
3130292827 26 25 24
–– DATE
2322 21 20 19 1817 16
DAY MONTH
15 14 1312 11 10 9 8
YEAR
76543210
–CENT
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15.6.5 RTC Time Alarm Register
Name: RTC_TIMALR
Address: 0x400E1470
Access: Read-write
Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and re-enable it
after the value has been changed. This requires up to 3 accesses to the RTC_TIMALR register. First access to only clear the
enable corresponding to the field to change (SECEN, MINEN, HOUREN), this access is not required if the field is already cleared.
The second access performs the change of the value (SEC, MIN, HOUR). The third access is require d to re-enable the field by
writing 1 in SECEN, MINEN, HOUREN fields.
• SEC: Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable
0 = The second-matching alarm is disabled.
1 = The second-matching alarm is enabled.
• MIN: Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Ena ble
0 = The minute-matching alarm is disabled.
1 = The minute-matching alarm is enabled.
• HOUR: Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable
0 = The hour-matching alarm is disabled.
1 = The hour-matching alarm is enabled.
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––––––––
2322 21 20 19 1817 16
HOUREN AMPM HOUR
15 14 1312 11 10 9 8
MINEN MIN
76543210
SECEN SEC
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15.6.6 RTC Calendar Alarm Register
Name: RTC_CALALR
Address: 0x400E1474
Access: Read-write
Note: To change one of the DA TE, MONTH fields, it is recommended to disable the field before changing the value and re-enable it after
the value has been changed. This requires up to 3 accesses to the RTC_CALALR register. First access to only clear the enable
corresponding to the field to change (DATEEN, MTHEN), this access is not required if the field is already cleared. The second
access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in
DATEEN, MTHEN fields.
• MONTH: Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable
0 = The month-matching alarm is disabled.
1 = The month-matching alarm is enabled.
•DATE: Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable
0 = The date-matching alarm is disabled.
1 = The date-matching alarm is enabled.
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DATEEN – DATE
2322 21 20 19 1817 16
MTHEN – – MONTH
15 14 1312 11 10 9 8
––––––––
76543210
––––––––
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15.6.7 RTC Status Register
Name: RTC_SR
Address: 0x400E1478
Access: Read-only
• ACKUPD: Acknowledge for Update
0 (FREERUN) = Time and calendar registers cannot be updated.
1 (UPDATE) = Time and calendar registers can be updated.
• ALARM: Alarm Flag
0 (NO_ALARMEVENT) = No alarm matching condition occurred.
1 (ALARMEVENT) = An alarm matching condition has occurred.
• SEC: Second Event
0 (NO_SECEVENT) = No second event has occurred since the last clear.
1 (SECEVENT) = At least one second event has occurred since the last clear.
• TIMEV: Time Event
0 (NO_TIMEVENT) = No time event has occurred since the last clear.
1 (TIMEVENT) = At least one time event has occurre d since the last clear.
The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following
events: minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event
0 (NO_CALEVENT) = No calendar event has occurred since the last clear.
1 (CALEVENT) = At least one calendar event has occurred since the last clear.
The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week
change, month change and year change.
• TDERR: Time and/or Date Free Running Error
0 (CORRECT) = The inter n al fre e ru nn in g co unte rs ar e ca rrying valid values since the last read of RTC_SR.
1 (ERR_TIMEDATE) = The internal free running counters have been corrupted (invalid date or time, non-BCD values)
since the last read and/or they are still invalid.
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––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
– – TDERR CALEV TIMEV SEC ALARM ACKUPD
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15.6.8 RTC Status Clear Command Register
Name: RTC_SCCR
Address: 0x400E147C
Access: Write-only
• ACKCLR: Acknowledge Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TDERRCLR: Time and/or Date Free Running Error Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
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––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
– – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR
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15.6.9 RTC Interrupt Enable Register
Name: RTC_IER
Address: 0x400E1480
Access: Write-only
• ACKEN: Acknowledge Update Interrupt Enable
0 = No effect.
1 = The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable
0 = No effect.
1 = The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable
0 = No effect.
1 = The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable
0 = No effect.
1 = The selected time ev ent interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable
0 = No effect.
1 = The selected calendar event interrupt is enabled.
• TDERREN: Time and/or Date Error Interrupt Enable
0 = No effect.
1 = The time and date error interrupt is enabled.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
– – TDERREN CALEN TIMEN SECEN ALREN ACKEN
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15.6.10 RTC Interrupt Disable Register
Name: RTC_IDR
Address: 0x400E1484
Access: Write-only
• ACKDIS: Acknowledge Update Interrupt Disable
0 = No effect.
1 = The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable
0 = No effect.
1 = The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable
0 = No effect.
1 = The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable
0 = No effect.
1 = The selected time ev ent interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable
0 = No effect.
1 = The selected calendar event interrupt is disabled.
• TDERRDIS: Time and/or Date Error Interrupt Disable
0 = No effect.
• 1 = The time and date error interrupt is disabled.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
– – TDERRDISCALDISTIMDISSECDISALRDISACKDIS
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15.6.11 RTC Interrupt Mask Register
Name: RTC_IMR
Address: 0x400E1488
Access: Read-only
• ACK: Acknowledge Update Interrupt Mask
0 = The acknowledge for update interrupt is disabled.
1 = The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask
0 = The alarm interrupt is disabled.
1 = The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask
0 = The second periodic interrupt is disabled.
1 = The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask
0 = The selected time ev ent interrupt is disabled.
1 = The selected time ev ent interrupt is enabled.
• CAL: Calendar Event Interrupt Mask
0 = The selected calendar event interrupt is disabled.
1 = The selected calendar event interrupt is enabled.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
–––CALTIMSEC ALR ACK
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15.6.12 RTC Valid Entry Register
Name: RTC_VER
Address: 0x400E148C
Access: Read-only
• NVTIM: Non-valid Time
0 = No invalid data has been detected in RTC_TIMR (Time Register).
1 = RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar
0 = No invalid data has been detected in RTC_CALR (Calendar Register).
1 = RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm
0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).
1 = RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm
0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).
1 = RTC_CALALR has contained invalid data since it was last programmed.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
––––NVCALALRNVTIMALRNVCALNVTIM
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16. Watchdog Timer (WDT)
16.1 Description
The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a
deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around
32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the
processor is in debug mode or idle mode.
16.2 Embedded Characteristics
12-bit key-pro tec te d pr og ra m m ab le co un te r
Watchdog Clock is independent from Processor Clock
Provides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode
16.3 Block Diagram
Figure 16-1. Watchdog Timer Block Diagram
=0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
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16.4 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becom es trapped in a deadlock. It is
supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the
Mode Register (WDT_ MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum
Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the
external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default
Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in
WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the
application requires.
If the watchdog is restarted by writin g into the WDT _CR register, the WDT_M R register must not be program med
during a period of time of 3 slow clock periods following the WDT_CR write access. In any case, programmin g a
new value in the WDT_MR register automatically initiates a restart instruction.
The Watchdog Mode Register (WDT_MR) can be written only once . Only a processor reset resets it. Writing the
WDT_MR register reloads the timer with the newly programmed mode parameters.
In normal oper ation, the user reloads the Watchdog at regu lar intervals before the timer underflow occurs, b y
writing the Control Register (WDT_CR) with the bit WDRSTT to 1. T he Watchdog counter is then immediately
reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR
register is write-protected. As a re sult, writing WDT_CR without the correct hard-coded key ha s no effect. If an
underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the
Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR).
To prevent a software deadlock that continu ously triggers the Watchdog, the relo ad of the Watchdog m ust occur
while the Watchdog cou nter is within a window between 0 and WDD , WDD is defined in the WatchDog Mode
Register WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a
Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault”
signal to the Reset Controller is asserted.
Note that this feature can be disabled by progr amming a WDD value greater than or equal to the WDV value. In
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not
generate an error. This is the default configuration on reset (the WDD and WDV va lues are equal).
The status bits WDUNF (Watch dog Unde rflow) and WDERR ( Watch dog Erro r) trigger an inter rupt, provide d the bit
WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the
WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the
processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”
signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value
programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 16-2 . Wa tc hdog Behavior
0
WDV
WDD
WDT_CR = WDRSTT
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
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16.5 Watchdog Timer (WDT) User Interface
Table 16-1 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register WDT_CR Write-only –
0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF
0x08 Status Register WDT_SR Read-only 0x0000_0000
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16.5.1 Watchdog Timer Control Register
Name: WDT_CR
Address: 0x400E1450
Access: Write-only
• WDRSTT: Watchdog Rest art
0: No effect.
1: Restarts the Watchdog if KEY is written to 0xA5.
• KEY: Password.
3130292827 26 25 24
KEY
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
–––––––WDRSTT
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
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16.5.2 Watchdog Timer Mode Register
Name: WDT_MR
Address: 0x400E1454
Access: Read-write Once
Note: The first write access prevents any further modification of the value of this register, read accesses remain possible.
Note: The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog
performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than
expected.
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
3130292827 26 25 24
WDIDLEHLT WDDBGHLT WDD
2322 21 20 19 1817 16
WDD
15 14 1312 11 10 9 8
WDDISWDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
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• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
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16.5.3 Watchdog Timer Status Register
Name: WDT_SR
Address: 0x400E1458
Access Read-only
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred sin ce th e las t rea d of WD T_ SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
––––––WDERRWDUNF
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17. Supply Controller (SUPC)
17.1 Description
The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup Low Power
Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from
this mode is possible on multiple wake-up sources. The SUPC also generates the Slow Clock by selecting either
the Low Power RC oscillator or the Low Power Crystal oscillator.
17.2 Embedded Characteristics
Manages the Core Power Supply VDDCORE and the Backup Low Power Mode by Controlling the
Embedded Voltage Regulator
A Supply Monitor Detection on VDDIO or a Brownout Detection on VDDCORE can Trigger a Core Reset
Generates the Slow Clock SLCK, by Sele cting Eith er the 22- 42 kHz Low Powe r RC Osci llator or th e 32 kHz
Low Power Crystal Oscillator
Supports Multiple Wake-up Sources, for Exit from Backup Low Power Mode
16 Wake-up Inputs (including Tamper inputs), with Programmable Debouncing
Real Time Clock Al arm
Real Time Timer Alarm
Supply Monitor Detection on VDDIO, with Programmable Scan Period and Voltage Threshold
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17.3 Block Diagram
Figure 17-1. Supply Controller Block Diagram
Software Controlled
Voltage Regulator
ADC
PIOA/B/C
Matrix
SRAM
Flash
Peripherals
Peripheral
Bridge
Zero-Power
Power-on Reset
Supply
Monitor
(Backup)
RTC
Embedded
32 kHz RC
Oscillator
Xtal 32 kHz
Oscillator
Supply
Controller
Brownout
Detector
(Core)
General Purpose
Backup Registers
Reset
Controller
Backup Power Supply
Core Power Supply
sm_on =
SMSMPL control
sm_out
rtc_alarm
SLCK
rtc_nreset
proc_nreset
periph_nreset
ice_nreset
Master Clock
MCK
SLCK
core_nreset
Main Clock
MAINCK
SLCK
NRST
XIN32
XOUT32
on = XTALSEL
XTALSEL
Slow Clock
SLCK
on = !XTALSEL
core_nreset
VDDIO
VDDCORE
VDDOUT
ADVREF
ADx
WKUP0 - WKUP15
on = !BODDIS
core_brown_out
RTT
rtt_alarm
SLCK
rtt_nreset
XIN
XOUT
VDDIO
VDDIN
PIOx
DAC
DAC0x
PLL
Embedded
12/8/4 MHz
RC
Oscillator
Xtal
Oscillator
Watchdog
Timer
Power
Management
Controller
Cortex-M
Processor
vr_on = VROFF / ONREG
controlled
Note1: FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins but are not physical
FSTT0 - FSTT15 (Note 1)
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17.4 Supply Controller Functional Description
17.4.1 Supply Controller Overview
The device can be div i de d int o two power supply areas:
The Backup VDDIO Power Supply: including the Supply Controller, a part of the Reset Controller, the Slow
Clock switch, the General Purpose Backup Registers, the Supply Monitor and the Clock which includes the
Real Time Timer and the Real Time Clock
The Core Power Supply: including the other part of the Reset Controller, the Brownout Detector, the
Processor, the SRAM memo ry, the FLASH memo ry an d th e Per iph e ral s
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when
the VDDIO power supply rises (when the system is starting) or when the Backup Low Power Mode is entered.
The SUPC also integrates the Slow Clock generator which is based on a 32 kHz crystal oscillator and an
embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, bu t the software can enable the
crystal oscillator and select it as the Slow Clock source.
The Supply Controller and the VDDIO power supply have a rese t circuitry based on a zero-power power-on reset
cell. The zero-power power-on reset allows the SUPC to start properly as soon as the VDDIO voltage becomes
valid.
At start-up of the system, once the backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is
stabilized, the SUPC starts up the core by sequentially enabling the internal Voltage Regulator, waiting that the
core voltage VDDCORE is valid, then releasing the reset signal of the core “vddcore_nreset” signal.
Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply
monitor detects a voltage on VDDIO that is too low, the SUPC can assert the reset signal of the core
“vddcore_nreset” signal until VDDIO is valid. Likewise, if the brownout detector detects a core voltage VDDCORE
that is too low, the SUPC can assert the reset signal “vddcore_nreset” until VDDCORE is valid.
When the Backup Low Power Mode is entered, the SUPC sequentially asserts the reset signal of the core power
supply “vddcore_nreset” and disables the voltage regulator, in order to supply only the VDDIO power supply. In
this mode the current consu mption is re duced to a fe w microam ps for Backup pa rt retention. Exit from this mode is
possible on multiple wake-up sources including an event on WKUP pins, or a Clock alarm. To exit this mode, the
SUPC operates in the same way as system start-up.
17.4.2 Slow Clock Generator
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as
the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the
embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate
frequency. The command is made by writing the Supply Controller Control Register (SUPC_CR) with the
XTALSEL bit at 1.This results in a sequence which first configures the PIO lines multiplexed with XIN32 and
XOUT32 to be driven by the oscillator, then enables the crystal oscillator, then counts a number of slow RC
oscillator clock periods to cover the start-up time of the cry stal oscillator (refer to electrical characteristics for
details of 32KHz crystal oscillator start-up time), then switches the slow clock on the output of the crystal oscillator
and then disables the RC oscillator to save power. The switching time may vary according to the slow RC oscillator
clock frequency range. The switch of the slow clock source is glitch free. The OSCSEL bit of the Supply Cont ro ller
Status Register (SUPC_SR) allows knowing when the switch sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal osci llator in bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the
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product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) needs to be set at 1.
17.4.3 Core Voltage Regulator Control/Backup Low Power Mode
The Supply Controller can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. Please
refer to the electrical characteristics section.
The programme r can switch off the voltage regulator, and th us put the device in Backup mode, by writing the
Supply Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This asserts the vddcore_nrese t signal after the write resynchronization time which lasts, in the worse case, two
slow clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one
slow clock cycle before the core power supply shuts off.
When the user does not use the internal voltag e regulat or and wants to supply VDDCORE by an external supply, it
is possible to disable the voltage regulator. This is done through ONREG bit in SUPC_MR.
17.4.4 Supply Monitor
The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply and which monitors
VDDIO power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power
supply drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV.
This threshold is programmed in the SMTH field of the Supply Controller Supply Monitor Mode Register
(SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow
clock period s, according to t he choice of the use r. This c an be configured by programm ing the SMSMPL field in
SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consump tion
respectively by factors of 32, 256 or 2048, if the user does not need a continuous monitoring of the VDDIO power
supply.
A supply monitor detection can either ge nerate a reset of the core power supply or a wake-up of the core power
supply. Generating a core re se t whe n a sup ply moni to r de te ction occur s is enable d by writing the SMRST EN bit to
1 in SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the
SMEN bit to 1 in the Supply Controller Wake-up Mod e Register (SUPC_WUMR).
The Supply Controller pro vides two status bits in the Supply Controller Status Register for the sup ply monitor
which allows to determine whether the last wake-up was due to the supply monitor:
The SMOS bit provides real time info r ma tio n, which is updated at each measurement cycle or updated at
each Slow Clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurre d since the last
read of SUPC_SR.
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Su pply Monitor Mode
Register (SUPC_SMMR).
309
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Figure 17-2. Supply Monitor Status Bit and Associated Interrupt
17.4.5 Backup Power Supply Reset
17.4.5.1Raising the Backup Power Supply
As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset
cell maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply
Controller is entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is
released, a counter is started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to
stabilize.
After this time,the voltage regulator is enabled. T he core power supply rises and the brownout detector provid es
the bodcore_in signal as soo n as the core vo ltage VDDCORE is valid. This results in releasing the vdd core_nr eset
signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow
clock cycle.
Supply Monitor ON
3.3 V
0 V
Threshold
SMS and SUPC interrupt
Read SUPC_SR
Periodic Sampling
Continuous Sampling (SMSMPL = 1)
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Figure 17-3. Raising the VDDIO Power Supply
17.4.6 Core Reset
The Supply Controller manage s the vddcore_nreset signal to the Reset Controller, as describ ed previously in
Section 17.4.5 “Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting
down the core powe r su pp ly an d re lea se d as soo n as the cor e powe r su pp ly is corr e ctly re gu la te d.
There are two additional sources which can be programmed to activate vddcore_nreset:
a supply monitor detection
a brownout detection
17.4.6.1Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This can be enabled by sett ing the SMRSTEN
bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcor e_nrese t signal is immediately activated for
a minimum of 1 slow clock cycle.
Zero-Power Power-On
Reset Cell output
22 - 42 kHz RC
Oscillator output
Fast RC
Oscillator output
Backup Power Supply
vr_on
bodcore_in
vddcore_nreset
NRST
(no ext. drive assumed)
proc_nreset
Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.
periph_nreset
7 x Slow Clock Cycles 3 x Slow Clock
Cycles
2 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
TON Voltage
Regulator
Zero-Power POR
Core Power Supply
RSTC.ERSTL
(5 for startup slow RC + 2 for synchro.)
default = 2
311
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17.4.6.2Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage re gulation is
operating as progra mmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is
enabled, the Supply Controller can assert vddcore_nreset. This feature is enabled by writing the bit, BODRSTEN
(Brownout Detector Reset Enable) to 1 in the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulati on is lost (ou tp ut voltage of the re gulat or too low), the vdd core_nr eset
signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The
BODRSTS bit is set in the Su pply Contro ller Stat us Register (SUPC_SR) so that the user can know t he source of
the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
17.4.7 Wake-up Sources
The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically reenables the core power supply.
Figure 17-4. Wak e-up Sources
17.4.7.1Wake-up Inputs
The wake-up inputs, WKUP0 to WKUP15, can be programmed to perform a wake-up of the core power supply.
Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake-up
Inputs Register (SUPC_WUIR). The wa ke-up level can be selected with the correspo ndin g pol arity bit, WKUP PL0
to WKUPPL15, also located in SUPC_WUIR.
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
WKUPT0
WKUPT1
WKUP0
WKUP1
RTTEN
rtt_alarm
Debouncer
RTCOUT0
LPDBC
Debouncer
LPDBC
RTCOUT0
LPDBCS0
LPDBCS1
LPDBCEN1
Low/High
Level Detect
WKUPT1
LPDBCEN0
Low/High
Level Detect
WKUPT0
Low/High
Level Detect
Low/High
Level Detect
Low/High
Level Detect
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All the resulting signals are wired-ORed to trigger a debounce counter, which can be programmed with the
WKUPDBC field in the Supply Controller Wake-up Mode Register (SUPC_WUMR). The WKUPDBC field can
select a debouncing period of 3 , 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to
about 100 µs, abo ut 1 ms, about 16 ms, about 128 ms and ab out 1 second (for a typical slow clock frequency of 3 2
kHz). Programming WKUPDBC to 0x0 selects an immediate wake-up, i.e., an enabled WKUP pin must be active
according to its polarity during a minimum of one slow clock period to wake up the core power supply.
If an enabled WKUP pin is asserted for a time longer than the debouncing period, a wake-up of the core power
supply is started and the signals, WKUP0 to WKUP15 as shown in Figure 17-4, are latched in the Supply
Controller Status Register (S UPC_SR). This allows the us er to identify the source of the wake-up, however, if a
new wake-up cond itio n occurs, the primary information is lost. No new wake-up can be detected since the primary
wake-up condition has disappeared.
17.4.7.2Low-power Debouncer Inputs
It is possible to generate a wave fo rm (RTCOUT0) in all modes (including backup mode). It can be useful to contr ol
an external sensor and/or tampering function without waking up the processo r. Please refe r to the RTC section for
waveform ge ne ra tio n .
Two separate debouncers are embedded for WKUP0 and WKUP1 inputs.
The WKUP0 and/or WKUP1 inputs can be programmed to perform a wake-up of the core power supply with a
debouncing done by RTCOUT0.
These inputs can be also used when VDDCORE is powered to get tamper detection function with a low power
debounce function.
This can be enabled by setting LPDBC0 bit and/or LPDBC1 bit in SUPC_WUMR.
In this mode of operation, WKUP0 and/or WKUP1 must not be configured to also act as debouncing source for the
WKUPDBC counter (WKUPEN0 and/or WKUPEN1 must be cleared in SUPC_WUIR). Refer to Figure 17-4.
This mode of operation requires the RTC Output (RTCOUT0) to be configured to generate a duty cycle
programmable pu lse ( i.e . OUT0 = 0x7 in RTC_MR) in o rder to create the sampling points of both debou ncer s. Th e
sampling point is the falling edge of the RTCOUT0 waveform.
Figure 17-5 shows an example of an application where two tamper switch es are used. RTCOUT0 powers the
external pull-up used by the tampers.
Figure 17-5. Lo w Power Debouncer (Push-to-Make switch, pull-up resistors)
AT91SAM
WKUP0
WKUP1
RTCOUT0
Pull-Up
Resistor
Pull-Up
Resistor
GND
GND
GND
313
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Figure 17-6. Low Power Debouncer (Pus h-to-Break switch, pu ll-down resistors)
The debouncing parameters can be adjusted and are shared (except the wake-up input polarity) by both
debouncers. The number of successive identical samples to wa ke up the core ca n be config ure d from 2 up to 8 in
the LPDBC field of SUPC_WUMR. The period of time between 2 samples can be configured by programming the
TPERIOD field in the RTC_MR register.
Power parameters can be adjusted by modifying the period of time in the THIGH field in RTC_MR.
The wake-up pola rity of the inputs can be independentl y configured by writing WKUPT0 and WKUPT1 fields in
SUPC_WUMR.
In order to determine which wake-up pin triggers the core wake-up or simply which debouncer triggers an event
(even if there is no wake-up, so when VDDCORE is powered on), a status flag is associated for each low power
debouncer. These 2 flags can be read in the SUPC_SR.
A debounce event can perform an immediate clea r (0 delay) on f irst half the general purpose backup register s
(GPBR). The LPDBCCLR bit must be set to 1 in SUPC_MR.
Please note that it is not mandatory to use the RTCOUT pins when using the WKUP0/WKUP1 pins as tampering
inputs (TMP0/TMP1) in backup mo de or any other modes. Using RTCOUT0 pins provid es a “sampling mode” to
further reduce the power consumption in low power modes. However the RTC must be configure d in the same
manner as RTCOUT0 is used in order to create a sampling point for the debouncer logic.
Figure 17-7 s hows how to use WKUP0/WKUP1 without RTCOUT pins.
AT91SAM
WKUP0
WKUP1
RTCOUT0
Pull-Down
Resistors
GND GND
GND
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314
Figure 17-7. Using WKUP0/WKUP1 without RTCOUT Pins
17.4.7.3Low-power Tamper Detection Inputs
WKUP0 and WKUP1 can be used as tamper detect inputs.
In Backup Mode they can be used also to wake up the core.
If a tamper is detected, it performs an immediate clear (0 delay) on first half the general purpose backup registers
(GPBR).
Refer to “Wake-up Sources” on page 311 for more details.
17.4.7.4Clock Alarms
The RTC and the RTT alarm s can generate a wake-up of the core power supply. This can be enabled by writing
respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake-up Mode Register (SUPC_WUMR).
The Supply Controller does not provide any status as the information is available in the User Interface of either the
Real Time Timer or the Real Time Clock.
17.4.7.5Supply Monitor Detection
The supply monitor can generate a wake-up of the core power supply. See Section 17.4.4 “Supply Monitor”.
AT91SAM
WKUP0
WKUP1
RTCOUT0
VDD
Pull-Up
Resistor
Pull-Up
Resistor
GND
GND
GND
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17.5 Supply Controller (SUPC) User Interface
The User Interface of the Supply Controller is part of the System Controller User Interface.
17.5.1 System Controller (SYSC) User Interface
17.5.2 Supply Controller (SUPC) User Interface
Table 17-1. System Controller Registers
Offset System Controller Peripheral Name
0x00-0x0c Reset Controller RSTC
0x10-0x2C Supply Controller SUPC
0x30-0x3C Real Time Timer RTT
0x50-0x5C Watchdog Timer WDT
0x60-0x8C Real Time Clock RTC
0x90-0xDC General Purpose Backup Register GPBR
0xE0 Reserved
0xE4 Write Protect Mode Register SYSC_WPMR
0xE8-0xF8 Reserved
Table 17-2 . Register Mapping
Offset Register Name Access Reset
0x00 Supply Controller Control Register SUPC_CR Write-only N/A
0x04 Supply Controller Supply Monitor Mode Register SU PC_SMMR Read-write 0x00 00_0000
0x08 Supply Controller Mode Register SUPC_MR Read-write 0x0000_5A00
0x0C Supply Controller Wake-up Mode Register SUPC_WUMR Read-write 0x0000_0000
0x10 Supply Controller Wake-up Inputs Register SUPC_WUIR Read-write 0x0000_0000
0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0000
0x18 Reserved
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316
17.5.3 Supply Controller Control Register
Name: SUPC_CR
Address: 0x400E1410
Access: Write-only
• VROFF: Voltage Regulator Off
0 (NO_EFFECT) = no effect.
1 (STOP_VREG) = if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator.
• XTALSEL: Crystal Oscillator Select
0 (NO_EFFECT) = no effect.
1 (CRYSTAL_SEL) = if KEY is correct, switches the slow clock on the crystal oscillator output.
• KEY: Password
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––XTALSELVROFF––
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
317
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17.5.4 Supply Controller Supply Monitor Mode Register
Name: SUPC_SMMR
Address: 0x400E1414
Access: Read-write
• SMTH: Supply Monitor Threshold
Allows to select the threshold voltage of the supply monitor. Refer to electrical characteristics for voltage values.
• SMSMPL: Supply Monitor Sampling Period
• SMRSTEN: Supply Monitor Reset Enable
0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a supply monitor detection occurs.
1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
• SMIEN: Supply Monitor Interrupt Enable
0 (NOT_ENABLE) = the SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 (ENABLE) = the SUPC interrupt signal is asserted when a supply monitor detection occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – SMIEN SMRSTEN – SMSMPL
76543210
–––– SMTH
Value Name Description
0x0 SMD Supply Monitor disabled
0x1 CSM Continuous Supply Monitor
0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods
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17.5.5 Supply Controller Mode Register
Name: SUPC_MR
Address: 0x400E1418
Access: Read-write
• BODRSTEN: Brownout Detector Reset Enable
0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs.
1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
• BODDIS: Brownout Detector Disable
0 (ENABLE) = the core brownout detector is enabled.
1 (DISABLE) = the core brownout detector is disabled.
• ONREG: Voltage Regulator enable
0 (ONREG_UNUSED) = Internal voltage regulator is not used (external power supply is used)
1 (ONREG_USED) = internal voltage regulator is used
• OSCBYPASS: Oscillator Bypass
0 (NO_EFFECT) = no effect. Clock selection depends on XTALSEL value.
1 (BYPASS) = the 32-KHz XTAL oscillator is selected and is put in bypass mode.
• KEY: Password Key
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––OSCBYPASS––––
15 14 13 12 11 10 9 8
ONREGBODDISBODRSTEN––––
76543210
––––––––
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
319
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17.5.6 Supply Controller Wake-up Mode Register
Name: SUPC_WUMR
Address: 0x400E141C
Access: Read-write
• SMEN: Supply Monitor Wake-up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake-up effect.
1 (ENABLE) = the supply monitor detection forces the wake-up of the core power supply.
• RTTEN: Real Time Timer Wake-up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake-up effect.
1 (ENABLE) = the RTT alarm signal forces the wake-up of the core power supply.
• RTCEN: Real Time Clock Wake-up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake-up effect.
1 (ENABLE) = the RTC alarm signal forces the wake-up of the core power supply.
• LPDBCEN0: Low power Debouncer ENable WKUP0
0 (NOT_ENABLE) = the WKUP0 input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP0 input pin is connected with low power debouncer and can force a core wake-up.
• LPDBCEN1: Low power Debouncer ENable WKUP1
0 (NOT_ENABLE) = the WKUP1input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP1 input pin is connected with low power debouncer and can force a core wake-up.
• LPDBCCLR: Low power Debouncer Clear
0 (NOT_ENABLE) = a low power debounce event does not create an immediate clear on first half GPBR regis te rs.
1 (ENABLE) = a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR
registers.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– LPDBC
15 14 13 12 11 10 9 8
– WKUPDBC ––––
76543210
LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –
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• WKUPDBC: Wake-up Inputs Debouncer Period
• LPDBC: Low Power DeBounCer Period
Value Name Description
0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge.
1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods
2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods
3 512 _SCLK WKUPx shall be in its active state for at least 512 SLCK periods
4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods
5 3 2768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods
6 Reserved Reserved
7 Reserved Reserved
Value Name Description
0 DISABLE Disable the low power debouncer.
1 2_RTCOUT0 WKUP0/1 in its active state for at least 2 RTCOUT0 periods
2 3_RTCOUT0 WKUP0/1 in its active state for at least 3 RTCOUT0 periods
3 4_RTCOUT0 WKUP0/1 in its active state for at least 4 RTCOUT0 periods
4 5_RTCOUT0 WKUP0/1 in its active state for at least 5 RTCOUT0 periods
5 6_RTCOUT0 WKUP0/1 in its active state for at least 6 RTCOUT0 periods
6 7_RTCOUT0 WKUP0/1 in its active state for at least 7 RTCOUT0 periods
7 8_RTCOUT0 WKUP0/1 in its active state for at least 8 RTCOUT0 periods
321
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17.5.7 System Controller Wake-up Inputs Register
Name: SUPC_WUIR
Address: 0x400E1420
Access: Read-write
• WKUPEN0 - WKUPEN15: Wake-up Input Enable 0 to 15
0 (DISABLE) = the corresponding wake-up input has no wake-up effect.
1 (ENABLE) = the corresponding wake-up input forces the wake-up of the core power supply.
• WKUPT0 - WKUPT15: Wake-up Input Type 0 to 15
0 (LOW) = a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the
core power supply.
1 (HIGH) = a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the
core power supply.
31 30 29 28 27 26 25 24
WKUPT15 WKUPT14 WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8
23 22 21 20 19 18 17 16
WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0
15 14 13 12 11 10 9 8
WKUPEN15 WKUPEN14 WKUPEN13 WKUPEN12 WKUPEN11 WKUPEN10 WKUPEN9 WKUPEN8
76543210
WKUPEN7 WKUPEN6 WKUPEN5 WKUPEN4 WKUPEN3 WKUPEN2 WKUPEN1 WKUPEN0
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17.5.8 Supply Controller Status Register
Name: SUPC_SR
Address: 0x400E1424
Access: Read-only
Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK), the status register flag reset is taken
into account only 2 slow clock cycles after the read of the SUPC_SR.
• WKUPS: WKUP Wake-up Status
0 (NO) = no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of
SUPC_SR.
• SMWS: Supply Monitor Detection Wake-up Status
0 (NO) = no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
• BODRSTS: Brownout Detector Reset Status
0 (NO) = no core brownout rising edge event has been detected since the last read of the SUPC_SR.
1 (PRESENT) = at least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detec-
tion cell. The rising edge event occurs only when there is a voltage transition below the threshold.
• SMRSTS: Supply Monitor Reset Status
0 (NO) = no supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1 (PRESENT) = at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
• SMS: Supply Monitor Status
0 (NO) = no supply monitor detection since the last read of SUPC_SR.
1 (PRESENT) = at least one supply monitor detection since the last read of SUPC_SR.
• SMOS: Supply Monitor Output Status
0 (HIGH) = the supply monitor detected VDDIO higher than its threshold at its last measurement.
1 (LOW) = the supply monitor detected VDDIO lower than its threshold at its last measurement.
31 30 29 28 27 26 25 24
WKUPIS15 WKUPIS14 WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8
23 22 21 20 19 18 17 16
WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0
15 14 13 12 11 10 9 8
–LPDBCS1LPDBCS0–––––
76543210
OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS –
323
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• OSCSEL: 32-kHz Oscillator Selection Status
0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator.
1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator.
• LPDBCS0: Low Power Debouncer Wake-up Status on WKUP0
0 (NO) = no wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of
SUPC_SR.
• LPDBCS1: Low Power Debouncer Wake-up Status on WKUP1
0 (NO) = no wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of
SUPC_SR.
• WKUPIS0-WKUPIS15: WKUP Input Status 0 to 15
0 (DIS) = the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up
event.
1 (EN) = the corresponding wake-up input was active at the time the debouncer triggered a wake- up event.
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17.5.9 System Controller Write Protect Mode Register
Name: SYSC_WPMR
Access: Read-write
•WPEN:
0: The Write Protection is disabled.
1: The Write Prote c tio n is enab le d.
LList of the write-pr ot ec te d re gisters:
RSTC Mode Register
RTT Mode Register
RTT Alarm Register
RTC Control Register
RTC Mode Register
RTC Time Alarm Register
RTC Calendar Alarm Register
General Purpose Backup Registers
SUPC Control Register
SUPC Supply Monitor Mode Register
SUPC Mode Register
SUPC Wake-up Mode Register
SUPC Wake-up Input Mode Register
•WPKEY:.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x525443 PASSWD Writing any other value in this field ab orts the write operation of the WPEN bit.
Always reads as 0.
325
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18. General Purpose Backup Registers (GPBR)
18.1 Description
The System Controller embeds Eight general-purpose backup registers.
It is possible to generate an immediate clear of the content of general-purpose backup registers 0 to 3 (first half), if
a low power debounce event is detected on a wakeup pin, WKUP0 or WKUP1. The content of the other general-
purpose backup registers (second half) remains unchanged.
To enter this mode of operation, the supply controller module must be programmed accordingly. In supply
controller SUPC_WUMR register, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and
LPDBC must be other than 0.
If a tamper event has been detected, it is not possible to write into general-purpose backup registers while the
LPDBCS0 or LPDBCS1 flags are not cleared in supply controller status register SUPC_SR.
18.2 Embedded Characteristics
Eight 32-bit General Purpose Backup Registers
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18.3 General Purpose Backup Registers (GPBR) User In terface
Table 18-1 . Register Mapping
Offset Register Name Access Reset
0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write –
... ... ... ... ...
0x1C General Purpose Backup Register 7 SYS_GPBR7 Read-write –
327
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18.3.1 General Purpose Backup Regi ster x
Name: SYS_GPBRx
Address: 0x400E1490 [0] .. 0x400E14AC [7]
Access: Read-write
• GPBR_VALUE: Value of GPBR x
If a tamper event has been detected, it is not possible to write GPBR_VALUE while the LPDBCS0 or LPDBCS1
flags are not cleared in supply controller status register SUPC_SR.
3130292827 26 25 24
GPBR_VALUE
2322 21 20 19 1817 16
GPBR_VALUE
15 14 1312 11 10 9 8
GPBR_VALUE
76543210
GPBR_VALUE
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19. Embedded Flash Controller (EFC)
19.1 Description
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal
bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing,
locking and unlockin g sequences of the Flash u sing a full set of commands. One of the commands returns the
embedded Flash descriptor definition that informs the system about the Flash organization, thus making the
software generic.
19.2 Embedded Characteristics
Interface of the Flash Block with the 32-bit Internal Bus
Increases Performance in Thumb2 Mode with 128-bit or -64 bit Wide Memory Interface up to 80 MHz
Code loops optimization
128 Lock Bits, Each Protecting a Lock Region
GPNVMx General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erases the Entire Flash
Erases by Plane
Erase by Sector
Erase by Pages
Possibility of Erasing before Programming
Locking and Un loc king Op er at ion s
Possibility to read the Calibration Bits
19.3 Product Dependencies
19.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller
has no effect on its behavior.
19.3.2 Interrupt Sources
The Enhanced Em bedded Flash Controller (EEFC) int errupt line is connected to the Nested Vect ored Interrupt
Controller (NVIC). Using the Enhanced Embedded Flash Controller (EEFC) interrupt requires the NVIC to be
programmed first. The EEFC interrupt is generated only on FRDY bit rising.
Table 19-1. Peripheral IDs
Instance ID
EFC 6
329
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19.4 Functional Description
19.4.1 Embedded Flash Organization
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:
One memory plane organized in several pages of the same size.
Two 128-bit or 64-bit read buf fers used for code read optimization.
One 128-bit or 64-bit read buffer used for data read optimization.
One write buf fer that manage s page programming. The write buf fer size is equal to the pag e size. This buffer
is write-only and acce ssible all along the 1 MByte addr ess space, so that each word can be written to its final
address.
Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is
associated with a lock region composed of several pages in the memory plane.
Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC)
interface, called General Purpose Non Volatile Memory bits (GPNVM bits).
The embedded Flash size, the page size, the lock regions organization and GPNVM bits definition are specific to
the produc t. T h e En ha nc ed Em be dd e d Fl as h Co n tro lle r (EEFC) returns a descriptor of the Flash controlled after a
get descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on page 335).
Figure 19-1. Embedded Flash Organization
19.4.2 Read Operations
An optimized controller manage s embedded Flash reads, thus increasing perfor mance when the processor is
running in Thumb2 mode by means of the 128- or 64- bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space rese rved for the internal memory area, the embedded
Flash wraps around the address space and appears to be repeated within it.
Start Address
Page 0
Lock Region 0
Lock Region 1
Memory Plane
Page (m-1)
Lock Region (n-1)
Page (n*m-1)
Start Address + Flash size -1
Lock Bit 0
Lock Bit 1
Lock Bit (n-1)
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The read operations can be performed with or without wait states. Wait states must be programmed in the field
FWS (Flash Read Wait State) in the Flash Mode Register (EEFC_FMR). Defining FWS to be 0 en able s the sin gle-
cycle access of the embedded Flash. Refer to the Electrical Characteristics for more details.
19.4.2.1128-bit or 64-bit Access Mode
By default the read accesses of the Flash are performed through a 12 8-bit wide memory interface. It enables
better system performance especially when 2 or 3 wait state needed.
For systems requiring only 1 wait state, or to privilege current consumption rather than performance, the user can
select a 64-bit wide memory access via the FAM bit in the Flash Mode Register (EEFC_FMR)
Please refer to the electrical characteristics section of the product datasheet for more details.
19.4.2.2Code Read Optimization
This feature is enabled if the EEFC_FMR register bit SCOD is cleared.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch.
Note: Immediate consecutive code rea d accesses are not mandatory to benefit from this optimization.
The sequential code rea d optimi zation is en abled by d efault. If the bit SCOD in Flash Mode Register (EEFC_FMR)
is set to 1, these buffers are disabled and the sequential code read is not optimized anymore.
Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch (see “Code Loops
Optimization” on page 331).
Figure 19-2. Code Read Op timization for FWS = 0
Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31 Bytes 32-47
Bytes 0-15
Buffer 1 (128bits)
Bytes 32-47
Bytes 0-3Bytes 4-7 Bytes 8-11 Bytes 12-15 Bytes 16-19 Bytes 20-23Bytes 24-27
XXX
XXX Bytes 16-31
@Byte 0 @Byte 4 @Byte 8@Byte 12 @Byte 16 @Byte 20 @Byte 24 @Byte 28@Byte 32
Bytes 28-31
331
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Figure 19-3. Code Read Optimization for FWS = 3
Note: When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
19.4.2.3Code Loops Optimization
The Code Loops optimization is enabled when the CLOE bit of the EEFC_FMR register is set at 1.
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken, and it
becomes inefficient. In this case the loop code read optimization takes over from the sequential code read
optimization to avoid insertion of wait states. The loop code read optimization is enabled by default. If in Flash
Mode Register (EEFC_FMR), the bit CLOE is reset to 0 or the bit SCOD is se t to 1 , th ese bu ffe rs are di sa bled an d
the loop code read is not optimized anymore.
When this feature is enabled, if inner loop body instructions L0 to Ln lay from the 128-bit flash memory cell Mb0 to
the memory cell Mp1, after recognition of a first backward branch, the two first flash memory cells Mb0 and Mb1
targeted by this branch are cached for fast access from the processor at the next loop iterations.
Afterwards, combining the sequential prefetch (described in Section 19.4.2.2 “Code Read O ptimization”) through
the loop body with the fast read access to the loop entry cache, the whole loop can be iterated with no wait-state.
Figure 19-4 below illustrates the Code Loops optimization.
Figure 19-4. Code Loops Optimization
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
@Byte 0 @4 @8
Bytes 0-15 Bytes 16-31 Bytes 32-47 Bytes 48-63
XXX Bytes 0-15
4-7 8-11 12-15
@12 @16 @20
24-27 28-3132-3536-3916-19 20-2340-4344-47
@24 @28@32@36 @40 @44 @48@52
Bytes 32-47
48-51
L
n
L
n-1
L
n-2
L
n-3
L
n-4
L
n-5
L
5
L
4
L
3
L
2
L
1
L
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
0
M
b
0
M
b0
M
b1
M
p0
M
p1
Backward address jump
2x128-bit loop entry
cache 2x128-bit prefetch
buffer
L
0
Loop Entry instruction
L
n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1
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19.4.2.4Data Read Optimization
The organi zation of the Flas h in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and
one 128-bit (or 64-b it) data read buffer, thus pro viding maximum system performance. This buffe r is added in order
to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up
sequential data reads if, for example, FWS is equal to 1 (see Figure 19-5). The data read optimization is enabled
by default. If the bit SCOD in Flash Mode Register (EEFC_FMR) is set to 1, this buffer is disabled and the data
read is not optimized anymore.
Note: No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 19-5. Data Read Optimization for FWS = 1
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31
Bytes 0-15
Bytes 0-34-7 8-11 12-15 16-19 20-23
XXX
Bytes 16-31
@Byte 0 @ 4 @ 8@ 12 @ 16 @ 20 @ 24 @ 28@ 32@ 36
XXX Bytes 32-47
24-27 28-3132-35
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19.4.3 Flash Commands
The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory
Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash er as in g , etc .
In order to perform one of these commands, the Flash Command Register (EEFC_FCR) has to be written with the
correct command using the FCMD field. As soon as the EEFC_FCR register is written, the FRDY flag and the
FVALUE field in the EEFC_FRR register are automatically cleared. Once the current command is achieved, then
the FRDY flag is automatically set. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the
corresponding interrupt line of the NVIC is activated. (Note that this is true for all command s except for the STUI
Command. The FRDY flag is not set when the STUI command is achieved.)
All the commands are protected by the same keyword, which has to be written in the 8 highest bits of the
EEFC_FCR register.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect
on the whole memory plane, but the FCMDE flag is set in the EEFC_FSR register. This flag is automatically
cleared by a read access to the EEFC_FSR register.
When the current command writes or erases a page in a locked region, the command has no effect on the whole
memory plane, but the FLOCKE flag is set in th e EEFC_F SR regis ter. This f lag is au tomatica lly cleare d by a read
access to the EEFC_FSR register.
Table 19-2. Set of Commands
Command Value Mnemonic
Get Flash Descriptor 0x00 GETD
Write page 0x01 WP
Write page and lock 0x02 WPL
Erase page and write page 0x03 EWP
Erase page and write page then lock 0x04 EWPL
Erase all 0x05 EA
Erase Pages 0x07 EPA
Set Lock Bit 0x08 SLB
Clear Lock Bit 0x09 CLB
Get Lock Bit 0x0A GLB
Set GPNVM Bit 0x0B SGPB
Clear GPNVM Bit 0x0C CGPB
Get GPNVM Bit 0x0D GGPB
Start Read Unique Identifier 0x0E STUI
Stop Read Unique Identifier 0x0F SPUI
Get CALIB Bit 0x10 GCALB
Erase Sector 0x11 ES
Write User Signature 0x12 WUS
Erase User Signature 0x13 EUS
Start Read User Signature 0x14 STUS
Stop Read User Signature 0x15 SPUS
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Figure 19-6. Command State Chart
Check if FRDY flag Set No
Yes
Read Status: MC_FSR
Write FCMD and PAGENB in Flash Command Register
Check if FLOCKE flag Set
Check if FRDY flag Set No
Read Status: MC_FSR
Yes
Yes Locking region violation
No
Check if FCMDE flag Set Yes
No
Bad keyword violation
Command Successfull
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19.4.3.1Getting Embedded Flash Descriptor
This command allows the system to le ar n a bout the Flash organization. The system can take full advantage of this
information. For instan ce , a device coul d be rep laced by one with more Flash capacity, and so the software is able
to adapt itself to the new configuration.
To get the embedded Flash de scr i ptor, th e app lica tio n wr ites the GETD command in the EEFC_FCR register. The
first word of the descriptor can be read by the software ap plication in the EEFC_FRR register as soon as the
FRDY flag in the EEFC_FSR register rises. The next reads of the EEFC_FRR register provide the following word
of the descriptor. If extra read operations to the EEFC_FRR register are done after the last word of the descriptor
has been returned, then the EEFC_FRR register value is 0 until the next valid command.
Table 19-3 . Flash Descriptor Definition
Symbol Word Index Description
FL_ID 0 Flash Interface Description
FL_SIZE 1 Flash size in bytes
FL_PAGE_SIZE 2 Page size in bytes
FL_NB_PLANE 3 Number of planes.
FL_PLANE[0] 4 Number of bytes in the first plane.
...
FL_PLANE[FL_NB_PLANE-1] 4 + FL_NB_PLANE - 1 Number of bytes in the last plane.
FL_NB_LOCK 4 + FL_NB_PLANE
Number of lock bits. A bit is associated
with a lock region. A lock bit is used to
prevent write or erase operations in the
lock region.
FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region.
...
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19.4.3.2Write Commands
Several commands can be used to program the Flash.
Flash technology requir es that an e rase be d one be fore progra mming. The full me mory pla ne can be erased at the
same time, or several pages can be erased at the same time (refer to Figure 19-7, "Example of Partial Page
Programming", and the paragraph below the figure.). Also, a page erase can be automatically done before a page
write using EWP or EWPL commands.
After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase
sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size.
The latch buffer wraps around within the internal memory area address space and is repeated as many times as
the number of pages within this address space.
Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in a number of wait states equal to the number of wait states for read operations.
Data are written to the latch buffe r before the programming comm and is written to the Flash Command Re gister
EEFC_FCR. The sequence is as follows:
Write the full page, at any page address, within the internal memory area address space.
Programming starts as soon as the p age number and the programming command are written to the Fl ash
Command Register. The FRDY bit in the Flash Programming Status Register (EEFC_FSR) is automatically
cleared.
When progra m m ing is comp le te d, th e FR DY bit in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the corresponding interrupt
line of the NVIC is activated.
Two errors can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to
unlock the corresponding region.
Flash Error: at the end of the programming, the Wr iteVerify test of the Flash memory has failed.
By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure
19-7 below). This mode is called Partial Programming.
The Partial Progra mming mode works only with 32-b it (or higher) boundaries . It cannot be used with boundaries
lower than 32 bits (8 or 16- bit for example). To wr ite a single byte o r a 16-bit halfword, the rem aining byte of the 32-
bit word must be filled with 0xFF, then the 32-bit word must be written to Flash buffer.
Note: If several 32-bit words need to be programmed, they must be written in ascending order to Flash buffer before
executing the write page command. If a write page command is executed after writing each single 32-bit word, the
write order of the word sequence does not matter.
After any power-on sequence, the Flash memory internal latch buffer is not initialized. Thus the latch buffer must
be initialized by writing the part-select to be programmed with user data and the remaining of the buffer must be
written with logical 1.
This action is not required for the next partial programming sequence because the latch buffer is automatically
cleared after programming the page.
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Figure 19-7. Example of Partial Page Programming
Erase All Flash Programming of the second part of Page Y Programming of the third part of Page Y
32-bit wide 32-bit wide 32-bit wide
X words FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
...
CA FE CA FE
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF CA FE CA FE
CA FE CA FE
CA FE CA FE
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1. Step 2. Step 3.
...
...
...
...
...
...
...
...
...
...
...
X words
X words
X words
So Page Y erased
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19.4.3.3Erase Commands
Erase commands are allowed only o n u nlocked re gion s. Depend ing on th e Flash memor y, several comm and s can
be used to erase the Flash:
Erase all memory (EA): all memory is erased. The processor must not fetch code from the Flash memory.
Erase pages (EPA): 4, 8, 16 or 32 pages are erase d in the memory plane. The first page to be erased is
specified in the FARG[15:2] field of the MC_FCR register. The first page numb er must be modulo 4, 8,16 or
32 according to the numb er of p ages to e rase at the same time. The processor must not fetch code from the
Flash memory.
Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. FARG must
be set with a page number that is in the sector to be erased. The processor must not fetch code from the
Flash memory.
The erase sequence is:
Erase starts as soon as one of the eras e co mm and s an d th e FARG field are written in the Fl as h Co mm a nd
Register.
For the EPA command, the 2 lowest bits of the FARG field define the number of pages to be erased
(FARG[1:0]):
When the prog ra m ming com ple te s, th e FRDY bit in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC
is activated.
Two errors can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Lock Error: at least one page to be erased belongs to a locked region. The erase command has been
refused, no page has been erased. A command must be run previously to unlock the corresponding region.
Flash Error: at the end of the programming, the EraseVerify test of the Flash memory has failed.
19.4.3.4Lock Bit Protection
Lock bits are associated with several pages in the embed ded Flash memo ry plane. This defines lock re gions in the
embedded Fla sh me mo ry pl an e. Th ey pr ev en t writing/erasing pr ot ec te d pa ge s.
The lock sequence is:
The Set Lock command (SLB) and a page number to be protected are written in the Flash Command
Register.
When the locking completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is
activated.
The result of the SLB command can be checked running a GLB (Get Lock Bit) command.
Note: The value of the FARG argument passed together with SLB command must not excee d the higher lock bit index
available in the product.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Table 19-4. FARG Field for EPA command:
FARG[1:0] Number of pages to be erased with EPA command
0 4 pages
1 8 pages
2 16 pages
3 32 pages
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Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
It is possible to clear lock bits previously set. Then th e locked region can be erased or progra mmed. The unlock
sequence is:
The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command
Register.
When the unlock completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is
activated.
Note: The value of the FARG argument passed together with CLB command must not exceed the higher lock bit index
available in the product.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC) . The Get Lock Bit
status sequence is:
The Get Lock Bit command (GLB) is written in the Flash Command Register, FARG field is meaningless.
Lock bits can be read by the software application in the EEFC_FRR register. The first word read
corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful.
Extra reads to the EEFC_FRR register return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock region is locked.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
Note: Access to the Flash in read is permitted when a set, clear or get lock bi t command is performed.
19.4.3.5GPNVM Bit
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to specific product details for
information on GPNVM bit action.
The set GPNVM bit sequence is:
Start the Set GPNVM Bit command (SGPB) by writing the Flash Comm an d Re gis ter with th e SGPB
command and the number of the GPNVM bit to be set.
When the GPNVM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt was enable d by settin g the F RDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
The result of the SGPB command can be checked by running a GGPB (Get GPNVM Bit) command.
Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index
available in the product. Flash Data Content is not altered if F ARG exceeds the limit. Command Error is detected only
if FARG is greater than 8.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
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It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
Start the Clear GPNVM Bit command (CGPB) by writing the Fl ash Command Register with CGPB and the
number of the GPNVM bit to be cleared.
When the clear comp letes, the FRDY bit in the F lash Progra mming Status Register (EEFC_FSR) rises. If an
interrupt has been enabled by settin g the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
Note: The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index
available in the product. Flash Data Content is not altered if F ARG exceeds the limit. Command Error is detected only
if FARG is greater than 8.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
The status of GPNVM bits can be returned by t he Enhanced Embedded Flash Controller (EEFC). The sequence
is:
Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The FARG field is
meaningless.
GPNVM bits can be read by the software application in the EEFC_FRR register. The first word read
corresponds to the 32 first GPNVM bits , following reads provide the next 32 GPNVM bits as long as it is
meaningful. Extra reads to the EEFC_FRR register return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third GPNVM bit is active.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Note: Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is performed.
19.4.3.6Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
It is impossible to modify the calibration bits.
The status of calibration bits can be returned by the Enhanced Embe dded Flash Contr oller (EEFC). The sequence
is:
Issue the Get CALIB Bit command by writing the Flash Command Register with GCALB (see Table 19-2).
The FARG field is meaningless.
Calibration bits can be read by the software application in the EEFC_FRR register. The first word read
corresponds to th e 3 2 fir st calibra tion b its, following reads p rovide th e next 32 calibr ation bits as long as it is
meaningful. Extra reads to the EEFC_FRR register return 0.
The 12/8/4 MH z Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB
Bit command. The table below shows the bit implementation for each frequency:
Table 19-5. Calibration Bit Indexes
The RC calibration for the 12 MHz is set to ‘1000000’.
RC Calibration Frequency EEFC_FRR Bits
8 MHz output [28 - 22]
4 MHz output [38 - 32]
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19.4.3.7Security Bit Protection
When the security is enabled, access to the Fl ash, either through the JTAG/SWD interface or through the Fa st
Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0 .
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
19.4.3.8Unique Identifier
Each part is programmed with a 2*512-bytes Unique Identifier. It can be used to generate keys for example. To
read the Unique Identifier the sequence is:
Send the Start Read unique Identifier command (STUI) by writing the Flash Command Register with the
STUI command.
When the Unique Identifier is ready to be read, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) falls.
The Unique Identifier is located in the first 128 bits of the Flash memory mapping, thus, at the address
0x00400000-0x004003FF.
To stop the Unique Identifier mode, the user needs to send the S top Read unique Identifier command (SPUI)
by writing the Flash Command Register with the SPUI command.
When the Stop read Unique Identifier command (SPUI) has been performed, the FRDY bit in the Flash
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Note that during the sequence, the software can not run out of Flash (or the second plane in case of dual plane).
19.4.3.9User Signature
Each part contains a User Signature of 512-bytes. It can be used by the user for stora ge. Re ad , write an d er ase of
this area is allowed.
To read the User Signature, the sequence is as follows:
Send the Start Read User Signature command (STUS) by writing the Flash Command Register with the
STUS command.
When the User Signature is ready to be read, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) falls.
The User Signature is located in the first 512 bytes of the Flash memory mapping, thus, at the address
0x00400000-0x004001FF.
To stop the User Signature mode, the user needs to send the S top Read User Signature command (SPUS)
by writing the Flash Command Register with the SPUS command.
When the Stop Read User Signature command (SPUI) has been performed, the FRDY bit in the Flash
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Note that during the sequence, the software can not run out of Flash (or the second plane, in case of dual plane).
One error can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
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To write the User Signature, the sequence is:
Write the full page, at any page address, within the internal memory area address space.
Send the Write User Signature command (WUS) by writing the Flash Command Register with the WUS
command.
When progra m m ing is comp le te d, th e FR DY bit in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt
line of the NVIC is activated.
Two errors can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the Wr iteVerify test of the Flash memory has failed.
To erase the User Signature, the sequence is:
Send the Erase User Signature command (EUS) by writing the Flash Command Register with the EUS
command.
When progra m m ing is comp le te d, th e FR DY bit in the Flash Programming Status Register (EEFC_FSR)
rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt
line of the NVIC is activated.
Two errors can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify test of the Flash memory has failed.
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19.5 Enhanced Embedded Flash Controller (EEFC) User Interface
The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with
base address 0x400E0800.
Table 19-6 . Register Mapping
Offset Register Name Access Reset State
0x00 EEFC Flash Mode Register EEFC_FMR Read-write 0x0400_0000
0x04 EEFC Flash Command Regist er EEFC_FCR Write-only –
0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x00000001
0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0
0x10 Reserved – – –
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19.5.1 EEFC Flash Mode Register
Name: EEFC_FMR
Address: 0x400E0A00
Access: Read-write
Offset: 0x00
• FRDY: Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
Number of cycles for Read/Write operations = FWS+1
• SCOD: Sequential Code Optimization Disable
0: The sequential code optimization is enabled.
1: The sequential code optimization is disabled.
No Flash read should be done during change of this register.
• FAM: Flash Access Mode
0: 128-bit access in read Mode only, to enhance access speed.
1: 64-bit access in read Mode only, to enhance power consumption.
No Flash read should be done during change of this register.
• CLOE: Code Loops Optimization Enable
0: The opcode loops optimization is disabled.
1: The opcode loops optimization is enabled.
No Flash read should be done during change of this register.
3130292827 26 25 24
–––––CLOE–FAM
2322 21 20 19 1817 16
–––––––SCOD
15 14 1312 11 10 9 8
–––– FWS
76543210
–––––––FRDY
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19.5.2 EEFC Flash Command Register
Name: EEFC_FCR
Address: 0x400E0A04
Access: Write-only
Offset:0x04
• FCMD: Flash Command
3130292827 26 25 24
FKEY
2322 21 20 19 1817 16
FARG
15 14 1312 11 10 9 8
FARG
76543210
FCMD
Value Name Description
0x00 GETD Get Flash Descriptor
0x01 W P Write page
0x02 WP L Write page and lock
0x03 EW P Era se page and write page
0x04 EW PL Erase page and write page then lock
0x05 EA Erase all
0x07 EPA Erase Pages
0x08 SL B Set Lock Bit
0x09 C LB Clear Lock Bit
0x0A GLB Get Lock Bit
0x0B SGPB Set GPNVM Bit
0x0C CGPB Clear GPNVM Bit
0x0D GGPB Get GPNVM Bit
0x0E STUI Start Read Unique Identifier
0x0F SPUI Stop Read Unique Identifier
0x10 GCALB Get CALIB Bit
0x11 ES Erase Sector
0x12 WUS Write User Signature
0x13 EUS Erase User Signature
0x14 STUS Start Read User Signature
0x15 SPUS Stop Read User Signature
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• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key
Erase all command Field is meaningless.
Erase sector command FARG must be set with a page number that is in the sector to be erased.
Erase pages command
FARG[1:0] defines the number of pages to be erased.
The page number from which the erase will start is defined as follows:
FARG[1:0]=0, start page = 4*FARG[15:2]
FARG[1:0]=1, start page = 8*FARG[15:3], FARG[2] undefined
FARG[1:0]=2, start page = 16*FARG[15:4], FARG[3:2] undefined
FARG[1:0]=3, start page = 32*FARG[15:5], FARG[4:2] undefined
Note: undefined bit must be written to 0.
Refer to Table 19-4 on page 338
Programming command FARG defines the page number to be programmed.
Lock command F ARG defines the page number to be locked.
GPNVM command FARG defines the GPNVM number.
Value Name Description
0x5A PASSWD The 0x5A value enables the command defined by the bits of
the register . If the field is written with a different value, the write
is not performed and no action is started.
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19.5.3 EEFC Flash Status Register
Name: EEFC_FSR
Address: 0x400E0A08
Access: Read-only
Offset:0x08
• FRDY: Flash Ready Status
0: The Enhanced Embedded Flash Controller (EEFC) is busy.
1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command.
When it is set, this flags triggers an interrupt if the FRDY flag is set in the EEFC_FMR register.
This flag is automatically cleared when the Enhanced Embedded Flash Controller (EEFC) is busy.
• FCMDE: Flash Command Error Status
0: No invalid commands and no bad keywords were written in the Flash Mode Register EEFC_FMR.
1: An invalid command and/or a bad keyword was/were written in the Flash Mode Register EEFC_FMR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLOCKE: Flash Lock Error Status
0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLERR: Flash Error Status
0: No Flash Memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed).
1: A Flash Memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed).
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
––––FLERRFLOCKEFCMDEFRDY
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19.5.4 EEFC Flash Result Register
Name: EEFC_FRR
Address: 0x400E0A0C
Access: Read-only
Offset:0x0C
• FVALUE: Flash Result Value
The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next
resulting value is accessible at the next register read.
3130292827 26 25 24
FVALUE
2322 21 20 19 1817 16
FVALUE
15 14 1312 11 10 9 8
FVALUE
76543210
FVALUE
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20. Fast Flash Programming Interface (FFPI)
20.1 Description
The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang
programmer. The parallel interface is fully handshaked and the device is conside red to be a standard EEPROM .
Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Although the Fast Flash Programming Mode is a dedicated mode for high volu me programming, this mode is not
designed for in-situ programming.
20.2 Embedded Characteristics
Programming Mode for High-volume Flash Programming Using Gang Programmer
Offers Read and Write Access to the Flash Memory Plane
Enables Control of Lock Bits and General-purpose NVM Bits
Enables Security Bit Activation
Disabled Once Security Bit is Set
Parallel Fast Flash Programming Interface
Provides an 16-bit Parallel Interface to Program the Embedded Flash
Full Handshake Protocol
20.3 Parallel Fast Flash Programming
20.3.1 Device Configuration
In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is sign ificant. The
rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left
unconnected.
Figure 20-1. SAM4NxB/C Para llel Programming Interface
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[15:0] PGMD[15:0]
XIN
TST
VDDIO
PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
GND
VDDIO
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20.3.2 Signal Names
Depending on the MO DE settings, DATA is latched in different internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command
register.
Table 20-1 . Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIO I/O Lines Power Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Suppl y Power
GND Ground Ground
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input 32 KHz to 50 MHz
Test
TST Test Mode Select Input High Must be connected to VDDIO
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PIO
PGMNCMD Valid command available Input Low Pulled-up input at reset
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Lo w Pulled-up input at reset
PGMNVALID 0: DATA[15:0] is in input mode
1: DATA [15:0] is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (see Table 20-2) Input Pulled-up input at reset
PGMD[15:0] Bi-directional data bus Input/Output Pulled-up input at reset
Table 20-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0101 DATA Data Register
Default IDLE No register
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20.3.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
Apply the supplies as described in Table 20-1.
Apply XIN clock within TPOR_RESET if an external clock is available.
Wait for TPOR_RESET
Start a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32
kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher
frequency on XIN speeds up the programmer handshake.
20.3.4 Programmer Handshaking
An handshake is de fined for read and writ e operations. When th e device is ready to start a new oper ation (RDY
signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once
NCMD signal is high and RDY is high.
20.3.4.1Write Handshaking
For details on the write handshaking sequence, refer to Figure 20-2 and Table 20-4.
Table 20-3. Command Bit Coding
DATA[15:0] Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Flash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page an d Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
0x0015 GLB Get Lock Bit
0x0034 SGPB Set General Purpose NVM bit
0x0044 CGPB Clear General Purpose NVM bit
0x0025 GGPB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x001E GVE Get Ve rsion
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Figure 20-2. Parallel Programming Timing, Write Sequence
20.3.4.2Read Handshaking
For details on the read handshaking sequence, refer to Figure 20-3 and Table 20-5.
Figure 20-3. Parallel Pro gramming Timing, Read Sequen ce
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
Table 20-4. Write Handshake
Step Programmer Action Device Action Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Releases MODE and DATA signals Executes command and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Se ts RDY Input
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
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20.3.5 Device Operations
Several commands on the Flash memo ry are available. These commands are summarized in Table 20-3 on page
351. Each command is driven by the programmer through the parallel interface running several read/write
handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command
after a write automatically flushes the load buffer in the Flash.
20.3.5.1Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid
address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-5. Read Handshake
Step Programmer Action Device Action DATA I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latch MODE and DATA Input
3 W ait s for RDY low Clears RDY signal Input
4 Sets DATA sign al in tristate Waits for NOE Low Input
5 Clears NOE signal Tristate
6 Wait s for NVALID low Sets DATA bus in output mode and outputs the flash contents. Output
7 Clears NVALID signal Output
8 Reads value on DATA Bus Waits for NOE high Output
9 Sets NOE signal Output
10 Waits for NVALID high Sets DATA bus in input mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal Waits for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
Table 20-6. Read Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Read handshaking DATA *Memory Address++
5 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Read handshaking DATA *Memory Address++
n+3 Read handshaking DATA *Memory Address++
... ... ... ...
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20.3.5.2Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that
corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:
before access to any page other than the current one
when a new command is validated (MODE = CMDE)
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write op eration. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is eras ed.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
20.3.5.3Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
Table 20-7. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-8. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
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20.3.5.4Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the
command. When bit 0 of the bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits.
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask
is set..
20.3.5.5Flash General-purpose NVM Commands
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command
also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set,
then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The general-
purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1.
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is
active when bit n of the bit mask is set..
20.3.5.6Flash Security Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disabled. No other command can be run. An event on the Erase pin can eras e the security bit
once the contents of the Flash have been erased.
Table 20-9. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SLB or CLB
2 Write handshaking DATA Bit Mask
Table 20-10. Get Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
Table 20-11. Set/Clear GP NVM Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SGPB or CGPB
2 Write handshaking DATA GP NVM bit pattern value
Table 20-12. Get GP NVM Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GGPB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
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Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
Power-off the chip
Power-on the chip with TST = 0
Assert Erase during a period of more than 220 ms
Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
20.3.5.7Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
20.3.5.8Get Version Command
The Get Version (GVE) command retrieves the ver sio n of the F FPI inte rfa ce .
Table 20-13. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
Table 20-14. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-15. Get Version Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GVE
2 Read handshaking DATA Version
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Figure 20-4. Serial Programing
TDI
TDO
TMS
TCK
XIN
TST
VDDIO PGMEN0
PGMEN1
0-50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
VDDIO
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21. SAM-BA Boot Program
21.1 Description
The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the d ifferent
memories of the pr od u ct.
21.2 Hardware and Software Constraints
SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size
can be used for user's code.
UART0 requiremen ts: None.
21.3 Flow Diagram
The Boot Program implements the algorithm illustrated in Figure 21-1.
Figure 21-1. Boot Program Algorithm Flow Diagram
The SAM-BA Boot Program uses the internal 12 MHz RC oscillator as source clock for PLL. The MCK runs from
PLL divided by 2. The core runs at 48 MHz.
21.4 Device Initialization
The initialization sequence is the following:
1. S tack setup
2. Set up the Embedded Flash Controller
3. Switch on internal 12 MHz RC oscillator
4. Config ur e PLL to ru n at 96 MHz
5. Switch MCK to run on PLL divided by 2
6. Configure UART0
7. Disable Watchdog
8. Wait for a character on UART0
9. Jump to SAM-BA monitor (see Section 21.5 “SAM-BA Monitor”)
Table 21-1. Pins Driven during Boot Prog ram Execution
Peripheral Pin PIO Line
UART0 URXD0 PA9
UART0 UTXD0 PA10
Device
Setup Character # received
from UART0?
Run SAM-BA Monitor
Yes
No
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21.5 SAM-BA Monitor
Once the communication interface is identified, the monitor runs in an infinite loop waiting for different commands
as shown in Table 21-2.
Mode commands:
Normal mode configures SAM-BA Monitor to send/receive data in binary format
Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format
Write commands: Write a byte (O), a half-word (H) or a word (W) to the target
Address: Address in hexadecimal
Value: Byte, half-word or word to write in hexadecimal
Output: ‘>’
Read commands: Read a byte (o), a half-word (h) or a word (w) from the target
Address: Address in hexadecimal
Output: The byte, half-word or word read in hexadecimal following by ‘>’
Send a file (S) : Sen d a file to a spec ifie d addr e s s
Address: Address in hexadecimal
Output: ‘>’
Note: There is a time-out on this command which is reach ed whe n the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receive data into a file from a specified address
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Output: ‘>’
Go (G): Jump to a specified address and execute the code
Address: Address to jump in hexadecimal
Output: ‘>’
Get Version (V): Return the SAM-BA boot version
Output: ‘>’
Table 21-2. Commands Available through the SAM-BA Boot
Command Action Argument(s) Example
NSet Normal mode No argument N#
TSet Terminal mode No argument T#
OWrite a byte Address, Value# O200001,CA#
oRead a byte Address,# o200001,#
HWrite a half-word Address, Value# H200002,CAFE#
hRead a half-word Address,# h200002,#
WWrite a word Address, Value# W200000,CAFEDECA#
wRead a word Address,# w200000,#
SSend a file Address,# S200000,#
RReceive a file Address, NbOfBytes# R200000,1234#
GGo Address# G200200#
VDisplay version No argument V#
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21.5.1 UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send th e application file to the target. The size of the binary file to se nd depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work. See Section 21.2 “Hardware and Software
Constraints”.
21.5.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver repo rt successful transmission. Each
block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data by te s-- ><c he ck sum > in wh ich:
<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16
Figure 21-2 s ho w s a tra ns m issio n us ing this pr ot oc ol.
Figure 21-2. Xmodem Tr ansfer Example
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
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21.5.3 In Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready
(looping while the FRDY bit is not set in the EEFC_FSR).
Since this fu nction is executed fro m ROM, this allows Flash programming (such as sector write) to be done by
code running in Flash.
The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the EEFC_FSR.
IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void){
unsigned long FlashSectorNum = 200; //
unsigned long flash_cmd = 0;
unsigned long flash_status = 0;
unsigned long EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function addre ss from NMI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x00800008;
/* Send your data to the sector here */
/* build the command to send to EEFC */
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) |
AT91C_MC_FCMD_EWP;
/* Call the IAP function with appropriate command */
flash_status = IAP_Function (EFCIndex, flash_cmd);
}
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22. Bus Matrix (MATRIX)
22.1 Description
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multiple AHB masters
and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 3 AHB Masters to 4 AHB
Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the
accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers that allow to
support application specific features.
22.2 Embedded Characteristics
22.2.1 Matrix Masters
The Bus Matrix of the SAM4N product manage s 3 masters, which means that each master can perform an access
concurrently with others, to an available slave.
Each master has its own deco der, which is d efined specifica lly for each master . In order to simpli fy the addressing,
all the masters have the same decodings.
22.2.2 Matrix Slaves
The Bus Matrix of the SAM4N product manages 4 slaves. Each slave has its own arbiter, allowing a different
arbitration per slave.
Table 22-1. List of Bus Matrix Masters
Master 0 Cortex-M4 Instruction/Data
Master 1 Cortex-M4 System
Master 2 Peripheral DMA Controller (PDC)
Table 22-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 Peripheral Bridge
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22.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example
allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not
wired and shown as “-” in the following table.
22.3 Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The deco der offers each AHB Master seve ral
memory mappings. In fact, depending on the product, each memory area may be assigned to seve ral slaves.
Booting at the same address while using different AHB slaves (i.e. internal ROM or internal Flash) becomes
possible.
22.4 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access req uests from
some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus
granting mechanism allows to set a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of defau lt masters: no default master, last access
master and fixed default master.
22.4.1 No Default Master
At the end of the current acce ss, if no other request is pending, the slav e is disconnected from all masters. No
Default Master suits low power mode.
22.4.2 Last Access Master
At the end of th e current access, if no oth er request is pending, the slave remains connected to the last master that
performed an access request.
22.4.3 Fixed Default Master
At the end of the current access, if no other request is pending , the slave connects to its fixed default master.
Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field
FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave
Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave
Configuration Register contains two fields:
DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master
type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEF MSTR field allows to
choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the
Bus Matrix user interface de scription.
Table 22-3. SAM4N Master to Slave Access
Masters 0 1 2
Slaves Cortex-M4 I/D Bus Cortex-M4 S Bus PDC
0Internal SRAM - X X
1Internal ROM X - X
2Internal Flash X - -
3 Peripheral Bridge - X X
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22.5 Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur,
basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is
provided, allowing to arbitrate each slave differently.
The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and this for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is given through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each slave.
When a re-arbitration has to be done, it is realized only under some specific conditions detailed in the following
paragraph.
22.5.1 Arbitration Rules
Each arbiter has the ability to arbitrate b etween two or more different master’s requests. In order to avoid burst
breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst,
predicted end of burst matches the size of the transfer but is managed differently for undefined length burst
(See Section 22.5.1.1 “Undefined Length Burst Arbitration” on page 364“).
4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master
access is too long and mu st be br ok en (S ee Section 22.5.1.2 “Slot Cycle Limit Arbitratio n” on page 364).
22.5.1.1Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific
logic in order to re-arbitrate before the end of the INCR transfe r.
A predicted end of burst is used as for defined length burst transfer, which is selected between the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR
transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR
transfer.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside
INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
22.5.1.2Slot Cycle Limit Arbitration
The Bus Matrix contains spe cific logic to break too long access es such as very long bursts on a very slow slave
(e.g. an external low speed memory). At the beginning of the burst access, a counter is loaded with th e value
previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and
decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end
of the current byte, half word or word transfer.
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22.5.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the sam e slave in a
round-robin manne r. If two or more master’s req uests arise at the same time, the master with the lowest number is
first serviced then the others are serviced in a round-robin manner.
There are th re e ro un d -r ob in alg o rith m imple m en te d:
Round-Robin arbitration without default master
Round-Robin arbitration with last access master
Round-Robin arbitration with fixed default master
22.5.2.1Round-Robin arbitration without default master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different
masters to the same slave in a pu re round-robin manner. At the end of th e current access, if no other request is
pending, the slave is disconnected fro m all ma sters. T his co nfigu ration incurs one latency cycle for th e first acce ss
of a burst. Arbitration without default master can be used for masters that perform significant bursts.
22.5.2.2Round-Robin arbitration with last access master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one
latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other
master request is pending, the slave remains connected to the last master that performs the access. Other non
privileged masters will still get one latency cycle if they want to access the same slave. This technique can be used
for masters that mainly perform single accesses.
22.5.2.3Round-Robin arbitration with fixed default master
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for
the fixed defaul t master per slave. At the end o f the curr ent access, the slave remains connected to its fixed default
master. Every request attempted by this fixed default master will not cause any latency whereas other non
privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform
single acces se s.
22.5.3 Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by
using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the
master with the highest priority numbe r is serviced first. If two or more master’s requests with the same priority are
active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for Slaves
(MATRIX_PRAS and MATRIX_PRBS).
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22.6 System I/O Configuration
The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in System I/O mode
(such as JTAG, ERASE, etc...) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in
peripheral mode o r in PIO mode ( PIO_PER or PIO_ PDR reg i sters) in the PIO controller as no effect. However, the
direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.
22.7 Write Protect Registers
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from
address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode
Register (MATRIX _WPMR).
If a write access to an yw he re in th e M AT RIX a dd re ss sp ace from address offset 0x000 to 0x1FC is detected, then
the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC
indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the
appropriate access key WPKEY.
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22.8 Bus Matrix (MATRIX) User Interface
Table 22-4 . Register Mapping
Offset Register Name Access Reset
0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000000
0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000
0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000
0x000C - 0x003C Reserved – – –
0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Re ad-write 0x00010010
0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Re ad-write 0x00050010
0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Re ad-write 0x00000010
0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x00000010
0x0050 - 0x007C Reserved – – –
0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Re ad-write 0x00000000
0x0084 Reserved – – –
0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Re ad-write 0x00000000
0x008C Reserved – – –
0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Re ad-write 0x00000000
0x0094 Reserved – – –
0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Re ad-write 0x00000000
0x009C - 0x0110 Reserved – – –
0x0114 System I/O Configuration register CCFG_SYSIO Read/Write 0x00000000
0x0118- 0x011C Reserved – – –
0x0120 - 0x010C Reserved – – –
0x0110 - 0x01FC Reserved – – –
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22.8.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0..MATRIX_MCFG2
Address: 0x400E0200
Access: Read-write
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR
burst.
2: Four Beat Burst
The undefine d len gt h burst is split into a 4-beat bursts allo win g re ar bit ra tio n at ea ch 4-be at bu r st en d.
3: Eight Beat Burst
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– ULBT
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22.8.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0..MATRIX_SCFG3
Address: 0x400E0240
Access: Read-write
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst it may be broken by another master tryin g to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small though. An unreasonable small value will break every burst and the Bus Matrix will
spend its time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of cu rr en t slave access, if no other master re que st is p end ing, the slave stays co nnected to the last master hav-
ing accessed it.
This results in not having the one cycle latency when the last master re-tries acc es s on th e sla ve ag a in.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the
number that has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEF MST R : Fix e d Defa ul t Ma s te r
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a
master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– – – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
––––––––
76543210
SLOT_CYCLE
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22.8.3 Bus Matrix Priority Registers For Slaves
Name: MATRIX_PRAS0..MATRIX_PRAS3
Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3]
Access: Read-write
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–– M3PR –– M2PR
76543210
–– M1PR –– M0PR
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22.8.4 System I/O Configuration Register
Name: CCFG_SYSIO
Address: 0x400E0314
Access Read-write
Reset: 0x0000_0000
• SYSIO4: PB4 or TDI Assignment
0 = TDI function selected.
1 = PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0 = TDO/TRAC ESWO function selected.
1 = PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0 = TMS/SWDIO function selected.
1 = PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0 = TCK/SWCLK function selected.
1 = PB7 function selected.
• SYSIO12: PB12 or ERASE Assignment
0 = ERASE function selected .
1 = PB12 function selected.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––SYSIO12––––
76543210
SYSIO7 SYSIO6 SYSIO5 SYSIO4 ––––
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22.8.5 Write Protect Mode Register
Name: MATRIX_WPMR
Access: Read-write
For more details on MATRIX_WPMR, refer to Section 22.7 “Write Protect Registers” on page 366.
• WPEN: Write Protec t ENa bl e
0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
Protects the entire MATRIX address space from address offset 0x 000 to 0x1FC.
• WPKEY: Write Protect KEY (Write-only)
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x4D4154 PASSWD Writing any other value in this field aborts the write operation of th e WPEN bit.
Always reads as 0.
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22.8.6 Write Protect Status Register
Name: MATRIX_WPSR
Access: Read-only
For more details on MATRIX_WPSR, refer to Section 22.7 “Write Protect Registers” on page 366.
• WPVS: Write Protect Violation Status
0: No Write Protect Viola tio n ha s oc cur red since the last write of MATRIX_WPMR.
1: At least one Write Protect Violation has occurred since the last write of MATRIX_WPMR.
• WPVSRC: Write Protect Violation Source
Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
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23. Peripheral DMA Controller (PDC)
23.1 Description
The Peripheral DMA Controller (PDC) transfer s data b etween on-chip serial peripher als and the o n- and/or o ff-chip
memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The u ser
interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointer s and two
16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The
bi-directional channel user interface contains four 32-bit m emory pointers and four 16-bit counters. Each set
(pointer, counter) is used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly
reduces the number of clock cycles required for a data transfer, which improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals.
When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
23.2 Embedded Characteristics
Performs Transfers to/from APB Communication Serial Peripherals
Supports Half-duplex and Full-duplex Peripherals
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23.3 Block Diagram
Figure 23-1. Block Diagram
PDC
FULL DUPLEX
PERIPHERAL
THR
RHR
PDC Channel A
PDC Channel B
Control
Status & Control
Control
PDC Channel C
HALF DUPLEX
PERIPHERAL
THR
Status & Control
RECEIVE or TRANSMIT
PERIPHERAL
RHR or THR
Control
Control
RHR
PDC Channel D
Status & Control
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23.4 Functional Description
23.4.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for each channel. The
user interface of each PDC channel is integrated into the associat ed peripheral user interface.
The user interface of a serial pe rip heral, whethe r it is full or half du plex, contains four 32-bit pointer s (RPR, RNPR,
TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive
parts of each type are programmed differently: the transmit and receive parts o f a full duplex peripheral can be
programmed at the same time, wh ereas only one part (transmit or receive) of a half duplex peripheral can be
programmed at a time.
32-bit pointer s define the a ccess location in memory for current and next transfer, whether it is for read (transmit)
or write (receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to
read the number of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The
status for each channel is located in the associated peripheral status register . Transfers can be enabled and/or
disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in
the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 23.4.3 and to the
associated peripheral user interface.
23.4.2 Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels
have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or of f-chip
memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit
memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or
receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-wo rd or word), the memo ry pointer is in cremented respective ly by 1,
2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the
new address.
23.4.3 Transfer Counters
Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters
define the size of data to be transferred by the channel. The current transfer counter is decremented first as the
data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches
zero, the channel checks its next transfer counter. If the value of next counter is zero, the channel stops
transferring data and sets the appropriate flag. But if the next counter value is greater than zero, the values of the
next pointer/next counter ar e copied into the current pointer/current counter and the channel resumes the transfer
whereas next pointer/next counte r get zero/zero as values.At the end of this transfer the PDC channel sets th e
appropriate flags in the Periphera l Status Register.
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The following list gives an overview of how status register flags behave depending on the counters’ values:
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the Peripheral Status Register.
23.4.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive
enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which
then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the
peripheral Receive Holding Register (RHR). The read data are stored in an internal buffer and then written to
memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then
requests access to the Matrix. When access is granted, the PDC tra nsmit channel reads data from mem ory and
puts them to Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data
according to its mechanism.
23.4.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back
flags to the peripheral. All these flags are only visible in the Peripheral Status Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two
different channels.
23.4.5.1Receive Transfer End
This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
23.4.5.2Transmit Transfer End
This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
23.4.5.3Receive Buffer Full
This flag is set when PERIPH_R CR register reaches zero with PERIPH_RNCR also set to zero and the last data
has been transferred to memory.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
23.4.5.4Transmit Buffer Empty
This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data
has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
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23.5 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the desired peripheral.)
Table 23-1 . Register Mapping
Offset Register Name Access Reset
0x00 Receive Pointer Register PERIPH(1)_RPR Read-write 0
0x04 Receive Counter Register PERIPH_RCR Read-write 0
0x08Transmit Pointer Register PERIPH_TPR Read-write 0
0x0C Transmit Counter Register PERIPH_TCR Read-write 0
0x10 Receive Next Pointer Register PERIPH_RNPR Read-write 0
0x14 Receive Next Counter Register PERIPH_RNCR Read-write 0
0x18Transmit Next Pointer Register PERIPH_TNPR Read-write 0
0x1C Transmit Next Counter Register PERIPH_TNCR Read-wr ite 0
0x20 Transfer Control Register PERIPH_PTCR Write-only 0
0x24 Transfer Status Register PERIPH_PTSR Read-only 0
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23.5.1 Receive Pointer Register
Name: PERIPH_RPR
Access: Read-write
• RXPTR: Receive Pointer Register
RXPTR must be set to receive buffer address.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
3130292827 26 25 24
RXPTR
2322 21 20 19 1817 16
RXPTR
15 14 1312 11 10 9 8
RXPTR
76543210
RXPTR
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23.5.2 Receive Counter Register
Name: PERIPH_RCR
Access: Read-write
• RXCTR: Receive Counter Register
RXCTR must be set to receive buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the receiver
1 - 65535 = Starts peripheral data transfer if corresponding channel is active
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
RXCTR
76543210
RXCTR
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23.5.3 Transmit Pointer Register
Name: PERIPH_TPR
Access: Read-write
• TXPTR: Transmit Counter Registe r
TXPTR must be set to transmit buffer addr ess.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
3130292827 26 25 24
TXPTR
2322 21 20 19 1817 16
TXPTR
15 14 1312 11 10 9 8
TXPTR
76543210
TXPTR
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23.5.4 Transmit Counter Register
Name: PERIPH_TCR
Access: Read-write
• TXCTR: Transmit Counter Register
TXCTR must be set to transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the transmitter
1- 65535 = Starts peripheral data transfer if corresponding channel is active
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
TXCTR
76543210
TXCTR
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23.5.5 Receive Next Pointer Register
Name: PERIPH_RNPR
Access: Read-write
• RXNPTR: Receive Next Poin t er
RXNPTR contains next receive buffer address.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
3130292827 26 25 24
RXNPTR
2322 21 20 19 1817 16
RXNPTR
15 14 1312 11 10 9 8
RXNPTR
76543210
RXNPTR
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23.5.6 Receive Next Counter Register
Name: PERIPH_RNCR
Access: Read-write
• RXNCTR: Receive Next Counter
RXNCTR contains next receive buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
RXNCTR
76543210
RXNCTR
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23.5.7 Transmit Next Pointer Register
Name: PERIPH_TNPR
Access: Read-write
• TXNPTR: Transmit Next Pointer
TXNPTR contain s ne xt tra n sm i t bu ffer ad dr e ss.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
3130292827 26 25 24
TXNPTR
2322 21 20 19 1817 16
TXNPTR
15 14 1312 11 10 9 8
TXNPTR
76543210
TXNPTR
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23.5.8 Transmit Next Counter Register
Name: PERIPH_TNCR
Access: Read-write
• TXNCTR: Transmit Counter Next
TXNCTR contains next transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
TXNCTR
76543210
TXNCTR
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23.5.9 Transfer Control Register
Name: PERIPH_PTCR
Access: Write-only
• RXTEN: Receiver Transfer Enable
0 = No effect.
1 = Enables PDC receiver channel requests if RXTDIS is not set.
When a half duplex peripheral is co nnecte d to the PDC, enab ling the r eceiver ch annel req uests automa tically disab les the
transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex pe ripheral.
• RXTDIS: Receiver Transfer Disable
0 = No effect.
1 = Disables the PDC receiver channel requests.
When a half duplex per ipheral is co nnected to the PDC, disabl ing the rece iver channel re quests also disable s the transmit-
ter channel requests.
• TXTEN: Transmitter Transfer Enable
0 = No effect.
1 = Enables the PDC tran sm itte r chan n el re qu es ts.
When a half duplex peripheral is connected to the PDC, it enables the tran smitter channel requests only if RXTEN is not
set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• TXTDIS: Transmitter Transfer Disable
0 = No effect.
1 = Disables the PDC transmitter chan nel requests.
When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver
channel requests.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––TXTDISTXTEN
76543210
––––––RXTDISRXTEN
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23.5.10 Transfer Status Register
Name: PERIPH_PTSR
Access: Read-only
• RXTEN: Receiver Transfer Enable
0 = PDC receiver channel requests are disabled.
1 = PDC receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable
0 = PDC transmitter ch an n el requ es ts ar e disabled.
1 = PDC transmitter ch an n el requ es ts ar e en ab le d.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––––TXTEN
76543210
–––––––RXTEN
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24. Clock Generator
24.1 Description
The Clock Generator User Interface is embedd ed within the Power Management Controller and is described in
Section 25.16 “Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are
named CKGR_.
24.2 Embedded Characteristics
The Clock Generator is made up of:
A Low Power 32768 Hz Slow Clock Oscillator with bypass mode.
A Low Power RC Oscillator
A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator, which can be bypassed.
A factory programmed Fast RC Oscillator. 3 output frequencies can be selected: 12/8/4 MHz. By default 4
MHz is selected.
A 80 to 240 MHz programmable PLL (input from 8 to 32 MHz), capable of providing the clock MCK to the
processor and to the peripherals.
Write Protected Registers
It provides the following clocks:
SLCK, the Slow Clock, which is the only permanent clock within the system.
MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic Resonator-based
Oscillator or 12/8/4 MHz Fast RC Oscillator.
PLLACK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLA).
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24.3 Block Diagram
Figure 24-1. Clock Generator Block Diagram
24.4 Slow Clock
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as
the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the
embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
The Slow Clock is generated either by the Slow Clock Crystal Oscillator or by the Slow Clock RC Oscillator.
The selection between the RC or the crystal oscillator is made by writing the XTALSEL bit in the Supply Controller
Control Register (SUPC_CR).
24.4.1 Slow Clock RC Oscillator
By default, the Slow Clock RC Oscillator is enabled and selected. The user has to take into account the possible
drifts of the RC Oscillator. More details are given in the section “DC Characteristics” of the product datasheet.
It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR).
Power
Management
Controller
Main Clock
MAINCK
PLLA Cloc
k
PLLACK
ControlStatus
3-20 MHz
Crystal
Oscillator
MOSCSEL
Clock Generator
PLLA and
Divider
Embedded
12/8/4 MHz
Fast
RC Oscillator
XIN
XOUT
XIN32
XOUT32
Slow Clock
SLCK
XTALSEL
(Supply Controller)
Embedded
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
0
1
0
1
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24.4.2 Slow Clock Crystal Oscillator
The Clock Generator integrates a 32768 Hz low-power oscillator. In order to use this oscillator, the XIN32 and
XOUT32 pins must be connecte d to a 32768 Hz crysta l. Two externa l capacito rs must be wired a s shown in Figure
24-2. More details are give n in the section “DC Characteristics” of the product datasheet.
Note that the user is not obliged to use the Slow Clock Crystal and can use the RC oscillator instead.
Figure 24-2. Typical Slow Clock Crystal Oscillator Connection
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate
frequency. The command is made by writing the Supply Controller Control Register (SUPC_CR) with the
XTALSEL bit at 1. This results in a sequence which first configures the PIO lines multiplexed with XIN32 and
XOUT32 to be driven by the oscillator, then enables the crystal oscillator and then disables the RC oscillator to
save power. The switch of the slow clock source is glitch free. The OSCSEL bit of the Supply Controller Status
Register (SUPC_SR) tracks the oscillator frequency downstream. It must be read in order to be informed when the
switch sequence, initiated when a new value is written in MOSCSEL bit of CKGR_MOR, is done.
Coming back on the RC oscillator is only possible by shutting dow n the VDDIO power supply. If the user does not
need the crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected since by default the XIN32 and
XOUT32 system I/O pins are in PIO input mode with pull-up after reset.
The user can also set the crystal osci llator in bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the
product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) needs to be set at 1.
The user can set the Slow Clock Crystal Oscillator in bypass mode instead of connecting a crystal. In this case, the
user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin under these
conditions are given in the product electrical characteri stics section.
The programmer has to be sure to set the OSCBYPASS bit in the Supply Controller Mode Register (SUPC_MR)
and XTALSEL bit in the Supply Controller Control Register (SUPC_CR).
XIN32 XOUT32 GND
32768 Hz
Crystal
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24.5 Main Clock
Figure 24-3 shows the Main Clock block diagram.
Figure 24-3. Main Clock Block Diagram
The Main Clock has two sources:
12/8/4 MHz Fast RC Oscillator which starts very quickly and is used at start-up.
3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator which can be bypassed.
24.5.1 Fast RC Oscillator
After reset, the 12/8/4 MHz Fast RC Oscillator is enabled with the 4 MHz frequency selected and it is selected as
the source of MAINCK. MAINCK is the default clock selected to start up the system.
The Fast RC Oscillator frequencies are calibrated in production except the lowest frequency which is not
calibrated.
Please refer to the “DC Characteristics” section of the product datasheet.
The software can disable or enabl e the 12/8/4 MHz Fast RC Osc illator with the MOSCRCEN bit in the Clock
Generator Main Oscillator Register (CKGR_MOR).
The user can also select the output frequency of the Fast RC Oscillator, either 12/8/4 MHz are available. It can be
done through MOSCRCF bits in CKGR_MOR. When changing this frequency selection, the MOSCRCS bit in the
Power Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until
the oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and MOSCRCS is set.
XIN
XOUT
MOSCXTEN
MOSCXTCNT
MOSCXTS
Main Clock
Frequency
Counter
MAINF
MAINRDY
SLCK
Slow Clock
3-20 MHz
Crystal
or
Ceramic Resonator
Oscillator
3-20 MHz
Oscillator
Counter
MOSCRCEN
Fast RC
Oscillator
MOSCRCS
MOSCRCF
MOSCRCEN
MOSCXTEN
MOSCSEL
MOSCSEL MOSCSELS
1
0
MAINCK
Main Clock
MAINCK
Main Clock
Ref.
RCMEAS
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When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power
Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger
an interrupt to the processor.
It is recommended to disable the Main Clock as soon as the processor no longer uses it and runs out of SLCK.
The CAL4, CAL8 and CAL12 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values
set by Atmel during production. These values are stored in a specific Flash memory area different from the main
memory plane. These values cannot be modified by the user and cannot be erased by a Flash erase command or
by the ERASE pin. Values written by the user's application in PMC_OCR are reset after each power up or
peripheral reset.
24.5.2 Fast RC Oscillator Clock Frequency Adjustment
It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default, SEL4/8/12 are
low, so the RC oscillator will be driven with Flash calibration bits which are programmed during chip production.
The user can adjust the trimming of the 12/8/4 MHz Fast RC Oscillator through this register in order to obtain more
accurate frequency (to compensate derating factors such as temperature and voltage).
In order to calibrate the oscillator lower frequency, SEL4 must be set to 1 and a good frequency value must be
configured in CAL4. Likewise, SEL8/12 must be set to 1 and a trim value must be configured in CAL8/12 in order
to adjust the other frequencies of the oscillator.
It is possible to adjust the oscillator frequency while operating from this clock. For example, when running on
lowest frequency it is possible to change the CAL4 value if SEL4 is set in PMC_OCR.
It is possible to restart, at anytim e, a measurem ent of the main frequency by means of the RCMEAS bit in Main
Clock Frequency Register (CKGR_MCFR). T hus, when MAINFRDY flag reads 1, another r ead access on Main
Clock Frequency Register (CKGR_MCFR) provides an image of the frequency of the main clock on MAINF field.
The software can calculate the error with an expected frequen cy and correct the CAL4 (or CAL8/CAL12) field
accordingly. This may be used to compensate frequency drift due to derating factors such as temperature and/or
voltage.
24.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillat or
After reset, the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is disabled and it is not selected as the
source of MAINCK.
The user can select the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of MAINCK,
as it provides a more accurate frequency. The software enables or disables the m ain oscillator so as to reduce
power consumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR
is automatically cleared, indicating the Main Clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to
the start-up time of the oscillator. This start-up time depends on the crystal frequency connected to the oscillator.
When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the XIN
and XOUT pins are automatically switched into oscillator mode and MOSCXTS bit in the Power Management
Controller Status Register (PMC_SR) is cleared and the counter starts coun ti ng down on the slow clock divided by
8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum start-up time is
about 62 ms.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the
MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor.
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24.5.4 Main Clock Oscillator Selection
The user can select either the 12/8/4 MH z Fast RC Oscillator or the 3 to 20 MHz Crystal or Ceramic Resonator-
based oscillator to be the source of Main Clock.
The advantage of the 12/8/4 MHz Fast RC Oscillator is that it provides fast start-up time, this is why it is selec ted
by default (to start up the system) and when entering Wait Mode.
The advantage of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is that it is very accurate.
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
the Main Clock source is glitch free, so there is no need to run out of SLCK, PLLACK in order to change the
selection. The MOSCSELS bit of the Power Management Controller Status Register (PMC_SR) allows knowing
when the switch se qu en ce is don e.
Setting the MOSCSELS bit in PMC_IMR can trig ge r an interr up t to the pr oc essor.
Enabling the Fast RC Oscillator (MOSCRCEN = 1) and changing the Fast RC Frequency (MOSCCRF) at the
same time is not allowed.
The Fast RC must be enabled first and its frequency changed in a second step.
24.5.5 Software Sequence to Detect the Presence of Fa st Crystal
The frequency meter carried on the CKGR_MCFR register is operating on the selected main clock and not on the
fast crystal clock nor on the fast RC Oscillator clock.
Therefore, to check for the presence of the fast crystal clock, it is necessary to have the main clock (MAINCK)
driven by the fast crystal clock (MOSCSEL=1).
The following software sequence order must be followed:
MCK must select the slow clock (CSS=0 in the PLL_MCKR register).
Wait for the MCKRDY flag in the PLL_SR register to be 1.
The fast crystal must be enabled by programming 1 in the MOSCXTEN field in the CKGR_MOR
register with the MOSCXTST field being programmed to the appropriate value (see the Electrical
Characteristics chapter).
Wait for the MOSCXTS flag to be 1 in the PLL_SR register to get the end of a start-up period of the
fast crystal oscillator.
Then, MOSCSEL must be programmed to 1 in the CKGR_MOR register to select fast main crystal
oscillator for the main clock.
MOSCSEL must be read until its value equals 1.
Then the MOSCSELS status flag must be checked in the PLL_SR register.
At this point, 2 cases may occur (either MOSCSELS = 0 or MOSCSELS = 1).
If MOSCSELS = 1, there is a valid crystal connected and its frequency can be determined by initiating
a frequency measure by programming RCMEAS in the CKGR_MCFR register.
If MOSCSELS = 0, there is no fast crystal clock (either no crystal connected or a crystal clock out of
specification).
A frequency measure can reinforce this status by initiating a frequency measure by programming
RCMEAS in the CKGR_MCFR register.
If MOSCSELS=0, the selection of the main clock must be programmed back to the main RC oscillator
by writing MOSCSEL to 0 prior to disabling the fast crystal oscillator.
If MOSCSELS=0, the crystal oscillator can be disabled (MOSCXTEN=0 in the CKGR_MOR register).
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24.5.6 Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock freq uency counter is reset and starts incrementing at the Main Clo ck speed after the next rising
edge of the Slow Clock in the following cases:
When the 12/8/4 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this
oscillator becomes stable (i.e., when the MOSCRCS bit is set)
When the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is selected as the source of Main
Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
When the Main Clock Oscillator selection is modified
When the RCMEAS bit of CKGR_MFCR is written to 1.
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Cloc k Frequency
Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of
CKGR_MCF R and gives the numbe r of Main C lock cycle s during 16 periods of Slow Clock, so that the f requency
of the 12/8/4 MHz Fast RC Oscillator or 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator can be
determined.
24.6 Divider and PLL Block
The device features one Divider/PLL Block that permits a wid e range of frequencies to be selected on either the
master clock, the pr ocess or clock or the programmable clock outputs. Figure 24-4 shows the bloc k diagram of the
dividers and PLL blocks.
Figure 24-4. Divider and PLL Block Diagram
24.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding di vider and the PLL outpu t is a continuous signa l at level 0. On re set, ea ch DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
The PLL (PLLA) allows multiplication of the divider’s outp ut. The PLL clock signal has a fr equency that de pends on
the respective source signal frequ en cy and on the pa rameters DIV (DIVA) and MUL (MULA). The factor applied to
the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0 and DIV=0, the PLL is disabled and its
power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL
field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC _SR is
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR)
are loaded in the PLL cou nter . The PLL cou nter then de cr ements at the speed of the Slow Clock until it reache s 0.
At this time, the LOCK bit is set in PMC_SR and can tr igg e r an inter rupt to the processor . The user has to load the
number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
Divider
DIVA
PLLA
MULA
PLLACOUNT
LOCKA
OUTA
SLCK
MAINCK PLLACK
PLLA
Counter
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The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC Master Clock Register
(PMC_MCKR).
It is forbidden to change 12/8/4 MHz Fast RC Oscillator, or main selection in CKGR_MOR register while Master
Clock source is PLL and PLL reference clock is the Fast RC Oscillator.
The user must:
Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_IER.
Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
Wait for PLLRDY.
Switch back to PLL.
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25. Power Management Controller (PMC)
25.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user
peripheral clocks. The PMC en ables/disables the clock inputs to many of the pe ripherals and the Cortex-M4
Processor.
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is
disabled automatically so that power consumption is optimized.
By default, at start-up the chip runs out of the Master Clock using the Fast RC Oscillator running at 4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequencies by software.
25.2 Embedded Characteristics
The Power Management Controller prov ides the following clocks:
MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the
device. It is available to the modules running permanently, such as the Enhanced Embedded Flash
Controller.
Processor Clock (HCLK) , must be switched off when entering the processor in Sleep Mode.
Free running processor Clock (FCLK)
The Cortex-M4 SysTick external clock
Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SPI, TW I, TC , HSMC I,
etc.) and inde pend e nt ly con tro lla ble . In or de r to reduc e th e nu m be r of clo ck nam es in a pr od u ct, th e
Peripheral Clocks are named MCK in the product datasheet.
Programmable Clock Output s can be selected from the cl ocks provided by the clock generator an d driven on
the PCKx pins.
Write Protected Registers
The Power Mana ge m en t Con tr olle r als o pr ov ide s the follo win g op er at ion s on clock s:
A main crystal oscillator clock failure detector.
A 32768 kHz crystal oscillator frequency monitor.
A frequency counter on main clock and an on-the-fly adjustable main RC oscillator frequency.
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25.3 Block Diagram
Figure 25-1. Gen eral Clock Block Diagram
25.4 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided
to all the peripherals.
The Master Clock is selected from on e of the clocks provided by the Clock Generator. Selecting the Slow Clock
provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL.
The Master Clock Co nt ro ller is mad e up of a clock sele cto r an d a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master
Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and
the division by 3. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Cl ock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the Master Clock is established. Then, the MCKRDY bit is set and can tr igger an interrupt to the processor.
This feature is useful wh en switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
Management
Controller
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
PLLA and
Divider/2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/3,/4,/8,
/16,/32,/64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
Clock Controller
(PMC_PCERx) ON/OFF
Prescaler
/1,/2,/4,/8,
/16,/32,/64 pck[..]
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
Processor clock
Free Running Clock
Master Clock
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
PRES
PLLADIV2 PRESCSS
CSS
MCK
Clock Generator
XTALSEL
Slow Clock
Power
Peripherals
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Figure 25-2. Master Clock Controller
25.5 Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode. The
Processor Clock can be disabled by execu ting the WFI (WaitForInterrupt) or the WFE (Wa itForEvent) processor
instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
Processor Sleep Mo de is achieved by disabling the Process or Clock, which is automatically re-enabled b y any
enabled fast or normal interrupt, or by the reset of the product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is stopped, but this
does not prevent data transfers from other masters of the system bus.
25.6 SysTick Clock
The SysTick calibration value is fixed to 10000 which allows the generation of a time base of 1 ms with SysTick
clock to the maximum frequency on MCK divided by 8.
25.7 Peripheral Clock Controller
The Power Management Controller cont rols the clocks of each embedded peripheral by m eans of the Peripheral
Clock Controller. The user can individually enable and disable the Clock on the peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0),
Peripheral Clock Disable 0 (PMC_PCDR0). The status of the peripheral clock activity can be read in the Peripheral
Clock Status Register (PMC_PCSR0) .
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peri pheral has executed it s
last programmed operatio n before disabling the clock. Th is is to avoid data corruption or erroneous behavior of the
system.
The bit number within the Peripheral Clock Control regist ers (PMC_PCER0, PMC_PC DR0, and PMC_PCSR0) is
the Peripheral Identifier defined at the product level. The bit number corresponds to the interrupt source number
assigned to the peripheral.
25.8 Free Running Processor Clock
The Free Runnin g Processor Clock (FCLK) used for samp ling interrupts and clocking debug blo cks ensures tha t
interrupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to
Master Clock (MCK).
SLCK
Master Clock
Prescaler MCK
PRESCSS
MAINCK
PLLACK
To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
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25.9 Programmable Clock Output Controller
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently programmed
via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock (MAINCK), the PLLA Clock
(PLLACK),and the Master Clock (MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be
divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the correspon ding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR (System Clock Status Register).
Moreover, lik e the PCK, a stat us bit in PM C_SR ind icates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.
As the Program mable Clock Controller d oes not mana ge with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the
change is actually performed.
25.10 Fast Start-up
The device allows the processor to restart in less than 10 microseconds while the device is in Wait Mode.
The system enters Wait Mode either by writing the WAITMODE bit at 1 in the PMC Clock Generator Main
Oscillator Register (CKGR_MOR), or by executing the WaitForEvent (WFE) instruction of the processor while the
LPM bit is at 1 in the PMC Fast Start-up Mode Register (PMC_FSMR). Waiting for the MOSCRCEN bit to be
cleared is strongly recommended to ensure that the core will not execute undesired instructions.
Important: Prior to instructing the system to enter the Wait Mode, the internal sources of wake-up must be
cleared. It must be verified that none of the enabled external wake-up inputs (WKUP) hold an active po larity.
A Fast Start-up is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or
upon an active alarm from the RTC, RTT. The polarity of the 16 wake-up inputs is programmable by writing the
PMC Fast Start-up Polarity Register (PMC _F SPR).
The Fast Restart circuitry, as shown in Figure 25-3, is fully asynchronous and provides a fast start-up signal to the
Power Management Controller. As soon as the fast start- up signal is asserted, th e embedde d 12/8/4 MHz Fast RC
Oscillator restarts automatically.
When entering the Wait Mode, the embedded flash can be placed in low power mode depending on the
configurat ion of the FL PM in PM C_F S MR re gist er . This bitfield can be pr og r am m ed an yt ime an d will be taken into
account at the next time the system enters Wait Mode.
The power consumption reduction is optimal when configuring 1 (deep power down mode) in FLPM. If 0 is
programmed (standb y mode), the power consumption is slightly higher as compared to the deep power down
mode.
When programming 2 in FLPM, the Wa it Mode flash power consumption is equivalent to the active mode when
there is no read access on the flash.
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Figure 25-3. Fast Start-up Circuitry
Each wake-up input pin and alarm can be enabled to generate a Fast Start-up event by writing 1 to the
corresponding bit in the Fast Start-up Mode Register (PMC_FSMR).
The user interface does not pr ovide any status for Fast Start-up, but the user can easily recover this information by
reading the PIO Controller and the status registers of the RTC, RTT.
25.11 Main Crystal Clock Failure Detector
The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to identify an
eventual defect of this oscillator (for example, if the crystal is unconnected).
The clock failure detector can be enable d or disabled by means of the CFDEN bit in the PMC Clock Generator
Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if the 3 to 20 MHz Crystal or
Ceramic Resonator-based Oscillator is disabled, the clock failure detector is disabled too.
The slow RC oscillator must be enabled.The clock failure detection must be enabled only when system clock MCK
selects the fast RC Oscillator. Then the status register must be read 2 slow clock cycles after enabling.
A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or Ceramic
Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC oscillator controlling the
counter. The counter is cleared when the slow clock RC oscillator signal is low and enabled when the slow clock
RC oscillator is high. Thus the failure detection time is 1 slow clock RC oscillator clock period. If, during the high
level period of the slow clock RC oscillator, less than 8 fast crystal oscillator clock periods have been counted, then
a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the CFDEV flag is
set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not masked. The interrupt remains
active until a rea d operatio n in the PMC_ SR register. T he user can know the status of the clock failure detector at
any time by reading the CFDS bit in the PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock of MAINCK
(MOSCSEL = 1), and if the Master Clock Source is PL LACK (CSS = 2), a clock failure detection automatically
fast_restart
WKUP15
FSTT15
FSTP15
WKUP1
FSTT1
FSTP1
WKUP0
FSTT0
FSTP0
RTTAL
RTCAL
RTT Alarm
RTC Alarm
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402
forces MAINCK to be the source clock for the master clock (MCK).Then, regar dless of the PMC configuration, a
clock failure detection automatically forces the 12/8/4 MHz Fast RC Oscillator to be the source clock for MAINCK.
If the Fast RC Oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the
clock failure detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or Ceramic Resonator-
based Oscillator, to the 12/8/4 MHz Fas t RC Oscillator if the Master Clock source is Main Clock, or 3 slow clock
RC oscillator cycles if the Master Clock source is PLLACK .
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller.
With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock
failure is detected. This fault output rema ins active until the defect is detected and until it is cleared by the bit
FOCLR in the PMC Fault Output Clear Register (PMC_FOCR).
The user can know the status of the fault ou tp ut at an y time by reading the FOS bit in the PMC_SR register.
25.12 Slow Crystal Clock Frequency Monitor
The frequency of the slow clock crystal oscillator can be monitored by means of logic driven by the main RC
oscillator known as a reliable clock source. This function is enabled by configuring the X T32KFME bit of the Main
Oscillator Register (CKGR_MOR).
An error flag (XT32KERR in PMC_SR) is asserted when the slow clock crystal oscillator frequency is out of the +/-
10% nominal frequency value (i.e. 32768 kHz). The error flag can be cleared only if the slow clock frequency
monitoring is disabled.
When the main RC oscillator frequency is 4 MHz, the accuracy of the measurement is +/-40% as this frequency is
not trimmed during production. Therefore, +/-10% accuracy is obtained only if the RC oscillator frequency is
configured for 8 or 12 MHz.
The monitored clock frequency is declared invalid if at least 4 consecutive clock period measurement results are
over the nominal period +/-10%.
Due to the possible frequency variation of the embedded main RC oscillator acting as reference clock for the
monitor logic, any slow clock crystal frequency deviation over +/-10% of the nominal frequency is systematically
reported as an err or by m eans of XT 32KERR in PMC_SR. Be tween - 1% and -1 0% and +1% an d +10%, the error
is not systematica lly re po rt ed .
Thus only a crystal running at 32768 kHz frequency ensures that the error flag will not be asserted. The permitted
drift of the crystal is 10000ppm (1%), which allows any standard crystal to be used.
If the main RC frequency needs to be changed while the slow clock frequency monitor is operating, the monitoring
must be stopped prior to change the main RC frequency. Then it can be re-enabled as soon as MOSCRCS is set
in PMC_SR register.
The error flag can be defined as an interrupt source of the PMC by setting the XT32KERR bit of PMC_IER.
25.13 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register
(CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the
MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for
MOSCXTS field in the PMC_SR register to be set. This can be done either by polling the status register, or
by waiting the interrupt line to be raised if the associated interrupt to MOSCXTS has been enabled in the
PMC_IER register.
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
The main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
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2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main clock frequency. This measure can
be accomplished via the Main Clock Frequency Regis ter (CKG R_ MCFR).
Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in CKGR_MCFR by
performing another CKGR_MCFR read access. This provides the num ber of main clock cycles within
sixteen slow clock cycles.
3. Setting PLL and Divider:
All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR.
The DIV field is used to cont ro l the div ide r itse lf. It must be set to 1 when PLL is used. By default, DIV
parameter is set to 0 which means that the divider is turned off.
The MUL field is the PL L mu ltip lier fact or . Th is pa rame te r ca n be progr a mm e d be twe e n 0 and 62 . If MUL is
set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by
(MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR, after
CKGR_PLLAR has been written.
Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be set in the
PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if
the associated interrupt to LOCK has been enabled in PMC_IER. All parameters in CKGR_PLLAR can be
programmed in a single write operation. If at some stage one of the following parameters, MUL or DIV is
modified, the LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set
again. The user is constrained to wait for LOCK bit to be set before using the PLL output clock.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable vi a the Master Clock Regist er (PMC _MCKR).
The CSS field is used to select the Master Clock divider source. By default, the selected clock source is
main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between different va lues
(1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default,
PRES parameter is set to 1 which means that master clock is equal to main clock.
Once PMC_MCKR has bee n written, th e user must wait for the MCKRDY bit to be set in PMC_SR. This can
be done either by polling the status register or by waiting for the interrupt line to be raised if the associated
interrupt to MCKRDY has been enabled in the PMC_IER register.
The PMC_MCKR must not be programmed in a single write operation. The preferred programming
sequence for PMC_MCKR is as follows:
If a new value for CSS field corresponds to PLL Clock,
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to Main Clock or Slow Clock,
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in the PMC_SR.
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
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If at some stage one of the following parameters, CSS or PRES is modified, the MCKRDY bit will go low to
indicate that th e Ma st er Clock and the Pro ce sso r Clock ar e no t re ad y yet . The user must wait for MCK RDY
bit to be set again before using the Master and Processor Clocks.
Note: I F PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the
MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock. For further information, see
Section 25.14.2 “Clock Switching Waveforms” on page 405.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 2.
The Processor Clock is the Master Clock.
5. Selection of Prog ra m mab l e Cloc ks
Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. 3 Programmable
clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable
clock is enabled. By defa ult all Prog ra m ma bl e cloc ks ar e dis ab led .
Programmable Clock Registers (PMC_PCKx) are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are available:
main clock, slow clock, PLLACK, . By default, the clock source selected is slow clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose between
different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES
parameter. By default, the PRES parameter is set to 0 which means that master clock is equal to slow clock.
Once PMC_PCKx has b een programmed, The corr esponding Programmable clock must be enabled and th e
user is constrained to wait for the PCKRDYx bit to be set in PMC_SR. This can be done either by polling the
status register or by waiting the interrupt line to be raised, if the associated interrupt to PCKRDYx has been
enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
If the CSS and PRES parameters are to be modified, the correspond ing Prog r amm ab le clo ck mu st be
disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the
Programmable clock and wait for the PCKRDYx bit to be set.
6. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled
via registers PMC_PCER0, PMC_PCDR0.
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25.14 Clock Switching Details
25.14.1 Master Clock Switching T imings
Table 25-1 and give the worst case timings required for the Master Clock to switch from one selected clock to
another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional
time of 64 clock cycles of the newly selected clock has to be added.
Notes: 1. PLL designates the PLLA .
2. PLLCOUNT designates PLLACOUNT .
25.14.2 Clock Switching Waveforms
Figure 25-4. Switch Master Clock fro m Slo w Clock to PLLx Clock
Table 25-1. Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main
Clock –4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK 0.5 x Main Clock +
4.5 x SLCK –3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLLx Clock
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Figure 25-5. Switch Master Clock from Ma in Clock to Slow Clock
Figure 25-6. Change PLLx Prog ramming
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
Slow Clock
Slow Clock
PLLx Clock
LOCKx
MCKRDY
Master Clock
Write CKGR_PLLxR
407
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Figure 25-7. Programmable Clock Output Programming
25.15 Write Protection Registers
To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write
protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status
Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the appropriate
access key, WPKEY.
The protected registers are:
“PMC System Clock Enable Register”
“PMC System Clock Disable Register”
“PMC Peripheral Clock Enable Register 0”
“PMC Peripheral Clock Disable Register 0”
“PMC Clock Generator Main Oscillator Register”
“PMC Clock Generator PLLA Register”
“PMC Master Clock Register”
“PMC Programmable Clock Register”
“PMC Fast Start-up Mode Register”
“PMC Fast Start-up Polarity Register”
“PMC Oscillator Calibration Register”
PLLx Clock
PCKRDY
PCKx Output
Write PMC_PCKx
Write PMC_SCER
Write PMC_SCDR PCKx is disabled
PCKx is enabled
PLL Clock is selected
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25.16 Power Management Controller (PMC) User Interface
Note: If an offset is not listed in the table it must be considered as “reserved”.
Table 25-2 . Register Mapping
Offset Register Name Access Reset
0x0000 System Clock Enable Register PMC_SCER Write-only –
0x0004 System Clock Disable Register PMC_SCDR Write-only –
0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001
0x000C Reserved – – –
0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only –
0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only –
0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000 _0000
0x001C Reserved – – –
0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0000_0008
0x0024 Main Clock Frequency Register CKGR_MCFR Read-write 0x0000_0000
0x0028 PLLA Register CKGR_PLLAR Read-write 0x0000_3F00
0x002C Reserved – – –
0x0030 Master Clock Register PMC_ MCKR Read-write 0x0000 _0001
0x0034 - 0x003C Rese rved – – –
0x0040 Programmable Clock 0 Re gister PMC_PCK0 Read-write 0x0000_0000
0x0044 Programmable Clock 1 Re gister PMC_PCK1 Read-write 0x0000_0000
0x0048 Programmable Clock 2 Re gister PMC_PCK2 Read-write 0x0000_0000
0x004C - 0x005C Reserved – – –
0x0060 Interrupt Enable Register PMC_IER Write-only –
0x0064 Interrupt Disable Register PMC_ID R Write-only –
0x0068 Status Register PMC_SR Read-only 0x0001_0008
0x006C Interrupt Mask Register PMC_IMR Read-only 0 x0000_0000
0x0070 Fast Start-up Mode Register PMC_FSMR Read-write 0x0000_0000
0x0074 Fast S tart-up Polarity Register PMC_FSPR Read-write 0x0000_0000
0x0078 Fault Output Clear Register PMC_FOCR Write-only –
0x007C- 0x00E0 Reserved – – –
0x00E4 Write Protect Mode Register PMC_WPMR Read-write 0x0
0x00E8 Write Protect Status Register PMC_WPSR Read-only 0x0
0x00EC-0x00FC Reserved – – –
0x0100 - 0x0108 Reserved – – –
0x010C Reserved – – –
0x0110 Osci llator Calibration Register PMC_OCR Read-write 0x0040_4040
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25.16.1 PMC System Clock Enable Register
Name: PMC_SCER
Address: 0x400E0400
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––PCK2PCK1PCK0
76543210
––––––––
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410
25.16.2 PMC System Clock Disable Register
Name: PMC_SCDR
Address: 0x400E0404
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––PCK2PCK1PCK0
76543210
––––––––
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25.16.3 PMC System Clock Status Register
Name: PMC_SCSR
Address: 0x400E0408
Access: Read-only
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––PCK2PCK1PCK0
76543210
––––––––
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25.16.4 PMC Peripheral Clock Enable Register 0
Name: PMC_PCER0
Address: 0x400E0410
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corr es po nd in g pe rip he r al cloc k.
Note: To get PIDx, refer to identifiers as defined in th e se ction “Peripheral Identifiers” in the product datasheet.
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
3130292827 26 25 24
PID31PID30PID29PID28PID27 PID26 PID25 PID24
2322 21 20 19 1817 16
PID23PID22 PID21 PID20 PID19 PID18PID17 PID16
15 14 1312 11 10 9 8
PID15 PID14 PID13PID12 PID11 PID10 PID9 PID8
76543210
––––––––
413
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25.16.5 PMC Peripheral Clock Disable Register 0
Name: PMC_PCDR0
Address: 0x400E0414
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: To get PIDx, refer to identifiers as defined in th e se ction “Peripheral Identifiers” in the product datasheet.
3130292827 26 25 24
PID31PID30PID29PID28PID27 PID26 PID25 PID24
2322 21 20 19 1817 16
PID23PID22 PID21 PID20 PID19 PID18PID17 PID16
15 14 1312 11 10 9 8
PID15 PID14 PID13PID12 PID11 PID10 PID9 PID8
76543210
––––––––
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414
25.16.6 PMC Peripheral Clock Status Register 0
Name: PMC_PCSR0
Address: 0x400E0418
Access: Read-only
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: To get PIDx, refer to identifiers as defined in th e se ction “Peripheral Identifiers” in the product datasheet.
3130292827 26 25 24
PID31PID30PID29PID28PID27 PID26 PID25 PID24
2322 21 20 19 1817 16
PID23PID22 PID21 PID20 PID19 PID18PID17 PID16
15 14 1312 11 10 9 8
PID15 PID14 PID13PID12 PID11 PID10 PID9 PID8
76543210
––––––––
415
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25.16.7 PMC Clock Generator Main Oscillator Register
Name: CKGR_MOR
Address: 0x400E0420
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• KEY: Write Access Password
• MOSCXTEN: Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Crystal Oscillator is disabled.
1 = The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0.
When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator start-up time is achieved.
• MOSCXTBY: Main Crystal Oscillator Bypass
0 = No effect.
1 = The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN.
When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set.
Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag.
• WAITMODE: Wait Mode Command
0 = No effect.
1 = Enters the device in Wait Mode.
Note: The WAITMODE bit is write-onl y.
• MOSCRCEN: Ma in On -C hip RC Oscillator Enable
0 = The Main On-Chip RC Oscillator is disabled.
1 = The Main On-Chip RC Oscillator is enabled.
When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator start-up time is achieved.
31 30 29 28 27 26 25 24
–––––XT32KFMECFDENMOSCSEL
23 22 21 20 19 18 17 16
KEY
15 14 13 12 11 10 9 8
MOSCXTST
76543210
– MOSCRCF MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN
Value Name Description
0x37 PASSWD Writing any other value in this field aborts the write operation.
Always reads as 0.
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• MOSCRCF: Main On-Chip RC Oscillator Frequency Selection
At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz.
Note: M OSCRCF must be changed only if MOSCRCS is set in the PMC_SR register. Therefore MOSCRCF and MOSCRCEN cannot
be changed at the same time.
• MOSCXTST: Main Crystal Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time.
• MOSCSEL: Main Oscillator Selection
0 = The Main On-Chip RC Oscillator is selected.
1 = The Main Crystal Oscillator is selected.
• CFDEN: Clock Failure Detector Enable
0 = The Clock Failure Detector is disabled.
1 = The Clock Failure Detector is enabled.
Note: 1. The slow RC oscillator must be enabled when the CFDEN is enabled.
2. The clock failure detection must be enabled only when system clock MCK selects the fast RC Oscillator.
3. Then the status register must be read 2 slow clock cycles after enabling.
• XT32KFME: Slow Crystal Oscillator Frequency Monitoring Enable
0 = The 32768 Hz Crystal Oscillator Frequency Monitoring is disabled.
1 = The 32768 Hz Crystal Oscillator Frequency Monitoring is enabled.
Value Name Description
0x0 12_MHz The Fast RC Oscillator Frequency is at 12 MHz (default)
0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz
0x2 4_MHz The Fast RC Oscillator Frequency is at 4 MHz
417
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.8 PMC Clock Generator Main Clock Frequency Register
Name: CKGR_MCFR
Address: 0x400E0424
Access: Read-Write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• MAINF: Main Clock Frequency
Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINFRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled or a measure has just been started by means of RCMEAS.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
Note: To ensure that a correct value is read on the MAINF bitfield, the MAINFRDY flag must be read at 1 then another read access must
be performed on the register to get a stable value on the MAINF bitfield.
• RCMEAS: RC Oscillator Frequency Measure (write-only)
0 = No effect.
1 = Restarts measuring of the main RC frequency. MAINF will carry the new frequency as soon as a low to high transition
occurs on the MAINFRDY flag.
The measure is performed on the main frequency (i.e. not limited to RC oscillator only), but if the main clock frequency
source is the fast crystal oscillator, the restart of measuring is not needed because of the well known stability of crystal
oscillators.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––RCMEAS–––MAINFRDY
15 14 13 12 11 10 9 8
MAINF
76543210
MAINF
SAM4N8/SAM4N16 [DATASHEET]
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418
25.16.9 PMC Clock Generator PLLA Register
Name: CKGR_PLLAR
Address: 0x400E0428
Access: Read-write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• DIVA: Divider
0 = Divider output is stuck at 0 and PLLA is disabled.
1 = Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated (PLLA also disabled if DIVA = 0).
1 up to 62 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
31 30 29 28 27 26 25 24
––ONE–– MULA
23 22 21 20 19 18 17 16
MULA
15 14 13 12 11 10 9 8
– – PLLACOUNT
76543210
DIVA
419
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.10 PMC Master Clock Register
Name: PMC_MCKR
Address: 0x400E0430
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLADIV2: PLLA Divisor by 2
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––PLLADIV2––––
76543210
–PRES–– CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_8 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
7 CLK_3 Selected clock divided by 3
PLLADIV2 PLLA Clock Division
0 PLLA clock frequency is divided by 1.
1 PLLA clock frequency is divided by 2.
SAM4N8/SAM4N16 [DATASHEET]
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420
25.16.11 PMC Programmable Clock Register
Name: PMC_PCKx
Address: 0x400E0440
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CSS: Master Clock Source Selection
• PRES: Programmable Clock Prescaler
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
–PRES–CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
4MCK Master Clock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_8 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
421
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.12 PMC Interrupt Enable Register
Name: PMC_IER
Address: 0x400E0460
Access: Write-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Oscillator Selection Status Interrupt Enable
• MOSCRCS: Main On-Chip RC Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
• XT32KERR: Slow Crystal Oscillator Error Interrupt Enable
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––XT32KERR – – CFDEV MOSCRCSMOSCSELS
15 14 1312 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY–LOCKAMOSCXTS
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
422
25.16.13 PMC Interrupt Disable Register
Name: PMC_IDR
Address: 0x400E0464
Access: Write-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• MCKRDY: Master Clock Re ady Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Oscillator Selection Status Interrupt Disa ble
• MOSCRCS: Main On-Chip RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
• XT32KERR: Slow Crystal Oscillator Error Interrupt Disable
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––XT32KERR – – CFDEV MOSCRCSMOSCSELS
15 14 1312 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY–LOCKAMOSCXTS
423
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.14 PMC Status Register
Name: PMC_SR
Address: 0x400E0468
Access: Read-only
• MOSCXTS: Main XTAL Oscillator Status
0 = Main XTAL oscillator is not stabilized.
1 = Main XTAL oscillator is stabilized.
• LOCKA: PLLA Lock Status
0 = PLLA is not locked
1 = PLLA is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• OSCSELS: Slow Clock Oscillator Selection
0 = Internal slow clock RC oscillator is selected.
1 = External slow clock 32 kHz oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
• MOSCSELS: Main Oscillator Selection Status
0 = Selection is in progress.
1 = Selection is done.
• MOSCRCS: Main On-Chip RC Oscillator Status
0 = Main on-chip RC oscillator is not stabilized.
1 = Main on-chip RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event
0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.
1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
– – XT32KERR FOS CFDS CFDEV MOSCRCS MOSCSELS
15 14 1312 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
OSCSELS – – – MCKRDY – LOCKA MOSCXTS
SAM4N8/SAM4N16 [DATASHEET]
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424
• CFDS: Clock Failure Detector Status
0 = A clock failure of the main on-chip RC oscillator clock is not detected.
1 = A clock failure of the main on-chip RC oscillator clock is detected.
• FOS: Clock Failure Detector Fault Output Status
0 = The fault output of the clock failure detector is inactive.
1 = The fault output of the clock failure detector is active.
• XT32KERR: Slow Crystal Oscillator Error
0 = The frequency of the slow crystal oscillator is correct (32768 Hz +/- 1%) or the monitoring is disabled.
1 = The frequency of the slow crystal oscillator is incorrect or has been incorrect for an elapsed period of time since the
monitoring has been enabled.
425
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.15 PMC Interrupt Mask Register
Name: PMC_IMR
Address: 0x400E046C
Access: Read-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Oscillator Selection Status Interrupt Mask
• MOSCRCS: Main On-Chip RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
• XT32KERR: Slow Crystal Oscillator Error Interrupt Mask
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––XT32KERR – – CFDEV MOSCRCSMOSCSELS
15 14 1312 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY–LOCKAMOSCXTS
SAM4N8/SAM4N16 [DATASHEET]
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426
25.16.16 PMC Fast Start-up Mode Register
Name: PMC_FSMR
Address: 0x400E0470
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• FSTT0 - FSTT15: Fast Start-up Input Enable 0 to 15
0 = The corresponding wake-up input has no effect on the Power Management Controller.
1 = The corresponding wake-up input enables a fast restart signal to the Po wer Management Controller.
• RTTAL: RTT Alarm Enable
0 = The RTT alarm has no effect on the Power Management Controller.
1 = The RTT alarm enables a fast restart signal to the Power Management Controller.
• RTCAL: RTC Alarm Enable
0 = The RTC alarm has no effect on the Power Management Controller.
1 = The RTC alarm enables a fast restart signal to the Power Management Controller.
• LPM: Low Power Mode
0 = The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep
Mode.
1 = The WaitForEvent (WFE) instruction of the processor makes the system to enter in Wait Mode.
• FLPM: Flash Low Power Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– FLPM LPM – – RTCAL RTTAL
15 14 13 12 11 10 9 8
FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8
76543210
FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0
Value Name Description
0 FLASH_STANDBY Flash is in St andby Mode when system enters Wait Mode
1 FLASH_DEEP_POWERDOWN Flash is in deep power down mode when system enters Wait Mode
2 FLASH_IDLE idle mode
427
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.17 PMC Fast Start-up Polarity Register
Name: PMC_FSPR
Address: 0x400E0474
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• FSTPx: Fast Start-up In pu t Polarity x
Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the
FSTP level, it enables a fast restart signal.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8
76543210
FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0
SAM4N8/SAM4N16 [DATASHEET]
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428
25.16.18 PMC Fault Output Clear Register
Name: PMC_FOCR
Address: 0x400E0478
Access: Write-only
• FOCLR: Fault Output Clear
Clears the clock failure detector fault output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––FOCLR
429
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.19 PMC Write Protect Mode Register
Name: PMC_WPMR
Address: 0x400E04E4
Access: Read-write
Reset: See Table 25-2
• WPEN: Write Protec t En ab le
0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
Protects the reg ist er s:
“PMC System Clock Enable Register”
“PMC System Clock Disable Register”
“PMC Peripheral Clock Enable Register 0”
“PMC Peripheral Clock Disable Register 0”
“PMC Clock Generator Main Oscillator Register”
“PMC Clock Generator PLLA Register”
“PMC Master Clock Register”
“PMC Programmable Clock Register”
“PMC Fast Start-up Mode Register”
“PMC Fast Start-up Polarity Register”
“PMC Oscillator Calibration Register”
• WPKEY: Write Protect KEY
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x504D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
SAM4N8/SAM4N16 [DATASHEET]
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430
25.16.20 PMC Write Protect Status Register
Name: PMC_WPSR
Address: 0x400E04E8
Access: Read-only
Reset: See Table 25-2
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unauthor-
ized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Reading PMC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
431
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
25.16.21 PMC Oscillator Calibration Regi ster
Name: PMC_OCR
Address: 0x400E0510
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CAL4: RC Oscillator Calibration bits for 4 MHz
Calibration bits applied to the RC Oscillator when SEL4 is set.
• SEL4: Selection of RC Oscillator Calibration bits for 4 MHz
0 = Default value stored in Flash memory.
1 = Value written by user in CAL4 field of this register.
• CAL8: RC Oscillator Calibration bits for 8 MHz
Calibration bits applied to the RC Oscillator when SEL8 is set.
• SEL8: Selection of RC Oscillator Calibration bits for 8 MHz
0 = Factory determined value stored in Flash memory.
1 = Value written by user in CAL8 field of this register.
• CAL12: RC Os cillator Calibration bits for 12 MHz
Calibration bits applied to the RC Oscillator when SEL12 is set.
• SEL12: Selection of RC Oscillator Calibration bits for 12 MHz
0 = Factory determined value stored in Flash memory.
1 = Value written by user in CAL12 field of this register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
SEL12 CAL12
15 14 13 12 11 10 9 8
SEL8 CAL8
76543210
SEL4 CAL4
SAM4N8/SAM4N16 [DATASHEET]
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432
26. Chip Identifier (CHIPID)
26.1 Description
Chip Identifier (CHIPID) registers permit recognition of the device and its revision. These registers provide the
sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Exte nsion ID).
Both registers contain a hard-wired value that is read-only. The first register contains the following fields:
EXT - shows the use of the extension identifier register
NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
ARCH - identifies the set of embedded peripherals
SRAMSIZ - indicates the size of the embedded SRAM
EPROC - indicates the embedded ARM processor
VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
26.2 Embedded Characteristics
Chip ID Registers
Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals,
Embedded Processor
Table 26-1. SAM4N Chip IDs Registers
Chip Name CHIPID_CIDR CHIPID_EXID
SAM4N16B (Rev A) 0x2946_0CE0 0x0
SAM4N16C (Rev A) 0x2956_0CE0 0x0
SAM4N8A (Rev A) 0x293B_0AE0 0x0
SAM4N8B (Rev A) 0x294B_0AE0 0x0
SAM4N8C (Rev A) 0x295B_0AE0 0x0
433
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
26.3 Chip Identifier (CHIPID) User Interface
Table 26-2 . Register Mapping
Offset Register Name Access Reset
0x0 Chip ID Register CHIPID_CIDR Read-only –
0x4 Chip ID Extension Register CHIPID_EXID Read-only –
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
434
26.3.1 Chip ID Register
Name: CHIPID_CIDR
Address: 0x400E0740
Access: Read-only
• VERSION: Version of the De vi ce
Current version of the device.
• EPROC: Embedded Processor
• NVPSIZ: Nonvolatile Program Memory Size
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
Value Name Description
1 ARM946ES ARM946ES
2 ARM7TDMI ARM7TDMI
3 CM3 Cortex-M3
4 ARM920T ARM920T
5 ARM926EJS ARM926EJS
6 CA5 Cortex-A5
7 CM4 Cortex-M4
Value Name Description
0 NONE None
18K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4– Reserved
5 64K 64 Kbytes
6– Reserved
7 128K 128 Kbytes
8– Reserved
9 256K 256 Kbytes
10 512K 512 Kbytes
11 – Reserved
435
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• NVPSIZ2: Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
12 1024K 1024 Kbytes
13 – Reserved
14 2048K 2048 Kbytes
15 – Reserved
Value Name Description
0 NONE None
18K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4– Reserved
5 64K 64 Kbytes
6– Reserved
7 128K 128 Kbytes
8– Reserved
9 256K 256 Kbytes
10 512K 512 Kbytes
11 – Reserved
12 1024K 1024 Kbytes
13 – Reserved
14 2048K 2048 Kbytes
15 – Reserved
Value Name Description
0 48K 48 Kbytes
1 192K 192 Kbytes
22K 2 Kbytes
36K 6 Kbytes
4 24K 24 Kbytes
54K 4 Kbytes
6 80K 80 Kbytes
7 160K 160 Kbytes
88K 8 Kbytes
9 16K 16 Kbytes
10 32K 32 Kbytes
11 64K 64 Kbytes
12 128K 128 Kbytes
Value Name Description
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
436
• ARCH: Architecture Identifier
13 256K 256 Kbytes
14 96K 96 Kbytes
15 512K 512 Kbytes
Value Name Description
0x19 AT91SAM9xx AT91SAM9xx Series
0x29 AT91SAM9XExx AT91SAM9XExx Series
0x34 AT91x34 AT91x34 Series
0x37 CAP7 CAP7 Series
0x39 CAP9 CAP9 Series
0x3B CAP11 CAP11 Series
0x40 AT91x40 AT91x40 Series
0x42 AT91x42 AT91x42 Series
0x45 AT91SAM4SH2 AT91SAM4SH2 Series
0x55 AT91x55 AT91x55 Series
0x60 AT91SAM7Axx AT91SAM7Axx Se ries
0x61 AT91SAM7AQxx AT91SAM7AQxx Series
0x63 AT91x63 AT91x63 Series
0x64 SAM4CxxC SAM4CxC Series (100-pin version)
0x66 SAM4CxxE SAM4CxE Series (144-pin version)
0x70 AT91SAM7Sxx AT91SAM7Sxx Se ries
0x71 AT91SAM7XCxx AT 91SAM7XCxx Series
0x72 AT91SAM7SExx AT91SAM7SExx Series
0x73 AT91SAM7Lxx AT91SAM7Lxx Series
0x75 AT91SAM7Xxx AT91SAM7Xxx Se ries
0x76 AT91SAM7SLxx AT91SAM7SLxx Series
0x80 SAM3UxC SAM3UxC Series (100-pin version)
0x81 SAM3UxE SAM3UxE Series (144-pin version)
0x83 SAM3AxC SAM3AxC Series (100-pin version)
0x84 SAM3XxC SAM3XxC Series (100-pin version)
0x85 SAM3XxE SAM3XxE Series (144-p in version)
0x86 SAM3XxG SAM3XxG Series (208/217-pin version)
0x92 AT91x92 AT91x92 Series
0x93 SAM4NxA SAM4NxA Series (48-pin version)
0x94 SAM4NxB SAM4NxB Series (64-pin version)
0x95 SAM4NxC SAM4NxC Series (100-pin version)
0x99 SAM3SDxB SAM3SDxB Series (64-pin version)
Value Name Description
437
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
0x9A SAM3SDxC SAM3SDxC Series (100-pin version)
0xA5 SAM5A SAM5A
0xB0 SAM4LxA SAM4LxA Series (48-pin version)
0xB1 SAM4LxB SAM4LxB Series (64-pin version)
0xB2 SAM4LxC SAM4LxC Series (100-pin version)
0xF0 AT75Cxx AT75Cxx Series
Value Name Description
0ROM ROM
1 ROMLESS ROMless or on-chip Flash
4 SRAM SRAM emulating ROM
2 FLASH Embedded Flash Memory
3 ROM_FLASH ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
Value Name Description
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
438
26.3.2 Chip ID Extension Register
Name: CHIPID_EXID
Address: 0x400E0744
Access: Read-only
• EXID: Chip ID Extension
Reads 0 if the EXT bit in CHIPID_CIDR is 0.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
439
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27. Parallel Input/Output (PIO) Controller
27.1 Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line
may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures
effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
Each I/O line of the PIO Controller features:
An input change interrupt enabling level change detection on any I/O line.
Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.
A glitch filter providing rejection of glitches lower than one-half of PIO clo ck cycle.
A debouncing filter providing rejection of unwanted pulses from key or push button operations.
Multi-drive capability similar to an open drain I/O line.
Control of the pull-up and pull-down of the I/O line.
Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write
operation.
27.2 Embedded Characteristics
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
Input Change Interrupt
Programmable Glitch Filter
Programmable Debouncing Filter
Multi-drive Option Enables Driving in Open Drain
Programmable Pull Up on Each I/O Line
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low Level or High
Level
Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
Write Protect Registers
Programmable Schmitt Trigger Inputs
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27.3 Block Diagram
Figure 27-1. Block Diagram
Figure 27-2. App lication Block Diagram
Embedded
Peripheral
Embedded
Peripheral
PIO Interrupt
PIO Controller
Up to 32 pins
PMC
Up to 32
peripheral IOs
Up to 32
peripheral IOs
PIO Clock
APB
Interrupt Controller
Data, Enable
PIN 31
PIN 1
PIN 0
Data, Enable
On-Chip Peripherals
PIO Controller
On-Chip Peripheral Drivers
Control & Command
Driver
Keyboard Driver
Keyboard Driver General Purpose I/Os External Devices
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27.4 Product Dependencies
27.4.1 Pin Multiplexing
Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line
multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent,
the hardware designer and programmer must carefully determine the configuration of the PIO controllers required
by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O,
programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO
Controller can control how the pin is driven by the product.
27.4.2 External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. Ho we ve r,
it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and
the interrupt lines (FIQ or IRQs) are used only as inputs.
27.4.3 Power Management
The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the
registers of the user interface does not require the PIO Controller clock to be enabled. This means that the
configuration of the I/O lines does not require the PIO Controller cl ock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch
filtering. Note that the Input Change Interru pt, Interrupt Mode s on a programma ble event and the r ead of the pin
level require the cloc k to be valid at ed .
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
27.4.4 Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller
interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the
product description to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller
requires the Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
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27.5 Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O
is represented in Figure 27-3. In this description each signal shown represents but one of up to 32 possible
indexes.
Figure 27-3. I/O Line Control Logic
1
0
1
0
1
0
1
0
DQ DQ
DFF
1
0
1
0
11
00
01
10
Programmable
Glitch
or
Debouncing
Filter
PIO_PDSR[0] PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
Resynchronization
Stage
Peripheral A Input
Peripheral D Output Enable
Peripheral A Output Enable
EVENT
DETECTOR
DFF
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
PIO Clock
Clock
Divider
PIO_IFSCSR[0]
PIO_IFSCER[0]
PIO_IFSCDR[0]
PIO_SCDR
Slow Clock
Peripheral B Output Enable
Peripheral C Output Enable
11
00
01
10
Peripheral D Output
Peripheral A Output
Peripheral B Output
Peripheral C Output
PIO_ABCDSR2[0]
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO_PPDDR[0]
PIO_PPDSR[0]
PIO_PPDER[0]
VDD
GND
Integrated
Pull-Down
Resistor
Integrated
Pull-Up
Resistor
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27.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up
resistor can be enabled or disabled by writing respecti vely PIO_PUER (Pull-up Enable Register) and PIO_PUDR
(Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in
PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0
means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing respectively
PIO_PPDER (Pull-down Enable Register) and PIO_PPDDR (Pull-down Disable Resistor). Writing in these
registers results in settin g or cle aring the corre sponding bit in PIO_PPDSR (Pull-down Status Register). Reading a
1 in PIO_PPDSR means the pull-up is disabled and rea ding a 0 means the pull-down is enabled.
Enabling the pull-down resistor while th e pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down
resistor is still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are
disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
27.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers
PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status
Register) is the result of the set and clear registers and indicates whether the pin is controlled by the
corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the
corresponding on-chip per iphe ral selecte d in th e PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A
value of 1 indicates the pin is controlled by the PIO controller.
If a pin is used as a g ene ra l purp ose I/O line (n ot mult ip lexed with an on -chip perip heral) , PIO_PER and PIO_ PDR
have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller , i.e. PIO_PSR resets at 1. However, in
some events, it is important that PIO lines are controlled by the peripher al (as in the case of memory chip select
lines that must be driven in active after reset or for address lines that must be driven low for booting out of an
external memory). Thus, the rese t value of PIO_PSR is de fined at the product level, dependin g on the multiple xing
of the device.
27.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is
performed by writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
For each pin:
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2
means peripheral A is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2
means peripheral B is selected.
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2
means peripheral C is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2
means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connec te d to th e pin input.
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Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplex ing regardless of the config uration of the
pin. However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers
(PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in P IO_ PDR .
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on
peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
27.5.4 Output Control
When the I/0 line is assign ed to a p eriphe ral fun ction, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the
I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 (ABCD Select Registers) determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing
PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write
operations are detected in PIO_OSR (Output Status Register). When a bit in this register i s at 0, the corr esponding
I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and
PIO_CODR (Clear Output Data Register). These write op erations respectively set and clear PIO_ODSR (Output
Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR
manages PIO_OSR whether the pin is co nfigure d to be cont rolled b y the PIO contro ller or assigned to a peripher al
function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level
driven on the I/O line.
27.5.5 Synchronous Data Output
Clearing one (or mor e) PIO line(s) an d se tting an other on e (or mo re ) PIO line( s) sync hro nously can not be don e by
using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different
registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to
PIO_ODSR (Output Data Status Register).Only bits unmasked by PIO_OWSR (Output Writ e Status Regist er) are
written. The mask bits in PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) a nd cleare d
by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
27.5.6 Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain b y using the Multi Drive feature. This feature permits
several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor
(or enabling of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver
Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or
assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured
to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
27.5.7 Output Line Timings
Figure 27-4 shows how the outputs ar e driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Fi gure 2 7-4 also shows when
the feedback in PIO_PDSR is available.
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Figure 27-4. Output Line Timings
27.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the
level of the I/O lines regardless o f their configur ation, whet her uniquely as an input or driven by the PIO cont roller
or driven by a periph er al.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the cloc k was disab le d.
27.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can
filter a pulse of less than 1/2 Period of a Programmable Divided Slow Clock.
The selection between glitch filtering or d ebounce filtering is done by writing in the registers PIO_IFSCDR (PIO
Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing
PIO_IFSCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter Slow Clock Status
Register).
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master
Clock.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the
Programmable Divided Slow Clock.
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the
PIO_SCDR (Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock
Cycle (Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER
programming) is automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow
Clock) cycle or more is accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock
cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for
a pulse to be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in Figure 27-5 a nd Figure 27-6.
2 cycles
APB Access
2 cycles
APB Access
MCK
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
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The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets
and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the
peripherals. It acts only on the value re ad in PIO_PDSR and on th e input change inte rrupt detection. The glitch and
debouncing filters require that the PIO Controller clock is enabled.
Figure 27-5. Input Glitch Filter Timing
Figure 27-6. Input Debouncing Filter Timing
27.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line.
The Input Edge/Level Interrupt is controll ed by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt
Disable Register), which respectively enable and disable the input change interrup t by setting and clearing the
corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing
two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change
Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by
the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interr upt modes can be enabled/disabled by writ ing in the PIO_AIMER (Additional Interrupt
Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this
selection can be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register)
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Divided Slow Clock
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle Tdiv_slclk
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
PIO_IFCSR = 1
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These Additional Modes are:
Rising Edge Detection
Falling Edge Detection
Low Level Detection
High Level Detection
In order to select an Additional Int errupt Mode:
The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR
(Edge Select Register) and PIO_LSR (Level Sele ct Register) which enable respectively, the Edge and Level
Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status
Register).
The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in
the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising
Edge/High Level Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the
PIO_ELSR) Edge or High or Low Level Detection (if Level is selected in the PIO_ELSR). The curr ent status
of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status
Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the
interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt
is generated as long as th e interrupt source is not clea red, even if some re ad accesses in PIO_ISR are performed.
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Figure 27-7. Event Dete ctor on Input Lines (Figure represents line 0)
27.5.10.1Example
If generating an interrupt is required on the following:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low Level on PIO line 3
High Level on PIO line 4
High Level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the othe r line s
The configuration required is described below.
27.5.10.2Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
27.5.10.3Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously configured.
Otherwise, lines 0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR.
27.5.10.4Falling/Rising Edge or Low/High Level Detection Configuration.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in
PIO_REHLSR.
The other lines are configured in Falling Edge or Low Level detection by default, if they have not been prev iously
configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing
32’h0000_004A in PIO_FELLSR.
Event Detector
0
1
0
1
1
0
0
1
Edge
Detector
Falling Edge
Detector
Rising Edge
Detector
PIO_FELLSR[0]
PIO_FRLHSR[0]
PIO_REHLSR[0]
Low Level
Detector
High Level
Detector
PIO_ESR[0]
PIO_ELSR[0]
PIO_LSR[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
PIO_AIMER[0]
Event detection on line 0
Resynchronized input on line 0
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Figure 27-8. In put Change Interrupt Timings if there are no Additional I nterrupt Modes
Figure 27-9.
27.5.11 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is active. Disabling the
Schmitt Trigger is requested when using the QTouch™ Library.
27.5.12 Write Protection Registers
To prevent any single software e rror that ma y corrupt PI O behavior, cer tain addre ss spaces can be write-pro tected
by setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (P IO_WPMR) with the appropriate access
key, WPKEY.
The protected registers are:
“PIO Enable Register” on page 454
“PIO Disable Register” on page 455
“PIO Output Enable Register” on page 457
“PIO Output Disable Register” on page 458
“PIO Input Filter Enable Register” on page 460
“PIO Input Filter Disable Register” on page 461
“PIO Multi-driver Enable Register” on page 471
“PIO Multi-driver Disable Register” on page 472
“PIO Pull Up Disable Register” on page 474
“PIO Pull Up Enable Register” on page 475
“PIO Peripheral ABCD Select Register 1” on page 477
“PIO Peripheral ABCD Select Register 2” on page 478
“PIO Output Write Enable Register” on page 486
“PIO Output Write Disable Register” on page 487
“PIO Pad Pull Down Disable Register” on page 483
“PIO Pad Pull Down Status Register” on page 485
MCK
Pin Level
Read PIO_ISRAPB Access
PIO_ISR
APB Access
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27.6 I/O Lines Programming Example
The programing example as shown in Table 27-1 below is used to obtain the following configuration.
4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up
resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor,
no pull-down resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch
filters and input change interrupts
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change
interrupt), no pull-up resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down
resistor
I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor
Table 27-1. Programming Example
Register Value to be Written
PIO_PER 0x0000_FFFF
PIO_PDR 0xFFFF_0000
PIO_OER 0x0000_00FF
PIO_ODR 0xFFFF_FF00
PIO_IFER 0x0000_0F00
PIO_IFDR 0xFFFF_F0FF
PIO_SODR 0x0000_0000
PIO_CODR 0x0FFF_FFFF
PIO_IER 0x0F00_0F00
PIO_IDR 0xF0FF_F0FF
PIO_MDER 0x0000_000F
PIO_MDDR 0xFFFF_FFF0
PIO_PUDR 0xFFF0_00F0
PIO_PUER 0x000F_FF0F
PIO_PPDDR 0xFF0F_FFFF
PIO_PPDER 0x00F0_0000
PIO_ABCDSR1 0xF0F0_0000
PIO_ABCDSR2 0xFF00_0000
PIO_OWER 0x0000_000F
PIO_OWDR 0x0FFF_ FFF0
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27.7 Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Eac h register is 32 bits wide. If a pa rallel I/O line is not define d, writing to the corr esponding bits has no
effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the
PIO Controller and PIO_PSR returns 1 systematically.
Table 27-2 . Register Mapping
Offset Register Name Access Reset
0x0000 PIO Enable Register PIO_PER Write-only –
0x0004 PIO Disable Register PIO_PDR Write-only –
0x0008 PIO Status Register PIO_PSR Read-only (1)
0x000C Reserved – – –
0x0010 Output Enable Register PIO_OER Write-only –
0x0014 Output Disable Register PIO_ODR Write-only –
0x0018 Output St atus Register PIO_OSR Read-only 0x0000 0000
0x001C Reserved – – –
0x0020 Glitch Input Filter Enable Registe r PIO_IFER Write-only –
0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only –
0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000
0x002C Reserved – – –
0x0030 Set Output Data Register PIO_SODR Write-only –
0x0034 Clear Output Data Register PIO_CODR Write-only
0x0038 Output Data Status Register PIO_ODSR Read-only
or(2)
Read-write –
0x003C Pin Data Status Register PIO_PDSR Read-only (3)
0x0040 Interrupt Enable Register PIO_IER Write-only –
0x0044 Interrupt Disable Register PIO_IDR Write-only –
0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000
0x004C Interrupt S tatus Register(4) PIO_ISR Read-only 0x00000000
0x0050 Multi-driver Enabl e Register PIO_MDER Write-only –
0x0054 Multi-driver Disable Register PIO_MDDR Write-only –
0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000
0x005C Reserved – – –
0x0060 Pull-up Disable Register PIO_PUDR Write-only –
0x0064 Pull-up Enable Register PIO_PUER Write-only –
0x0068 Pad Pull-up Status Registe r PIO_PUSR Read-only (1)
0x006C Reserved – – –
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
452
0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read-write 0x00000000
0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read-write 0x00000000
0x0078
to
0x007C Reserved – – –
0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only –
0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only –
0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000
0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read-write 0x00000000
0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only –
0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only –
0x0098 Pad Pull-down Status Register PIO_PPDSR Read-only (1)
0x009C Reserved – – –
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved – – –
0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only –
0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write-only –
0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x0000000 0
0x00BC Reserved – – –
0x00C0 Edge Select Register PIO_ESR Write-only –
0x00C4 Leve l Select Register PIO_LSR Write-only –
0x00C8 Edge/L evel Sta tus Register PIO_ELSR Read-only 0x00000000
0x00CC Reserved – – –
0x00D0 Falli ng Edge/Low Level Select Register PIO_FELLSR Write-only –
0x00D4 Rising Edge / High Level Select Register PIO_REHLSR Write-only –
0x00D8 Fall/Rise - Low/High Status Regi ster PIO_FRLHSR Read-only 0x00000000
0x00DC Reserved – – –
0x00E0 Reserved – – –
0x00E4 Write Protect Mode Register PIO_WPMR Read-write 0x0
0x00E8 Write Protect Status Register PIO_WPSR Read-only 0x0
0x00EC
to
0x00F8 Reserved – – –
0x0100 Schmitt Trigger Register PIO_SCHMITT Read-write 0x00000000
0x0104-
0x010C Reserved – – –
Table 27-2. Re gister Mapping (Continued)
Offset Register Name Access Reset
453
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Notes: 1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line level s requires th e clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
Note: If an offset is not listed in the table it must be considered as reserved.
0x0110 Reserved – – –
0x0114-
0x011C Reserved – – –
0x0120
to
0x014C Reserved – – –
Table 27-2. Re gister Mapping (Continued)
Offset Register Name Access Reset
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
454
27.7.1 PIO Enable Register
Name: PIO_PER
Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
455
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.2 PIO Disable Register
Name: PIO_PDR
Address: 0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x400E1204 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: PIO Disable
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
456
27.7.3 PIO Status Register
Name: PIO_PSR
Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC)
Access: Read-only
• P0-P31: PIO Status
0: PIO is inactive on the corresponding I/O line (peripheral is active).
1: PIO is active on the corresponding I/O line (peripheral is inactive).
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
457
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.4 PIO Output Enable Register
Name: PIO_OER
Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Enable
0: No effect.
1: Enables the output on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
458
27.7.5 PIO Output Disable Register
Name: PIO_ODR
Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Disable
0: No effect.
1: Disables the output on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
459
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.6 PIO Output Status Register
Name: PIO_OSR
Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC)
Access: Read-only
• P0-P31: Output Status
0: The I/O line is a pure input.
1: The I/O line is enabled in output.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
460
27.7.7 PIO Input Filter Enable Register
Name: PIO_IFER
Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
461
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.8 PIO Input Filter Disable Register
Name: PIO_IFDR
Address: 0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Input Filter Disable
0: No effect.
1: Disables the input glitch filter on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
462
27.7.9 PIO Input Filter Status Register
Name: PIO_IFSR
Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC)
Access: Read-only
• P0-P31: Input Filer Status
0: The input glitch filter is disabled on the I/O line.
1: The input glitch filter is enabled on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
463
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.10 PIO Set Output Data Register
Name: PIO_SODR
Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC)
Access: Write-only
• P0-P31: Set Output Data
0: No effect.
1: Sets the data to be driven on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
464
27.7.11 PIO Clear Output Data Register
Name: PIO_CODR
Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC)
Access: Write-only
• P0-P31: Clear Output Data
0: No effect.
1: Clears the data to be driven on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
465
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.12 PIO Output Data Status Register
Name: PIO_ODSR
Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC)
Access: Read-only or Read-write
• P0-P31: Output Data Status
0: The data to be driven on the I/O line is 0.
1: The data to be driven on the I/O line is 1.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
466
27.7.13 PIO Pin Data Status Register
Name: PIO_PDSR
Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC)
Access: Read-only
• P0-P31: Output Data Status
0: The I/O line is at level 0.
1: The I/O line is at level 1.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
467
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.14 PIO Interrupt Enable Register
Name: PIO_IER
Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC)
Access: Write-only
• P0-P31: Input Change Interrupt Enable
0: No effect.
1: Enables the Input Change Interrupt on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
468
27.7.15 PIO Interrupt Disable Register
Name: PIO_IDR
Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC)
Access: Write-only
• P0-P31: Input Change Interrupt Disable
0: No effect.
1: Disables the Input Change Interrupt on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
469
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.16 PIO Interrupt Mask Register
Name: PIO_IMR
Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC)
Access: Read-only
• P0-P31: Input Change Interrupt Mask
0: Input Change Interrupt is disabled on the I/O line.
1: Input Change Interrupt is enabled on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
470
27.7.17 PIO Interrupt Status Register
Name: PIO_ISR
Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC)
Access: Read-only
• P0-P31: Input Change Interrupt Status
0: No Input Change has been detected on the I/ O line since PIO_ISR was last read or since reset.
1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
471
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.18 PIO Multi-driver Enable Register
Name: PIO_MDER
Address: 0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Multi Drive Enable
0: No effect.
1: Enables Multi Drive on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
472
27.7.19 PIO Multi-driver Disable Register
Name: PIO_MDDR
Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Multi Drive Disable.
0: No effect.
1: Disables Multi Drive on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
473
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.20 PIO Multi-driver Status Register
Name: PIO_MDSR
Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC)
Access: Read-only
• P0-P31: Multi Drive Status.
0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
474
27.7.21 PIO Pull Up Disable Register
Name: PIO_PUDR
Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Up Disable.
0: No effect.
1: Disables the pull up resistor on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
475
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.22 PIO Pull Up Enable Register
Name: PIO_PUER
Address: 0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x400E1264 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Up Enable.
0: No effect.
1: Enables the pull up resistor on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
476
27.7.23 PIO Pull Up Status Regi ster
Name: PIO_PUSR
Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC)
Access: Read-only
• P0-P31: Pull Up Status.
0: Pull Up resistor is enabled on the I/O line.
1: Pull Up resistor is disabled on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
477
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.24 PIO Peripheral ABCD Select Register 1
Name: PIO_ABCDSR1
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Periphera l Select.
If the same bit is set to 0 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral B function.
If the same bit is set to 1 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral C function.
1: Assigns the I/O line to the Peripheral D function.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
478
27.7.25 PIO Peripheral ABCD Select Register 2
Name: PIO_ABCDSR2
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Periphera l Select.
If the same bit is set to 0 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to 1 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral B function.
1: Assigns the I/O line to the Peripheral D function.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
479
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.26 PIO Input Filter Slow Clock Disable Register
Name: PIO_IFSCDR
Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC)
Access: Write-only
• P0-P31: PIO Clock Glitch Filtering Select.
0: No Effect.
1: The Glitch Filter is able to filter glitches with a duration < Tmck/2.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
480
27.7.27 PIO Input Filter Slow Clock Enable Register
Name: PIO_IFSCER
Address: 0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x400E1284 (PIOC)
Access: Write-only
• P0-P31: Debouncing Filtering Select.
0: No Effect.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
481
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.28 PIO Input Filter Slow Clock Status Register
Name: PIO_IFSCSR
Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC)
Access: Read-only
• P0-P31: Glitch or Debouncing Filter Selection Status
0: The Glitch Filter is able to filter glitches with a duration < Tmck2.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
482
27.7.29 PIO Slow Clock Divider Debouncing Register
Name: PIO_SCDR
Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC)
Access: Read-write
• DIV: Slow Clock Divider Selection for Debouncing
Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–– DIV
76543210
DIV
483
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.30 PIO Pad Pull Down Disable Register
Name: PIO_PPDDR
Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x400E1290 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Disable
0: No effect.
1: Disables the pull down resistor on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
484
27.7.31 PIO Pad Pull Down Enable Register
Name: PIO_PPDER
Address: 0x400E0E94 (PIOA), 0x400E1094 (PIOB), 0x400E1294 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Enable
0: No effect.
1: Enables the pull down resistor on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
485
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.32 PIO Pad Pull Down Status Register
Name: PIO_PPDSR
Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x400E1298 (PIOC)
Access: Read-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Status
0: Pull Down resistor is enabled on the I/O line.
1: Pull Down resistor is disabled on the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
486
27.7.33 PIO Output Write Enable Register
Name: PIO_OWER
Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Write Enable
0: No effect.
1: Enables writing PIO_ODSR for the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
487
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.34 PIO Output Write Disable Register
Name: PIO_OWDR
Address: 0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x400E12A4 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Write Disable
0: No effect.
1: Disables writing PIO_ODSR for the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
488
27.7.35 PIO Output Write Status Register
Name: PIO_OWSR
Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC)
Access: Read-only
• P0-P31: Output Write Status
0: Writing PIO_ODSR does not affect the I/O line.
1: Writing PIO_ODSR affects the I/O line.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
489
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.36 PIO Additional Interrupt Modes Enable Register
Name: PIO_AIMER
Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC)
Access: Write-only
• P0-P31: Additional Interrupt Modes Enable
0: No effect.
1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
490
27.7.37 PIO Additional Interrupt Modes Disable Register
Name: PIO_AIMDR
Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC)
Access: Write-only
• P0-P31: Additional Interrupt Modes Disable
0: No effect.
1: The interrupt mode is set to the default interrupt mode (Both Edge detection).
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
491
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.38 PIO Additional Interrupt Modes Mask Register
Name: PIO_AIMMR
Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC)
Access: Read-only
• P0-P31: Peripheral CD Status
0: The interrupt source is a Both Edge detection event.
1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
492
27.7.39 PIO Edge Select Register
Name: PIO_ESR
Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC)
Access: Write-only
• P0-P31: Edge Interrupt Selection
0: No effect.
1: The interrupt source is an Edge detection event.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
493
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.40 PIO Level Select Register
Name: PIO_LSR
Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC)
Access: Write-only
• P0-P31: Level Interrupt Selection
0: No effect.
1: The interrupt source is a Level detection event.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
494
27.7.41 PIO Edge/Level Status Register
Name: PIO_ELSR
Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC)
Access: Read-only
• P0-P31: Edge/Level Interrupt Source Selection
0: The interrupt source is an Edge detection event.
1: The interrupt source is a Level detection event.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
495
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.42 PIO Falling Edge/Low Level Select Register
Name: PIO_FELLSR
Address: 0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x400E12D0 (PIOC)
Access: Write-only
• P0-P31: Fa ll in g Ed ge /L o w Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a Falling Edge detection or Low Level detection event, depending on PIO_ELSR.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
496
27.7.43 PIO Rising Edge/High Level Select Re gister
Name: PIO_REHLSR
Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC)
Access: Write-only
• P0-P31: Rising Edge /High Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR.
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
497
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.44 PIO Fall/Rise - Low/High Status Register
Name: PIO_FRLHSR
Address: 0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x400E12D8 (PIOC)
Access: Read-only
• P0-P31: Edge /Level Interrupt Source Selection
0: The interrupt source is a Falling Edge detection (if PIO_ELSR = 0) or Low Level detection event (if PIO_ELSR = 1).
1: The interrupt source is a Rising Edge detection (if PIO_ELSR = 0) or High Level detection event (if PIO_ELSR = 1).
3130292827 26 25 24
P31P30P29P28P27 P26 P25 P24
2322 21 20 19 1817 16
P23P22 P21 P20 P19 P18P17 P16
15 14 1312 11 10 9 8
P15 P14 P13P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3P2 P1 P0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
498
27.7.45 PIO Write Protect Mode Register
Name: PIO_WPMR
Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC)
Access: Read-write
Reset: See Table 27-2
For more information on Write Protection Registers, refer to Section 27.7 “Parallel Input/Output Controller (PIO) User
Interface”.
• WPEN: Write Protec t En ab le
0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1: Enables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII) .
Protects the reg ist er s:
“PIO Enable Register” on page 454
“PIO Disable Register” on page 455
“PIO Output Enable Register” on page 457
“PIO Output Disable Register” on page 458
“PIO Input Filter Enable Register” on page 460
“PIO Input Filter Disable Register” on page 461
“PIO Multi-driver Enable Register” on page 471
“PIO Multi-driver Disable Register” on page 472
“PIO Pull Up Disable Register” on page 474
“PIO Pull Up Enable Register” on page 475
“PIO Peripheral ABCD Select Register 1” on page 477
“PIO Peripheral ABCD Select Register 2” on page 478
“PIO Output Write Enable Register” on page 486
“PIO Output Write Disable Register” on page 487
“PIO Pad Pull Down Disable Register” on page 483
“PIO Pad Pull Down Status Register” on page 485
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––
WPEN
499
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• WPKEY: Write Protect KEY.
Value Name Description
0x50494F PASSWD Writing any other val ue in this field aborts the write operation of the WPEN bit. Always reads
as 0.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
500
27.7.46 PIO Write Protect Status Register
Name: PIO_WPSR
Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC)
Access: Read-only
Reset: See Table 27-2
• WPVS: Write Protect Violation Status
0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
1: A Write Protect Violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Note: Reading PIO_WPSR automa tically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––
WPVS
501
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
27.7.47 PIO Schmitt Trigger Register
Name: PIO_SCHMITT
Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x400E1300 (PIOC)
Access: Read-write
Reset: See Table 27-2
• SCHMITTx [x=0..31]: Schmitt Trigger Control
0: Schmitt Trigger is enabled.
1: Schmitt Trigger is disabled.
31 30 29 28 27 26 25 24
SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24
23 22 21 20 19 18 17 16
SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16
15 14 13 12 11 10 9 8
SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8
76543210
SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
502
28. Serial Peripheral Interface (SPI)
28.1 Description
The Serial Per ipheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Master or Slave Mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple
Master Protocol oppo site to Single Maste r Protocol wh er e one CPU is alwa ys the master while all of the other s are
always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may
drive its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist , the master
generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line su pp lies the output data from the master shifted into the input(s)
of the slave(s).
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The
master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is
transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
28.2 Embedded Characteristics
Supports Communication with Serial External Devices
Master Mode can drive SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)
Slave Mode operates on SPCK, asynchronously to Core and Bus Clock
Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals
Serial Memories, such as DataFlash and 3-wire EEPROMs
Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External Copr oce ss ors
Master or Slave Serial Peripheral Bus Interface
8-bit to 16-bit Programmable Data Length Per Chip Select
Programmable Phase and Polarity Per Chip Select
Programmable Transfer Delay Between Consecutive Transfers and Delay before SPI Clock per Chip
Select
Programmable Delay Between Chip Selects
Selectable Mode Fault Detection
Connection to PDC Channel Capabilities Optimizes Data Transfers
One Channel for the Receiver, One Channel for the Transmitter
503
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
28.3 Block Diagram
Figure 28-1. Block Diagram
28.4 Application Block Diagram
Figure 28-2. Application Block Diagram: Single Master/Multip le Slave Implementation
SPI Interface
Interrupt Control
PIO
PDC
PMC MCK
SPI Interrupt
SPCK
MISO
MOSI
NPCS0/NSS
NPCS1
NPCS2
NPCS3
APB
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
504
28.5 Signal Description
28.6 Product Dependencies
28.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the SPI pins to th eir peripheral functions.
28.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
Table 28-1. Sign al Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Sele ct/Slave Select Output Input
Table 28-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI MISO PA12 A
SPI MOSI PA13 A
SPI NPCS0 PA11 A
SPI NPCS1 PA9 B
SPI NPCS1 PA31 A
SPI NPCS1 PB14 A
SPI NPCS1 PC4 B
SPI NPCS2 PA10 B
SPI NPCS2 PA30 B
SPI NPCS2 PB2 B
SPI NPCS2 PC7 B
SPI NPCS3 PA3 B
SPI NPCS3 PA5 B
SPI NPCS3 PA22 B
SPI SPCK PA14 A
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28.6.3 Interrupt
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
28.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full
description of the PDC, refer to the corresponding section in the full datasheet.
Table 28-3. Peripheral IDs
Instance ID
SPI 21
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28.7 Functional Description
28.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to
NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the
MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output,
the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver.
The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not
driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is
activated only in Master Mode.
28.7.2 Data Transfer
Four combinations of polarity and phase are availab le for data transfers. The clock po larity is prog rammed with the
CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters
determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two
possible states, resulting in four possible combinations that are incompatible with one another. Thus, a
master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed
in different configurations, the master must reconfigure itself each time it needs to communicate with a different
slave.
Table 28-4 shows the four modes and corres po nd in g paramete r se ttin gs .
Table 28-4. SPI Bus Protocol Mode
SPI Mode CPOL NCPHA Shift SPCK Edge Capture SPCK Edge SPCK Inactive Level
0 0 1 Falling Rising Low
1 0 0 Rising Falling Low
2 1 1 Rising Falling High
3 1 0 Falling Rising High
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Figure 28-3 and Figure 28-4 show examples of data transfers.
Figure 28-3. SPI Trans f er Fo rmat (NCPHA = 1, 8 bits per transfer)
Figure 28-4. SPI Trans f er Fo rmat (NCPHA = 0, 8 bits per transfer)
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined, but normally MSB of previous character received.
12345 786
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
12345 7
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined but normally LSB of previous character transmitted.
2
2
6
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28.7.3 Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud
rate generator. It fu lly controls the data transfe rs to and from the slave (s) connected to the SPI bus. The SPI drives
the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single
Shift Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_T DR (Transmit Da ta Register).
The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data
in the Shift Register is shifted on the M OSI line, the MISO line is sampled and shifted in the Shift Register.
Receiving data cannot occur without transmitting data. If receiving mode is not needed, for example when
communicating with a slave receiver only (such as an LCD), the receive status flags in the status register can be
discarded.
Before writing the TDR, the PCS field in the SPI_MR register must be set in or der to select a slave.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_T DR (Transmit Da ta Register).
The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data
in the Shift Register is shifted on the M OSI line, the MISO line is sampled and shifted in the Shift Register.
Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfe r is comp lete d. Then , t he
received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift
Register and a ne w transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data
Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is c leared. The
TDRE bit is used to trigger the TransmitPDC channel.
The end of tran sfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is
greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The mast er clock (MCK)
can be switched off at this time.
The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data
Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit
(OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status
register to clear the OVRES bit.
Figure 28-5, shows a block diagram of the SPI when operating in Master Mode. Figure 28-6 on page 510 shows a
flow chart describing how transfers are handled.
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28.7.3.1Master Mode Block Diagram
Figure 28-5. Master Mod e Block Diagram
Shift Register
SPCK
MOSI
LSBMSB
MISO
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0..3
CPOL
NCPHA
BITS
MCK Baud Rate Generator
SPI_CSR0..3
SCBR
NPCS3
NPCS0
NPCS2
NPCS1
NPCS0
0
1
PS
SPI_MR PCS
SPI_TDR PCS
MODF
Current
Peripheral
SPI_RDR PCS
SPI_CSR0..3
CSAAT
PCSDEC
MODFDIS
MSTR
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28.7.3.2Master Mode Flow Diagram
Figure 28-6. Master Mode Flo w Dia gr am
SPI Enable
CSAAT ?
PS ?
1
0
0
1
1
NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
TDRE ?
NPCS = 0xF
Delay DLYBCS
Fixed
peripheral
Variable
peripheral
Delay DLYBCT
0
1CSAAT ?
0
TDRE ? 1
0
PS ? 0
1
SPI_TDR(PCS)
= NPCS ?
no
yes SPI_MR(PCS)
= NPCS ?
no
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_MR(PCS),
SPI_TDR(PCS)
Fixed
peripheral
Variable
peripheral
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
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Figure 28-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission
Register Empty (TXEMPTY) status flag s behavior within the SPI_SR (Status Registe r) during an 8-bit data tr ansfer
in fixed mode and no Peripheral Data Controller involved.
Figure 28-7. Status Register Flags Behavior
Figure 28-8 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer
(ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR
(Status Register) during an 8- bit data tran sfer in fixed mode with the Peripheral Data Controller involved. The PDC
is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and
TDRE are not shown because these flags are managed by the PDC when using the PDC.
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
12345 786
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty
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Figure 28-8. PDC Status Register Flags Beh avior
28.7.3.3Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clo ck and a minimum operating baud rate of MCK
divided by 255.
Programming the SCBR field at 0 is forb idden. Triggering a transfer while SCBR is at 0 can lead to unpredictable
results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independen tly for each chip select, as it has to be programmed in the SCBR field of th e
Chip Select Registers. This allows the SPI to automatically ada pt the baud rate for each interfaced peripheral
without reprogramming.
28.7.3.4Transfer Delays
Figure 28-9 shows a chip select tran sfer change and consecutive transfers on the same chip select. Three delays
can be programmed to modify the transfer waveforms:
The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field
in the Mode Register. Allows insertion of a delay between release of one chip se lect and befo re asse rtion of
a new one.
The delay before SPCK, independently programmable for each chip select by writing the field DLYBS.
Allows the start of SPCK to be delayed after the chip select has been ass er te d.
The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
654321
SPCK
MOSI
(from master)
NPCS0
MSB
LSB
654321
12 3
ENDTX
TXEMPTY
MSB
LSB
654321
654321
MISO
(from slave)
654321
654321
ENDRX
TXBUFE
RXBUFF
TDRE
(not required
if PDC is used) PDC loads first byte
PDC loads 2nd byte
(double buffer effect) PDC loads last byte
MSB
MSBMSB MSB
LSBLSB
LSB
LSB
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Figure 28-9. Prog rammable Delays
28.7.3.5Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the
NPCS signals are high before and after each transfer.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the
current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to
reprogram the NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the
current per ipheral. This m eans that the perip heral selectio n can be d efined for each new data . The value to write in
the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip
select to assert as defined in Section 28.8.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending
on CSAAT bit.
Note: 1. Optional.
CSAAT, LASTXFER and CSNAAT bits are discussed in Section 28.7.3.9 “Peripheral Deselection with PDC”.
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the
user can use the SPIDIS co mmand. After the end of the PDC transfer , wait for the TXEMPTY flag, then write
SPIDIS into the SPI_CR register (this will not change the configuration register values); the NPCS will be
deactivated after the last character transfer. Then, another PDC transfer can be started if the SPIEN was
previously written in the SPI_CR register.
28.7.3.6SPI Peripheral DMA Controller (PDC)
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However,
changing the peripheral selection requires the Mo de Register to be reprogrammed.
The Variable Peripheral Select ion allows buffer transfers with multiple peripherals witho ut reprogramming the
Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and
the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be
transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal
means in term of memory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
DLYBCSDLYBSDLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK
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Transfer Size
Depending on the d ata size to transm it, from 8 to 16 bits, the PDC manages automatically the type of pointe r's size
it has to point to. The PDC will perform the following transfer size depending on the mode and number of bits per
data.
Fixed Mode:
8-bit Data:
Byte transfer, PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1
8-bit to 16-bit Data:
2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1
Variable Mode:
In variable Mode , PDC Po inter Add re ss = Addr ess +4 bytes a nd PDC Co un ter = Co unter - 1 for 8 to 16-b it tr an sfer
size. When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does
not have to check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF),
TX Buffer Empty (TXBUFE) a re significant. For further details about the Periph eral DMA Controller and user
interface, re fe r to the PDC section of the produ ct da ta sh ee t.
28.7.3.7Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0
to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writin g the PCSDEC bit at 1 in the
Mode Register (SPI_MR).
When oper ating without de coding, the SPI makes sure th at in any case only one chip select line is activated, i.e.,
one NPCS line driven low at a time. If two bits ar e defined lo w in a PCS field, only the lowest numbered chip select
is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either
the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing
any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally de coded peripherals 0 to 3, correspon ding to the PCS values 0x 0 to 0x3. Thus, the user has to make
sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure
28-10 below shows such an implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This
is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
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Figure 28-10. Chip Select Decoding Application Block Diag ram: Single Master/Multiple Slave Implementation
28.7.3.8Peripheral Deselection without PDC
During a transfer of more than one data on a Chip Select without the PDC, the SPI_TDR is loaded by the
processor, the flag TDRE rises as so on as the conten t of the SPI_TDR is transferred into the internal shift register.
When this flag is detected h igh, the SPI_TDR can be reloaded. If this reload by the processor oc curs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current tr ansfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive
Transfer (DLYBCT) value in the SPI_CSR register, will give even less time for the processor to reload the
SPI_TDR. With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of
transfers might lead to communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the
CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state
(low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select
will remain active. To have the chip select line to ra ise at t he end of the tran sfer the L ast tran sfer Bit (LAST XFER)
in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR.
28.7.3.9Peripheral Deselection with PDC
When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the
TDRE flag is managed b y the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE fla g
is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other PDC
channels connected to other periph erals are in use as well, the SPI PDC mig ht be delayed by another (PDC with a
higher priority on th e b us). Havin g PDC bu ffers in slo wer memories like flash memory or SDRAM compared to fast
internal SRAM, may lengthen the reload time of the SPI_TDR by the PDC as well. Thi s means that th e SPI_TDR
might not be reload ed in time to keep the chip select line low. In this case the chip select line may toggle between
data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT
bit might be needed. When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on
the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the content of the
SPI_TDR is transferred into the internal shifter. When this flag is detected the SPI_TDR can be reloaded. If this
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
1-of-n Decoder/Demultiplexer
MISOMOSI
NSS
Slave 0
SPCK MISOMOSI
NSS
Slave 1
SPCK MISOMOSI
NSS
Slave 14
NPCS3
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reload occurs be fore the en d of the current tr ansfer and if th e next transfer is performed on the same chip select as
the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for
interfacing with some serial peripherals requiring the chip select to be de-asserted after each tran sfer. To facilitate
interfacing with such devices, the Chip Select Register can be programmed with the C SNAAT bit (Chip Select Not
Active After Transfer) at 1. This allows to de-assert systematically the chip select lines during a time DLYBCS.
(The value of the CSNAAT bit is taken into account only if the CSAAT bit is set at 0 for the same Chip Select).
Figure 28-11 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
Figure 28-11. Peripheral Deselection
A
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
ADLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
DLYBCT
AA
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 1
NPCS[0..3]
Write SPI_TDR
TDRE
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
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28.7.3.10Mode Fault Detection
A mode fault is detecte d when the SPI is programmed in Ma ster Mode and a low level is driven by an external
master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins
must be configured in open drain (through the PIO controller). When a mode fault is detected, th e MODF bit in th e
SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN
bit in the SPI_CR (Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the
MODFDIS bit in the SPI Mode Register (SPI_MR).
28.7.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the
clock is validated on the se rialize r, which pro c esse s the n umb er of bits de fi ned by the BITS field of the Chip Select
Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the
NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers
have no effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BIT S field, see also, the (Note:) below the register table; Section 28.8.9 “SPI Chip Select
Register” on page 530.)
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit
rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error
bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the
status register to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Sh ift Register . If no data ha s been writte n in
the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the
last reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediate ly in th e Shift Register and th e TDRE bit rises. If
new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the
SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the
TDRE bit rises. This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to
be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift
Register, the SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR.
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Figure 28-12 shows a block diagram of the SPI when oper ating in Slave Mode.
Figure 28-12. Slave Mode Functional Block Diagram
28.7.5 Write Protected Registers
To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-
protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SPI Write Protection Status
Register (SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset after reading the SPI Write Protection Status Register (SPI_WPSR).
List of the write-protected registers:
Section 28.8.2 “SPI Mode Register”
Section 28.8.9 “SPI Chip Select Register”
Shift Register
SPCK
SPIENS
LSBMSB
NSS
MOSI
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
519
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28.8 Serial Peripheral Interface (SPI) User Interface
Table 28-5 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register SPI_CR Write-only ---
0x04 Mode Register SPI_MR Read-write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only ---
0x10 Status Register SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only ---
0x18 Interrupt Disable Register SPI_IDR Write-only ---
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20 - 0x2C Reserved
0x30 Chip Select Register 0 SPI_CSR0 Read-write 0x0
0x34 Chip Select Register 1 SPI_CSR1 Read-write 0x0
0x38 Chip Select Register 2 SPI_CSR2 Read-write 0x0
0x3C Chip Select Register 3 SPI_CSR3 R ead-write 0x0
0x40 - 0xE0 Reserved – – –
0xE4 Write Protection Control Register SPI_WPMR Read-write 0x0
0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0
0x00EC - 0x00F8 Reserved – – –
0x00FC Reserved – – –
0x100 - 0x124 Reserved for PDC Registers – – –
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28.8.1 SPI Control Register
Name: SPI_CR
Address: 0x40008000
Access: Write-only
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
As soon as SPIDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
• SWRST: SPI Software Reset
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interfac e is perfo rm e d.
The SPI is in slave mode after software reset.
PDC channels are not affected by software reset.
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with th e current serial pe ripheral by raising the corresponding NPCS lin e as soon as TD
transfer has completed.
Refer to Section 28.7.3.5 “Peripheral Selection”for more details.
3130292827 26 25 24
–––––––LASTXFER
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
––––––––
76543210
SWRST–––––SPIDISSPIEN
521
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28.8.2 SPI Mode Register
Name: SPI_MR
Address: 0x40008004
Access: Read-write
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”.
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are dir ec tly con n ec ted to a pe rip h eral de vice .
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals on e, up to 15 Chip Select signals can b e generated with the fo ur lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data.
This mode prevents overrun error in reception.
3130292827 26 25 24
DLYBCS
2322 21 20 19 1817 16
–––– PCS
15 14 1312 11 10 9 8
––––––––
76543210
LLB – WDRBT MODFDIS–PCSDEC PSMSTR
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• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on
MOSI.)
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects DLYBCS
MCK
-----------------------
=
523
SAM4N8/SAM4N16 [DATASHEET]
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28.8.3 SPI Receive Data Register
Name: SPI_RDR
Address: 0x40008008
Access: Read-only
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
zero.
Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to also set the WDRBT field to 1 if the SPI_RDR
PCS field is to be processed.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
–––– PCS
15 14 1312 11 10 9 8
RD
76543210
RD
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28.8.4 SPI Transmit Data Register
Name: SPI_TDR
Address: 0x4000800C
Access: Write-only
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the
transmit data register in a right-justified format.
• PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with th e current serial pe ripheral by raising the corresponding NPCS lin e as soon as TD
transfer has completed.
This field is only used if Variable Peripheral Select is active (PS = 1).
3130292827 26 25 24
–––––––LASTXFER
2322 21 20 19 1817 16
–––– PCS
15 14 1312 11 10 9 8
TD
76543210
TD
525
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28.8.5 SPI Status Register
Name: SPI_SR
Address: 0x40008010
Access: Read-only
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has be en transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the ser ializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reache d 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full
0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
–––––––SPIENS
15 14 1312 11 10 9 8
–––––UNDESTXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRESMODF TDRE RDRF
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• TXBUFE: TX Buffer Empty
0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.
• NSSR: NSS Rising
0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty
0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of
such delay.
• UNDES: Underrun Error Status (Slave Mode Only)
0 = No underrun has been detected since the last read of SPI_SR.
1 = A transfer begins whereas no data has been loaded in the Transmit Data Register.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
527
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28.8.6 SPI Interrupt Enable Register
Name: SPI_IER
Address: 0x40008014
Access: Write-only
0 = No effect.
1 = Enables the corr es po nd in g inte r ru pt .
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
• UNDES: Underrun Error Interrupt Enable
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––UNDESTXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRESMODF TDRE RDRF
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28.8.7 SPI Interrupt Disable Register
Name: SPI_IDR
Address: 0x40008018
Access: Write-only
0 = No effect.
1 = Disables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
• UNDES: Underrun Error Interrupt Disable
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––UNDESTXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRESMODF TDRE RDRF
529
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28.8.8 SPI Interrupt Mask Register
Name: SPI_IMR
Address: 0x4000801C
Access: Read-only
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
• UNDES: Underrun Error Interrupt Mask
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
–––––UNDESTXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRESMODF TDRE RDRF
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28.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Address: 0x40008030
Access: Read/Write
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”.
Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the
translated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required cloc k/d a ta re lat ion sh ip between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first
transfer and if the two transfers occur on the same Chip Select.
1 = The Peripheral Chip Select rises systematically after each transfer pe rformed on the same slave. It remains active after
the end of transfer for a minimal duration of:
– (if DLYBCT field is different from 0)
– (if DLYBCT field equals 0)
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
3130292827 26 25 24
DLYBCT
2322 21 20 19 1817 16
DLYBS
15 14 1312 11 10 9 8
SCBR
76543210
BITSCSAAT CSNAAT NCPHA CPOL
DLYBCT
MCK
-----------------------
DLYBCT 1+
MCK
---------------------------------
531
SAM4N8/SAM4N16 [DATASHEET]
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• BITS: Bits Per Transfer
(See the (Note:) below the register table; Section 28.8.9 “SPI Chip Select Regi ster” on page 530.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Maste r Clock MCK. The
Baud rate is selected by writing a value fro m 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are required
to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
Value Name Description
0 8_BIT 8 bits for transfer
1 9_BIT 9 bits for transfer
2 10_BIT 10 bits for transfer
3 11_BIT 11 bits for transfer
4 12_BIT 12 bits for transfer
5 13_BIT 13 bits for transfer
6 14_BIT 14 bits for transfer
7 15_BIT 15 bits for transfer
8 16_BIT 16 bits for transfer
9– Reserved
10 – Reserved
11 – Reserved
12 – Reserved
13 – Reserved
14 – Reserved
15 – Reserved
SPCK Baudrate MCK
SCBR
---------------
=
Delay Before SPCK DLYBS
MCK
-------------------
=
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When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers 32 DLYBCT×MCK
------------------------------------
=
533
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28.8.10 SPI Write Protection Mode Register
Name: SPI_WPMR
Address: 0x400080E4
Access: Read-write
• WPEN: Write Protec t En ab le
0: Disables the Write Protect if WPKEY corresponds to 0x535049 (“SPI” in ASCII).
1: Enables the Write Protect if WPKEY corresponds to 0x535049 (“SPI” in ASCII).
Protects the reg ist er s:
•Section 28.8.2 “SPI Mode Register”
•Section 28.8.9 “SPI Chip Select Register”
• WPKEY: Write Protect Key
3130292827 26 25 24
WPKEY
2322 21 20 19 1817 16
WPKEY
15 14 1312 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x535049 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
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28.8.11 SPI Write Protection Status Registe r
Name: SPI_WPSR
Address: 0x400080E8
Access: Read-only
• WPVS: Write Protection Violation Status
0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the SPI_WPSR re gister. If this viola tion is an unau thorize d
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
3130292827 26 25 24
––––––––
2322 21 20 19 1817 16
––––––––
15 14 1312 11 10 9 8
WPVSRC
76543210
–––––––WPVS
535
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29. Two-wire Interface (TWI)
29.1 Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock
line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can
be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time
Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is
programmable as a master or a slave with sequential or single-byte access. Multiple master capability is
supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is
lost.
A configurable baud rate g enerator permits the output data rate to be adapted to a wide range of core clock
frequencies.
Below, T able 29-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C
compatible device.
Note: 1. START + b000000001 + Ack + Sr
29.2 Embedded Characteristics
3 x TWI
Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1)
One, Two or Three Bytes for Slave Address
Sequential Read-write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbits
General Call Supported in Slave mode
SMBUS Quick Command Supported in Master Mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers
One Channel for the Receiver, One Channel for the Transmitter
Note: 1. See Table 29-1 for details on compatibility with I²C Standard.
Table 29-1. Atmel TWI compatibility with I2C Standard
I2C Standard Atmel TWI
Standard Mode S peed (100 KHz) Supported
Fast Mode Speed (400 KHz) Supported
7 or 10 bits Slave Addressing Supporte d
START BYTE(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope control and input filter ing (Fast mode) Not Supported
Clock stretching Supported
Multi Master Capability Supported
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29.3 List of Abbreviations
29.4 Block Diagram
Figure 29-1. Block Diagram
Table 29-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
RRead
WWrite
APB Bridge
PMC MCK
Two-wire
Interface
PIO
Interrupt
Controller
TWI
Interrupt
TWCK
TWD
537
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29.5 Application Block Diagram
Figure 29-2. App lication Block Diagram
29.5.1 I/O Lines Description
29.6 Product Dependencies
29.6.1 I/O Lines
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a cur ren t source o r pu ll-up
resistor (see Figure 29-2 on page 537). When the bus is free, both lines are high. The output stages of devices
connected to the bus must have an open-drain or open-collector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the
following step:
Program the PIO controller to dedicate TWD and TWCK as peripheral lines.
The user must not program TWD and TWCK as open-drain. It is already done by the hardware.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
Table 29-3. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
Table 29-4. I/O Lines
Instance Signal I/O Line Peripheral
TWI0 TWCK0 PA4 A
TWI0 TWD0 PA3 A
TWI1 TWCK1 PB5 A
TWI1 TWD1 PB4 A
TWI2 TWCK2 PB1 B
TWI2 TWD2 PB0 B
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29.6.2 Power Management
Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must
first configure the PMC to enable the TWI clock.
29.6.3 Interrupt
The TWI interface has an interru pt line connected to the Interrupt Controller. In order to handle interrupts, the
Interrupt Controller must be programmed before configuring the TWI.
Table 29-5. Peripheral IDs
Instance ID
TWI0 19
TWI1 20
TWI2 22
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29.7 Functional Description
29.7.1 Transfer Format
The data put on th e T W D line mu st b e 8 bits long. Data is transf erred MSB firs t; each by te must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see Figure 29-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure 29-3).
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 29-3. START and STOP Cond itions
Figure 29-4. Transfer Format
29.7.2 Modes of Operation
The TWI has different modes of operations:
Master transmitter mode
Master receiver mode
Multi-master transmitter mode
Multi-master receiver mode
Slave transmitter mode
Slave receiver mode
These modes are described in the following chapters.
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
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29.8 Master Mode
29.8.1 Definition
The Master is the device that starts a transfer, generates a clock and stops it.
29.8.2 Application Block Diagram
Figure 29-5. Ma ster Mode Typical Application Block Diagram
29.8.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in
read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
29.8.4 Master Transmitter Mode
After the master initiates a Start con dition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-
bit slave address, configured in the Master Mode register (DADR in TW I_MMR), to notify the slave device. The bit
following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in
the status register if the slave does not acknowledge th e byte. As with the other status bits, an interrupt can be
generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data
written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected,
the TXRDY bit is set until a new write in the TWI_THR.
TXRDY is used as Transmit Ready for the PDC transmit channel.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the
TWI_THR, the SCL is rele ased an d the data is sent. To genera te a STOP event, the STOP command must be
performed by writing in the STOP field of TWI_CR.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
541
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After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the
TWI_THR or until a STOP command is performed.
See Figure 29-6, Figure 29-7, and Figure 29-8.
Figure 29-6. Master Write with One Data Byte
Figure 29-7. Master Wr ite with Multiple Data Bytes
TXCOMP
TXRDY
Write THR (DATA)
STOP Command sent (write in TWI_CR)
TWD ADATAAS DADR W P
A DATA n ASDADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD
TWCK
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Figure 29-8. Master Write with One Byte Internal Address and Multiple Data Bytes
29.8.5 Master Receiver Mode
The read sequence begins by setting the START b it. After th e start condition has been sent, the master sends a 7-
bit slave address to notify the sla ve device. The bit following the slave address indicates the transfer direction, 1 in
this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), th e master releases the
data line (HIGH), enabling the slave to pull it do wn in order to generate the acknowledge. The master polls the
data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the
byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
received, the master sends an acknowledge condition to notify the slave that the data has been received except
for the last data, after the stop condition. See Figur e 29-9. When the RXRDY bit is set in the stat us register, a
character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the
TWI_RHR.
When a single data byte read is performed, with or without internal ad dress (IADR), the START and STOP bits
must be set at the same time. See Figure 29-9. When a multiple data byte read is performed, with or without
internal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 29-10. For
Internal Address usage see Section 29.8.6.
Figure 29-9. Master Read with One Data Byte
A DATA n ASDADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD IADR A
TWCK
ASDADR R DATA NA P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD
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Figure 29-10. Master Rea d with Multiple Data Bytes
RXRDY is used as Receive Ready for the PDC receive channel.
29.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit
slave address devices.
29.8.6.17-bit Slave Addressing
When Addressing 7 -bit slave devices, th e internal addres s bytes are used t o perform random address (read or
write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
When performing read operations with an internal address, the TWI performs a write operation to set the internal
address into th e slave device, and then switch to Master Receiver mode. Note that the se cond start condition (a fter
sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully- compatible devices. See Figure 2 9-1 2. See
Figure 29-11 and Figure 29-13 for Master Write operation with inte rn al ad dre ss.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
NA
ASDADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n Read RHR
DATA (n+1) Read RHR
DATA (n+m)-1 Read RHR
DATA (n+m)
SStart
Sr Repeated Start
PStop
WWrite
RRead
AAcknowledge
NA Not Acknowledge
DADR Device Address
IADR Internal Address
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Figure 29-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-12. Master Rea d with One, Two or Three Bytes Internal Address and One Data Byte
29.8.6.210-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8]
and IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
Figure 29-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 29-13. Internal Ad dress Usage
29.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CP U load.
To assure correct implementation, respect the following programming sequences:
SDADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
SDADR W A IADR(15:8) A IADR(7:0) A P
DATA A
A IADR(7:0) A P
DATA ASDADR W
TWD Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
SDADR WA IADR(23:16) A IADR(15:8)AIADR(7:0) A
SDADR W A IADR(15:8)A IADR(7:0) A
AIADR(7:0) A
SDADR W
DATA NA P
Sr DADR R A
Sr DADR R A DATA NA P
SrDADR R A DATA NA P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
M
S
B
Device
Address
0
L
S
B
R
/
W
A
C
K
M
S
B
W
R
I
T
E
A
C
K
A
C
K
L
S
B
A
C
K
FIRST
WORD ADDRESS SECOND
WORD ADDRESS DATA
S
T
O
P
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29.8.7.1Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, transfer size - 1).
2. Configure the master (DADR, CKDIV, etc.) or slave mode.
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
5. Disable the PDC by setting the PDC TXTDIS bit.
6. Wait for the TXRDY flag in TWI_SR register
7. Set the STOP command in TWI_CR.
8. Write the last character in TWI_THR
9. (Optional) Wait for the TXCOMP flag in TWI_SR register before disabling the peripheral clock if required
29.8.7.2Data Receive with the PDC
The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be
managed without PDC to ensure that the exa ct number of bytes are received whatever the system bus latency
conditions encountered during the end of buffer transfer period.
In slave mode, the number of characters to receive must be known in order to configure the PDC.
1. Initialize the receive PDC (memory pointers, transfer size - 2).
2. Configure the master (DADR, CKDIV, etc.) or slave mode.
3. Set the PDC RXTEN bit.
4. (Master Only) Write the START bit in the TWI_CR register to start the transfer
5. Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt.
6. Disable the PDC by setting the PDC RXTDIS bit.
7. Wait for the RXRDY flag in TWI_SR register
8. Set the STOP command in TWI_CR
9. Read the penultimate character in TWI_RHR
10. Wait for the RXRDY flag in TWI_SR register
11. Read the last character in TWI_RHR
12. (Optional) Wait for the TXCOMP flag in TWI_SR register before disabling the peripheral clock if required
29.8.8 SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 29-14. SMBUS Quick Command
TXCOMP
TXRDY
Write QUICK command in TWI_CR
TWD AS DADR R/W P
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29.8.9 Read-write Flowcharts
The following flowcharts shown in Figure 29-16 on page 547, Figure 29-17 on page 548, Figure 29-18 on page
549, Figure 29-19 on page 550 and Figure 29-20 on page 551 give examples for read and write operations. A
polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt
enable register (TWI_IER) be configured first.
Figure 29-15. TWI Wr ite Operation with Single Data Byte without Internal Address
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Yes
Yes
BEGIN
No
No
Write STOP Command
TWI_CR = STOP
547
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Figure 29-16. TWI Write Oper ation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Load transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Set the internal address
TWI_IADR = address
Yes
Yes
No
No
Write STOP command
TWI_CR = STOP
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548
Figure 29-17. TWI Wr ite Operation with Multiple Data Bytes with or without Intern al Addr ess
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Data to send?
Read Status register
TXCOMP = 1?
END
BEGIN
Set the internal address
TWI_IADR = address
Yes
TWI_THR = data to send
Yes
Yes
Yes
No
No
No
Write STOP Command
TWI_CR = STOP
No
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
549
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Figure 29-18. TWI Rea d Op eration with Single Data Byte without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
RXRDY = 1?
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Read Receive Holding Register
No
No
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Figure 29-19. TW I Rea d Operation with Single Data Byte and Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Yes
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
RXRDY = 1?
Read Receive Holding register
No
No
551
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Figure 29-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address
Internal address size = 0?
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1?
Last data to read
but one?
Read status register
TXCOMP = 1?
END
Set the internal address
TWI_IADR = address
Yes
Yes
Yes
No
Yes
Read Receive Holding register (TWI_RHR)
No
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
No
No
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
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29.9 Multi-master Mode
29.9.1 Definition
More than one master may handle the bus at the same time without data corruption by using arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops
(arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting
arbitration.
Arbitration is illustrated in Figure 29-22 on page 553.
29.9.2 Different Multi-master Modes
Two multi-master modes may be distinguished:
1. TWI is considered as a Master only and will never be addressed.
2. TWI may be either a Master or a Slave and may be addressed.
Note: In both Multi-master modes arbitration is supported.
29.9.2.1TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with
the ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically
waits for a STOP condition on the bus to initiate the transfer (see Figure 29-21 on page 553).
Note: The state of the bus (busy or free) is not indicated in the user interface.
29.9.2.2TWI as Master or Slave
The automatic reversal from Ma ste r to Slav e is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-
master mode described in the steps below.
1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed).
2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the
bus is considered as free, TWI initiates the transfer.
5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and
the user must monitor the ARBLST flag.
6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case
where the Master that won the arbitration wanted to access the TWI.
7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in
Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.
553
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Figure 29-21. Programmer Sends Data While the Bus is Busy
Figure 29-22. Arbitration Cases
The flowchart shown in Figure 29-23 on page 554 gives an example of read and write operations in Multi-master
mode.
TWCK
TWD DATA sent by a master
STOP sent by the master START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
TWCK
Bus is busy Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI S0
S00
1
1
1
ARBLST
S0
S00
1
1
1
TWD S00
1
11
11
Arbitration is lost
TWI stops sending data
P
S0
1
P0
11
11
Data from the master Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD
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Figure 29-23. Multi-master Flowchart
Programm the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 1 ?
Read Status Register
RXRDY= 1 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
Need to perform
a master access ?
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
ARBLST = 1 ?
MREAD = 1 ?
TXRDY= 0 ?
Write in TWI_THR
Data to send ?
RXRDY= 0 ?
Read TWI_RHR Data to read?
Read Status Register
TXCOMP = 0 ?
GENERAL CALL TREATMENT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Stop Transf er
TWI_CR = STOP
No
No No
No
No
No
No
No
No
No
No
No
No
No No
No
START
555
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29.10 Slave Mode
29.10.1 Definition
The Slave Mode is defined as a mode where the device receives the clock and the address from another device
called the maste r .
In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and
STOP conditions are always provided by the master).
29.10.2 Application Block Diagram
Figure 29-24. Slave Mode Typical Application Block Diagram
29.10.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write
mode.
2. MSDIS (TWI_CR): Disable the master mode.
3. SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
29.10.4 Receiving Data
After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave
address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave
READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is dete cted. When such a condition is detected,
EOSACC (End Of Slave ACCess) flag is set.
29.10.4.1Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit
Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected.
Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set
when the shift regi ster is empty and the sent data acknowledg ed or not. If the data is not acknowledged, the NACK
flag is set.
Note that a STOP or a repeated START always follows a NACK.
See Figure 29-25 on page 556.
Host with
TWI
Interface
TWD
TWCK
LCD Controller
Slave 1 Slave 2 Slave 3
RR
VDD
Host with TWI
Interface Host with TWI
Interface
Master
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29.10.4.2Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Hold ing Register Ready) flag is set as
soon as a character has been rece ived in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when
reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR
is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See Figure 29-26 on page 557.
29.10.4.3Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 29-28 on page 558 and Figure 29-29 on page 559.
29.10.4.4General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the
new address programming sequence.
See Figure 29-27 on page 557.
29.10.5 Data Transfer
29.10.5.1Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR
register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 29-25 on page 556 describes the write operation.
Figure 29-25. Read Access Ordered by a MASTER
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
Write THR Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
SADRSADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK ACK/NACK from the Master
557
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29.10.5.2Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded,
SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 29-26 on page 557 describes the Write operation.
Figure 29-26. Write Access Ordered by a Master
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
29.10.5.3General Call
The general call is per fo rm ed in or de r to chan g e th e ad dres s of the s lav e.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.
In case of a WRITE command, the prog rammer has to decode the program ming sequence and program a ne w
SADR if the programming sequence matches.
Figure 29-27 on page 557 describes the General Call access.
Figure 29-27. Master Performs a General Call
Note: This method allows the user to create an own programming sequence by choo sing the programming bytes and the
number of them . Th e programming sequence has to be provi d ed to the master.
29.10.5.4Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the
emission/reception of a new character. In this case, to avoi d sending/receiving undesired data, a clock stretching
mechanism is implemented.
RXRDY
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
SVACC
SVREAD
EOSVACC
SADR does not match,
TWI answers with a NACK
SADRSADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
0000000 + W
GENERAL CALL P
SA
GENERAL CALL Reset or write DADD A New SADR
DATA1 ADATA2 A
A
New SADR
Programming sequence
TXD
GCACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read
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Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the shift register is loaded.
Figure 29-28 describes the clock synchronization in Read mode.
Figure 29-28. Clock Synchronization in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mech anism is started.
Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a S TOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.
Figure 29-29 on page 559 describes the clock synchronization in Read mode.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register Ack or Nack from the master
DATA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
SSADR
SRDATA0AADATA1 ADATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected
559
SAM4N8/SAM4N16 [DATASHEET]
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Figure 29-29. Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the
mechanism is finished.
29.10.5.5Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read com man d an d fin ish es it by a write command.
Figure 29-30 describes the repeated start + reversal from Read to Write mod e.
Figure 29-30. Repeated Start + Reversal from Read to Write Mode
Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command. Figure 29-31 on
page 560 describes the repeated start + reversal from Write to Read mode.
Rd DATA0 Rd DATA1 Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1 DATA2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADRSSADR W ADATA0A A DATA2DATA1 S
NA
SSADR R ADATA0A DATA1 SADRSr
NA
W A DATA2 A DATA3AP
Cleared after read
DATA0 DATA1
DATA2 DATA3
SVACC
SVREAD
TWD
TWI_THR
TWI_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected
SAM4N8/SAM4N16 [DATASHEET]
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Figure 29-31. Repeated Start + Reversal from Write to Read Mode
Notes: 1. In this case, if TWI_THR has not been written at the end of the read comma nd, the clock is automati cally stretched before
the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
29.10.6 Read Write Flowcharts
The flowchart sh own in Figu re 29 -32 on page 561 gives a n example of re ad and write operatio ns in Slave mo de. A
polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt
enable register (TWI_IER) be configured first.
SSADR W ADATA0A DATA1 SADRSr
A
R A DATA2 A DATA3NA P
Cleared after read
DATA0
DATA2 DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWI_RHR
SVACC
SVREAD
TWD
TWI_RHR
TWI_THR
EOSACC
561
SAM4N8/SAM4N16 [DATASHEET]
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Figure 29-32. Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 0 ?
Read Status Register
RXRDY= 0 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
END
GENERAL CALL TREATMENT
No
No
No No
No
No
No
No
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562
29.11 Two-wire Interface (TWI) User Interface
Note: 1. All unlisted offset values are considered as “reserved”.
Table 29-6 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register TWI_CR Write-only N / A
0x04 Master Mode Register TWI_MMR Read-write 0x00000000
0x08 Slave Mode Register TWI_SMR Read-write 0x000000 00
0x0C Internal Address Register TWI_IADR Read-write 0x00000000
0x10 Clock Waveform Generator Register TWI_CWGR Read-write 0x00000000
0x14 - 0x1C Reserved –––
0x20 Status Register TWI_SR Read-only 0x0000F009
0x24 Interrupt Enable Register TWI_IER Write-only N / A
0x28 Interrupt Disable Register TWI_IDR Write-only N / A
0x2C Interrupt Mask Register TWI_IMR Read-only 0x00 000000
0x30 Receive Holding Register TWI_RHR Read-only 0x00000000
0x34 Transmit Holding Register TWI_THR Write-only 0x00000000
0xEC - 0xFC(1) Reserved – – –
0x100 - 0x128 Reserved for PDC registers – – –
563
SAM4N8/SAM4N16 [DATASHEET]
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29.11.1 TWI Control Register
Name: TWI_CR
Address: 0x40018000 (0), 0x4001C000 (1), 0x40040000 (2)
Access: Write-only
Reset: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI per ipheral wants to read data from a slave. Wh en configure d in Master Mode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the ST OP m ust be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In master data write operation, a STOP condition will be sent after the transmission of the current data is
finished.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note: S witching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pend ing data is transmitte d. The shifter and hold ing characte rs (if it contains data ) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received
before disabling.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST QUICK SVDIS SVEN MSDISMSEN STOP START
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• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.
• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disable d. The shifter and h olding characters (if it contain s data) are transmitted in case of read oper-
ation. In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBUS Quick Command
0 = No effect.
1 = If Master mode is enabled, a SMBUS Quick Command is sent.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
565
SAM4N8/SAM4N16 [DATASHEET]
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29.11.2 TWI Master Mode Register
Name: TWI_MMR
Address: 0x40018004 (0), 0x4001C004 (1), 0x40040004 (2)
Access: Read-write
Reset: 0x00000000
• IADRSZ: Internal Device Address Size
• MREAD: Master Read Direction
0 = Master write direction.
1 = Master read direction.
• DADR: Device Address
The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–DADR
15 14 13 12 11 10 9 8
–––MREAD–– IADRSZ
76543210
––––––––
Value Name Description
0 NONE No internal device address
1 1_BYTE One-byte internal device address
2 2_BYTE Two-byte internal device address
3 3_BYTE Three-byte internal device address
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29.11.3 TWI Slave Mode Register
Name: TWI_SMR
Address: 0x40018008 (0), 0x4001C008 (1), 0x40040008 (2)
Access: Read-write
Reset: 0x00000000
• SADR: Slave Address
The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– SADR
15 14 13 12 11 10 9 8
––––––
76543210
––––––––
567
SAM4N8/SAM4N16 [DATASHEET]
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29.11.4 TWI Internal Address Register
Name: TWI_IADR
Address: 0x4001800C (0), 0x4001C00C (1), 0x4004000C (2)
Access: Read-write
Reset: 0x00000000
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
IADR
15 14 13 12 11 10 9 8
IADR
76543210
IADR
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568
29.11.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address: 0x40018010 (0), 0x4001C010 (1), 0x40040010 (2)
Access: Read-write
Reset: 0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– CKDIV
15 14 13 12 11 10 9 8
CHDIV
76543210
CLDIV
Tlow CLDIV(2CKDIV
×()4)+TMCK
×=
Thigh CHDIV(2CKDIV
×()4)+TMCK
×=
569
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
29.11.6 TWI Status Register
Name: TWI_SR
Address: 0x40018020 (0), 0x4001C020 (1), 0x40040020 (2)
Access: Read-only
Reset: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of th e cu rr ent fra m e.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 29-8 on page 542 and in Figure 29-10 on page 543.
TXCOMP used in Slav e mo de:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 29-28 on page 558, Figure 29-29 on page 559, Figure 29-30 on
page 559 and Figure 29-31 on page 560.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 29-1 0 on page 543.
RXRDY behavior in Slav e mo d e can be seen in Figure 29-26 on page 557, Figure 29-29 on page 559, Figure 29-30 on
page 559 and Figure 29-31 on page 560.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 29.8.4 on page 540.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
76543210
–OVREGACC SVACC SVREAD TXRDY RXRDY TXCOMP
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TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
programmer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Figure 29-25 on page 556, Figure 29-28 on page 558, Figure 29-30 on
page 559 and Figure 29-31 on page 560.
• SVREAD: Slave Re ad (aut omatically set / rese t )
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write ac ce ss is perfo rm e d by a Ma st er .
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in Figure 29-25 on page 556, Figure 29-26 on page 55 7, Figure 29-30 on page 559 and
Figure 29-31 on page 560.
• SVACC: Slave Access (automatically set / reset)
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a
NACK or a STOP condition is detected.
SVACC behavior can be seen in Figure 29-25 on pag e 556, Figure 29-26 on page 557 , Fig ure 29-3 0 on pa ge 559 an d Fig-
ure 29-31 on page 560.
• GACC: General Call Access (clear on read)
This bit is only used in Slave mode.
0 = No General Call has been detected.
1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge
this access and decode the following bytes and respond according to the value of the bytes.
GACC behavior can be seen in Figure 29-27 on page 557.
• OVRE: Overrun Error (clear on read)
This bit is only used in Master mode.
0 = TWI_RHR has not be en loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (cle ar on read )
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill
TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
571
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• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new
character.
SCLWS behavior can be seen in Figure 29-28 on page 558 and Figure 29-29 on page 559.
• EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 29-30 on page 559 and Figure 29-31 on page 560
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full
0 = TWI_RCR or TWI_RNCR have a value other than 0.
1 = Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = TWI_TCR or TWI_TNCR have a value other than 0.
1 = Both TWI_TCR and TWI_TNCR have a value of 0.
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572
29.11.7 TWI Interrupt Enab le Register
Name: TWI_IER
Address: 0x40018024 (0), 0x4001C024 (1), 0x40040024 (2)
Access: Write-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the corr es po nd in g inte r ru pt .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
573
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29.11.8 TWI Interrupt Disable Register
Name: TWI_IDR
Address: 0x40018028 (0), 0x4001C028 (1), 0x40040028 (2)
Access: Write-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
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574
29.11.9 TWI Interrupt Mask Register
Name: TWI_IMR
Address: 0x4001802C (0), 0x4001C02C (1), 0x4004002C (2)
Access: Read-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
575
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29.11.10TWI Receive Holding Register
Name: TWI_RHR
Address: 0x40018030 (0), 0x4001C030 (1), 0x40040030 (2)
Access: Read-only
Reset: 0x00000000
• RXDATA: Master or Slave Receive Holding Data
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
––––––––
76543210
RXDATA
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576
29.11.11TWI Transmit Holding Register
Name: TWI_THR
Address: 0x40018034 (0), 0x4001C034 (1), 0x40040034 (2)
Access: Read-write
Reset: 0x00000000
• TXDATA: Master or Slave Transmit Holding Data
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
TXDATA
577
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30. Universal Asynchronous Receiver Transmitter (UART)
30.1 Description
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication
and trace purposes and offers an ideal medium for in-situ programming solutions.
Moreover, the association with peripheral DMA controller (PDC) permits packet handling for these tasks with
processor time reduced to a minimum.
30.2 Embedded Characteristics
Two-pin UART
Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Fram in g and Overrun Error Dete ct ion
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two PDC Channels with Connection to Receiver and Transmitter
30.3 Block Diagram
Figure 30-1. UART Functional Block Diagram
Peripheral DMA Controller
Baud Rate
Generator
Transmit
Receive
Interrupt
Control
Peripheral
Bridge
Parallel
Input/
Output
UTXD
URXD
Power
Management
Controller
MCK
uart_irq
APB UART
Table 30-1. UART Pin Description
Pin Name Description Type
URXD UART Receive Data Input
UTXD UAR T Transmit Data Output
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30.4 Product Dependencies
30.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO
Controller to enable I/O line operations of the UART.
30.4.2 Power Management
The UART clock is controllable through the Power Managemen t Controller . In th is case, the p ro gramme r must fir st
configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
30.4.3 Interrupt Source
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling
requires programming of the Interrupt Controller before configuring the UART.
Table 30-2. I/O Lines
Instance Signal I/O Line Peripheral
UART0 URXD0 PA9 A
UART0 UTXD0 PA10 A
UART1 URXD1 PB2 A
UART1 UTXD1 PB3 A
UART2 URXD2 PA16 A
UART2 UTXD2 PA15 A
UART3 URXD3 PB10 B
UART3 UTXD3 PB11 B
579
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30.5 UART Operations
The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no
clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented
features are compatible with those of a standard USART.
30.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in UART_BRGR (Baud Rate
Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive .
The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master
Clock divided by (16 x 65536).
Figure 30-2. Baud Rate Generator
30.5.2 Receiver
30.5.2.1Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be
enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the re ceiver starts
looking for a start bit.
The programmer can d isable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for
a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the
data, it waits for the stop bit before actually stopping its operation.
The programmer can also pu t the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing
so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is
applied when data is being processed, this data is lost.
Baud Rate MCK
16 CD ×
---------------------- =
MCK 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Cloc
k
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580
30.5.2.2Start Detection and Data Sampling
The UART only supports asynchron ous operations, and this affects only its receiver. The UART re ceiver detects
the start of a received character by samp ling the URXD signal until it detects a valid start bit. A low level (space) on
URXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16
times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A
space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It
is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is theref ore 24 cycles (1.5-bit periods) after the
falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 30-3. Start Bit Detection
Figure 30-4. Character Reception
30.5.2.3Receiver Ready
When a complete character is re ceived, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is
read.
Figure 30-5. Rece iver Ready
Sampling Clock
URXD
True Start
Detection D0
Baud Rate
Clock
D0 D1 D2 D3D4 D5 D6 D7
URXD
True Start Detection
Sampling Parity Bit Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
D0 D1 D2 D3D4 D5 D6 D7 PSSD0 D1 D2 D3D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
581
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30.5.2.4Receiver Overrun
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set.
OVRE is cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.
Figure 30-6. Receiver Overrun
30.5.2.5Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit
PARE in UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register
UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received befo re the reset status
command is written, the PARE bit remains at 1.
Figure 30-7. Parity Error
30.5.2.6Receiver Framing Error
When a start bit is detecte d, it generates a characte r reception whe n all the data bi ts have been sa mpled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UA RT_SR is set at the same
time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit
RSTSTA at 1.
Figure 30-8. Rece iver Framing Error
D0 D1 D2 D3D4 D5 D6 D7 PSSD0 D1 D2 D3D4 D5 D6 D7 P
URXD
RSTSTA
RXRDY
OVRE
stop stop
stop
D0 D1 D2 D3D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
D0 D1 D2 D3D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
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30.5.3 Transmitter
30.5.3.1Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is
enabled by writing the co ntrol r egister U ART_ C R wit h th e bit TXEN at 1 . From this command, the transmitter waits
for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the
transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a
character has been wr itten in th e Transmit Holding Register, the character s are completed be fore the transmitte r is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whether or not it is processing characters.
30.5.3.2Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the
format defined in the Mo de Register and the data stored in the Shift Register. One start bit at level 0, then the 8
data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are co nsecutively shifted
out as shown in the following figure. T he field PARE in the mode register UART_MR defines whether or not a
parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even par ity, or a
fixed space or mark bit.
Figure 30-9. Cha racter Transmission
30.5.3.3Transmitter Control
When the transmitte r is enabled, the bit TXRDY (Transmitter Ready) is set in the sta tus register UART_SR. The
transmission starts when the programmer writes in the Transm it Holding Register (UART_THR), and after the
written character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second
character is written in UART_THR. As soon as the first character is completed, the last character written in
UART_THR is transferred into the shift registe r and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been
processed, the TXEMPTY bit rises after the last stop bit has been completed.
D0 D1 D2 D3D4 D5 D6 D7
UTXD
Start
Bit Parity
Bit Stop
Bit
Example: Parity enabled
Baud Rate
Clock
583
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Figure 30-10. Transmitter Control
30.5.4 Peripheral DMA Controller
Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within the UART user
interface from the o ffset 0x100. The status bits are report ed in the UART status register (UART_ SR) and can
generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in
UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of
data in UART_THR.
30.5.5 Test Modes
The UART supports three test m odes. These modes of operation a re programmed by using the fie ld CHMODE
(Channel Mode) in the mode register (UART_MR).
The Automatic Echo mode allo ws bit-by-bit retransmission. When a bit is received o n the URXD line, it is sent to
the UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
The Local Loopback mode allows the transm itted characters to be received. UTXD and URXD pins are not used
and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no
effect and the UTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver
are disabled and have no effect. This mode allows a bit-by-bit retransmission.
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Data 1SSPP
Write Data 0
in UART_THR Write Data 1
in UART_THR
stop
stop
SAM4N8/SAM4N16 [DATASHEET]
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584
Figure 30-11. Test Modes
Receiver
Transmitter Disabled
RXD
TXD
Receiver
Transmitter Disabled
RXD
TXD
VDD
Disabled
Receiver
Transmitter Disabled
RXD
TXD
Disabled
Automatic Echo
Local Loopback
Remote Loopback VDD
585
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30.6 Universal Asynchronous Receiver Transmitter (UART) User Interface
Table 30-3 . Register Mapping
Offset Register Name Access Reset
0x0000 Control Register UART_CR Write-only –
0x0004 Mode Register UART_MR Read-write 0x0
0x0008 Interrupt Enable Register UART_IER Write-only –
0x000C Interrupt Disable Register UART_IDR Write-only –
0x0010 Interrupt Mask Register UART_IMR Read-only 0x0
0x0014 Status Register UART_SR Read-only –
0x0018 Receive Holding Register UART_RHR Read-only 0x0
0x001C Transmit Hol ding Register UART_THR Write-only –
0x0020 Baud Rate Generator Register U ART_BRGR Read-write 0x0
0x0024 - 0x003C Reserved – – –
0x004C - 0x00FC Reserved – – –
0x0100 - 0x0124 Reserved for PDC registers – – –
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30.6.1 UART Control Register
Name: UART_CR
Address: 0x400E0600 (0), 0x400E0800 (1), 0x40044000 (2), 0x40048000 (3)
Access: Write-only
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled. If a character is be ing processed and RSTRX is not set, the cha racter is completed before th e
receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the UART_SR.
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–––––––RSTSTA
76543210
TXDISTXEN RXDISRXEN RSTTX RSTRX – –
587
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30.6.2 UART Mode Register
Name: UART_MR
Address: 0x400E0604 (0), 0x400E0804 (1), 0x40044004 (2), 0x40048004 (3)
Access: Read-write
•PAR: Parity Type
• CHMODE: Channel Mode
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15 14 1312 11 10 9 8
CHMODE – – PAR –
76543210
––––––––
Value Name Description
0 EVEN Even Parity
1ODD Odd Parity
2SPACE Space: parity forced to 0
3MARK Ma rk: parity forced to 1
4NO No Parity
Value Name Description
0 NORM AL Normal Mode
1AUTOMATIC Au tomatic Echo
2 LOCAL_LOOPBACK Local Loopback
3 REMOTE_LOOPBACK Remote Loopback
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588
30.6.3 UART Interrupt Enable Register
Name: UART_IER
Address: 0x400E0608 (0), 0x400E0808 (1), 0x40044008 (2), 0x40048008 (3)
Access: Write-only
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
0 = No effect.
1 = Enables the corr es po nd in g inte r ru pt .
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2322 21 20 19 1817 16
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15 14 1312 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
589
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30.6.4 UART Interrupt Disable Register
Name: UART_IDR
Address: 0x400E060C (0), 0x400E080C (1), 0x40044 00C (2), 0x4004800C (3)
Access: Write-only
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
3130292827 26 25 24
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2322 21 20 19 1817 16
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15 14 1312 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
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30.6.5 UART Interrupt Mask Register
Name: UART_IMR
Address: 0x400E0610 (0), 0x400E0810 (1), 0x40044010 (2), 0x40048010 (3)
Access: Read-only
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
3130292827 26 25 24
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2322 21 20 19 1817 16
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15 14 1312 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
591
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30.6.6 UART Status Register
Name: UART_SR
Address: 0x400E0614 (0), 0x400E0814 (1), 0x40044014 (2), 0x40048014 (3)
Access: Read-only
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to UART_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to UART_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer
0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the receiver Peripheral Da ta Controller channel is active.
• ENDTX: End of Transmitter Transfer
0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.
• OVRE: Overrun Error
0 = No overrun error has occurred since the last RSTSTA.
1 = At least one overru n er ro r has occurred since the last RS T STA.
•FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing er ro r ha s occu r red since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in UART_THR and there are no characters being processed by the transmitter.
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2322 21 20 19 1817 16
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15 14 1312 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
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• TXBUFE: Transmission Buffer Empty
0 = The buffer empty signal from the transmitter PDC channel is inactive.
1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0 = The buffer full signal from the receiver PDC channel is inactive.
1 = The buffer full signal from the receiver PDC channel is active.
593
SAM4N8/SAM4N16 [DATASHEET]
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30.6.7 UART Receiver Holding Register
Name: UART_RHR
Address: 0x400E0618 (0), 0x400E0818 (1), 0x40044018 (2), 0x40048018 (3)
Access: Read-only
• RXCHR: Received Character
Last received character if RXRDY is set.
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RXCHR
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594
30.6.8 UART Transmit Holding Register
Name: UART_THR
Address: 0x400E061C (0), 0x400E081C (1), 0x40044 01C (2), 0x4004801C (3)
Access: Write-only
• TXCHR: Chara cte r to be Transmi tt ed
Next character to be transmitted after the current character if TXRDY is not set.
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15 14 1312 11 10 9 8
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76543210
TXCHR
595
SAM4N8/SAM4N16 [DATASHEET]
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30.6.9 UART Baud Rate Generator Register
Name: UART_BRGR
Address: 0x400E0620 (0), 0x400E0820 (1), 0x40044020 (2), 0x40048020 (3)
Access: Read-write
• CD: Clock Divisor
0 = Baud Rate Clock is disabled
1 to 65,535 = MCK / (CD x 16)
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15 14 1312 11 10 9 8
CD
76543210
CD
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596
31. Universal Synchronous Asynchronous Receiver Transmitter (USART)
31.1 Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of
stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun
error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard
facilitates communications with slow remote devices. Multidrop communications are also supported through
address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific op era ting mod es providin g in te rfaces on RS48 5 and SPI buses, with ISO7816 T = 0
or T = 1 smart card slots and infrared transceivers. The ha rdware handshaking feature enables an out-of-ba nd
flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the
transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
31.2 Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
Parity Generation and Error Detection
Framing Error Detection, Overrun Error Detection
MSB- or LSB-first
Optional Break Generation and Detection
By 8 or by 16 Over-sampling Receiver Frequency
Optional Hardware Handshaking RTS-CTS
Receiver Time-out and Transmitter Timeguard
Optional Multidrop Mode with Address Generation and Detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
NACK Handling, Error Counter with Repetition and Iteration Limit
IrDA Modulation and Demodulation
Communication at up to 115.2 Kbps
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
Supports Connection of:
Two Peripheral DMA Controller Channels (PDC)
Offers Buffer Transfer without Processor Intervention
597
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31.3 Block Diagram
Figure 31-1. USART Block Diagram
Table 31-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –
(Peripheral) DMA
Controller
Channel Channel
Interrupt
Controller
Receiver
USART
Interrupt
RXD
TXD
SCK
USART PIO
Controller
CTS
RTS
Transmitter
Baud Rate
Generator
User Interface
PMC MCK
SLCK
DIV MCK/DIV
APB
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31.4 Application Block Diagram
Figure 31-2. App lication Block Diagram
31.5 I/O Lines Description
Smart
Card
Slot
USART
RS485
Drivers
Differential
Bus
IrDA
Transceivers
Field Bus
Driver EMV
Driver IrDA
Driver
IrLAP
RS232
Drivers
Serial
Port
Serial
Driver
PPP SPI
Driver
SPI
Bus
Table 31-2. I/O Line Description
Name Description Type Active Level
SCK Serial Clock I/O
TXD Transmit Serial Data
or Master Out Slave In (MOSI) in SPI Master Mode
or Master In Slave Out (MISO) in SPI Slave Mode I/O
RXD Receive Serial Data
or Master In Slave Out (MISO) in SPI Master Mode
or Master Out Slave In (MOSI) in SPI Slave Mode Input
CTS Clear to Send
or Slave Select (NSS) in SPI Slave Mode Input Low
RTS Request to Send
or Slave Select (NSS) in SPI Master Mode Output Low
599
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31.6 Product Dependencies
31.6.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the desired USART pins to their per iphera l function. If I/O lines of the USART
are not used by the application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
hardware handshaking feature is used, the internal pull up on TXD must also be enabled.
31.6.2 Power Management
The USART is not continuously clocked. The p rogrammer must first enable the USART Clock in the Power
Management Cont roller (PMC) before using the USART. However, if th e application does not require USART
operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will
resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
Table 31-3. I/O Lines
Instance Signal I/O Line Peripheral
USART0 CTS0 PA8 A
USART0 RTS0 PA7 A
USART0 RXD0 PA5 A
USART0 SCK0 PA2 B
USART0 TXD0 PA6 A
USART1 CTS1 PA25 A
USART1 RTS1 PA24 A
USART1 RXD1 PA21 A
USART1 SCK1 PA23 A
USART1 TXD1 PA22 A
USART2 CTS2 PC17 A
USART2 RTS2 PC16 A
USART2 RXD2 PC9 A
USART2 SCK2 PC14 A
USART2 TXD2 PC10 A
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31.6.3 Interrupt
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART
interrupt requires the Interrupt Controller to be programmed first. No te that it is not recommended to use the
USART interrupt line in edge sensitive mode.
Table 31-4. Peripheral IDs
Instance ID
USART0 14
USART1 15
USART2 17
601
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31.7 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications.
It supports the following communication modes:
5- to 9-bit full-duplex asynchronous serial communication
MSB- or LSB-first
1, 1.5 or 2 stop bits
Parity even, odd, marked, space or none
By 8 or by 16 over-sampling receiver frequency
Optional hardware handshaking
Optional break management
Optional multidrop serial communication
High-speed 5- to 9-bit full-duplex synchronous serial communication
MSB- or LSB-first
1 or 2 stop bits
Parity even, odd, marked, space or none
By 8 or by 16 over-sampling frequency
Optional hardware handshaking
Optional break management
Optional multidrop serial communication
RS485 with driver control signal
ISO7816, T0 or T1 protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit, inverted data.
InfraRed IrDA Modulation and Demodulation
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
Test modes
Remote loopback, local loopback, automatic echo
31.7.1 Baud Rate Generator
The Baud Rate Generator provide s the bit period clock named the Baud Rate Clock to both the receiver and the
transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register
(US_MR) betwe e n:
The Master Clock MCK
A division of the Master Clock, the divider being product dependent, but generally set to 8
The external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any
clock. If CD is programmed to 1, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a Master Clo ck (MCK) pe riod. Th e frequen cy of the signal provided on SCK mu st be at least 3
times lower than MCK in USART mode, or 6 times lower in SPI mode.
SAM4N8/SAM4N16 [DATASHEET]
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602
Figure 31-3. Baud Rate Generator
31.7.1.1Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is
field programme d in the Baud Rate Generator Reg ister (US_BRGR). The re sulting clock is provided to the receiver
as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the
sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that
OVER is programmed to 1.
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
Baudrate SelectedClock
82 Over–()CD()
--------------------------------------------
=
603
SAM4N8/SAM4N16 [DATASHEET]
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Baud Rate Calculation Examp le
Table 31-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies.
This table also shows the actual resulting baud rate and the error.
The baud rate is calcu la te d with the following formula:
The baud rate error is calcula ted with the following formula. It is not recommended to work with an error higher
than 5%.
Table 31-5. Baud Rate Example (OVER = 0)
Source Clock Expected Baud
Rate Calculation Result CD Actual Baud Rate Error
MHz Bit/s Bit/s
3 686 400 38 400 6.00 6 38 400.00 0.00%
4 915 200 38 400 8.00 8 38 400.00 0.00%
5 000 000 38 400 8.14 8 39 062.50 1.70%
7 372 800 38 400 12.00 12 38 400.00 0.00%
8 000 000 38 400 13.02 13 38 461.54 0.16%
12 000 000 38 400 19.53 20 37 500.00 2.40%
12 288 000 38 400 20.00 20 38 400.00 0.00%
14 318 180 38 400 23.30 23 38 908.10 1.31%
14 745 600 38 400 24.00 24 38 400.00 0.00%
18 432 000 38 400 30.00 30 38 400.00 0.00%
24 000 000 38 400 39.06 39 38 461.54 0.16%
24 576 000 38 400 40.00 40 38 400.00 0.00%
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
BaudRate MCK CD 16×⁄=
Error 1ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
–=
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604
31.7.1.2Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by
only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock
generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a
fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate
Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is
calculated using the following formula:
The modified arc hit ec tu re is pres en te d be low :
Figure 31-4. Fra ction al Baud Rate Generator
31.7.1.3Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD
in US_BRGR.
In synchronous mode, if the extern al clock is selected (USCLKS = 3), the clock is provided directly by the signal on
the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock
frequency must be at least 3 times lower than the system cloc k. In synchronous mode master (USCLKS = 0 or 1,
CLK0 set to 1), the receive part limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI
mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in
CD must be even if the user has to ensure a 50:50 mark/s pace ratio on the SCK pin. If the internal clock MCK is
selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in
CD is odd.
Baudrate SelectedClock
82 Over–()CD FP
8
-------
+
----------------------------------------------------------------
=
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
Glitch-free
Logic
Modulus
Control
FP
FP
BaudRate SelectedClock
CD
--------------------------------------
=
605
SAM4N8/SAM4N16 [DATASHEET]
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31.7.1.4Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represen ted in Table 31-6.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-7.
Table 31-8 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock.
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register
(US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register
(US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means
that the CLKO bit can be set in US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register
(US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode.
The non-integer va lue s of the Fi/Di Ratio ar e no t sup ported and the user must program the FI_DI_RAT IO fiel d to a
value as close as possible to the expected value.
The FI_DI _RATIO field r esets to the value 0x174 (372 in decimal) and is the most common divider between the
ISO7816 clock and the bit rate (Fi = 372, Di = 1).
Figure 31-5 shows the relation between the Elementary Time Unit, corr esponding to a bit time, and the ISO 7816
clock.
BDi
Fi
------f×=
Table 31-6. Bina ry and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal) 1 2 4 8 16 32 12 20
Table 31-7. Bina ry and Decimal Values for Fi
FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 31-8 . Possible Values for the Fi/Di Ratio
Fi/Di 372 558 774 1116 1488 1806 512 768 1024 1536 2048
1 372 558 744 1116 1488 1860 512 768 1024 1536 2048
2 186 279 372 558 744 930 256 384 512 768 1024
4 93 139.5 186 279 372 465 128 192 256 384 512
8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
SAM4N8/SAM4N16 [DATASHEET]
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606
Figure 31-5. Elementary Time Unit (ETU)
31.7.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control
Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register
(US_CR). However, the transmitter registers can be programmed before being enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear
the status flag and reset internal state machines but the user interface configuration registers hold the value
configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the
communication is immediately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively
in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of
the current character, then the re ception is stopped. If the transmitter is disabled while it is operating, the USART
waits the end of transmission of both the current character and character being stored in the Transmit Holding
Register (US_THR). If a timeguard is programmed, it is handled normally.
31.7.3 Synchronous and Asynchronous Modes
31.7.3.1Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC
= 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on
the TXD pin at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field an d the MODE 9 bit in the Mode Register (US_MR). Nine
bits are selected by setting the MODE 9 b it reg ardless of the CHRL field. The parity bit is set according to the PAR
field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR
configures which data bit is sent first. If w ritten to 1, the most significant bit is sent first. If written to 0, the les s
significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. T he 1.5 stop bit is
supported in asynchronous mode only.
1 ETU
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles
607
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 31-6. Character Transmit
The characters are sent by writing in the Transmit Holding Register (U S_THR ). The tr ansmitte r repo rts two s tatus
bits in the Channel Status Register (US_CSR): TXRDY (Trans mitter Ready), which indicates that US_THR is
empty and TX EMPTY, which indicate s that all the char acters wr itten in US_THR h ave been pr ocessed . When the
current character processing is completed, the last character written in US_THR is transferred into the Shift
Register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
Figure 31-7. Transmitter Status
31.7.3.2Asynchronous Receiver
If the USART is programmed in asynchronous operating mo de (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode
Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversa mpling is 16, (O VER to 0), a sta rt is detected at the eig hth sample to 0. Then, da ta bits, pa rity bit and
stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER to 1), a start bit is detected
at the fourth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter,
i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that
resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is
sampled, the receiver starts looking for a new start bi t so that resynchronization can also be accomplished when
the transmitter is operating with one stop bit.
Figure 31-8 and Figure 31-9 illustrate start detection and character reception when USART operates in
asynchronous mode.
D0 D1 D2 D3D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
D0 D1 D2 D3D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
Write
US_THR
D0 D1 D2 D3D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
SAM4N8/SAM4N16 [DATASHEET]
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608
Figure 31-8. Asynchronous Start Detection
Figure 31-9. Asynchronous Character Reception
31.7.3.3Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate
Clock. If a low level is detected, it is considered as a start. All data bits, the pa rity bit an d the stop bits ar e sa mple d
and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 31-10 illus trates a charac ter reception in synchronous mode.
Figure 31-10. Synchronous Mode Character Reception
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
12345678
123456701234
123456789 1011121314 15 16 D0
Sampling
D0 D1 D2 D3D4 D5 D6 D7
RXD
Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples
D0 D1 D2 D3D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
609
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31.7.3.4Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the
RXRDY bit in the Status Register (US_CSR) rises. If a c haracter is completed while the RXRD Y is set, the OV RE
(Overrun Error) bit is set. The last character is tran sferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
Figure 31-11. Receiver Status
31.7.3.5Parity
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR).
The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 610. Even and odd parity bit
generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a pa rity error if the sampled parity bit does not correspo nd. If odd parity is
selected, th e parity gen erator of the transmitt er drives the parity bit to 1 if a number of 1s in the character da ta bit
is even, and to 0 if the nu mber of 1 s is odd. Accordingl y, the r eceiver parity ch ecker counts the n umber of receive d
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity
generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error
if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit
to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is
disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 31-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Be cause there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added
when a parity is even .
D0 D1 D2 D3D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0 D1 D2 D3D4 D5 D6 D7
Start
Bit Parity
Bit Stop
Bit
RSTSTA = 1
Read
US_RHR
Table 31-9. Parity Bit Examples
Character Hexa Binary Parity Bit Parity Mode
A 0x41 0100 0001 1 Odd
A 0x41 0100 0001 0 Even
A 0x41 0100 0001 1 Mark
A 0x41 0100 0001 0 Space
A 0x41 0100 0001 None None
SAM4N8/SAM4N16 [DATASHEET]
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610
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register
(US_CSR). The PARE bit can be cleared by wr iting the Control Register (US_CR) with the RSTSTA bit to 1. Figure
31-12 illustrates the parity bit status setting and clearing.
Figure 31-12. Parity Error
31.7.3.6Multidrop Mode
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in
Multidrop Mode. This mode differentiates the data characters and the address character s. Data is transmitted with
the parity bit to 0 and addresses are transmitted with the parity bit to 1.
If the USART is configured in multid rop m ode, the receiver sets th e PARE parity error bit when the parity bi t is high
and the transmitter is able to send a character with the parity bit high when the Control Register is written with the
SENDA bit to 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA to 1.
The transmitter sen ds an address byte (par ity bit se t) when SENDA is written to US_CR. In this case, the next byte
written to US_THR is transmitted as an address. Any ch aracter written in US_THR without having written the
command SENDA is transmitted normally with the parity to 0.
31.7.3.7Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line betwee n two characters. This
idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR).
When this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on
TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of
stop bits.
As illustrated in Figure 31-13, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of
a timeguard. TXRDY rises only when the start bit of the next character is sent, and th us remains to 0 during the
timeguard transmission if a character has been written in US_THR. TXEMPTY re mains low until the timeguard
transmission is completed as the timeguard is part of the current character being transmitted.
D0 D1 D2 D3D4 D5 D6 D7
RXD
Start
Bit Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1
Parity Error
Detect
Time Flags
Report
Time
611
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Figure 31-13. Timeguard Operations
Table 31-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the
function of the Baud Rate.
D0 D1 D2 D3D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
US_THR
D0 D1 D2 D3D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 31-10. Maximum Timeguard Length Depending on Baud Rate
Baud Rate Bit time Timeguard
Bit/sec µs ms
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
38400 26 6.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21
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31.7.3.8Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition
on the RXD line. When a time-out is de tected, the bit TIMEOUT in the Channel Stat us Register (US_CSR) rises
and can generate an interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programm ed in the TO field of
the Receiver Time-out Register ( US_RT OR ). If the TO fie ld is pr ogr amm ed to 0, the Receiver Time-out is disabled
and no time-ou t is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit
counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time
a new character is received. If th e coun te r reache s 0, the TIMEOUT bit in the Statu s Register rises. Then , the user
can either:
Stop the counter clock until a new characte r is received. This is performed by writing the Control Register
(US_CR) with the STTT O (Start T im e-out) bit to 1. In this case , the idle st ate on RXD before a new character
is received will not provide a time-out. This prevents having to handle an interrupt before a character is
received and allows waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO
(Reload and Start T ime-out) bit to 1. If RETTO is performed, the counter st arts counting down immediately
from the value T O. This enable s generation of a periodic interrupt so that a user time-out can be h andled, for
example when no key is pressed on a keyboard.
If STTTO is performed, th e counter cloc k is stopped until a first ch aracter is received . The idle state on RXD b efore
the start of the frame does not provide a time-out. This pre vents having to obtain a period ic interrupt and ena bles a
wait of the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation
of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 31-14 shows the block diagram of the Receiver Time-out feature.
Figure 31-14. Rece iver Time-out Block Diagram
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear
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Table 31-11 gives the maximum time-out period for some standard baud rates.
31.7.3.9Framing Error
The receiver is capable of detecting framing errors. A framing e rror happens when the stop bit of a received
character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is
asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control
Register (US_CR) with the RSTSTA bit to 1.
Figure 31-15. Framing Error Status
31.7.3.10Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the
TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity
and the stop bits to 0. However, the transmitter holds the TXD line at least during one character until the user
requests the break condition to be removed.
Table 31-11. Maximum Time-out Period
Baud Rate Bit Time Time-out
bit/sec µs ms
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
38400 26 1 704
56000 18 1 170
57600 17 1 138
200000 5 328
D0 D1 D2 D3D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
FRAME
RXRDY
RSTSTA = 1
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A break is transmitted by writing the Contro l Register (U S_CR) with the STTBRK bit to 1. Th is can be pe rformed at
any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a
character is being transmitted. If a break is requested whil e a character is being shifted out, the character is first
completed before the TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is
completed.
The break condition is removed by writing US_CR with the STPBRK bit to 1. If the STPBRK is requested before
the end of the minimum bre ak duration (one character, including start , data, parity and stop bits), the transmitter
ensures that the break condition completes.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are
taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break cond ition clears the TXRDY
and TXEMPTY bits as if a character is processed.
Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK
commands request ed wi thout a pr eviou s STTB RK comman d ar e ignored. A byte written into the Transmit Holding
Register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a m inimu m of 12 bit times. Thus, the
transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character.
If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 31-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the
TXD line.
Figure 31-16. Break Transmission
31.7.3.11Receive Break
The receiv er dete cts a brea k con ditio n whe n all d ata, par ity a nd s top bi ts are lo w. Th is corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by
writing the Control Register (US_CR) with the bit RSTSTA to 1.
An end of receive break is detected by a hi gh level fo r at least 2/ 16 of a bit p eriod in as ynchro nous operat ing mod e
or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK
bit.
D0 D1 D2 D3D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
615
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31.7.3.12Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to
connect with the remote device, as shown in Figure 31-17.
Figure 31-17. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the
Mode Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard
synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level
on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the
PDC channel for reception. The transmitter can handle hardware handshaking in any case.
Figure 31-18 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if
the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high.
Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the
Receiver is enabled, the RTS falls, indicating to the remo te device that it can start transmitting. Defining a new
buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.
Figure 31-18. Receiver Behavior when Operatin g with Hardware Handshaking
Figure 31-19 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the
transmitter. If a charac ter is being processing, the transm itter is disabled only after the comp letion of the current
character and transmission of the next character happens as soon as the pin CTS falls.
Figure 31-19. Transmitter Behavior when Operating with Hardware Handshaking
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS
RTS
RXBUFF
Write
US_CR
RXEN = 1
RXD RXDIS = 1
CTS
TXD
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31.7.4 ISO7816 Mode
The USART features an ISO7816-compat ib le operat ing mode. This mo de permits inte rfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined
by the ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register
(US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.
31.7.4.1ISO7816 Mode Overview
The ISO7816 is a half duplex commu nication on only one bidirectional line. The baud rate is determ ined by a
division of the clock provided to the remote device (see “Baud Rate Generator” on page 602).
The USART connects to a smart card as shown in Figure 31-20. The TXD line b ecomes bidirectional and the Baud
Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin become s bidirectional, its outpu t remains
driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input
of the receiver. The USART is considered as the master of the communication as it gene rates the clock.
Figure 31-20. Connection of a Smart Card to the USART
When operatin g in ISO7816, either in T = 0 o r T = 1 modes, the charact er format is fixed. Th e configuration is 8
data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and
CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in
normal or inverse mode. Refer to “USART Mode Register” on page 633 and “PAR: Parity Type” on page 634.
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is
unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the
receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816
mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted
on the I/O line at their negative value.
31.7.4.2Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which
lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line re mains to 1 during the guard time and the transmitter can continue with
the transmission of the next character, as shown in Figure 31-21.
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 31-
22. This error bit is also named NA CK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as
the guard time length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erron eous character in the Receive
Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the
software can handle the error.
Smart
Card
SCK CLK
TXD I/O
USART
617
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Figure 31-21. T = 0 Protocol without Parity Error
Figure 31-22. T = 0 Protocol with Parity Error
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER)
register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the
NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode
Register (US_MR). If INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK is set, the e rroneous received character is stored in the Receive Holding Register, as if no
error occurred and the RXRDY bit does rise.
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before
moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register
(US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus
seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetitio n number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Sta tus
Register (US_CSR). If the repetition of the charact er is ackn owledged by the receiver, the repetitions are stopped
and the iteration counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit to 1.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed
by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is
programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered
as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.
31.7.4.3Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one
stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the
PARE bit in the Channel Status Register (US_CSR).
D0 D1 D2 D3D4 D5 D6 D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Next
Start
Bit
Guard
Time 2
D0 D1 D2 D3D4 D5 D6 D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Start
Bit
Guard
Time 2 D0 D1
Error
Repetition
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31.7.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure
31-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data
transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s.
The USART IrDA mo de is en ab le d b y se ttin g th e USART _ MODE field in the Mode Register (US_MR) to the value
0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and
receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and
the demodulator are activated.
Figure 31-23. Connection to IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be
managed.
To receive IrDA signals, the following needs to be done:
Disable TX and Enable RX
Configure th e TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-
up (better for power consumption).
Receive data
31.7.5.1IrDA Modulation
For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a
light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 31-12.
Figure 31-24 shows an example of character transmission.
IrDA
Transceivers
RXD RX
TXD TX
USART
Demodulator
Modulator
Receiver
Transmitter
Table 31-12. IrDA Pulse Duration
Baud Rate Pulse Duration (3/16)
2.4 Kb/s 78.13 µs
9.6 Kb/s 19.53 µs
19.2 Kb/s 9.77 µs
38.4 Kb/s 4.88 µs
57.6 Kb/s 3.26 µs
115.2 Kb/s 1.63 µs
619
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Figure 31-24. IrDA Modulation
31.7.5.2IrDA Baud Rate
Table 31-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on
the maximum acceptable error of ±1.87% must be met.
Bit Period Bit Period
3
16
Start
Bit Data Bits Stop
Bit
00
000
111 1
1
Transmitter
Output
TXD
Table 31-13. IrDA Baud Rate Error
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 115 200 2 0.00% 1.63
20 000 000 11 5 200 11 1.38% 1.63
32 768 000 11 5 200 18 1.25% 1.63
40 000 000 11 5 200 22 1.38% 1.63
3 686 400 57 600 4 0.00% 3.26
20 000 000 57 600 22 1.38% 3.26
32 768 000 57 600 36 1.25% 3.26
40 000 000 57 600 43 0.93% 3.26
3 686 400 38 400 6 0.00% 4.88
20 000 000 38 400 33 1.38% 4.88
32 768 000 38 400 53 0.63% 4.88
40 000 000 38 400 65 0.16% 4.88
3 686 400 19 200 12 0.00% 9.77
20 000 000 19 200 65 0.16% 9.77
32 768 000 19 200 107 0.31% 9.77
40 000 000 19 200 130 0.16% 9.77
3 686 400 9 600 24 0.00% 19.53
20 000 000 9 600 130 0.16% 19.53
32 768 000 9 600 213 0.16% 19.53
40 000 000 9 600 260 0.16% 19.53
3 686 400 2 400 96 0.00% 78.13
20 000 000 2 400 521 0.03% 78.13
32 768 000 2 400 853 0.04% 78.13
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31.7.5.3IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the
value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting
down at the Master Clock ( MCK) speed. If a rising edge is detected on the RXD pin, the cou nter stops and is
reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven
low during one bit time.
Figure 31-25 illus trates the operations of the IrDA demodulator.
Figure 31-25. IrDA Demodulator Operations
The program m ed valu e in the U S_I F re gister must always mee t th e follo win g crite ria:
TMCK * (IRDA_FILTER + 3) < 1.41 us
As the IrDA mode u ses the same lo gic as the ISO7 816 , no te that the FI_DI_RATIO field in US_FIDI must be set to
a value higher than 0 in order to assure IrDA communications operate correctly.
MCK
RXD
Receiver
Input
Pulse
Rejected
65432 6 1
65432 0
Pulse
Accepted
Counter
Value
621
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31.7.6 RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in asynchronou s or synchronou s mode an d configura tion of all the parameters is possible. The
difference is that the RTS pin is driven high when the tra nsmitter is operating. The behavior of the RTS pin is
controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-26.
Figure 31-26. Typical Connection to a RS485 Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mo de Registe r (US_MR) to th e
value 0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RT S pin rem ains hi gh wh en a timeg uar d is
programmed so that the line can remain driven after the last character completion. Figure 31-27 gives an example
of the RTS waveform during a character transmission when the timeguard is enabled.
Figure 31-27. Examp le of RTS Drive with Timegu ard
USART
RTS
TXD
RXD
Differential
Bus
D0 D1 D2 D3D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
TG = 4
Write
US_THR
TXRDY
TXEMPTY
RTS
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31.7.7 SPI Mode
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with
external devices in Master or Slave Mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one
master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single
Master Protocol, where one CPU is always the master while all of the others are always slaves.) However, only
one slave may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can
address only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of
the slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The
master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is
transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
31.7.7.1Modes of Operation
The USART can operate in SPI Master Mode or in SPI Slave Mode.
Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the Mode Register. In
this case the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TX D
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is prog rammed by writing to 0xF the USART_MODE field in the Mode Register. In
this case the SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TX D
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid u npredicted behavior, any ch ange of the SPI Mode mu st be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset).
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31.7.7.2Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See “Baud Rate
in Synchronou s Mo d e or SPI Mod e” on pag e 60 4. Howeve r, th er e ar e so me res tr ictio ns:
In SPI Master Mode:
The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to “1” in the
Mode Register (US_MR), in order to generate correctly the serial clock on the SCK pin.
To obta in correct behavior of the rece iver and the tran smitter, the value programmed in CD must be superior
or equal to 6.
If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a
50:50 mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode
Register (US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided
directly by the signal on the USART SCK pin.
To obt ain co rrect behavio r of th e receiver and the transmitter, the external clock (SCK) frequ ency must be at
least 6 times lower than the system clock.
31.7.7.3Data Transfer
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the M ode Regis ter (US_MR) . The 9
bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in
SPI Mode (Master or Slave).
Four combinations of polarity and phase ar e available for da ta transfers. T he clock polarity is pr ogrammed with the
CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters
determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has
two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a
master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed
in different configurations, the master must reconfigure itself each time it needs to communicate with a different
slave.
Table 31-14. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310
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Figure 31-28. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 31-29. SPI Transfer Format (CPHA=0, 8 bits per transfer)
31.7.7.4Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 606.
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
12345 786
MISO
SPI Master ->RXD
SPI Slave -> TXD
SCK
(CPOL = 0)
SCK
(CPOL = 1)
12345 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6
625
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31.7.7.5Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for
transmitting a character can be added when the USART is configured in SPI master mode. In the USART_MR
register, the value configured on INACK field can prevent any character transmission (even if US_THR has been
written) while the receiver side is not ready (character not read). When WRDBT equals 0, the character is
transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter waits for the receiver holding
register to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow
(character loss) on the receiver side.
The transmitter reports two status bi ts in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready),
which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR
have been processed. When the current character processing is completed, the last character written in US_THR
is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent wh ile the Tran sm it Holding Register (US_THR)
is empty, the UNRE (Underrun Error) bit is set. The TXD tr ansmission line stays at high level d uring all this time.
The UNRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit ( Time bit) be fore the tr ansmission of
the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS)
is always released between each character transmission and a minimum delay of 3 Tbits always inserted.
However, in order to address slave devices supporting the CSAAT mode (Chip Select Active Afte r Transfer), the
slave select line (NSS) can be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1.
The slave select line (NSS) can be released at high level only by writing the Control Register (US_CR) with the
RTSDIS bit to 1 (for example, when all data have been transfe rred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a
character transmission but only a low level. However, this low level must be present on the slave select line (NSS)
at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
31.7.7.6Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the
RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is tran sferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a
minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be
present on the slave select line (NSS) at least 1 Tbit be fore the first serial clock cycle corresponding to the MSB
bit.
31.7.7.7Receiver Timeout
Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is
impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
31.7.8 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows
on-board diagnostics. In the loopba ck mode the USART interface pins are disconnected or not and reconfigured
for loopback internally or externally.
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626
31.7.8.1Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 31-30. Normal Mode Configuration
31.7.8.2Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD
pin, as shown in Figure 31-31. Programming the transmitter has no effect on the TXD pin. The RXD pin is still
connected to the receiver input, thus the receiver remains active.
Figure 31-31. Automatic Echo Mode Configura ti on
31.7.8.3Local Loopback Mode
Local loopback mode con nects the outpu t of the tra nsmitte r d ire ctly to the in put o f the rece ive r, as shown in Figure
31-32. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is
continuously driven high, as in idle state.
Figure 31-32. Local Loopback Mode Configurat ion
31.7.8.4Remote Loopback Mode
Remote loopback mode di rectly connects the RXD pin to the TXD pin, as shown in Figure 31-33 . The transmitter
and the receiver are disabled and have no effect. This mode allows bit-by-bit r etransmission.
Figure 31-33. Remote Loopback Mode Configuration
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
1
Receiver
Transmitter
RXD
TXD
1
627
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31.7.9 Write Protection Registers
To prevent any single software error tha t may corrupt USART behavior, certain address spaces can be write-
protected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status
Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset by reading the USART Write Protect Mode Register (US_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“USART Mode Register”
“USART Baud Rate Generator Register”
“USART Receiver Time-out Register”
“USART Transmitter Timeguard Register”
“USART FI DI RATIO Register”
“USART IrDA FILTER Register”
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31.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
Table 31-1 5. Register Mapping
Offset Register Name Access Reset
0x0000 Control Register US_CR Write-only –
0x0004 Mode Register US_MR Read-write –
0x0008 Interrupt Enable Register US_IER Write-only –
0x000C Interrupt Disable Register US_IDR Write-only –
0x0010 Interrupt Mask Register US_IMR Read-only 0x0
0x0014 Channel Status Register US_CSR Read-only –
0x0018 Receiver Holding Register US_RHR Read-only 0x0
0x001C Transmitter Hold ing Register US_THR Write-only –
0x0020 Baud Rate Generator Register US_BRGR Read-write 0x0
0x0024 Receiver Time-out Registe r US_RTOR Read-write 0x0
0x0028 Transmitter Timegu ard Register US_TTGR Read-write 0x0
0x2C - 0x3C Reserved – – –
0x0040 FI DI Ratio Register US_FIDI Read-write 0x17 4
0x0044 Number of Errors Register US_NER Read-only –
0x0048 Reserved – – –
0x004C IrDA Filter Register US_IF Read-write 0x0
0x0050 Reserved – – –
0x0054 - 0x005C Reserved – – –
0x0060-0x00E0 Reserved – – –
0x00E4 Write Protect Mode Register US_WPMR Read-write 0x0
0x00E8 Write Protect Status Register US_WPSR Read-only 0x0
0x00EC - 0x00FC Reserved – – –
0x100 - 0x128 Reserved for PDC Registers – – –
629
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31.8.1 USART Control Register
Name: US_CR
Address: 0x40024000 (0), 0x40028000 (1), 0x4002C000 (2)
Access: Write-only
For SPI control, see “USART Contr ol Register (SPI_MODE)” on page 631.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE and RXBRK in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RTSDISRTSEN––
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
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• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a min imum of one character length and transmits a high level d uring 12-bit pe riods.
No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Rese t Ite r at io n s
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
631
SAM4N8/SAM4N16 [DATASHEET]
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31.8.2 USART Control Register (SPI_MODE)
Name: US_CR (SPI_MODE)
Address: 0x40024000 (0), 0x40028000 (1), 0x4002C000 (2)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits OVRE, UNRE in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RCSFCS––
15 14 13 12 11 10 9 8
–––––––RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
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• FCS: Force SPI Chip Select
– Applicable if USAR T operates in SPI Master Mode (USART_MODE = 0xE):
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
devices supporting the CSAAT Mode (Chip Select Active After Transfer).
• RCS: Release SPI Chip Select
– Applicable if USAR T operates in SPI Master Mode (USART_MODE = 0xE):
RCS = 0: No effect.
RCS = 1: Releases the Slave Sele ct Lin e NSS (RTS pin ).
633
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31.8.3 USART Mode Register
Name: US_MR
Address: 0x40024004 (0), 0x40028004 (1), 0x4002C004 (2)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
For SPI configuration, see “USART Mode Register (SPI_MODE)” on page 636 .
• USART_MODE: USART Mode of Operation
The PDC transfers are supported in all USART Mode of Operation.
• USCLKS: Clock Selection
• CHRL: Character Le ngth.
31 30 29 28 27 26 25 24
– – – FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
INVDATA – DSNACK INACK OVER CLKO MODE9 MSBF
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC
76543210
CHRL USCLKS USART_MODE
Value Name Description
0x0 NORMAL Normal mode
0x1 RS485 RS485
0x2 HW_HANDSHAKING Hardware Handshaking
0x4 IS07816_T_0 IS07816 Protocol: T = 0
0x6 IS07816_T_1 IS07816 Protocol: T = 1
0x8 IRDA IrDA
0xE SPI_MASTER SPI Master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Master Clock MCK is selected
1 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected
3 SCK Serial Clock SLK is selected
Value Name Description
0 5_BIT Ch aracter length is 5 bits
1 6_BIT Ch aracter length is 6 bits
2 7_BIT Ch aracter length is 7 bits
3 8_BIT Ch aracter length is 8 bits
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634
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
•PAR: Parity Type
• NBSTOP: Number of Stop Bits
• CHMODE: Channel Mode
•MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
Value Name Description
0 EVEN Even parity
1 ODD Odd parity
2 SPACE Parity forced to 0 (Space)
3 MARK Parity forced to 1 (Mark)
4NONo parity
6 MULTIDROP Multidrop mode
Value Name Description
0 1_BIT 1 stop bit
1 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 2_BIT 2 stop bits
Value Name Description
0 NORMAL Normal Mode
1 AUTOMATIC Auto matic Echo. Receiver input is connected to the TXD pin.
2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input.
3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
635
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• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• INVDATA: Inverted Data
0: The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR
is the same as RXD line. Normal mode of operation.
1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR reg-
ister or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted
Mode of operation, useful for contactless card application. To be used with configuration bit MSBF.
• MAX_ITERATION: Maximum Number of Automatic Iteration
0 - 7: Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
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636
31.8.4 USART Mode Register (SPI_MODE)
Name: US_MR (SPI_MODE)
Address: 0x40024004 (0), 0x40028004 (1), 0x4002C004 (2)
Access: Read-write
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• USART_MODE: USART Mode of Operation
• USCLKS: Clock Selection
• CHRL: Character Le ngth.
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which e dge of SPCK causes data to change a nd which edge causes da ta to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––WRDBT–––CPOL
15 14 13 12 11 10 9 8
–––––––CPHA
76543210
CHRL USCLKS USART_MODE
Value Name Description
0xE SPI_MASTER SPI Master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Master Clock MCK is selected
1 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected
3 SCK Serial Clock SLK is selected
Value Name Description
3 8_BIT Ch aracter length is 8 bits
637
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• CHMODE: Channel Mode
• CPOL: SPI Clock Polarity
– Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to prod uce the requir ed
clock/data relationship between master and slave devices.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR register (assuming TXRDY was set).
1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receiver Holding Reg-
ister has been read).
Value Name Description
0 NORMAL Normal Mode
1 AUTOMATIC Auto matic Echo. Receiver input is connected to the TXD pin.
2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input.
3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
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638
31.8.5 USART Interrupt Enable Register
Name: US_IER
Address: 0x40024008 (0), 0x40028008 (1), 0x4002C008 (2)
Access: Write-only
For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 639.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• ENDRX: End of Receive Transfer Interrupt Enable (availa ble in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Enable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Max number of Repetitions Reached Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Enable (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Enable (available in all USART modes of operation)
• NACK: Non AcknowledgeInterrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
0: No effect
1: Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSIC– – –
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
639
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31.8.6 USART Interrupt Enable Register (SPI_MODE)
Name: US_IER (SPI_MODE)
Address: 0x40024008 (0), 0x40028008 (1), 0x4002C008 (2)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• UNRE: SPI Underrun Error Interrupt Enable
0: No effect
1: Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
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640
31.8.7 USART Interrupt Disable Register
Name: US_IDR
Address: 0x4002400C (0), 0x4002800C (1), 0x4002C00C (2)
Access: Write-only
For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 641.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Disable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Disable (available in all USART modes of operation)
• NACK: Non AcknowledgeInterrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
0: No effect
1: Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSIC– – –
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
641
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31.8.8 USART Interrupt Disable Register (SPI_MODE)
Name: US_IDR (SPI_MODE)
Address: 0x4002400C (0), 0x4002800C (1), 0x4002C00C (2)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• UNRE: SPI Underrun Error Interrupt Disable
0: No effect
1: Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4N8/SAM4N16 [DATASHEET]
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642
31.8.9 USART Interrupt Mask Register
Name: US_IMR
Address: 0x40024010 (0), 0x40028010 (1), 0x4002C010 (2)
Access: Read-only
For SPI specific configuration, see “USART Interrupt Mask Regist er (SPI_MODE)” on page 643.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Transfer Interrupt Mask (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Mask (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Max Number of Repetitions Reached Interrupt Mask
• TXBUFE: Buffer Empty Interrupt Mask (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Mask (available in all USART modes of operation)
• NACK: Non AcknowledgeInterrupt Mask
• CTSIC: Clear to Send Input Change Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSIC– – –
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
643
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.10 USART Interrupt Mask Register (SPI_MODE)
Name: US_IMR (SPI_MODE)
Address: 0x40024010 (0), 0x40028010 (1), 0x4002C010 (2)
Access: Read-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• UNRE: SPI Underrun Error Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
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644
31.8.11 USART Channel Status Register
Name: US_CSR
Address: 0x40024014 (0), 0x40028014 (1), 0x4002C014 (2)
Access: Read-only
For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 646.
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has
been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transfer signal from the Transmit PDC channel is inactive.
1: The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurre d sin ce the las t R STSTA.
1: At least one overrun error has occurred since the last RSTSTA.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CTS – – – CTSIC – – –
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
645
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
•FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTT O in US_CR) or the Ti me- out Regi ster is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max Number of Repetitions Reached
0: Maximum number of repetitions has not been reached since the last RSTSTA.
1: Maximum number of repetitions has been reached since the last RSTSTA.
• TXBUFE: Transmission Buffer Empty
0: The signal Buffer Empty from the Transmit PDC channel is inactive.
1: The signal Buffer Empty from the Transmit PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Receive PDC channel is inactive.
1: The signal Buffer Full from the Receive PDC channel is active.
• NACK: Non AcknowledgeInterrupt
0: Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
• CTSIC: Clear to Send Input Change Flag
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
• CTS: Image of CTS Input
0: CTS is set to 0.
1: CTS is set to 1.
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31.8.12 USART Channel Status Register (SPI_MODE)
Name: US_CSR (SPI_MODE)
Address: 0x40024014 (0), 0x40028014 (1), 0x4002C014 (2)
Access: Read-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 633.
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As
soon as the tran sm itte r is enab led , T XRDY be co me s 1.
1: There is no character in the US_THR.
• OVRE: Overrun Error
0: No overrun error has occurre d sin ce the las t R STSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• UNRE: Underrun Error
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
647
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.13 USART Receive Holding Register
Name: US_RHR
Address: 0x40024018 (0), 0x40028018 (1), 0x4002C018 (2)
Access: Read-only
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last Character received is a Data.
1: Last Character received is a Command.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXSYNH ––––––RXCHR
76543210
RXCHR
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648
31.8.14 USART Transmit Holding Register
Name: US_THR
Address: 0x4002401C (0), 0x4002801C (1), 0x4002C01C (2)
Access: Write-only
• TXCHR: Chara cte r to be Transmi tt ed
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be Transmitted
0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXSYNH ––––––TXCHR
76543210
TXCHR
649
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.15 USART Baud Rate Generator Register
Name: US_BRGR
Address: 0x40024020 (0), 0x40028020 (1), 0x4002C020 (2)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• CD: Clock Divider
• FP: Fractional Part
0: Fractional divider is disabled.
1 - 7: Baud rate resolution, defined by FP x 1/8.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– FP
15 14 13 12 11 10 9 8
CD
76543210
CD
CD
USART_MODE ≠ ISO7816
USART_MODE =
ISO7816
SYNC = 0
SYNC = 1
or
USART_MODE = SPI
(Master or Slave)
OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
1 to 65535 Baud Rate =
Selected Clock/(16*CD) Baud Rate =
Selected Clock/(8*CD) Baud Rate =
Selected Clock /CD Baud Rate = Selected
Clock/(FI_DI_RATIO*CD)
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650
31.8.16 USART Receiver Time-out Register
Name: US_RTOR
Address: 0x40024024 (0), 0x40028024 (1), 0x4002C024 (2)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• TO: Time-out Value
0: The Receiver Time-out is disabled.
1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
3130292827 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TO
76543210
TO
651
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.17 USART Transmitter Timeguard Regi ster
Name: US_TTGR
Address: 0x40024028 (0), 0x40028028 (1), 0x4002C028 (2)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• TG: Timeguard Value
0: The Transmitter Timeguard is disabled.
1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TG
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31.8.18 USART FI DI RATIO Register
Name: US_FIDI
Address: 0x40024040 (0), 0x40028040 (1), 0x4002C040 (2)
Access: Read-write
Reset Value: 0x174
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
FI_DI_RATIO
76543210
FI_DI_RATIO
653
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.19 USART Number of Errors Register
Name: US_NER
Address: 0x40024044 (0), 0x40028044 (1), 0x4002C044 (2)
Access: Read-only
This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register” on page 633.
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
NB_ERRORS
SAM4N8/SAM4N16 [DATASHEET]
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654
31.8.20 USART IrDA FILTER Register
Name: US_IF
Address: 0x4002404C (0), 0x4002804C (1), 0x4002C04C (2)
Access: Read-write
This register is relevant only if USART_MODE=0x8 in “USART Mode Register” on page 633.
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 655.
• IRDA_FILTER: IrDA Filter
The IRDA_FIL TE R valu e m ust be defined to meet the following criteria:
TMCK * (IRDA_FILTER + 3) < 1.41 us
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IRDA_FILTER
655
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
31.8.21 USART Write Protect Mode Register
Name: US_WPMR
Address: 0x400240E4 (0), 0x400280E4 (1), 0x4002C0E4 (2)
Access: Read-write
Reset: See Table 31-1 5
• WPEN: Write Protec t En ab le
0 = Disables the Write Protect if WPKEY corresponds to 0x 555341 (“USA” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
Protects the reg ist er s:
“USART Mode Register” on page 633
“USART Baud Rate Generator Register” on page 649
“USART Receiver Time-out Register” on page 650
“USART Transmitter Timeguard Register” on page 651
“USART FI DI RATIO Register” on page 652
“USART IrDA FILTER Register” on page 654
• WPKEY: Write Protect KEY.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
———————WPEN
Value Name Description
0x555341 PASSWD Writi n g an y other value in this field aborts the write operation of the WPEN bit. Always reads
as 0.
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656
31.8.22 USART Write Prot ect Status Register
Name: US_WPSR
Address: 0x400240E8 (0), 0x400280E8 (1), 0x4002C0E8 (2)
Access: Read-only
Reset: See Table 31-1 5
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorize d
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Note: Reading US_WPSR automa tically clears all fields.
31 30 29 28 27 26 25 24
————————
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
———————WPVS
657
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32. Timer Counter (TC)
32.1 Description
A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is
device-specific.
Each TC channel can be independently programmed to perform a wide range of functions including frequency
measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals
which can be configured by the user. Each cha nnel drive s an internal inter rupt signal which can be progra mmed to
generate processor interrupts.
The TC embeds a quadrature decoder (QDEC) connected in front of the timers and driven by TIOA0, TIOB0 and
TIOB1 inputs. When enabled, the QDEC performs the input lines filtering, decoding of quadrature signals and
connects to the timers/counters in order to read the positi on an d spee d of th e mo to r th ro ug h the us er interfa c e .
The TC block has two global registers which act upon all TC channels:
Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction
Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be
chained
32.2 Embedded Characteristics
Total number of TC channels: 6
TC channel size: 16-bit
Wide range of functions including:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Up/down capabilities
Quadrature decoder
2-bit gray up/down count for stepper motor
Each channel is user-configurable and contains:
Three exte rn al cloc k inp uts
Five Internal clock inputs
Two multi-purpose input/output signals acting as trigger event
Internal interrupt signal
Read of the Capt ur e re gis te rs by the PDC
Compare event fault generation for PWM
Register Write Protection
SAM4N8/SAM4N16 [DATASHEET]
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32.3 Block Diagram
Note: 1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), SLCK input is equivalent
to Peripheral Clock.
Figure 32-1. Timer Counter Block Diagram
Note: The QDEC connections are detailed in Figure 32-1 6.
Table 32-1. Timer Counter Clock Assignment
Name Definition
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5 SLCK
Timer/Counter
Channel 0
Timer/Counter
Channel 1
Timer/Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TIMER_CLOCK1
FAULT
PWM
659
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.4 Pin Name List
Table 32-2. Signal Name Description
Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOB Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INT Interrupt Signal Output (internal signal)
SYNC Synchronization Input Signal (from configuration register)
Table 32-3. TC Pin List
Pin Name Description Type
TCLK0–TCLK2 Exte r nal Clock Input Input
TIOA0–TIOA2 I/O Line A I/O
TIOB0–TIOB2 I/O Line B I/O
SAM4N8/SAM4N16 [DATASHEET]
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660
32.5 Product Dependencies
32.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the TC pins to thei r peripheral functions.
32.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Timer Counter clock of each channel.
32.5.3 Interrupt Sources
The TC has an interrupt line per channel connected to the interrupt controller. Handling the TC interrupt requires
programming the interrupt controller before configuring the TC .
32.5.4 Fault Output
The TC has the FAULT output internally connected to the fault input of PWM. Refer to Sectio n 32.6.17 “Fault
Mode” and to the implementatio n of the Puls e Wid th M odula tio n (PW M) in this pr od u ct.
Table 32-4. I/O Lines
Instance Signal I/O Line Peripheral
TC0 TCLK0 PA4 B
TC0 TCLK1 PA28 B
TC0 TCLK2 PA29 B
TC0 TIOA0 PA0 B
TC0 TIOA1 PA15 B
TC0 TIOA2 PA26 B
TC0 TIOB0 PA1 B
TC0 TIOB1 PA16 B
TC0 TIOB2 PA27 B
TC1 TCLK3 PC25 B
TC1 TCLK4 PC28 B
TC1 TCLK5 PC31 B
TC1 TIOA3 PC23 B
TC1 TIOA4 PC26 B
TC1 TIOA5 PC29 B
TC1 TIOB3 PC24 B
TC1 TIOB4 PC27 B
TC1 TIOB5 PC30 B
Table 32-5. Peripheral IDs
Instance ID
TC0 23
TC1 24
661
SAM4N8/SAM4N16 [DATASHEET]
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32.6 Functional Description
32.6.1 Description
All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled.
The registers for channel programming are listed in Table 32-6, “Register Mapping,”.
32.6.2 16-bit Counter
Each 16-bit channel is org ani ze d a round a 16 -bit co un ter. The value of the counter is incr eme nted at each po sitive
edge of the selected clock. When the counter has reached the value 216-1 and passes to ze ro , an ove rflow occurs
and the COVFS bit in the TC Status Register (TC_SR) is set.
The current value of the counter is accessible in real time by reading the TC Counter Value Register ( TC_CV). The
counter can be reset by a trigge r. In this case, the counter value passes to zero on the next valid edge of the
selected clock.
32.6.3 Clock Selection
At block level, input clock signals of each ch annel can ei ther be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC
Block Mode Register (TC_BMR). See Figure 32-2.
Each channel can independently select an internal or external clock source for its counter:
External clock si gn als (1): XC0, XC1 or XC2
Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, SLCK
This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR).
The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges
of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the
TC_CMR defines this signal (none, XC0, XC1, XC2). See Figure 32-3.
Note: 1. In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral clock
period. The external clock fre quency must be at least 2.5 times lower than the peripheral clock.
SAM4N8/SAM4N16 [DATASHEET]
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662
Figure 32-2. Clock Chaining Selection
Figure 32-3. Clock Selection
Timer/Counter
Channel 0
SYNC
TC0XC0S
TIOA0
TIOB0
XC0
XC1 = TCLK1
XC2 = TCLK2
TCLK0
TIOA1
TIOA2
Timer/Counter
Channel 1
SYNC
TC1XC1S
TIOA1
TIOB1
XC0 = TCLK0
XC1
XC2 = TCLK2
TCLK1
TIOA0
TIOA2
Timer/Counter
Channel 2
SYNC
TC2XC2S
TIOA2
TIOB2
XC0 = TCLK0
XC1 = TCLK1
XC2
TCLK2
TIOA0
TIOA1
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
Synchronous
Edge Detection
BURST
Peripheral Clock
1
Selected
Clock
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32.6.4 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped.
See Figure 32-4.
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC
Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is
set to 1 in the TC_CMR. In W avefo rm mode, it can be disabled by an RC Comp are event if CPCDIS is set to
1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the
TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts
the clock. The clock can be stopped by an RB load event in Capture mode (LDBSTOP = 1 in TC_CMR) or
an RC compare event in Waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands
are effective only if the clock is enabled.
Figure 32-4. Clock Control
32.6.5 Operating Modes
Each channel can operate independently in two different modes:
Capture mode provides measurement on signals.
Waveform mode provides wave generation.
The TC operating mode is programmed with the WAVE bit in the TC_CMR.
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an outp ut if it is not selected to be the
external trigger.
32.6.6 Trigger
A trigger resets the coun ter and star ts the counter clock. Three types of triggers are common to both modes, and a
fourth external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This
means that the counte r value ca n be read differ ently from zer o just after a trigger, especially when a low frequen cy
signal is selected as the clock.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event Disable
Event
Counter
Clock
Selected
Clock Trigger
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The following triggers are common to both modes:
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has th e same effect as
a software trigger. The SYNC signals of all channels are asserted simult aneously by writing TC_BCR (Block
Control) with SYNC set.
Compar e RC Trigger: RC is implemented in each channel an d can pr ovide a trigg er wh en th e cou nter value
matches the RC value if CPCTRG is set in the TC_CMR.
The channel can also b e configured to ha ve an external trigger . In Capture mode, the external trigger signal can be
selected between TIOA and TIOB. In Wav eform mode, an external event can be programmed on one of the
following signals: TIOB, XC0, XC1 or XC2. This external event can then be programm ed to perform a trigger by
setting bit ENETRG in the TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the peripheral clock period in order to
be detected.
32.6.7 Capture Mode
Capture mode is entered by clearing the WAVE bit in the TC_CMR.
Capture mode allows the TC channel to perform measu rements such as pulse timing, frequency, period, duty
cycle and phase on TIOA and TIOB signals which are considered as inputs.
Figure 32-6 shows the configuration of the TC channel when programmed in Capture mode .
32.6.8 Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. They can be load ed wit h the counte r valu e whe n a
programmable event occurs on the signal TIOA.
The LDRA field in the TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB field
defines the TIOA selected edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of
RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR.
In this case, the old value is overwritten.
32.6.9 Transfer with PDC
The PDC can only perform access from timer to system memory.
Figure 32-5 illustrates how TC_RA and TC_RB can be loaded in the system memory without CPU intervention.
665
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Figure 32-5. Example of Transfer with PDC
32.6.10 Trigger Conditions
In addition to the SYNC signal, the so ftware trigger and t he RC compare trigger, an exter nal trigger can be defined.
The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger . The External Trigger
Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to
generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
TIOB
TIOA
RA
RB
Transfer to System Memory
Peripheral trigger
RA RB RA RB
T1,T2,T3,T4 = System Bus load dependent (tmin = 8 peripheral clocks)
T1 T2 T3 T4
ETRGEDG = 1, LDRA = 1, LDRB = 2, ABETRG = 0
ETRGEDG = 3, LDRA = 3, LDRB = 0, ABETRG = 0
TIOB
TIOA
RA
Transfer to System Memory
Peripheral trigger
RA RA
T1,T2,T3,T4 = System Bus load dependent (tmin = 8 peripheral clocks)
T1 T2 T3 T4
RA RA
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Figure 32-6. Capture Mode
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A Capture
Register B Compare RC =
Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC1_IMR
Trig
LDRBS
LDRAS
ETRGS
TC1_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is Loaded If RA is Loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK OVF
RESET
Timer/Counter Channel
Peripheral Clock
Synchronous
Edge Detection
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32.6.11 Waveform Mode
Waveform mode is entered by setting the TC_CMRx.WAVE bit.
In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and
independently progra mmable duty cycles, or generates different types of one-shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event
(EEVT parameter in TC_CMR).
Figure 32-7 shows the configuration of the TC channel when programmed in Waveform operating mode.
32.6.12 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR, the behavior of TC_CV varies.
With any selection, TC_RA, TC_RB and TC_RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly
configured) and RC Compare is used to control TIOA and/or TIOB outputs.
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Figure 32-7. Wav eform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
TC1_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC1_SR
CPCS
CPBS
CLK OVF
RESET
Output Controller Output Controller
INT
1
Edge
Detector
Timer/Counter Channel
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
WAVSEL
Peripheral Clock
Synchronous
Edge Detection
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32.6.12.1 WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 has been reached, the valu e
of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 32-8.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger
may occur at any time. See Figure 32-9.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare
can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in
TC_CMR).
Figure 32-8. WAVSEL = 00 without trigger
Figure 32-9. WAVSEL = 00 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
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32.6.12.2 WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a
RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 32-10.
It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are
programmed correctly. See Figure 32-11.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disabl e the counter clock
(CPCDIS = 1 in TC_CMR).
Figure 32-10. WAVSEL = 10 without Trigger
Figure 32-11. WAVSEL = 10 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
Waveform Examples
2n-1
(n = counter size)
Time
Counter Value
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with RC
Waveform Examples
Counter cleared by trigger
2n-1
(n = counter size)
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32.6.12.3 WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1 . Once 216-1 is reached, the value of
TC_CV is decremented to 0, then re-incremented to 216-1 and so on. See Figure 32-12.
A trigger such as an externa l event or a software trigger can mod ify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 32-13.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock
(CPCDIS = 1).
Figure 32-12. WAVSEL = 01 without Trigger
Figure 32-13. WAVSEL = 01 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
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32.6.12.4 WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV
is decremented to 0, then re-incremented to RC and so on. See Figure 32-14.
A trigger such as an externa l event or a software trigger can mod ify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 32-15.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 32-14. WAVSEL = 11 without Trigger
Figure 32-15. WAVSEL = 11 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with RC
Waveform Examples
2n-1
(n = counter size)
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with RC
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
2n-1
(n = counter size)
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32.6.13 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The
external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge
for each of the possible external triggers (r ising, falling or both) . If EEVTEDG is cleared (none), no external event
is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare
register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only
generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR.
As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can
also be used as a trigger depending on the parameter WAVSEL.
32.6.14 Output Controller
The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used
only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare
controls TIOA and RB co mpare contro ls TIOB. Each of th ese events can be programmed to set, clear or toggle th e
output as defined in the corresponding parameter in TC_CMR.
32.6.15 Quadrature Decoder
32.6.15.1 Description
The quadrature decoder (QDEC) is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of
channel 0 and 1. Ch annel 2 can be used as a time base in ca se of speed measurement req uirements (refer to
Figure 32-16).
When writing a 0 to bit QDEN of the TC_BMR, the QDEC is bypassed and the IO pins are directly routed to the
timer counte r fun ct i on . See
TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the
shaft of the off-chip motor.
A third signal fr om the rotar y sensor can be processed th rough pin TIOB1 and is typically dedicated to be driven by
an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA,
PHB.
Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as
soon as the QDEC is enabled.
Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB
input signa ls giving a high acc uracy on motor posit ion whereas channel 1 accumulates the index pulses of the
sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on
motion system position.
In Speed mode, position cannot be measured but revolution can be measured.
Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity,
phase definition and other factors are configurable.
Interruptions can be generated on different events.
A compare function (using TC _RC) is available on channel 0 (speed/position) or channel 1 (rotation) and can
generate an interrupt by means of the CPCS flag in the TC_SRx.
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Figure 32-16. Predefined Connection of the Quadrature Decoder with Timer Counters
32.6.15.2 Input Pre-processing
Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase
definition followed by configurable digital filtering.
Each input can be negated and swapping PHA, PHB is also configurable.
The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid.
When the filter is active, pulses with a duration lower than MAXFILT +1 ×tperipheral clock ns are not passed to down-
stream logic.
Timer/Counter
Channel 0
1
XC0
TIOA
TIOB
Timer/Counter
Channel 1
1
XC0
TIOB
QDEN
Timer/Counter
Channel 2
1
TIOB0
XC0
1
1
SPEEDEN
1
XC0
Quadrature
Decoder
(Filter + Edge
Detect + QD)
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
TIOB1
TIOA0
Index
Speed/Position
Rotation
Speed Time Base
Reset pulse
Direction
PHEdges QDEN
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Figure 32-17. Input Stage
Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate
contamination on the optical or magnetic disk of the rotary sensor.
Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if
vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the
beginning of one of the reflective or ma gnetic bars on the rotary sensor disk is aligned with the light or magnetic
(Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration.
1
1
1
MAXFILT
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
INVA
1
INVB
1
INVIDX
SWAP
1
IDXPHB
Filter
Filter
Filter
1
Direction
and
Edge
Detection
IDX
PHedge
DIR
Input Pre-Processing
MAXFILT > 0
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Figure 32-18. Filtering Examples
PHA,B
Filter Out
Peripheral Clock MAXFILT = 2
particulate contamination
PHA
PHB
motor shaft stopped in such a position that
rotary sensor cell is aligned with an edge of the disk
rotation
PHA
PHB
PHB Edge area due to system vibration
Resulting PHA, PHB electrical waveforms
PHA
Optical/Magnetic disk strips
stop
PHB
mechanical shock on system
vibration
stop
PHA, PHB electrical waveforms after filtering
PHA
PHB
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32.6.15.3 Direction Status and Change Detection
After filtering, the quadratur e signal s are analyzed to extract the r otatio n di rectio n a nd ed ge s of the two qua dr atur e
signals detected in order to be counted by timer/counter logic downstream.
The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status
depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
Any change in rotation direction is reported in the TC_QISR and can generate an interrupt.
The direction change co ndition is r epor ted as soon as two con secutive edg es on a phase sig nal have sam pled th e
same value on th e other phase sign al a nd the r e is an edge on the other signal. The two consecutive edges of one
phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the
reason that particulate contamination may mask one or more reflective bars o n the optical or magnetic disk of the
sensor. Refer to Figure 32-19 for waveforms.
Figure 32-19. Rotation Change Detec tion
The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case, the DIR flag report
must not be used.
A quadrature error is also reported by the Q DEC via the QERR flag in the TC_QISR. This error is reported if the
time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value is
PHA
PHB
Direction Change under normal conditions
DIR
DIRCHG
change condition
Report Time
No direction change due to particulate contamination masking a reflective bar
PHA
PHB
DIR
DIRCHG
spurious change condition (if detected in a simple way)
same phase
missing pulse
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configurable and corresp onds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have
two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation.
Figure 32-20. Quadr ature Error Detection
MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor
and rotation speed to be achieved.
32.6.15.4 Position and Rotation Measurement
When the POSEN bit is set in the TC_BMR, the motor axis position is processe d on channel 0 (by means of the
PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is
provided on the TIOB1 input. The position measu rement can be read in the TC_CV0 re gister and the rotation
measurem e nt can be rea d in the TC _CV1 register.
Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as
the External Trigger Edge ( TC_CMR.ETRGEDG = 0x01) and ‘TIOA’ must be selected as the External T rigger
(TC_CMR.ABETRG = 0x1).
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0
register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Peripheral Clock MAXFILT = 2
PHA
PHB
A
bnormally formatted optical disk strips (theoretical view)
PHA
PHB
strip edge inaccurary due to disk etching/printing process
resulting PHA, PHB electrical waveforms
PHA
PHB
Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
QERR
duration < MAXFILT
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Depending on the q uadrature signals, the directio n is decoded and allows to count up or down in timer/counter
channels 0 and 1. The direction status is reported on TC_QISR.
32.6.15.5 Speed Measurement
When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in
Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter
by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA outp u t.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set.
Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be
configured at 1 to select TIOA as a trigger for this channel.
EDGTRG must be set to 0x01, to clear the counter on a rising ed ge of the TIOA signal and fie ld LDRA must be set
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is
performed.
The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR.
The speed can be read on field RA in TC_RA0.
Channel 1 can still be used to count the number of revolutions of the motor.
32.6.16 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA,
TIOB outputs by means of the GCEN bit in TC_SMMRx.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx.
It is mandatory to configure the channel in Waveform mode in the TC_CMR.
The period of the counters can be programmed in TC_RCx.
Figure 32-21. 2-bit Gray Up/Down Counter
32.6.17 Fault Mode
At any time, the TC_RCx registers can be used to perform a comparison o n the respective cu rrent ch annel counte r
value (TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1.
Each source can be independently enabled/disabled in the TC_FMR.
TIOAx
TIOBx
DOWNx
TC_RCx
WAVEx = GCENx =1
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
680
This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act
immediately by using the FAULT output.
Figure 32-22. Fault Output Gener atio n
32.6.18 Register Write Protection
To prevent any single software error from corrupting TC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR).
The Timer Counter clock of the first channel must be enabled to access TC_WPMR.
TC_SR0 flag CPCS
TC_FMR / ENCF0
FAULT (to PWM input)
OR
AND
AND
TC_SR1 flag CPCS
TC_FMR / ENCF1
The following registers can be write-protected:
TC Block Mode Register
TC Channel Mode Register: Capture Mode
TC Channel Mode Register: Waveform Mode
TC Fault Mode Register
TC Stepper Motor Mode Register
TC Register A
TC Register B
TC Register C
681
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7 Timer Counter (TC) User Interface
Notes: 1. Channel index range s from 0 to 2.
2. Read-only if TC_CMRx.WAVE = 0
Table 32-6 . Register Mapping
Offset(1) Register Name Access Reset
0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only –
0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0
0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read/Write 0
0x00 + channel * 0x40 + 0x0C Reserved – – –
0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0
0x00 + channel * 0x40 + 0x14 Register A TC_RA Read/Write(2) 0
0x00 + channel * 0x40 + 0x18 Register B TC_RB Read/Write(2) 0
0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0
0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-o nly 0
0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only –
0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only –
0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0
0xC0 Block Control Register TC_BCR Write-only –
0xC4 Block Mo de Register TC_BMR Read/Write 0
0xC8 QDEC Interrupt Enable Register TC_QIER Write-only –
0xCC QDEC Interrupt Disable Register TC_QIDR Write-only –
0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0
0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0
0xD8 Fault Mode Register TC_FMR Read/Write 0
0xE4 Write Protection Mode Register TC_WPMR Read/Write 0
0xE8–0xFC Reserved – – –
0x100–0x1A4 Reserved for PDC Registers – – –
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
682
32.7.1 TC Channel Control Register
Name: TC_CCRx [x=0..2]
Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1],
0x40014080 (1)[2]
Access: Write-only
• CLKEN: Counter Clock Enable Command
0: No effect.
1: Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0: No effect.
1: Disables the clock.
• SWTRG: Software Trigger Command
0: No effect.
1: A software trigger is performed: the counter is reset and the clock is started.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––SWTRGCLKDISCLKEN
683
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.2 TC Channel Mode Re gister: Capture Mode
Name: TC_CMRx [x=0..2] (CAPTURE_MODE)
Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0: Counter clock is not stopped when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: internal SLCK clock sign al (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
684
• LDBDIS: Counter Clock Disable with RB Loading
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0: TIOB is used as an external trigger.
1: TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0: RC Compare has no effect on the counter and its clock.
1: RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0: Capture mode is enabled.
1: Capture mode is disabled (Waveform mode is enabled).
• LDRA: RA Loading Edge Selection
• LDRB: RB Loading Edge Selection
Value Name Description
0 NONE The clock is not gated by an external signal.
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING F alling edge of TIOA
3 EDGE Each edge of TIOA
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING F alling edge of TIOA
3 EDGE Each edge of TIOA
685
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.3 TC Channel Mode Re gister: Wavef orm Mode
Name: TC_CMRx [x=0..2] (WAVEFORM_MODE)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare
0: Counter clock is not stopped when counter reaches RC.
1: Counter clock is stopped when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: in ternal MCK/2 clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: in ternal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: in ternal SLCK clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
686
• CPCDIS: Counter Clock Disable with RC Compare
0: Counter clock is not disabled when counter reaches RC.
1: Counter clock is disabled when counter reaches RC.
• EEVTEDG: External Event Edge Selection
• EEVT: External Event Selection
Signal selected as external event.
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and
subsequently no IRQs.
• ENETRG: External Event Trigger Enable
0: The external event has no effect on the counter and its clock.
1: The external event resets the counter and starts the counter clock.
Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOA output and TIOB if not used as
input (trigger event input or other input used).
• WAVSEL: Waveform Selection
• WAVE: Waveform Mode
0: Waveform mode is disabled (Capture mode is enabled).
1: Waveform mode is enabled.
• ACPA: RA Compare Effect on TIOA
Value Name Description
0 NONE None
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge
Value Name Description TIOB Direction
0 TIOB TIOB(1) Input
1 XC0 XC0 Output
2 XC1 XC1 Output
3 XC2 XC2 Output
Value Name Description
0 UP UP mode without automatic trigger on RC Compare
1 UPDOWN UPDOWN mode without automatic trigger on RC Compare
2 UP_RC UP mode with automatic trigger on RC Compare
3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
687
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• ACPC: RC Compare Effect on TIOA
• AEEVT: External Event Effect on TIOA
• ASWTRG: Software Trigger Effect on TIOA
• BCPB: RB Compare Effect on TIOB
• BCPC: RC Compare Effect on TIOB
• BEEVT: External Event Effect on TIOB
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
688
• BSWTRG: Software Trigger Effect on TIOB
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
689
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.4 TC Stepper Motor Mode Register
Name: TC_SMMRx [x=0..2]
Address: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],
0x40014088 (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• GCEN: Gray Count Enable
0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.
• DOWN: Down Count
0: Up counter.
1: Down counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––DOWNGCEN
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
690
32.7.5 TC Counter Value Register
Name: TC_CVx [x=0..2]
Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1],
0x40014090 (1)[2]
Access: Read-only
• CV: Counter Value
CV contains the cou n ter valu e in re al tim e.
IMPORTANT: For 16-bit channels, CV field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
76543210
CV
691
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.6 TC Register A
Name: TC_RAx [x=0..2]
Address: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1],
0x40014094 (1)[2]
Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RA: Regist er A
RA contains the Register A value in real time.
IMPORTANT: For 16-bit channels, RA field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
76543210
RA
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
692
32.7.7 TC Register B
Name: TC_RBx [x=0..2]
Address: 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1],
0x40014098 (1)[2]
Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RB: Regist er B
RB contains the Register B value in real time.
IMPORTANT: For 16-bit channels, RB field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
76543210
RB
693
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.8 TC Register C
Name: TC_RCx [x=0..2]
Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1],
0x4001409C (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RC: Regist er C
RC contains the Register C value in real time.
IMPORTANT: For 16-bit channels, RC field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
76543210
RC
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
694
32.7.9 TC Status Register
Name: TC_SRx [x=0..2]
Address: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1],
0x400140A0 (1)[2]
Access: Read-only
• COVFS: Counter Overflow Status (cleared on read)
0: No counter overflow has occurred since the last read of the Status Register.
1: A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status (cle ared on read)
0: Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-
tus Register, if TC_CMRx.WAVE = 0.
• CPAS: RA Compare Status (cleared on read)
0: RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPBS: RB Compare St atus (cleared on read)
0: RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPCS: RC Compare St atus (cleared on read)
0: RC Compare has not occurred since the last read of the Status Register.
1: RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status (cleared on read)
0: RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
• LDRBS: RB Loading Status (cleared on read)
0: RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––MTIOBMTIOACLKSTA
15 14 13 12 11 10 9 8
––––––RXBUFFENDRX
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
695
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• ETRGS: Exte rn al Trig g er Status (cleared on read)
0: External trigger has not occurred since the last read of the Status Register.
1: External trigger has occurred since the last read of the Status Register.
• ENDRX: End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)
0: The Receive Coun te r Re gist er has not reached 0 since the last write in TC_RCR(1) or TC_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in TC_RCR or TC_RNCR.
• RXBUFF: Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)
0: TC_RCR or TC_RNCR have a value other than 0.
1: Both TC_RCR and TC_RNCR have a value of 0.
Note: 1. TC_RCR and TC_RNCR are PDC registers.
• CLKSTA: Clock Enabling Status
0: Clock is disabled.
1: Clock is enabled.
• MTIOA: TIOA Mirror
0: TIOA is low. If TC_CMRx.WAVE = 0, this means that TIOA pin is low. If TC_CMRx.WAVE = 1, this means that TIOA is
driven low.
1: TIOA is high. If TC_CMRx.WAVE = 0, this means that TIOA pin is high. If TC_CMRx.WAVE = 1, this means that TIOA is
driven high.
• MTIOB: TIOB Mirror
0: TIOB is low. If TC_CMRx.WAVE = 0, this means that TIOB pin is low. If TC_CMRx.WAVE = 1, this means that TIOB is
driven low.
1: TIOB is high. If TC_CMRx.WAVE = 0, this means that TIOB pin is high. If TC_CMRx.WAVE = 1, this means that TIOB is
driven high.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
696
32.7.10 TC Interrupt Enable Register
Name: TC_IERx [x=0..2]
Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1],
0x400140A4 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0: No effect.
1: Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0: No effect.
1: Enables the RA Compare Interrupt.
• CPBS: RB Compare
0: No effect.
1: Enables the RB Compare Interrupt.
• CPCS: RC Compare
0: No effect.
1: Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Enables the RA Load Interrupt.
• LDRBS: RB Loading
0: No effect.
1: Enables the RB Load Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––RXBUFFENDRX
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
697
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• ETRGS: External Trigger
0: No effect.
1: Enables the External Trigger Interrupt.
• ENDRX: End of Receiver Transfer
0: No effect.
1: Enables the PDC Receive End of Transfer Interrupt.
• RXBUFF: Reception Buffer Full
0: No effect.
1: Enables the PDC Receive Buffer Full Interrupt.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
698
32.7.11 TC Interrupt Disable Register
Name: TC_IDRx [x=0..2]
Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1],
0x400140A8 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0: No effect.
1: Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Disables the Load Overrun Interrupt (if TC_CMRx.WAVE = 0).
• CPAS: RA Compare
0: No effect.
1: Disables the RA Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPBS: RB Compare
0: No effect.
1: Disables the RB Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPCS: RC Compare
0: No effect.
1: Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Disables the RA Load Interrupt (if TC_CMRx.WAVE = 0).
• LDRBS: RB Loading
0: No effect.
1: Disables the RB Load Interrupt (if TC_CMRx.WAVE = 0).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––RXBUFFENDRX
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
699
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• ETRGS: External Trigger
0: No effect.
1: Disables the External Trigger Interrupt.
• ENDRX: End of Receiver Transfer
0: No effect.
1: Disables the PDC Receive End of Transfer Interrupt.
• RXBUFF: Reception Buffer Full
0: No effect.
1: Disables the PDC Receive Buffer Full Interrupt.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
700
32.7.12 TC Interrupt Mask Register
Name: TC_IMRx [x=0..2]
Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1],
0x400140AC (1)[2]
Access: Read-only
• COVFS: Counter Overflow
0: The Counter Overflow Interrupt is disabled.
1: The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0: The Load Overrun Interrupt is disabled.
1: The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0: The RA Compare Interrupt is disabled.
1: The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0: The RB Compare Interrupt is disabled.
1: The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0: The RC Compare Interr upt is disabled.
1: The RC Compare Interr upt is enabled.
• LDRAS: RA Loading
0: The Load RA Interrupt is disabled.
1: The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0: The Load RB Interrupt is disabled.
1: The Load RB Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––RXBUFFENDRX
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
701
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
• ETRGS: External Trigger
0: The External Trigger Interrupt is disabled.
1: The External Trigger Interrupt is enabled.
• ENDRX: End of Receiver Transfer
0: The PDC Receive End of Tr ansfer Interrupt is disabled.
1: The PDC Receive End of Tr ansfer Interrupt is enabled.
• RXBUFF: Reception Buffer Full
0: The PDC Receive Buffer Full Interrupt is disabled.
1: The PDC Receive Buffer Full Interrupt is enabled.
SAM4N8/SAM4N16 [DATASHEET]
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702
32.7.13 TC Block Co ntrol Register
Name: TC_BCR
Address: 0x400100C0 (0), 0x400140C0 (1)
Access: Write-only
• SYNC: Synchro Command
0: No effect.
1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SYNC
703
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.14 TC Block Mode Register
Name: TC_BMR
Address: 0x400100C4 (0), 0x400140C4 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
• QDEN: Quadrature Decoder Enabled
0: Disabled.
1: Enables the QDEC (filter, edge detection and quadrature decoding).
Quadrature decoding (direction change) can be disabled using QDTRANS bit.
One of the POSEN or SPEEDEN bits must be also enabled.
31 30 29 28 27 26 25 24
–––––– MAXFILT
23 22 21 20 19 18 17 16
MAXFILT – – IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
76543210
– – TC2XC2S TC1XC1S TC0XC0S
Value Name Description
0 TCLK0 Signal connected to XC0: TCLK0
1– Reserved
2 TIOA1 Signal connected to XC0: TIOA1
3 TIOA2 Signal connected to XC0: TIOA2
Value Name Description
0 TCLK1 Signal connected to XC1: TCLK1
1– Reserved
2 TIOA0 Signal connected to XC1: TIOA0
3 TIOA2 Signal connected to XC1: TIOA2
Value Name Description
0 TCLK2 Signal connected to XC2: TCLK2
1– Reserved
2 TIOA0 Signal connected to XC2: TIOA0
3 TIOA1 Signal connected to XC2: TIOA1
SAM4N8/SAM4N16 [DATASHEET]
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704
• POSEN: Position Enabled
0: Disable position.
1: Enables the position measure on channel 0 and 1.
• SPEEDEN: Speed Enabled
0: Disabled.
1: Enables the speed measure on channel 0, the time base being provided by channel 2.
• QDTRANS: Quadrature Decoding Transparent
0: Full quadrature decoding logic is active (direction change detected).
1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
• EDGPHA: Edge on PHA Count Mode
0: Edges are detected on PHA only.
1: Edges are detected on both PHA and PHB.
• INVA: Inverted PHA
0: PHA (TIOA0) is directly driving the QDEC.
1: PHA is inverted before driving the QDEC.
• INVB: Inverted PHB
0: PHB (TIOB0) is directly driving the QDEC.
1: PHB is inverted before driving the QDEC.
• INVIDX: Inverted Index
0: IDX (TIOA1) is directly driving the QDEC.
1: IDX is inverted before driving the QDEC.
• SWAP: Swap PHA and PHB
0: No swap between PHA and PHB.
1: Swap PHA and PHB internally, prior to driving the QDEC.
• IDXPHB: Index Pin is PHB Pin
0: IDX pin of the rotary sensor must drive TIOA1.
1: IDX pin of the rotary sensor must drive TIOB0.
• MAXFILT: Maximum Filter
1–63: Defines the filtering capabilities.
Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded.
705
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.15 TC QDEC Interrupt Enable Register
Name: TC_QIER
Address: 0x400100C8 (0), 0x400140C8 (1)
Access: Write-only
• IDX: Index
0: No effect.
1: Enables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Enables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Enables the interrupt when a quadrature error occurs on PHA, PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
706
32.7.16 TC QDEC Interrupt Disable Register
Name: TC_QIDR
Address: 0x400100CC (0), 0x400140CC (1)
Access: Write-only
• IDX: Index
0: No effect.
1: Disables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Disables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Disables the interrupt when a quadrature error occurs on PHA, PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
707
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.17 TC QDEC Interrupt Mask Register
Name: TC_QIMR
Address: 0x400100D0 (0), 0x400140D0 (1)
Access: Read-only
• IDX: Index
0: The interrupt on IDX input is disabled.
1: The interrupt on IDX input is enabled.
• DIRCHG: Direction Change
0: The interrupt on rotation direction change is disabled.
1: The interrupt on rotation direction change is enabled.
• QERR: Quadrature Error
0: The interrupt on quadrature error is disabled.
1: The interrupt on quadrature error is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
708
32.7.18 TC QDEC Interrupt Status Register
Name: TC_QISR
Address: 0x400100D4 (0), 0x400140D4 (1)
Access: Read-only
• IDX: Index
0: No Index input change since the last read of TC_QISR.
1: The IDX input has changed since the last read of TC_QISR.
• DIRCHG: Direction Change
0: No change on rota tio n dir ec tio n sinc e th e last rea d of TC_ QI S R.
1: The rotation direction changed since the last read of TC_QISR.
• QERR: Quadrature Error
0: No quadratur e er ro r sinc e th e last rea d of TC_ QISR.
1: A quadrature error occurred since the last read of TC_QISR.
•DIR: Direction
Returns an image of the actual rotation direction.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––DIR
76543210
–––––QERRDIRCHGIDX
709
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
32.7.19 TC Fault Mode Register
Name: TC_FMR
Address: 0x400100D8 (0), 0x400140D8 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• ENCF0: Enable Compare Fault Channel 0
0: Disables the FAULT output source (CPCS flag) from channel 0.
1: Enables the FAULT output source (CPCS flag) from channel 0.
• ENCF1: Enable Compare Fault Channel 1
0: Disables the FAULT output source (CPCS flag) from channel 1.
1: Enables the FAULT output source (CPCS flag) from channel 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––ENCF1ENCF0
SAM4N8/SAM4N16 [DATASHEET]
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710
32.7.20 TC Write Protection Mode Register
Name: TC_WPMR
Address: 0x400100E4 (0), 0x400140E4 (1)
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
The Timer Counter clock of the first channel must be enabled to access this register.
See Section 32.6.18 “Register Write Protection” for a list of registers that can be write-protected and T ime r Co un te r clock
conditions.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x54494D PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
711
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33. Pulse Width Modulation Controller (PWM)
33.1 Description
The PWM macrocell controls several channels independently. Each channel controls one square output
waveform. Characteristics of the output wavefor m su ch as period, duty-cycle and polarity are configurable through
the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock
generator provides several clocks resulting from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering
system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
33.2 Embedded characteristics
4 Channels
One 16-bit Counter Per Channel
Common Clock Generator Providing Thirteen Different Clocks
A Modulo n Counter Providing Eleven Clocks
Two Independent Linear Dividers Working on Modulo n Counter Outputs
Independent Channels
Independent Enable Disable Command for Each Channel
Independent Clock Selection for Each Channel
Independent Period and Duty Cycle for Each Channel
Double Buffering of Period or Duty Cycle for Each Channel
Programmable Selection of The Output Waveform Polarity for Each Chan ne l
Programmable Center or Left Aligned Output Waveform for Each Channel Block Diagram
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33.3 Block Diagram
Figure 33-1. Pulse Width Modulation Controller Block Diagram
33.4 I/O Lines Description
Each channel outp u ts on e wa ve for m on one external I/O line.
PWM
Controller
APB
PWMx
PWMx
PWMx
Channel
Update
Duty Cycle
Counter
PWM0
Channel
PIO
Interrupt ControllerPMC MCK Clock Generator APB Interface Interrupt Generator
Clock
Selector
Period
Update
Duty Cycle
Counter
Clock
Selector
Period
PWM0
PWM0
Comparator
Comparator
Table 33-1. I/O Line Description
Name Description Type
PWMx PWM Waveform Output for channel x Output
713
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33.5 Product Dependencies
33.5.1 I/O Lines
The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the
PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by
the application, they can be used for other purposes by the PIO controller.
All of the P WM outputs ma y or may not be enabled. If an application requires only four channels, then only four
PIO lines will be assigned to PWM outputs.
33.5.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power
Management Controller (PMC) before using the PWM. However, if the application does not require PWM
operations, the PWM clock can be stopped when not ne eded and be restarted later. In this case, the PWM will
resume its operations where it left off.
Table 33-2. I/O Lines
Instance Signal I/O Line Peripheral
PWM PWM0 PA0 A
PWM PWM0 PA11 B
PWM PWM0 PA23 B
PWM PWM0 PB0 A
PWM PWM0 PC8 B
PWM PWM0 PC18 B
PWM PWM0 PC22 B
PWM PWM1 PA1 A
PWM PWM1 PA12 B
PWM PWM1 PA24 B
PWM PWM1 PB1 A
PWM PWM1 PC9 B
PWM PWM1 PC19 B
PWM PWM2 PA2 A
PWM PWM2 PA13 B
PWM PWM2 PA25 B
PWM PWM2 PB4 B
PWM PWM2 PC10 B
PWM PWM2 PC20 B
PWM PWM3 PA7 B
PWM PWM3 PA14 B
PWM PWM3 PB14 B
PWM PWM3 PC11 B
PWM PWM3 PC21 B
SAM4N8/SAM4N16 [DATASHEET]
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All the PWM registers except PWM_CDTY and PWM_CPRD can be read without the PWM peripheral clock
enabled. All the registers can be written without the peripheral clock enabled.
33.5.3 Interrupt Sources
The PWM int errupt line is connec ted on one of the in ternal sources of the Interrupt Controller. Using the PWM
interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM
interrupt line in edge sensitive mode.
Table 33-3. Peripheral IDs
Instance ID
PWM 31
715
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.6 Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
Clocked by the system clock, MCK, the clock generator module provides 13 clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined independently for
each channel through the user interface registers.
33.6.1 PWM Clock Generator
Figure 33-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power
Managemen t Co nt ro ller (P MC ).
The PWM ma crocell master clock, M CK, is divided in the clock generator modu le to provide differ ent clocks
available for all channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:
a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32,
FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024
two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and clkB
modulo n counter
MCK
MCK/2
MCK/4
MCK/16
MCK/32
MCK/64
MCK/8
Divider A clkA
DIVA
PWM_MR
MCK
MCK/128
MCK/256
MCK/512
MCK/1024
PREA
Divider B clkB
DIVB
PWM_MR
PREB
SAM4N8/SAM4N16 [DATASHEET]
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Each linear divider can independently divide one of the clocks of the mod ulo n counte r. The selectio n of the cloc k
to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). T he resulting
clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This
implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.
33.6.2 PWM Channel
33.6.2.1Block Diagram
Figure 33-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
A clock selector which selects one of the clocks provided by the clock generator described in Section 33.6.1
“PWM Clock Generator” on page 715.
An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal
counter is 16 bits.
A comparator used to generate events according to the intern al counter value. It also computes the PWMx
output waveform according to the configuration.
33.6.2.2Waveform Properties
The differen t pr op ertie s of output wavefor ms are :
the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the
clock generator describ ed in the previous section. This channel param eter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
the waveform period. This channel parameter is define d in th e CPRD fie ld of the PWM _C PRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center aligned then the output waveform period depends o n the coun ter so urce clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
Comparator PWMx
output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
APB bus
Channel
XCPRD×()
MCK
-------------------------------
X*CPRD*DIVA()
MCK
-----------------------------------------------
X*CPRD*DIVB()
MCK
-----------------------------------------------
717
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
the waveform polarity . At the beginning of the period, the sign al can be at high or low level. This prop erty is
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
the waveform alignment. The output waveform can be lef t or center aligned. Center alig ned waveforms can
be used to generate non overlapped waveforms. This property is defined in the CALG field of the
PWM_CMRx register. The default mode is left aligned.
Figure 33-4. Non Overlapped Center Aligned Waveforms
Note: 1. See Figure 33-5 on page 718 for a detailed description of center aligned waveforms.
When center alig ne d , th e in ter n al ch an n el coun te r in cr ea se s up to CPRD an d .d ec re as es d ow n to 0. T h is en ds the
period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned
channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
2XCPRD××()
MCK
----------------------------------------
2*X*CPRD*DIVA()
MCK
------------------------------------------------------
2*X*CPRD*DIVB()
MCK
------------------------------------------------------
duty cycle period 1 fchannel_x_clock CDTY×⁄–()
period
----------------------------------------------------------------------------------------------------
=
duty cycle period 2⁄()1 fchannel_x_clock CDTY×⁄–())
period 2⁄()
-------------------------------------------------------------------------------------------------------------------
=
PWM0
PWM1
Period
No overlap
SAM4N8/SAM4N16 [DATASHEET]
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The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Changes on channel polarity are not taken into account while the channel is enabled.
Figure 33-5. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
Center Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 0
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
Left Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
CALG(PWM_CMRx) = 0
CALG(PWM_CMRx) = 1
Period
Period
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
719
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.6.3 PWM Controller Operations
33.6.3.1Initialization
Before enabling the output channel, this channel must have been configured by the software application:
Configuration of the clock generator if DIVA and DIVB are required
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
Configuration of the pe riod for each chan nel (CPRD in the PWM_CPRDx register). W r iting in PWM_CPRDx
Register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CUPDx Register to update PWM_CPRDx as explained below.
Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in
PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user
must use PWM_CUPDx Register to update PWM_CDTYx as explained below.
Configuration of the output waveform polarity for each chann el (CPOL in the PWM_CMRx register)
Enable Interrupts (Writing CHIDx in the PWM_IER register)
Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of writing
simultaneously several CHIDx bits in the PWM_ENA register.
In such a situation, all channels may have the same clock selector configuration and the same period
specified.
33.6.3.2Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the Period
Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event
number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than
1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRD x, th e user is ab le to se t a va lue betwee n 1 up to 14 in
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
33.6.3.3Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change
waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value
in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and
updates the value for th e next cycle. Depending o n the CPD field in the PWM_CMRx register, PWM_CUPDx eithe r
updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be
smaller than the duty cycle.
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Figure 33-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his
software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM
Controller level.
The first met hod ( pol l i ng met ho d) con si s ts of r ea di ng t he releva nt status bit in PWM_ISR Registe r according to the
enabled channel(s). See Figure 33-7.
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note: Reading the PWM_ISR register automatically cle ars CHIDx flags.
Figure 33-7. Polling Method
Note: Polarity and alignment can be modified only when the channel is disabled.
PWM_CUPDx Value
PWM_CPRDx PWM_CDTYx
End of Cycle
PWM_CMRx. CPD
User's Writing
10
Writing in PWM_CUPDx
The last write has been taken into account
CHIDx = 1
Writing in CPD field
Update of the Period or Duty Cycle
PWM_ISR Read
Acknowledgement and clear previous register state
YES
721
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33.6.3.4Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the
corresponding channe l period. The in terrupt r emains active until a r ead operation in the PWM_ISR register occurs.
A channel interrupt is enabled by se tting the corresponding bit in the PWM_IER register. A channel interrupt is
disabled by setting the corresponding bit in the PWM_IDR register.
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33.7 Pulse Width Modulation Controller (PWM) User Interface
Note: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
Table 33-4 . Register Mapping(1)
Offset Register Name Access Reset
0x00 PWM Mode Register PWM_MR Read-write 0
0x04 PWM Enable Register PWM_ENA Write-only -
0x08 PWM Disable Registe r PWM_DIS Write-only -
0x0C PWM Status Register PWM_SR Read-only 0
0x10 PWM Interrupt Enable Register PWM_IER Write-only -
0x14 PWM Interrupt Disable Register PWM_IDR Write-only -
0x18 PWM Interrupt Mask Register PWM_IMR Read-only 0
0x1C PW M Int er r up t Status Registe r PWM_ISR Read-only 0
0x20 - 0xFC Reserved – – –
0x100 - 0x1FC Reserved
0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register PWM_CMR Read-write 0x0
0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register PWM_CDTY Read-write 0x0
0x200 + ch_num * 0x20 + 0x08 PWM Channel Period Register PWM_CPRD Read-write 0x0
0x200 + ch_num * 0x20 + 0x0C PWM Channel Counter Register PWM_CCNT Read-only 0x0
0x200 + ch_num * 0x20 + 0x10 PWM Channel Update Register PWM_CUPD Write-only -
723
SAM4N8/SAM4N16 [DATASHEET]
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33.7.1 PWM Mode Register
Name: PWM_MR
Address: 0x40020000
Access: Read/Write
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
Values which are not listed in the table must be considered as “reserved”.
31 30 29 28 27 26 25 24
–––– PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
–––– PREA
76543210
DIVA
Value Name Description
0 CLK_OFF CLKA, CLKB clock is turned off
1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB
2-255 – CLKA, CLKB clock is clock selected by PREA, PREB
divided by DIVA, DIVB factor.
Value Name Description
0000 MCK Master Clock
0001 MCKDIV2 Master Clock divided by 2
0010 MCKDIV4 Master Clock divided by 4
0011 MCKDIV8 Master Clock divided by 8
0100 MCKDIV16 Master Clock divided by 16
0101 MCKDIV32 Master Clock divided by 32
0110 MCKDIV64 Master Clock divided by 64
0111 MCKDIV128 Master Clock divided by 128
1000 MCKDIV256 Master Clock divided by 256
1001 MCKDIV512 Master Clock divided by 512
1010 MCKDIV1024 Master Clock divided by 1024
SAM4N8/SAM4N16 [DATASHEET]
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724
33.7.2 PWM Enable Register
Name: PWM_ENA
Address: 0x40020004
Access: Write-only
• CHIDx: Channel ID
0 = No effect.
1 = Enable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
725
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.3 PWM Disable Register
Name: PWM_DIS
Address: 0x40020008
Access: Write-only
• CHIDx: Channel ID
0 = No effect.
1 = Disable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4N8/SAM4N16 [DATASHEET]
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726
33.7.4 PWM Status Register
Name: PWM_SR
Address: 0x4002000C
Access: Read-only
• CHIDx: Channel ID
0 = PWM output for channel x is disabled.
1 = PWM output for channel x is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
727
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.5 PWM Interrupt Enable Register
Name: PWM_IER
Address: 0x40020010
Access: Write-only
• CHIDx: Channel ID.
0 = No effect.
1 = Enable interrupt for PWM channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
728
33.7.6 PWM Interrupt Disable Register
Name: PWM_IDR
Address: 0x40020014
Access: Write-only
• CHIDx: Channel ID.
0 = No effect.
1 = Disable interrupt for PWM channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
729
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.7 PWM Interrupt Mask Register
Name: PWM_IMR
Address: 0x40020018
Access: Read-only
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4N8/SAM4N16 [DATASHEET]
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730
33.7.8 PWM Interrupt Status Register
Name: PWM_ISR
Address: 0x4002001C
Access: Read-only
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
731
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.9 PWM Channel Mode Register
Name: PWM_CMR[0..3]
Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3]
Access: Read/Write
• CPRE: Channel Pre-scaler
Values which are not listed in the table must be considered as “reserved”.
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––CPDCPOLCALG
76543210
–––– CPRE
Value Name Description
0000 MCK Master Clock
0001 MCKDIV2 Master Clock divided by 2
0010 MCKDIV4 Master Clock divided by 4
0011 MCKDIV8 Master Clock divided by 8
0100 MCKDIV16 Master Clock divid ed by 16
0101 MCKDIV32 Master Clock divid ed by 32
0110 MCKDIV64 Master Clock divided by 64
0111 MCKDIV128 Master Clock divided by 128
1000 MCKDIV256 Master Clock divided by 256
1001 MCKDIV512 Master Clock divided by 512
1010 MCKDIV1024 Master Clock divided by 1024
1011 CLKA Clock A
1100 CLKB Clock B
SAM4N8/SAM4N16 [DATASHEET]
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732
33.7.10 PWM Channel Duty Cycle Register
Name: PWM_CDTY[0..3]
Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3]
Access: Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
31 30 29 28 27 26 25 24
CDTY
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY
733
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.11 PWM Channel Period Register
Name: PWM_CPRD[0..3]
Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3]
Access: Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided b y an X giv en prescaler v alue (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided b y an X giv en prescaler v alue (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
31 30 29 28 27 26 25 24
CPRD
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
XCPRD×()
MCK
-------------------------------
CRPD DIVA×()
MCK
------------------------------------------
CRPD DIVAB×()
MCK
----------------------------------------------
2XCPRD××()
MCK
----------------------------------------
2CPRD DIVA××()
MCK
---------------------------------------------------
2CPRD×DIVB×()
MCK
---------------------------------------------------
SAM4N8/SAM4N16 [DATASHEET]
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734
33.7.12 PWM Channel Counter Register
Name: PWM_CCNT[0..3]
Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3]
Access: Read-only
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
the channel is enabled (writing CHIDx in the PWM_ENA register).
the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
31 30 29 28 27 26 25 24
CNT
23 22 21 20 19 18 17 16
CNT
15 14 13 12 11 10 9 8
CNT
76543210
CNT
735
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
33.7.13 PWM Channel Update Register
Name: PWM_CUPD[0..3]
Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Access: Write-only
CUPD: Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the wavefor m peri od or duty- cycle.
Only the first 16 bits (internal channel counter size) are significant.
When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD
value at the beg inn ing of th e nex t pe rio d.
When CPD field of PWM_CMRx register = 1, the perio d (CPRD of PWM_CPRDx register) is up dated with the CUPD value
at the beginning of the next period.
31 30 29 28 27 26 25 24
CUPD
23 22 21 20 19 18 17 16
CUPD
15 14 13 12 11 10 9 8
CUPD
76543210
CUPD
SAM4N8/SAM4N16 [DATASHEET]
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736
34. Analog-to-Digital Converter (ADC)
34.1 Description
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the
Block Diagram: . It also integrates a 17-to-1 analog multiplexer, making possible the analog-to-digital conversions
of 17 analog lines. The conve rsion s ex te nd fr om 0V to th e voltag e carrie d o n pi n ADVREF or the vo ltage pr ovide d
by the internal reference voltage which can be progr ammed in ADC_ACR register. The selection of reference
voltage source is defined by ONREF field in ADC_MR register.
The ADC supports the 8-bit or 10-bit reso lution mode. The 8-bit resolution mode prevents from using 16-bit
Peripheral DMA transfer into memory when only 8-bit resolution is required by the application. Please note that
using this low resolution mode does not increase the conversion rate.
Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
The 11-bit and 12-bit resolution modes are obtained by interpolating multiple samples to acquire better accuracy.
For 11-bit mode, 4 samples are used, which gives an effective sample rate of 1/4 of the actual samp le frequency.
For 12-bit mode, 16 samples are used, giving an effective sample rate of 1/16 of the actual sample frequency.
This arrangement allows conversion speed to be traded for better accuracy.
The last channel is inte rnally connected by a temperature sensor. The processing of this channel can be fully
configured for efficient downstream processing due to the slow frequency variation of the value carried on such a
sensor.
Software trigger, external trigge r on r ising edge of the ADTRG pin or intern al trigge rs from Timer Coun ter output( s)
are configurable.
The main comparison circuitry allows autom atic detection of values below a thr eshold, higher than a threshold, in a
given range or outside the range, thresholds and ranges being fully configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These
features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
737
SAM4N8/SAM4N16 [DATASHEET]
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34.2 Embedded Characteristics
10-bit Resolution with Enhanced Mode up to 12-bit
500 kHz Conversion Rate
Digital Averaging Function providing Enhanced Resolution Mode up to 12-bit
On-chip Temperature Sensor Management
Wide Range Power Supply Operation
Selectable External Voltage Reference or Programmable Internal Reference
Integrated Multiplexer Offering Up to 17 Independent Analog Inputs
Individual Enable and Disable of Each Channel
Hardware or Software Trigger
External Trigger Pin
Timer Counter Outputs (Corresponding TIOA Trigger)
PDC Support
Possibility of ADC Timings Configuration
Two Sleep Modes and Conversion Sequencer
Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
Possibility of Customized Channel Sequence
Standby Mode for Fast Wakeup Time Response
Power Down Capability
Automatic Window Comparison of Converted Values
Write Protect Registers
SAM4N8/SAM4N16 [DATASHEET]
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738
34.3 Block Diagram
Figure 34-1. Analog-to-Digital Converter Block Diagram
34.4 Signal Description
Note: 1. AD16 is not an actual pin but is internally connected to a temperature sensor.
ADC Interrupt
ADTRG
ADVREF
GND
Trigger
Selection Control
Logic
Successive
Approximation
Register
Analog-to-Digital
Converter
Timer
Counter
Channels
User
Interface
Interrupt
Controller
Peripheral Bridge
APB
PDC
System Bus
Analog Inputs
Multiplexed
with I/O lines
PIO
AD-
AD-
AD-
ADC Controller
PMC
MCK
ADC Cell
CHx
Internal
Voltage
Reference
ONREF
Temp.
Sensor
1Hz
RTC
FORCEREF
VDDIN
Table 34-1. ADC Pin Description
Pin Name Description
ADVREF External Reference voltage
AD0 - AD16(1) Analog input channel s
ADTRG E xternal trigger
739
SAM4N8/SAM4N16 [DATASHEET]
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34.5 Product Dependencies
34.5.1 Power Management
The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the
Power Management Con troller (PMC) before using the ADC Controller. However, if the application does not
require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when
necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled.
34.5.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC
interrupt requires the interrupt controller to be programmed first.
34.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is
automatically done as soon as the corresponding channel is enabled b y writing the register ADC_CHER. By
default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to
the GND.
34.5.4 Temperature Sensor
The temperature sensor is internally connected to channel index 16 of the ADC.
The temperature sensor provides an output voltage VT that is proportional to the absolute temperature (PTAT) . To
activate the temperature sensor, TEMPON bit (ADC_TEMPMR)needs to be set. After being set, the startup time of
the temperature sensor must be achieved prior to initiating any measure.
Table 34-2. Peripheral IDs
Instance ID
ADC 29
SAM4N8/SAM4N16 [DATASHEET]
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740
34.5.5 I/O Lines
The pin ADTRG may be shared with other peripheral functions through t he PIO Controller . In this case, the PIO
Controller should be set accordingly to assign the pin ADTRG to the ADC function.
34.5.6 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all
of the timer counters may be unconnected.
34.5.7 Conversion Performances
For performance and electrical characteristics of the ADC, see the product DC Characteristics section.
Table 34-3. I/O Lines
Instance Signal I/O Line Peripheral
ADC ADTRG PA8 B
ADC AD0 PA17 X1
ADC AD1 PA18 X1
ADC AD2/WKUP9 PA19 X1
ADC AD3/WKUP10 PA20 X1
ADC AD4 PB0 X1
ADC AD5 PB1 X1
ADC AD6/WKUP12 PB2 X1
ADC AD7 PB3 X1
ADC AD8 PA21 X1
ADC AD9 PA22 X1
ADC AD10 PC13 X1
ADC AD11 PC15 X1
ADC AD12 PC12 X1
ADC AD13 PC29 X1
ADC AD14 PC30 X1
ADC AD15 PC31 X1
741
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34.6 Functional Description
34.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-b it digital data
requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC M ode Register” on page 755. The
ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The tra cking phase
starts during the conversion of the previous channel. If the tracking time is longer than the conversion time, the
tracking phase is extended to the end of the previous conversion.
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to 255 (0xFF).
PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in
the product Electrical Characteristics section.
Figure 34-2. Sequence of ADC conversions
34.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage which can be defined by the
external pin ADVREF or programmed by using th e internal reference voltage which configuration is defined in
ADC_ACR register. Analog inputs between these voltages convert to values based on a linear conversion.
Internal reference drives pin ADVREF after reset. Therefore if the application uses an external voltage reference,
the external reference output must be in high-impedance mode after reset.
34.6.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the LOWRES bit in the
ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the
data registers is fully used. By setting the LOWRES bit, the ADC switches to the lowest resolution and the
conversion results can be read in the lowest significant bits of the data registers. The two highest bits of the DATA
field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
ADCClock
LCDR
ADC_ON
ADC_SEL
DRDY
ADC_Start
CH0 CH1
CH0
CH2
CH1
Start Up Time
(and tracking of CH0) Conversion of CH0 Conversion of CH1Tracking of CH1 Tracking of CH2
ADC_eoc
Trigger event
(Hard or Soft)
Analog cell IOs
SAM4N8/SAM4N16 [DATASHEET]
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742
34.6.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register
(ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the
TAG option in the ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data
in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC
channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY
bit.
Figure 34-3. EOCx and DRDY Flag Behavior
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx)
flag is set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
The OVREx flag is autom atically cleared when ADC_OVER is read, and GOVRE flag is automatica lly cleared
when ADC_SR is read.
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Write the ADC_CR
with START = 1
Write the ADC_CR
with START = 1
743
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 34-4. GOVRE and OVREx Flag Behavior
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled
during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are
unpredictable.
EOC0
GOVRE
CH0
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Trigger event
EOC1
CH1
(ADC_CHSR)
(ADC_SR)
OVRE0
(ADC_OVER)
Undefined Data Data A Data B
ADC_LCDR
Undefined Data Data A
ADC_CDR0
Undefined Data Data B
ADC_CDR1
Data C
Data C
Conversion C
Conversion A
DRDY
(ADC_SR)
Read ADC_CDR1
Read ADC_CDR0
Conversion B
Read ADC_OVER
Read ADC_SR
OVRE1
(ADC_OVER)
SAM4N8/SAM4N16 [DATASHEET]
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744
34.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigg er can be on e of the TIOA outputs of th e Timer Counter chan nels or the external trigg er input of
the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register (ADC_MR). The
selected hardware trigger is enabled with the TRGEN bit in the “ADC Mode Register”.
The minimum time between 2 consecutive trigger even ts must be strictly greater than the duration time o f the
longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of
the selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock period s to 1
ADC clock period.
Figure 34-5. Hardware Tr igger Delay
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in
Waveform Mode.
Only one start command is ne cessary to initiate a conversion sequ ence on all the channels. The ADC hard ware
logic automatically pe rforms the conver sions on the active chann els, then waits for a new reque st. The Channel
Enable (ADC_CHER) and Channel Disa ble (ADC_CHDR) Registers permit the analog channels to be enabled or
disabled independently.
If the ADC is used with a PDC, only th e tran sfer s of con verte d data fr om en able d chann els are perform ed a nd the
resulting data buffers should be interpre ted accordingly.
34.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not b eing used for
conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode Register ADC_MR.
The Sleep mode is automatically mana ged by a conversion sequencer, which can automatically process the
conversions of all channels at lowest power consumption.
This mode can be used when the minimum period of time between 2 successive trigger events is greater than the
startup period of Analog-Digital converter (See the product ADC Characteristics section).
When a sta rt co nv er sio n r equ est occurs, t he AD C is au to m atically activated. As the analog cell requires a start-up
time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are
complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into
account.
A fast wake-up mode is available in the ADC Mode Register (ADC_M R) as a comp romise betw een power sav ing
strategy and responsiven ess. Setting the FWUP bit to ‘1’ enable s the fast wake-up mode. In fast wake-u p mode
the ADC cell is not fully deactiv ated while no conversion is reque sted, thereby providing less pow er saving but
faster wakeup.
The conversion sequencer allows automatic processing with minimum processor inte rvention and optim ized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic
acquisition of several samples can be processed automatically without any intervention of the processor thanks to
the PDC.
trigger
start delay
745
SAM4N8/SAM4N16 [DATASHEET]
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The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and
ADC_SEQR2 and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific
order of channels a nd can p ro gram up to 17 co nver sio ns by seque nce. The user is totally free to create a pe rsonal
sequence, by writing channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be
written in any sequence, channel numbers can be repeated several times. Only enabled seque nce bitfields are
converted, consequently to program a 15-conversion sequence, the user can simply put a disable in
ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2.
If all ADC channels ( i.e. 17) are used on an application bo ard, there is no restriction of usage of the user sequence.
But as soon as some ADC channels are not enabled for conv ersion but rather used as pure digital inputs, the
respective indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2
bitfields). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields
USCH1 up to USCH1 7 must not co ntain the value 4. Thus the length of the user sequence may be limited by this
behavior.
As an example, if only 4 channels over 17 (CH0 up to CH3) are selected for ADC conversions, the user sequence
length cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any
combination of channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is
impossible).
A sequence that repeats severa l times the same channel requires more enabled channels than channels actually
used for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled chann els (4 free
channels on application boards) whereas only CH0, CH1 are really converted.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
34.6.7 Comparison Window
The ADC Controller features automatic comparison function s. It comp ares conve rted values to a low thresh old or a
high thresh old or both , a cco rd ing to the CM PM OD E fu nct i on chosen in the Extend ed M od e Reg iste r ( ADC_ EM R) .
The comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To
compare all channels the CMP_ALL parameter of ADC_EMR should be set.
Moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the
flag. This number can be written and read in the CMPFILTER field of ADC_EMR.
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR).
If the comparison windo w is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do no t need to be
adjusted as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds mus t always be
configured in consideration of the maximum ADC resolution.
34.6.8 ADC Timings
Each ADC has its own minimal Startup T ime that is programmed through the field STARTUP in the Mode Re gister,
ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two
channel selections. This time has to be programm ed through the TRACKTIM bit field in the Mode Register,
ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into
consideration to program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
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34.6.9 Temperature Sensor
The temperature senso r is inte rn ally conn ected to channel index 16. For temperature mea sure men t, the TEMPON
bit must be written to 1 into the ADC_TEMPMR register.
The temperature measurement can be made in different ways through the ADC controller. The different methods
for the measure depend on the configuration bits TRGE N in the ADC_MR register and CH16 in the ADC_CHSR
register.
The temperature measurement can be triggered like the other channels by enabling its associated conversion
channel index 16, writing 1 in CH16 of the ADC_CHER register.
The manual start can only be performed if TRGEN bit in ADC_MR is disabled. When the START bit in the
ADC_CR register is written to 1, the temperature sensor channel conversion will be scheduled together with the
other enabled channels (if any). The result of the conversion is placed in the ADC_CDR16 register and the
associated flag EOC16 is set in the ADC_ISR register.
If the TRGEN bit is set in ADC_MR, the channel of the temperature sensor is periodically converted together with
other enabled channels and the result is placed on the ADC_LCDR and ADC_CDR16 registers. Thus the
temperature conversion result is part of the Perip heral DMA Controller buffer. The temperature channel can be
enabled/disabled at anytime but this may not be optimal for downstream processing.
Figure 34-6. Non-o ptimized Temperature Conversi on
The temperature factor having a slow variation rate and potentially being totally different from the other conversion
channels, the ADC controller allows a different way of triggering the measure when TEMPON is set in the
ADC_TEMPMR register but CH16 is not set in the ADC_CHSR register.
Base Address (BA)
BA + 0x02
ADC_CDR[TEMP]0
ADC_CDR[0]0
ADC_CDR[0]0 BA + 0x04
ADC_CDR[0]0
ADC_CDR[TEMP]0
ADC_CDR[TEMP]0
BA + 0x06
BA + 0x08
BA + 0x0A
Assuming ADC_CHSR[0] = 1 and ADC_CHSR[TEMP] = 1
where TEMP is the index of the temperature sensor channel
trig.event1
DMA Buer
Structure
trig.event2
DMA Transfer
trig.event3
ADC_SEL CTCTTCT
C
C: Classic ADC Conversion Sequence - T: Temperature Sensor Channel
CT
ADC_CHSR[TEMP]= 1 and ADC_MR.TRGEN=1
ADC_CDR[TEMP] T1 T2T0
ADC_CDR[0] C0 C1 C2 C3 C4 C5
T3 T4 T5
ADC_LCDR C0 C1 C2 C3 C4
T1 T2T0 T3 T4 T5
Internal/External
Trigger event
(TRGSEL dened)
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Under these conditions, the measure is triggered every second by means of an internal trigger generated by RTC,
always enabled and totally independent of the internal/external triggers. The RTC event will be taken into account
on the next inter nal/externa l trig ger e v ent as descr ibe d in Fig ure 34-7, on pag e 747. The internal/exter nal trigger is
selected through TRGSEL bitfield of the ADC_MR register.
In this mode of operation, the temperature sensor is only powered for a period of time covering the startup time
and conversion time (refer to Figure 34-8, on page 748 for more details).
Every second, a conversion is scheduled for channel 16 but the result of the conversion is only uploaded in the
ADC_CDR16 register and not in the ADC_LCDR register. Therefore there is no change in the structure of the
Peripheral DMA Co ntro ller b uffe r due to the conver sio n of the temperatur e channe l, only the enable d channels are
kept in the buffer. The end of conversion of the temperature channel is reported by means of EOC16 flag in the
ADC_ISR register.
Figure 34-7. Optimized Temperature Conversion combined with classical conversions
If TEMPON=1, TRGEN is disabled and none of the channels is enabled in the ADC_CHSR register
(ADC_CHSR=0), then only channel 16 is converted at a rate of 1 conversion per second (see Figu re 34-8, on page
748).
This mode of operation, when combined with the sleep mode operation of the ADC controller, provides a low
power mode for te mpe ratu re me asur e ( assuming th ere is n o othe r ADC conversion to schedule at a high sampling
rate or simply no othe r ch an ne l to conve r t).
Base Address (BA)
BA + 0x02
ADC_CDR[0]0
BA + 0x04
ADC_CDR[0]0
Assuming ADC_CHSR[0] = 1
trig.event1
DMA Buer Structure
trig.event2
DMA Transfer
trig.event3
ADC_SEL CTCCT
C
C: Classic ADC Conversion Sequence - T: Temperature Sensor Channel
C
ADC_CHSR[TEMP]= 0 and ADC_MR.TRGEN=1
TEMPON=1
ADC_CDR[0]0
Internal RTC
Trigger event
ADC_CDR[TEMP] T1 T2T0
ADC_CDR[0] &
ADC_LCDR C0 C1 C2 C3 C4 C5
1 s
Internal/External
Trigger event
(TRGSEL dened)
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Figure 34-8. Tem per ature Conversion Only
Moreover it is possible to raise a flag only if th ere is a predefined chan ge in the temperatu re measure. The user
can define a range of temperature or a threshold in the AD C_TEMPCWR register, and the mode of comparison
that can be programmed into the ADC_TEMPMR register by means of TEMPCMPMOD bitfield. These values will
define the way the TEMPCHG flag will be raised in the ADC_ISR register.
This flag can be us ed to trigger an inte rrupt only if there is something to upd ate or modify in the sy stem, resulting
from a temperature change and not being interrupted for each temperature measure end of conversion, especially
if there is no change.
In any case, if TEMPON is set, the temperature can be read at anytime in ADC_CDR16 without any specific
software intervention.
34.6.10 Enhanced Resolution Mode an d Digital Averaging Function
The Enhanced Resolution Mode is enabled if LOWRES is cleared in the ADC Mode Register (ADC_MR), and the
OSR bitfield is set to 1, 2 in ADC Extended Mode Register (ADC_EMR). The enhancem ent is based on a digital
averaging function.
FREERUN must be set to 0 when digital averaging is used (OSR differs from 0 in ADC_EMR register).
There is no averaging on the last index channel if the measure is triggered by RTC event (see Section 34.6.9 on
page 746).
In this mode the ADC Controller will trade conversion performance for accuracy by averaging multiple samples,
thus providing a digital low-pass filter function.
If 1-bit enhancement res olution is selected (OSR=1 in the ADC_ EMR register), the ADC effective sample rate is
the maximum ADC sample rate divided by 4, ther efore the oversampling ratio is 4.
When the 2-bit enhancemen t resolution is selected (OSR=2 in the ADC_EMR regist er), the ADC effective sample
rate is the maximum ADC sample rate divided by 16 (oversampling ratio is 16).
The selected oversampling ratio applies to all enabled chan nels except for the temperat ure sensor channel when
triggered by RTC event.
The average result is valid into the ADC_CDRn (n corresponding to the index of the channel) registers only if
EOCn flag is set in the ADC_ISR register and OVREn flag is cleared in the ADC_OVER register. The average
result for all channels is valid in the ADC_LCDR register only if DRDY is set and GOVRE is cleared in the
ADC_ISR register.
ADC_SEL
ADC_CHSR= 0 and ADC_MR.TRGEN=0
Internal RTC
Trigger event
1 s
Automatic “On”
Temp. sensor
T T
30 us
on
o
ADC_CDR[TEMP] T1 T2T0
TEMPON=1
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34.6.10.1Averaging Function versus Trigger Events
The samples can be defined in different ways for the averaging function depending on the configuration of the
ASTE bit in the extended mode register (ADC_EMR) and the USEQ bit in the mode register (ADC_MR).
When USEQ is cleared, there are 2 possible ways to generate the averaging through the trigger event. If ASTE bit
is cleared in the ADC_EMR register, every trigger event generates one sample for each enabled ch annel a s
described in Figure 34-9, on page 749. Therefore 4 trigger events are requested to get the result of averaging if
OSR=1.
Figure 34-9. Digital Averaging Function Waveforms over multiple trigger events
If ASTE = 1 in the ADC_EMR register and USEQ=0 in the ADC_MR register then the sequence to be converted,
defined in the ADC_CHSR register is automatically repeated n times (where n corresponds to the oversampling
ratio defined in the OSR bitfield in the ADC_EMR register). As a consequence only 1 trigger is required to get the
result of the averaging function as described in Figure 34-9, on page 749.
Internal/External
Trigger event
ADC_SEL 01
ADC_EMR.OSR=1 ASTE=0, ADC_CHSR[1:0]= 0x3 and ADC_MR.USEQ=0
ADC_CDR[1]
ADC_CDR[0] CH0_0
ADC_LCDR
0i1
01010101
0i2 0i3 CH0_1 0i1
CH1_0 1i1 1i2 1i3 CH1_1 1i1
EOC[0]
Read ADC_CDR[1]
CH1_1CH0_1
EOC[1]
Read ADC_LCDR
DRDY
Note: 0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are nal result of average function.
Read ADC_CDR[0]
Read ADC_CDR[1]
OVR[0]
CH1_0
Read ADC_LCDR
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Figure 34-10. Digital Averaging Function Waveforms on a single trigger event
When USEQ is set, the user can define the channel sequence to be converted by configuring the ADC_SEQRx
and the ADC_CHER registers so that channels are not interleaved during averaging period. Under these
conditions, a sample is defined for each end of conversion as described in Fi gu r e 34 -1 1, on page 751.
Therefore if the sa me channel is configured to be converted 4 time s consecutively, and the OSR=1 in the exte nded
mode register (ADC_EMR), the averaging result will be placed in the corresponding channel data register
ADC_CDRx and last converted data register (ADC_LCDR) for each trigger event.
In such case, the ADC effective sample rate remains the maximum ADC sample rate divided by 4 or 16,
depending on OSR.
When USEQ=1, ASTE=1 and OSR is diffe rent from 0, it is important to notice that the user se quence must fol low a
specific pattern. The user sequence must be programmed in such a way that it generates a stream of conversion,
where a given channel is successively converted with an integer multiple depending on OSR value. Up to 4
channels can be converted in this specific mode.
When OSR=1, ea ch channel to convert m ust be consecutively repeated 4 times in the sequence, so the 4 firs t
single bit field enabled in the ADC_CHSR register mu st have their associated channel index prog rammed to the
same value in the ADC_SEQ1/2R registers. Therefor e for OSR=1 a maximum o f 4 chann els can be conve rted (the
user sequence allows a maximum of 16 conversions for each trigger event).
When OSR=2, a channel to convert must be consecutively repeated 16 times in the sequence, so all fields must
be enabled in the ADC_CHSR register, and their associated channel index programmed to the same value in the
ADC_SEQ1/2R registers. There fore for OSR=2 only on e channel can be con verted (the user sequence allows a
maximum of 16 conversions for each trigger event).
OSR=3 and OSR=4 are prohibited when USEQ=1 and ASTE=1.
Internal/External
Trigger event
ADC_SEL 0
ADC_EMR.OSR=1, ASTE=1 , ADC_CHSR[1:0]= 0x3 and ADC_MR.USEQ=0
ADC_CDR[1]
ADC_CDR[0] CH0_0
ADC_LCDR
0i1
0
0i2 0i3 CH0_1
EOC[0]
Read ADC_CDR[0]
Read ADC_CDR[1]
CH1_1CH0_1
EOC[1]
Read ADC_LCDR
DRDY
0111
00
CH1_0 1i1 1i2 1i3 CH1_1
Note: 0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are nal result of average function.
01 11
751
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Figure 34-11. Digital Averagin g Function Waveforms on single trig ger event, non-interleaved
34.6.10.2Oversampling Digital Output Range
When an oversampling is performed, the maximum value that can be read on the ADC_CDRx or ADC_LCDR
registers is not the full scale value, even if the maximum voltage is supplied on the analog input. This is due to the
digital averaging algorithm. For example, when OSR=1, 4 samples are accumulated and the result then is right
shifted by 1 (divided by 2).
The maximum output value carried on the ADC_CDRx or ADC_LCDR registers depends on the OSR value
configured in the ADC_EMR register.
34.6.11 Automatic Calibration
The ADC features an automatic calibration (AUTOCALIB) mode for gain errors (calibration).
The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of the ADC Control
Register. The automatic calibration sequence requires a software reset command (SWRST in the ADC_CR
register) prior to write AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in the interrupt
status register (ADC_ISR), and an interrupt is generated if EOCAL interrupt has been enabled (ADC_IER register).
The calibration sequence will perform an automatic calibration on all enabled channels. The channels required for
conversion do not need to be all enabled during the calibration process if they are programmed with the same
Internal/External
Trigger event
ADC_SEL 0
ADC_EMR.OSR=1 , ASTE=1, ADC_CHSR[7:0]= 0xFF and ADC_MR.USEQ=1
ADC_CDR[1]
ADC_CDR[0] CH0_0
ADC_LCDR
0i1
00
0i2 0i3 CH0_1
EOC[0]
Read ADC_CDR[0]
Read ADC_CDR[1]
CH1_1CH0_1
EOC[1]
Read ADC_LCDR
DRDY
01111 0000
CH1_0 1i1 1i2 1i3 CH1_1
Note: 0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are nal result of average function.
ADC_SEQ1R = 0x1111_0000
Table 34-4. Oversampling Digital Output Range Values
Resolution Samples Shift Full Scale Value Maximum Value
8-bit 1 0 255 255
10-bit 1 0 1023 1023
11-bit 4 1 2047 2046
12-bit 16 2 4095 4092
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gain. Only channels with different gain settings need to be enabled . The gain settings of all enabled channels must
be set before starting the AUTOCALIB sequence. If the gain settings (ADC_CGR and ADC_COR registers) for a
given channel are changed, the AUTOCALIB sequence must then be started again.
The calibration data (on one or more enabled channels) is stored in the internal ADC memory.
Then, when a new conversion is started (on one or more enabled channels), the converted value (in ADC_LCDR
or ADC_CDRx registers) is a calibrated value.
Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain has been already
calibrated, and a new channel with the same settings is enabled after the initial calibration, there is no need to
restart a calibration. If dif f erent enabled cha nnels have di f fer ent g ain setting s, the corr esponding cha nnels must b e
enabled before starting the calibration.
If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from Backup mode), the
calibration data in the ADC memory is lost.
Changing the ADC running mode (in ADC_CR register) does not affect the calibration data.
Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time, gain error after calibration, refer to the 12-bit ADC electrical characteristics section of the
product.
34.6.12 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of
data is repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of
operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data read to PDC
buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in
ADC_EMR register, the 4 most significant bits are carrying the channel number thus allowing an easier post-
processing in the PDC buffer or better checking the PDC buffer integ rity.
34.6.13 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-
protected by setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status
Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
“ADC Mode Register” on page 755
“ADC Channel Seq uen c e 1 Register” on page 757
“ADC Channel Seq uen c e 2 Register” on page 758
“ADC Channel Enable Register” on page 759
“ADC Channel Disable Register” on page 760
“ADC Temperature Sensor Mode Register” on page 768
“ADC Temperature Compare Window Register” on page 769
“ADC Extended Mode Register” on page 771
“ADC Compare Window Register” on page 773
“ADC Analog Control Register” on page 775
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34.7 Analog-to-Digital Converter (ADC) User Interface
Note: If an offset is not listed in the table it must be considered as “reserved”.
Table 34-5 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register ADC_CR Write-only –
0x04 Mode Register ADC_MR Read-write 0x00000000
0x08 Channel Sequence Register 1 ADC_SEQR1 Read-write 0x00000000
0x0C Channel Sequence Register 2 ADC_SEQR2 Read-write 0x00000000
0x10 Channel Enable Register ADC_CHER Write-only –
0x14 Channel Disable Register ADC_CHDR Write-only –
0x18 Channel S tatus Register ADC_CHSR Read-only 0x00000000
0x1C Reserved – – –
0x20 Last Converted Data Register ADC_LCDR R ead-only 0x00000000
0x24 Interrupt Enable Register ADC_IER Write-only –
0x28 Interrupt Disable Register ADC_IDR Write-only –
0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000
0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000
0x34 Temperature Sensor Mode Register ADC_TEMPMR Read-write 0x00000000
0x38 Temperature Compare Window Register ADC_TEMPCWR Read-write 0x00000000
0x3C Overrun Status Register ADC_OVER Read-only 0x00000000
0x40 Extended Mode Register ADC_EMR Read-write 0x00000000
0x44 Compare Window Register ADC_CWR Read-write 0x00000000
0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000
0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000
... ... ... ... ...
0x90 Channel Data Register 16 ADC_CDR16 Read-only 0x00000000
0x100 - 0x90 Reserved – – –
0x94 Analog Control Register ADC_ACR Read-write 0x00080000
0x98 - 0xAC Reserved – – –
0xC4 - 0xE0 Reserved – – –
0xE4 Write Protect Mode Register ADC_WPMR Read-write 0x00000000
0xE8 Write Protect Status Register ADC_WPSR Read-only 0x00000000
0xEC - 0xF8 Reserved – – –
0xFC Reserved – – –
0x100 - 0x124 Reserved for PDC registers – – –
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34.7.1 ADC Control Register
Name: ADC_CR
Address: 0x40038000
Access: Write-only
• SWRST: Software Reset
0 = No effect.
1 = Resets the ADC simulating a hardware reset.
• START: Start Conversion
0 = No effect.
1 = Begins analog-to-digital conversion.
• AUTOCAL: Automatic Calibrat ion of ADC
0 = No effect.
1 = Launches an automatic calibration of the ADC cell on the next sequence.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––AUTOCAL–STARTSWRST
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34.7.2 ADC Mode Register
Name: ADC_MR
Address: 0x40038004
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 776.
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• LOWRES: Resolution
• SLEEP: Sleep Mode
31 30 29 28 27 26 25 24
USEQ – TRANSFER TRACKTIM
23 22 21 20 19 18 17 16
–DIV1– – STARTUP
15 14 13 12 11 10 9 8
PRESCAL
76543210
FREERUN –SLEEP LOWRES TRGSEL TRGEN
Value Name Description
0 DIS Hardware triggers are disabled. Starting a conversion is only possible by software.
1 EN Hardware trigger selected by TRGSEL field is enabled.
Value Name Description
0 ADC_TRIG0 External trigger
1 ADC_TRIG1 TIO Output of the Timer Counter Channel 0
2 ADC_TRIG2 TIO Output of the Timer Counter Channel 1
3 ADC_TRIG3 TIO Output of the Timer Counter Channel 2
4 ADC_TRIG4 Reserved
5 ADC_TRIG5 Reserved
6 ADC_TRIG6 Reserved
7–Reserved
Value Name Description
0 BITS_10 10-bit resolution. For higher resolution by interpolation, please refer to
“ADC Extended Mode Register” on page 771
1 BITS_8 8-bit resolution
Value Name Description
0 NOR MAL Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
1 SLEEP Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions
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• FREERUN: Free Run Mode
Note: FREERUN must be set to 0 when digital averaging is used (OSR differs from 0 in ADC_EMR register).
• PRESCAL: Prescaler Rate Selection
•ADCClock = MCK / ( (PRESCAL+1) * 2 ). STARTUP: Start Up Time
• TRACKTIM: Tracking Time
Tracking Time = (TRACKTIM + 1) * ADCClock periods.
• TRANSFER: Transfer Period
This field must be programmed with value 2.
• USEQ: Use Sequence Enable
Value Name Description
0 OFF Normal Mode
1 ON Free Run Mode: Never wait for any trigger.
Value Name Description
0 SUT0 0 periods of ADCClock
1 SUT8 8 periods of ADCClock
2 SUT16 16 periods of ADCClock
3 SUT24 24 periods of ADCClock
4 SUT64 64 periods of ADCClock
5 SUT80 80 periods of ADCClock
6 SUT96 96 periods of ADCClock
7 SUT112 112 periods of ADCClock
8 SUT512 512 periods of ADCClock
9 SUT576 576 periods of ADCClock
10 SUT640 640 periods of ADCClock
11 SUT704 7 04 periods of ADCClock
12 SUT768 768 periods of ADCClock
13 SUT832 832 periods of ADCClock
14 SUT896 896 periods of ADCClock
15 SUT960 960 periods of ADCClock
Value Name Description
0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the
channel index.
1REG_ORDER
User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2
registers and can be used to convert several times the same channel.
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34.7.3 ADC Channel Sequence 1 Register
Name: ADC_SEQR1
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 16. So it is only possible to use the sequencer from CH0 to CH16.
This register activates only if ADC _MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
31 30 29 28 27 26 25 24
––
23 22 21 20 19 18 17 16
––
15 14 13 12 11 10 9 8
––
76543210
––
SAM4N8/SAM4N16 [DATASHEET]
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34.7.4 ADC Channel Sequence 2 Register
Name: ADC_SEQR2
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 16. So it is only possible to use the sequencer from CH0 to CH16.
This register activates only if ADC _MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
31 30 29 28 27 26 25 24
––
23 22 21 20 19 18 17 16
––
15 14 13 12 11 10 9 8
––
76543210
––
759
SAM4N8/SAM4N16 [DATASHEET]
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34.7.5 ADC Channel Enable Register
Name: ADC_CHER
Address: 0x40038010
Access: Write-only
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corr es po nd in g cha n ne l.
Note: If USEQ = 1 in the ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and
ADC_SEQR2.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––CH16
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
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34.7.6 ADC Channel Disable Register
Name: ADC_CHDR
Address: 0x40038014
Access: Write-only
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver-
sion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––CH16
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
761
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34.7.7 ADC Channel Status Register
Name: ADC_CHSR
Address: 0x40038018
Access: Read-only
• CHx: Chan ne l x Status
0 = The corresponding channel is disabled.
1 = The corresponding channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––CH16
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
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34.7.8 ADC Last Converted Data Register
Name: ADC_LCDR
Address: 0x40038020
Access: Read-only
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains un til a new conver-
sion is completed.
• CHNB: Channel Number
Indicates the last converted channel whe n the TAG option is set to 1 in the ADC_EMR r egister. If the TAG option is not set,
CHNB = 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHNB LDATA
76543210
LDATA
763
SAM4N8/SAM4N16 [DATASHEET]
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34.7.9 ADC Interrupt Enable Register
Name: ADC_IER
Address: 0x40038024
Access: Write-only
• EOCx: End of Conversion Interrupt Enable x
• TEMPCHG: Temperature Change Interrupt Enable
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• COMPE: Comparison Event Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the corr es po nd in g inte r ru pt .
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – – TEMPCHG – – EOC16
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
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34.7.10 ADC Interrupt Disable Register
Name: ADC_IDR
Address: 0x40038028
Access: Write-only
• EOCx: End of Conversion Interrupt Disable x
• TEMPCHG: Temperature Change Interrupt Dis able
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• COMPE: Comparison Event Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – – TEMPCHG – – EOC16
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
765
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34.7.11 ADC Interrupt Mask Regist er
Name: ADC_IMR
Address: 0x4003802C
Access: Read-only
• EOCx: End of Conversion Interrupt Mask x
• TEMPCHG: Temperature Change Interrupt Mask
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• COMPE: Comparison Event Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – – TEMPCHG – – EOC16
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
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34.7.12 ADC Interrupt Status Register
Name: ADC_ISR
Address: 0x40038030
Access: Read-only
• EOCx: End of Conversion x
0 = The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the
corresponding ADC_CDRx registers.
1 = The corresponding analog channel is enabled and conversion is complete.
• TEMPCHG: Temperature Change
0 = There is no comparison match (defined in the ADC_TEMPCWR register) since the last read of the ADC_ISR register.
1 = The temperature value reported on ADC_CDR16 has changed since the last read of ADC_ISR, according to what is
defined in the temp erature mo de re gister (ADC_ TEMPMR) and temper ature compar e window r egister (ADC_T EMPCWR).
• EOCAL: End of Calibration Sequence
0 = Calibration sequence is on going, or no calibration sequence has been requested.
1 = Calibration sequence is complete.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overru n Err or occur re d sinc e th e la st rea d of ADC_IS R.
1 = At least one General Overrun Error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Error
0 = No Comparison Erro r sinc e th e last read of ADC _I SR.
1 = At least one Comparison Error (defined in th e ADC_EMR and ADC_CWR registers) has occurred since the last read of
ADC_ISR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – – TEMPCHG – – EOC16
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
767
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• RXBUFF: RX Buffer Full
0 = ADC_RCR or ADC_RNCR have a value other than 0.
1 = Both ADC_RCR and ADC_RNCR have a value of 0.
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34.7.13 ADC Temperature Sensor Mode Register
Name: ADC_TEMPMR
Address: 0x40038034
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• TEMPON: Temperature Sensor ON
0 = The temperature sensor is not enabled.
1 = The temperature sensor is enabled and the measurements are triggered.
• TEMPCMPMOD: Te mperature Comparison Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–– TEMPCMPMOD –––TEMPON
Value Name Description
0 LOW Generates an event when the converted data is lower than the low threshold of the window.
1 HIGH Generates an event when the converted data is higher than the high threshold of the window.
2 IN Generates an event when the converte d data is in the comparison window.
3 OUT Generates an event when the converted data is out of the comparison window.
769
SAM4N8/SAM4N16 [DATASHEET]
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34.7.14 ADC Temperature Compare Window Register
Name: ADC_TEMPCWR
Address: 0x40038038
Access: Read-write
This register can only be written if the WPEN bit is cleared in the “ADC Write Protect Mode Register” .
• TLOWTHRES: Temperature Low Threshold
Low threshold associated to compare settings of the ADC_TEMPMR register.
• THIGHTHRES: Temperature High Threshold
High threshold associated to compare settings of the ADC_TEMPMR registe r.
31 30 29 28 27 26 25 24
–––– THIGHTHRES
23 22 21 20 19 18 17 16
THIGHTHRES
15 14 13 12 11 10 9 8
–––– TLOWTHRES
76543210
TLOWTHRES
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770
34.7.15 ADC Overrun Status Regist er
Name: ADC_OVER
Address: 0x4003803C
Access: Read-only
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
1 = There has been an overrun error on the corresponding channel since the last read of ADC_OVER.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
OVRE15 OVRE14 OVRE13 OVRE12 OVRE11 OVRE10 OVRE9 OVRE8
76543210
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
771
SAM4N8/SAM4N16 [DATASHEET]
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34.7.16 ADC Extended Mode Register
Name: ADC_EMR
Address: 0x40038040
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• CMPMODE: Comparison Mode
• CMPSEL: Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
• CMPALL: Compare All Channels
0 = Only channel indicated in CMPSEL field is compared.
1 = All channels are compared.
• CMPFILTER: Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1
When programmed to 0, the flag rises as soon as an event occurs.
• OSR: Over Sampling Rate
This field is active if LOWRES is cleared in “ADC Mode Register” on page 755.
Note: FREERUN (see ADC_MR register) must be set to 0 when digital averaging is used.
31 30 29 28 27 26 25 24
–––––––TAG
23 22 21 20 19 18 17 16
– – – ASTE – – OSR
15 14 13 12 11 10 9 8
– – CMPFILTER – – CMPALL –
76543210
CMPSEL – – CMPMODE
Value Name Description
0 LOW Generates an event when the converted data is lower than the low threshold of the window.
1 HIGH Generates an event when the converted data is higher than the high threshold of the window.
2 IN Generates an event when the converted da ta is in the comparison window.
3OUT Generates an event when the converted data is out of the comparison window.
Value Name Description
0 NO_AVERAGE no averaging. ADC sample rate is maximum.
1 OSR4 1 -bit enhanced resolution by interpolation . ADC sample rate divided by 4.
2 OSR16 2-bit enhanced resolution by interpolation. ADC sample rate divided by 16.
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• ASTE: Averaging on Single Trigger Event
• TAG: TAG of the ADC_LDCR register
0 = Sets CHNB to zero in ADC_LDCR.
1 = Appends the channel number to the conversion result in ADC_LDCR register.
Value Name Description
0 MULTI_TRIG_AVERAGE The average requests several trigger events.
1 SINGLE_TRIG_AVERAGE The average requests only one trigger event.
773
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34.7.17 ADC Compare Window Register
Name: ADC_CWR
Address: 0x40038044
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• LOWTHRES: Low Threshold
Low threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 10 LSB of LOWTHRES must be programmed. The 2 LSB will be automatically dis-
carded to match the value carried on ADC_CDR (8-bit).
• HIGHTHRES: High Threshold
High threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 10 LSB of HIGHTHRES must be programmed. The 2 LSB will be automatically dis-
carded to match the value carried on ADC_CDR (8-bit).
31 30 29 28 27 26 25 24
–––– HIGHTHRES
23 22 21 20 19 18 17 16
HIGHTHRES
15 14 13 12 11 10 9 8
–––– LOWTHRES
76543210
LOWTHRES
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34.7.18 ADC Channel Data Register
Name: ADC_CDRx [x=0..16]
Address: 0x40038050
Access: Read-write
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains un til a new conver-
sion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DATA
76543210
DATA
775
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34.7.19 ADC Analog Control Register
Name: ADC_ACR
Address: 0x40038094
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• IRVCE: Internal Reference Voltage Change Enable
0 (STUCK_AT_DEFAULT) = The internal reference voltage is stuck at the default value (see the product electrical charac-
teristics for further details).
1 (SELECTION) = The internal reference voltage is defined by field IRVS.
• IRVS: Internal Referenc e Vo ltage Selection
See the product electrical characteristics for further details.
• FORCEREF: Force Internal Reference Voltage
0 = The internal voltage reference is defined.
1 = The internal voltage reference is forced to VDDIN (ONREF must be set to 0).
FORCEREF=1 is the value driven after reset. Therefore if the application uses an external voltage refere nce, the external
reference output must be in high-impedance mode after reset.
• ONREF: Internal Voltage Reference ON
0 = The external pin ADVREF defines the voltage reference.
1 = The internal voltage reference is selected (FORCEREF must be set to 0).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––ONREFFORCEREF–––
15 14 13 12 11 10 9 8
––––––––
76543210
–IRVSIRVCE––
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34.7.20 ADC Write Protect Mode Register
Name: ADC_WPMR
Address: 0x400380E4
Access: Read-write
• WPEN: Write Protec t En ab le
0 = Disables the Write Protect if WPKEY corresponds to 0x 414443 (“ADC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
Protects the reg ist er s:
•“ADC Mode Register” on page 755
•“ADC Channel Seq uen c e 1 Register” on page 757
•“ADC Channel Seq uen c e 2 Register” on page 758
•“ADC Channel Enable Register” on page 759
•“ADC Channel Disable Register” on page 760
•“ADC Temperature Sensor Mode Register” on page 768
•“ADC Temperature Compare Window Register” on page 769
•“ADC Extended Mode Register” on page 771
•“ADC Compare Window Register” on page 773
•“ADC Analog Control Register” on page 775
• WPKEY: Write Protect KEY
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x414443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0
777
SAM4N8/SAM4N16 [DATASHEET]
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34.7.21 ADC Write Prot ect Status Register
Name: ADC_WPSR
Address: 0x400380E8
Access: Read-only
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register. If this violation is an unauthor-
ized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Reading ADC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
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35. Digital-to-Analog Converter Controller (DACC)
35.1 Description
The Digital-to-Analog Converter Controller (DACC) has one analog output, making it possible for the digital-to-
analog conversion to drive one analog line.
The DACC supports 10-bit resolutio n and data to be converted are sent in a common register. External triggers,
through the ext_trig pins, or internal triggers are configurable.
The DACC Controller connects with a PDC channel. This feature reduces processor intervention.
Finally, the user can configure DACC timings such as Startup Time and the Internal Trigger Period.
35.2 Embedded Characteristics
One Analog Output
10-bit resolution
Hardware Trigger
External Trigger Pins
PDC Support
Possibility of DAC Timings
Internal FIFO providing flexibility and high efficiency
779
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35.3 Block Diagram
Figure 35-1. Dig ital-to-Analog Converter Controller Block Diagram
35.4 Signal Description
Table 35-1. DAC Pin Description
Pin Name Description
DAC0 Analog output channel
DATRG External triggers
DAC Controller
Trigger
Selection Control
Logic
User
Interface
DAC Cell
DAC Core
DAC0
DATRG
Interrupt
Controller
DACC Interrupt
PDC
AHB
APB
Peripheral Bridge
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35.5 Product Dependencies
35.5.1 Power Management
The DAC can be enabled and disabled through the DACEN bit of the DACC Mode Register.
35.5.2 Interrupt Sources
The DACC interrupt lin e is connected on one of the intern al sources of the Interrupt Controlle r. Using the DACC
interrupt requires the Interrupt Controller to be programmed first.
35.5.3 Conversion Performances
For performance and electrical characteristics of the DAC, see the product DC Characteristics section.
Table 35-2. Peripheral IDs
Instance ID
DACC 30
781
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35.6 Functional Description
35.6.1 Digital-to-analog Conversion
The DAC uses the master clock (MCK) to perform conversions.
Once a conversion has started, the DAC will take a setup time to provide the analog result on the analog output.
Refer to the product electrical characteristics for more information.
35.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the DAC channel output.
35.6.3 Conversion Triggers
In internal trigger mode, conversion starts as soon as the DACC is enabled, data is written in the DACC
Conversion Data Register an d an internal tr igger even t occurs (see Figure 35-2). The internal trigger frequency is
configurable through the CLKDIV field of the DACC Mode Register and must not be above the maximum
frequency allowed by the DAC.
In external trigger mode, the conversion waits for a rising edge event on the selected trigger to begin (s ee Figure
35-3).
Warning: Disabling the external trigger mode will automatically set the DACC in internal trigger mode.
Figure 35-2. Internal trigger
Figure 35-3. External trigger
CLKDIV/2 CLKDIV CLKDIV CLKDIV
TXRDY
write
DACC_CDR
Internal
trigger
DACC
conversion
data1data2data3data4
data1data2data3data4
01234 3 2 1 0
Number of
bytes in FIFO
TXRDY
write
DACC_CDR
External
trigger
DACC
conversion
data1data2data3data4
data1data2data3data4data5
data5
012323 4 3 2 1 0
Number of
bytes in FIFO
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35.6.4 Conversion FIFO
To provide flexibility and high efficiency, a 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the DACC Interrupt Status Register is active the DAC Controller is ready to accept
conversion requests by writing data in the DACC Conversion Data Register (DACC_CDR). Data which cannot be
converted immediately are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO data.
35.6.5 Conversion Width
The WORD field of the DACC Mode Register allows the user to switch between half-word and word transfer.
In half-word tr an sfe r mod e on ly on e 10 -b it da ta item is sampled (DACC_MR[9:0]) per DACC_CDR register write.
In word transfer mode each time the DACC_CDR register is written 2 data items are sampled. First data item
sampled for conversion will be DACC_CDR[9:0] and the second DACC_CDR[25:16].
35.6.6 DAC Timings
The DAC startup time must be defined by the user in the STARTUP field of the DACC Mode Register.
The DAC maximum clock fre quency is 500 KHz, th erefore th e intern al trigger peri od can be configured thr ough the
CLKDIV field of the DACC Mode Register.
35.6.7 Write Protection Registers
In order to bring security to the DACC, a write protection system has been implemented.
The write protection mode prevents the write of the DACC Mode Register. When this mode is enabled and the
protected register is written an error is generated in the DACC Write Protect Status Register an d th e re gis te r w rite
request is canceled. When a write protectio n error occurs, the WPROTERR flag is set and the address of the
corresponding canceled register write is available in the WPROTADRR field of the DACC Write Protect Status
Register.
Due to the nature of the write pro tecti o n featu re, enab ling a nd d isa bling the write protection mode requires the use
of a security code. Thus when enabling or disabling the write protection mode, the WPKEY field of the DACC Write
Protect Mode Register must be filled with the “DAC” ASCII code (corresponding to 0x444143) otherwise the
register write will be canceled.
783
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
35.7 Digital-to-Analog Converter Controller (DACC) User Interface
Table 35-3 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register DACC_CR Wr ite-only –
0x04 Mode Register DACC_MR Read-write 0x00000000
0x08Conversion Data Register DACC_CDR Write-only 0x00000000
0x0C Interrupt Enable Register DACC_IER Write-only –
0x10 Interrupt Disable Register DACC_IDR Write-only –
0x14 Interrupt Mask Register DACC_IMR Read-only 0x00000000
0x18Interrupt Status Regi ster DACC_ISR Read-only 0x00000000
0xE4 Write Protect Mode Register DACC_WPMR Read-wr ite 0x00000000
0xE8Write Protect Status Register DACC_WPSR Read-only 0x00000000
0xEC - 0xFC Reserved – – –
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
784
35.7.1 DACC Control Register
Name: DACC_CR
Address: 0x4003C000
Access: Write-only
• SWRST: Software Reset
0 = No effect.
1 = Resets the DACC simulating a hardware reset.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
785
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
35.7.2 DACC Mode Register
Name: DACC_MR
Address: 0x4003C004
Access: Read-write
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• DACEN: DAC enable
• WORD: Word Transfer
• STARTUP: Start-up Time Selection
Start-up Time = (STARTUP+1) * 2 * Clock Period
• CLKDIV: DAC Clock Divider for Internal Trigger
Trigger Period = CLKDIV * Clock Period
31 30 29 28 27 26 25 24
CLKDIV
23 22 21 20 19 18 17 16
CLKDIV
15 14 13 12 11 10 9 8
STARTUP
76543210
– – WORD DACEN TRGSEL TRGEN
Value Name Description
0FREE_RUN External trigger mode disab led. DACC in fre e running mode.
1EXT_TRIG External trigger mode enabled.
Value Name Description
0TRGSEL0 External trigger
1TRGSEL1 TIO Output of the Timer Counter Channel 0
2TRGSEL2 TIO Output of the Timer Counter Channel 1
3TRGSEL3 TIO Output of the Timer Counter Channel 2
4TRGSEL4 Reserved
5TRGSEL5 Reserved
6TRGSEL6 Reserved
Value Name Description
0DISABLED DAC disabled.
1ENABLED DAC enabled.
Value Name Description
0HALF_WORD Half-Word transfer.
1WORD Word Transfer.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
786
35.7.3 DACC Conversion Data Register
Name: DACC_CDR
Address: 0x4003C008
Access: Write-only
• DATA: Data to Convert
Data to convert. Can be one half-word or two half-word s depending on WORD bit in DACC_MR register.
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
787
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
35.7.4 DACC Interrupt Enable Register
Name: DACC_IER
Address: 0x4003C00C
Access: Write-only
• TXRDY: T ransmission Ready Interrupt Enable
Enables ready for transmission interrupt.
• ENDTX: End of PDC Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Enable
Enables end of conv ersion IT.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––TXBUFEENDTXTXRDY
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
788
35.7.5 DACC Interrupt Disable Register
Name: DACC_IDR
Address: 0x4003C010
Access: Write-only
• TXRDY: Transmission Ready Interrupt Disable
Disables ready for transmission interrupt.
• ENDTX: End of PDC Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––TXBUFEENDTXTXRDY
789
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
35.7.6 DACC Interrupt Mask Register
Name: DACC_IMR
Address: 0x4003C014
Access: Read-only
• TXRDY: Transmission Ready Interrupt Mask
• ENDTX: End of PDC Interrupt Mask
• TXBUFE: Buffer Empty Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––TXBUFEENDTXTXRDY
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
790
35.7.7 DACC Interrupt Status Register
Name: DACC_ISR
Address: 0x4003C018
Access: Read-only
• TXRDY: Transmission Ready Interrupt Flag
• ENDTX: End of PDC Interrupt Flag
• TXBUFE: Buffer Empty Interrupt Flag
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––TXBUFEENDTXTXRDY
791
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
35.7.8 DACC Write Protect Mode Register
Name: DACC_WPMR
Address: 0x4003C0E4
Access: Read-write
• WPEN: Write Protec t En ab le
0 = Disables the Write Protect if WPKEY corresponds to 0x 444143 (“DAC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
Protects the DACC Mode Register .
• WPKEY: Write Protect KEY
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x444143 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
792
35.7.9 DACC Write Protect Status Register
Name: DACC_WPSR
Address: 0x4003C0E8
Access: Read-only
• WPROTERR: Write protection error
Indicates a write protection error.
• WPROTADDR: Write protection error address
Indicates the address of the register write request which generated the error.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WPROTADDR
76543210
–––––––WPROTERR
793
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36. SAM4N Electrical Characteristics
36.1 Absolute Maximum Ratings
Table 36-1. Absolute Maximum Ratin gs*
Operating Temperature (Industrial)...................-40°C to + 85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or other conditions beyond those indi-
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature......................................-60°C to + 150°C
Voltage on Input Pins
with Respect to Ground.....................................-0.3V to + 4.0V
Maximum Operating Voltage
(VDDCORE).....................................................................1.32V
Maximum Operating Voltage
(VDDIO).............................................................................3.6V
Total DC Output Current on all I/O lines
100-lead LQFP............................................................. .150 mA
100-ball TFBGA.............................................................150 mA
100-ball VFBGA.............................................................150 mA
64-lead LQFP.................................................................100 mA
64-pad QFN. ... ............................ ... .. ............................ ... 100 mA
48-lead LQFP.................................................................100 mA
48-pad QFN ...................................................................100 mA
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
794
36.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless
otherwise specified.
Notes: 1. Refer to Section 5.2.2 “VDDIO Versus VDDIN”
Table 36-2 . DC Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDCORE DC Supply Core 1.08 1.20 1.32 V
VDDIO DC Supply I/Os (1) 1.62 3.3 3.6 V
VDDPLL PLL and Main Oscillator
Supply 1.08 1.32 V
VIL Input Low-level Voltage PA[0–31], PB[0–14], PC[0–31], NRST -0.3 MIN
[0.8V:0.3 ×
VDDIO]V
VIH Input High-level Voltage PA[0–31], PB[0–14], PC[0–31], NRST MIN
[2.0V:0.7 ×
VDDIO]VDDIO + 0.3V V
VOH Output High-level Voltage PA[0–31], PB[0–14], PC[0–31]
IOL = 4.0mA VDDIO - 0.4V V
VOL Output Low-level V oltage PA[0–31], PB[0–14], PC[0–31]
IOH = 4.0mA 0.4 V
Vhys Hysteresis Voltage PA[0–31], PB[0–14], PC[0–31]
(Hysteresis mode enabled) 150 mV
IOH Source Current
VDDIO [1.65–3.60V]; VOH = VDDIO - 0.4
- PA[0–13], PA[15–28], PA[30–31], PB[0–14], PC[0–3 1]
- PA14, PA29
- NRST
-4
-6
-4
mA
IOL Sink Current
VDDIO [1.65–3.60V]; VOL = 0.4V
- PA[0–13], PA[15–28], PA[30–31], PB[0– 14], PC[0–31]
- PA14, PA29
- NRST
4
6
4
mA
IIL Input Low Pull-up OFF -1 1 µA
Pull-up ON 10 50
IIH Input High Pull-down OFF -1 1 µA
Pull-down ON 10 50
RPULLUP Pull-up Resistor PA[0–31], PB[0–14], PC[0–3 1], NRST 70 100 130 kΩ
RPULLDOWN Pull-down Resistor PA[0–31], PB[0–14], PC[0–31], NRST 70 100 130 kΩ
RODT On-die Series
Termination Resistor PA[4–31], PB[0–9], PB[12–14], PC[0 –31]
PA[0–3] 36
18 Ω
795
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Notes: 1. A 4.7 µF or higher ceramic capacitor must be connected between VDDIN and th e closest GND pin of the device.
This large decoupling capacitor is mandatory to reduce start-up current, improving transient response and noise re jection.
2. To ensure stability, an external 2.2 µF output capacitor, CDOUT must be connected between the VDDOUT and the closest
GND pin of the device. The ESR (Equivalent Series Resistance) of the capacitor must be in the range 0.1 to 10 Ω. Sol i d
tantalum, and multilayer ceramic capacitors are all suitable as output capacitor.
A 100 nF bypass capacitor between VDDOUT and the closest GND pin of the device helps decreasing output no ise and
improves the load transient response.
3. Defined as the current needed to charge external bypass/decoupling capacitor network.
4. Refer to Section 5.2.2 “VDDIO Versus VDDIN”
Table 36-3 . 1.2V Voltage Regulator Characteris tics
Symbol Parameter Conditions Min Typ Max Unit
VDDIN DC Input Voltage Range (4) 1.62 3.3 3.6 V
VDDOUT DC Output Voltage Normal Mode
Standby Mode 1.08 1.2
01.32 V
VO(accuracy) Output Voltage Accuracy ILoad = 0.8 mA to 80 mA (after trimming) -3 3 %
ILOAD Maximum DC Output Current VDDIN ≥ 1.8V
VDDIN < 1.8V 120
40 mA
ILOAD-START Maximum Peak Current during
Startup (3) 370 400 mA
VDROPOUT Dropout Voltage VDDIN = 1.6V; ILoad = Max 400 mV
VLINE Line Regulation VDDIN from 2.7V to 3.6V; ILoad Max 10 30 mV
VLINE-TR Transient Line Regulation VDDIN from 2.7V to 3.6V; tr = tf = 5 µs; ILoad Max 50 150 mV
VLOAD Load Regulation VDDIN ≥ 1.8V; ILoad = 10% to 90% Max 20 40 mV
VLOAD-TR T ransient Load Regulation VDDIN ≥ 1.8V ; I Load = 10% to 90 % Max;
tr = tf = 5 µs 50 150 mV
IQQuiescent Current
Normal Mode; @ ILoad = 0 mA 5
µANormal Mode; @ ILoad = 80 mA 500
Standby Mode 0.02 1
CDIN Input Decoupling Capacitor (1) 4.7 µF
CDOUT Output Decoupling Capacitor (2) 2.2 µF
ESR 0.1 10 Ω
ton Turn on Time
Standby to Normal Mode CDOUT = 2.2 µF, VDDOUT reaches 1.2V (± 3%) 300 µs
toff Turn off Time
Normal to Standby Mode CDOUT = 2.2 µF 40 ms
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
796
Figure 36-1. Core Brownout Output Waveform
Table 36-4. Core Power Supply Brownout Detect or Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VT- Supply Falling Threshold After trimming 0.98 1.0 1.04 V
Vhys Hysteresis Voltage — 110 mV
VT+ Supply Rising Threshold — 0.8 1.0 1.08 V
tRST Reset Period VDDIO rising from 0 to 1.2V ± 10% 90 - 320 µs
IDDON Current Consumption on VDDCORE Brownout Detector enabled 24 µA
IDDOFF Brownout Detector disabled 2
IDD33ON Current Consumption on VDDIO Brownout Detector enabled 24 µA
IDD33OFF Brownout Detector disabled 2
td- VT- Detection Pro pagation Time VDDCORE = VT+ to (VT- - 100 mV) 200 300 ns
tSTART Startup Time From disabled state to enabled state 300 µs
t
VDDCORE
VT-
VT+
BOD OUTPUT
t
td+
td-
Table 36-5. VDDIO Supply Monitor
Symbol Parameter Conditions Min Typ Max Unit
VTSupply Monitor Threshold 16 selectable steps 1.6 3.4 V
VT(accuracy) Threshold Level Accuracy -40 to +85°C -1 +1 %
Vhys Hysteresis Voltage 30 40 mV
IDDON
Current Consumption on VDDCORE
All temperatures, enabled
Normal mode
Standby mode 40
2µA
µA
IDDOFF
25°C, disabled
Normal mode
Standby mode 15.9
5.9 18.6
7.0 32
10.3 µA
nA
tSTART Startup Time From disabled state to enabled state 300 µs
797
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 36-2. VDDIO Supply Monitor
Table 36-6. Threshold Selection
Digital Code Threshold min (V) T hreshold typ (V) Threshold max (V)
0000 1.58 1.6 1.62
0001 1.7 1.72 1.74
0010 1.82 1.84 1.86
00111.941.961.98
0100 2.05 2.08 2.11
0101 2.17 2.2 2.23
0110 2.29 2.32 2.35
0111 2.41 2.44 2.47
1000 2.53 2.56 2.59
1001 2.65 2.68 2.71
1010 2.77 2.8 2.83
1011 2.8 2.92 2.95
1100 3.0 3.04 3.071
1101 3.12 3.16 3.2
1110 3.24 3.28 3.32
1111 3.36 3.4 3.44
VT
VT
+
Vhys
VDDIO
Reset
Table 36-7 . Zero-Power-On Reset Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VT+ Threshold Voltage Rising At start-up 1.45 1.53 1.595 V
VT- Threshold Voltage Falling 1.35 1.45 1.55 V
tRST Reset Period Whole temperature range 100 240 500 µs
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
798
Figure 36-3. Zer o-Po wer-on Reset Characteristics
VT-
VT+
VDDIO
Reset
Table 36-8 . DC Flash Characteristics
Symbol Parameter Conditions Typ Max Unit
ICC Active Current
Random 144-bit Read:
Maximum Read Frequency onto VDDCORE = 1.2V @ 25°C 16 25
mA
Random 72-bit Read:
Maximum Read Frequency onto VDDCORE = 1.2V @ 25°C 10 18
Program onto VDDCORE = 1.2V @ 25°C 3 5
Erase onto VDDCORE = 1.2V @ 25°C 3 5
799
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.3 Power Consumption
Power consumption of the device according to the different Low Power Mode Capabilities (Backup, Wait,
Sleep) and Active mode.
Power consumption on power supply in different modes: Backup, Wait, Sleep and Active.
Power consumption by peripheral: ca lculated as the dif ference in current measurement after having enabled
then disabled the corresponding clock.
36.3.1 Backup Mode Current Consumption
The Backup mode configuration and measurements are defined as follow.
Figure 36-4. Me asurement Setup
36.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTT used
One WKUPx enabled
Current measurement on AMP1 (see Figure 36-4, BOD disabled)
36.3.1.2 Configuration B: 32 kHz Crystal Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTT used
One WKUPx enabled
Current measurement on AMP1 (see Figure 36-4, BOD disabled)
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
Table 36-9. Power Consumption for Backup Mode Configuration A and B
Conditions Tota l Co ns ump t io n (AMP1 )
Configuration A Total Consumption (AMP1)
Configuration B Unit
VDDIO = 3.3V @ 25°C
VDDIO = 3.0V @ 25°C
VDDIO = 2.5V @ 25°C
VDDIO = 1.8V @ 25°C
1.4
1.3
1.1
0.9
1.3
1.1
1.0
0.7
µA
VDDIO = 3.3V @ 85°C
VDDIO = 3.0V @ 85°C
VDDIO = 2.5V @ 85°C
VDDIO = 1.8V @ 85°C
4.54
4.24
3.75
3.17
4.57
4.17
3.68
3.1
µA
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
800
36.3.2 Sleep and Wait Mode Current Consumption
The Wait mode and Sleep mode configuration and measurements are defined below.
Figure 36-5. Me asurement Setup for Sleep Mode
36.3.2.1 Sleep Mode
Core Clock OFF
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator
Fast start-up through pins WKUP0–15
Current mea su re m en t as sh own in figure Figure 36-5
All peripheral clocks deactivated
TA = 25°C
Table 36-10 gives current consumption in typical conditions.
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
Table 36-10. Typical Current Consumption for Sleep Mode
Conditions VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit
Figure 36-5 @ 25 °C MCK = 48 MHz
There is no activity on the I/Os of the device. 2.41 3.28 mA
801
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 36-6. Curren t Cons umption in Sleep Mode (AMP1) vs Master Clock Ranges (r efer to T able 36-11 and Table 36-12)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.125
0.25
0.5
1
2
4
8
12
24
32
48
60
72
80
mA
MHz
Sleep Mode SAM4N8/16 I
DDCORE
IDDCORE
Table 36-1 1. Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA
Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit
80 3.99 5.23 mA
72 3.60 4.75 mA
60 3.01 4.02 mA
48 2.41 3.28 mA
32 1.63 2.32 mA
24 1.23 1.84 mA
Table 36-12. Sleep Mode Current Consumption versus Master Clock (MCK) Variation with RC
Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit
12 0.77 1.69 mA
8 0.53 1.46 mA
4 0.29 0.92 mA
2 0.19 0.82 mA
1 0.15 0.78 mA
0.5 0.12 0.75 mA
0.25 0.11 0.74 mA
0.125 0.11 0.73 mA
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
802
36.3.2.2 Wait Mode
Figure 36-7. Measurement Setup for Wait Mode
Core clock and master clock stopped
Current measurement as shown in the above figur e (BOD disabled)
All peripheral clocks deactivated
Table 36-13 gives current consumption in typical conditions.
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
Table 36-13. Typical Current Consumption in Wait Mode
Conditions
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2) Unit
See Figure 36-7 @ 25°C
There is no activity on the I/Os of the device. With the Flash in Standby Mode 16 28.4
µA
See Figure 36-7 @ 25°C
There is no activity on the I/Os of the device. With the Flash in Deep Power Down Mode 15.8 23.9
See Figure 36-7 @ 85°C
There is no activity on the I/Os of the device. With the Flash in Standby Mode 209 227
See Figure 36-7 @ 85°C
There is no activity on the I/Os of the device. With the Flash in Deep Power Down Mode 209 223
803
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.3.3 Active Mode Power Consumption
The Active Mode configuration and measurements are defined as follows:
VDDIO = VDDIN = 3.3V
Application running from Flash memory with 128-bit access mode
All peripheral clocks ar e de a ctiva te d
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator
Current measurement on AMP1 (VDDCORE) and total current on AMP2
Figure 36-8. Active Mode Me asu rement Setup
Table 36-14 gives Active mode current consumption in typical conditions:
VDDCORE at 1.2V
TA = 25°C
Note: 1. Flash W ait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 36-14. CoreMark Active Power Consumption
Core Clock (MHz)
CoreMark
Unit
128-bit Flash Access(1) 64-bit Flash Acce ss(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP1 AMP2
80 11.62 16.63 8.58 13.44 8.91 12.24
mA
72 11.33 16.15 8.93 13.13 7.89 10.94
60 9.76 14.00 7.49 11.09 6.70 9.24
48 9.07 12.48 6.72 10.35 5.46 7.52
32 6.74 9.69 5.36 8.12 3.75 5.17
24 5.14 8.53 4.84 7.46 2.88 4.30
12 3.36 4.49 2.68 3.52 1.52 1.54
8 2.27 3.19 1.73 2.89 1.00 1.03
4 1.19 2.20 0.97 2.51 0.53 0.55
2 0.64 1.13 0.53 1.18 0.30 0.32
1 0.35 0.71 0.30 0.68 0.19 0.21
0.5 0.21 0.39 0.18 0.42 0.13 0.15
0.25 0.15 0.23 0.13 0.26 0.10 0.12
0.125 0.11 0.18 0.10 0.18 0.10 0.12
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
804
Figure 36-9. SAM4N8/16 Ac tive Power Consumption with VDDCORE @ 1.2V, TA = 25°C
0
5
10
15
20
25
30
0,125
0,25
0,5
1
2
4
8
12
24
32
48
60
72
80
Total consumpon (mA)
Frequency (MHz)
128-bit Flash Access
64-bit Flash Access
SRAM
805
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 36-15 gives Active mode current consumption in conditions:
VDDCORE at 1.2V
TA = 85°C
Note: 1. Flash W ait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 36-15. CoreMark Active Power Consumption
Core Clock (MHz)
CoreMark
Unit
128-bit Flash Access(1) 64-bit Flash Acce ss(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP1 AMP2
80 11.29 16.53 8.54 13.53 9.10 12.49
mA
72 11.80 16.09 8.46 13.17 8.07 11.14
60 9.31 14.02 7.49 11.23 6.89 9.50
48 8.56 12.56 6.80 10.52 5.68 7.76
32 6.87 9.85 5.91 8.24 3.96 5.42
24 5.44 8.00 5.02 7.55 3.09 4.55
12 3.54 4.58 2.67 3.75 1.76 1.78
8 2.45 3.56 1.89 3.06 1.21 1.24
4 1.43 2.27 1.16 2.67 0.74 0.76
2 0.84 1.36 0.73 1.43 0.51 0.53
1 0.55 0.90 0.50 0.87 0.40 0.42
0.5 0.41 0.58 0.39 0.60 0.34 0.36
0.25 0.35 0.42 0.34 0.45 0.31 0.33
0.125 0.32 0.38 0.31 0.37 0.31 0.33
SAM4N8/SAM4N16 [DATASHEET]
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806
Table 36-16 gives Active mode current consumption in conditions:
VDDCORE at 1.2V
TA = -40°C
Note: 1. Flash W ait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 36-16. CoreMark Active Power Consumption
Core Clock (MHz)
CoreMark
Unit
128-bit Flash Access(1) 64-bit Flash Acce ss(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP1 AMP2
80 11.84 17.21 8.52 13.51 8.56 12.16
mA
72 11.50 16.68 8.58 13.22 7.8 11.04
60 9.81 14.40 7.34 11.50 6.62 9.37
48 9.16 12.77 6.80 10.32 5.41 7.67
32 6.24 9.68 5.46 8.39 3.71 5.36
24 5.43 9.43 5.02 7.70 2.85 4.51
12 3.30 4.74 2.59 3.71 1.46 1.90
8 2.25 3.57 1.81 2.89 0.51 1.42
4 1.03 2.84 0.96 2.82 0.51 0.96
2 0.61 1.56 0.52 1.50 0.28 0.75
1 0.34 1.10 0.29 1.01 0.17 0.64
0.5 0.19 0.78 0.18 0.77 0.12 0.58
0.25 0.14 0.66 0.12 0.63 0.09 0.56
0.125 0.10 0.56 0.09 0.56 0.09 0.56
807
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 36-17 gives Active mode current consumption in conditions:
VDDCORE at 1.08V
TA = 25°C
Note: VDDCORE supplied by external power supply, so IDDOUT = IDDPLL. With MCK < 12 MHz, PLL not used, IDDOUT =
IDDPLL = 0.
Note: 1. Flash W ait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 36-17. CoreMark Active Power Consumption
Core Clock (MHz)
CoreMark
Unit
128-bit Flash Access(1) 64-bit Flash Acce ss(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP1 AMP2
80 11.70 4.96 9.10 4.58 8.29 3.37
mA
72 11.60 4.87 8.37 4.29 7.50 3.03
60 9.88 4.15 7.15 3.87 6.33 2.54
48 8.25 3.38 6.52 3.35 5.12 2.04
32 6.66 2.68 5.11 2.63 3.48 1.44
24 6.10 2.76 4.69 2.52 2.65 1.42
12 3.11 1.16 2.27 0.97 1.35 0.02
8 1.80 1.06 1.59 1.16 0.92 0.02
4 1.06 1.01 0.89 1.51 0.48 0.02
2 0.55 0.62 0.49 0.81 0.28 0.02
1 0.32 0.35 0.28 0.38 0.17 0.02
0.5 0.19 0.18 0.17 0.21 0.12 0.02
0.25 0.13 0.11 0.12 0.15 0.10 0.02
0.125 0.10 0.07 0.10 0.10 0.08 0.02
SAM4N8/SAM4N16 [DATASHEET]
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808
36.3.4 Peripheral Power Consumption in Active Mode
36.4 Oscillator Characteristics
36.4.1 32 kHz RC Oscillator Characteristics
Table 36-18. Power Consumption on VDDCORE (VDDIO = 3.3V, VDDCORE = 1.08V, TA = 25°C )
Peripheral Consumption (Typ) Unit
PIO Controller A (PIOA) 2.68
µA/MHz
PIO Controller B (PIOB) 1.47
PIO Controller C (PIOC) 2.94
UART0
UART1
UART2
UART3
2.60
3.09
2.96
0.93
USART0
USART1
USART2
4.07
4.03
4.67
PWM 2.21
TWI0
TWI1
TWI2
3.28
2.84
2.86
SPI 2.68
Timer Counter 0 (TC0)
TC1
TC2
TC3
TC4
TC5
1.95
1.15
2.42
1.93
1.22
1.23
ADC 3.06
DACC 1.74
Table 36-19. 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC RC Oscillator Frequency 20 32 44 kHz
Frequency Supply Dependency -3 3 %/V
Frequency Temperature
Dependency Over temperature range (-40 to 85 °C) versus
TA25°C -7 7 %
Duty Duty Cycle 45 50 55 %
tSTART Start-up Time 100 µs
IDDON Current Consumption After Startup T ime
Temp. range = -40 to 125 °C
Typical consumption at 2.2V supply and TA 25 °C 540 860 nA
809
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.4.2 4/8/12 MHz RC Oscillators Characteristics
Notes: 1. Frequency range can be configured in the Supply Controller Registers
2. Not trimmed from factory
3. After Trimming from factory
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB
Bit command (see EEFC section) and the frequency can be trimmed by software through the PMC.
Table 36-2 0. 4/8/12 MHz RC Oscillators Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC RC Oscillator Frequency Ran ge (1) 412MHz
ACC44 MHz Total Accuracy -40°C < Temp < +85°C
4 MHz output selected (1)(2) ±30 %
ACC88 MHz Total Accuracy
-40°C < Temp < +85°C
8 MHz output selected (1)(2) ±30 %
-40°C < Temp < +85°C
8 MHz output selected (1)(3) ±5
ACC12 12 MHz Total Accuracy
-40°C < Temp < +85°C
12 MHz output selected (1)(2) ±30 %
-40°C < Temp < +85°C
12 MHz output selected (1)(3) ±5
Frequency Deviation vs Trimming Code 8 MHz
12 MHz 47
64 kHz/trimming code
Duty Duty Cycle 45 50 55 %
tSTART Star tup Time 10 µs
Output clock edge 6 edge
tontrim Stabilizi ng time 5µs
IDD(standby) Standby Consumption 3 µA
IDDON
Active Current Consumption(2) 4 MHz
8 MHz
12 MHz
50
65
82
75
95
118 µA
Active Current Consumption(3) 4 MHz
8 MHz
12 MHz
50
65
82
68
86
102 µA
SAM4N8/SAM4N16 [DATASHEET]
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36.4.3 32.768 kHz Crystal Oscillator Characteristics
Note: 1. RS is the series resistor.
Figure 36-10. 32.768 kHz Crystal Oscillator Schematics
CLEXT = 2 × (Ccrystal – Cpara – CPCB)
where:
CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
36.4.4 32.768 kHz Crystal Characteristics
Table 36-21. 32 .768 kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC Operating Frequency Normal mode with crystal 32.768 kHz
Vrip(VDDIO) Supply Ripple Voltage (on VDDIO) RMS value, 10 kHz to 10 MHz 30 mV
Duty Cycle 40 50 60 %
tSTART Startup Time
RS < 50 kΩ(1) Ccrystal = 12.5 pF
Ccrystal = 6 pF 900
300 ms
RS < 100 kΩ(1) Ccrystal = 12.5 pF
Ccrystal = 6 pF 1200
500
IDDON Current consumption
RS < 50 kΩ(1) Ccrystal = 12.5 pF
Ccrystal = 6 pF 550
380 1150
980 nA
RS < 100 kΩ(1) Ccrystal = 12.5 pF
Ccrystal = 6 pF 820
530 1600
1350
PON Drive level 0.1 µW
RfInternal Resistor Between XIN32 and XOUT32 10 MΩ
CLEXT Maximum External Capacitor
on XIN32 and XOUT32 20 pF
Ccrystal Allowed Crystal Capacitance Load F rom crystal specification 6 12.5 pF
Cpara Internal Parasitic Capacitance 0.6 0.7 0.8 pF
XIN32 XOUT32
CLEXT CcrystalCLEXT
SAM4
Table 36-22. Cr ystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor (RS) Crystal @ 32.768 kHz 50 10 0 kΩ
CmMotional Capacitance Crystal @ 32.768 kHz 0.6 3 fF
CSHUNT Shunt Capacitance Crystal @ 32.768 kHz 0.6 2 pF
CLOAD Load Capacitance Cystal @ 32.768 kHz
Max external capacitor 20 pF 612.5pF
811
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.4.5 3 to 20 MHz Crystal Oscillator Characteristics
Figure 36-11. 3 to 20 MHz Crystal Oscillator Schematics
CLEXT = 2 × (Ccrystal – CL – CPCB)
where:
CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
Table 36-23. 3 to 20 MHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC Operating Frequency Normal mode with crystal 3 16 20 MHz
Vrip(VDDPLL) Supply Ripple Voltage (on VDDPLL) RMS value, 10 kHz to 10 MHz 30 mV
Duty Cycle 40 50 60 %
tSTART Startup Time
3 MHz, CSHUNT = 3 pF
8 MHz, CSHUNT = 7 pF
16 MHz, CSHUNT = 7 pF with Cm = 8 fF
16 MHz, CSHUNT = 7 pF with Cm = 1.6 fF
20 MHz, CSHUNT = 7 pF
14.5
4
1.4
2.5
1
ms
IDDON Current Consumption (on VDDIO)
3 MHz
8 MHz
16 MHz
20 MHz
230
300
390
450
350
400
470
560
µA
PON Drive Leve l 3 MHz
8 MHz
16 MHz, 20 MHz
15
30
50 µW
RfInternal Resistor Between XIN and XOUT 0.5 MΩ
CLEXT Maximum External Cap acitor on XIN and
XOUT 17 pF
CINTLOAD Internal Load Capacitance Integrated load capacitance ((XIN)
(GND) and (XOUT)(GND) in series) 7.5 9 10.5 pF
CLOAD Internal Equivalent Load Capacitance Integrated Load Capacitance
(XIN and XOUT in series) 7.5 9 10.5 pF
XIN XOUT
C
LEXT
C
L
C
LEXT
C
Crystal
SAM4
R = 1K if Crystal Frequency
is lower than 8 MHz
SAM4N8/SAM4N16 [DATASHEET]
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36.4.6 3 to 20 MHz Crystal Characteristics
36.4.7 3 to 20 MHz XIN Clock Input Characteristic s in Bypass Mode
Figure 36-12. XIN Cloc k Timing
Table 36-24. Cr ystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor (Rs)
Fundamental @ 3 MHz
Fundamental @ 8 MHz
Fundamental @ 16 MHz
Fundamental @ 20 MHz
200
100
80
50
Ω
CmMotional Capacitance 8fF
CSHUNT Shunt Capacitance 7pF
CLOAD Load Capacitance Max external capacitors: 17 pF 12.5 17.5 pF
Table 36-25. XIN Clock Electrical Characteristics (In Bypass Mode)
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPXIN) XIN Clock Frequency
3–20 MHz crystal
oscillator is in
Bypass mode
20 MHz
tCPXIN XIN Clock Period 50 ns
tCHXIN XIN Clock High Half-period 20 ns
tCLXIN XIN Clock Low Half-period 20 ns
tCLCH Rise Time 15 ns
tCHCL Fall Time 15 ns
VXIN_IL VXIN Input Low-level Voltage -0.3 [0.8V :0.3 × VDDIO]V
VXIN_IH VXIN Input High-level Voltage [2.0V:0.7 × VDDIO]V
VDDIO + 0.3V V
tCPXIN
tCLXIN
tCHXIN tCLCH tCHCL
VXIN_IL
VXIN_IH
813
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.4.8 Crystal Oscillator Design Considerations Information
36.4.8.1 Choosing a Crystal
When choosing a crystal for the 32.768 kHz Slow Clock Oscillator or for the 3–20 MHz oscillator, several
parameters must be taken into account. Important parameters between crystal and SAM4N specifications are as
follows:
Load Capacitance
Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the
target frequency. The crystal must be chosen according to the internal load capacitance (CLOAD) of the on-
chip oscillator. Having a mismatch for the load capacitance will result in a frequency drift.
Drive Level
Crystal Drive Level ≥ Oscillator Drive Level. Having a crystal drive level number lower than the oscillator
specification may damage the crystal.
Equivalent Series Resistor (ESR)
Crystal ESR ≤ Oscillator ESR max. Having a crystal with ESR value higher than the oscillator may cause the
oscillator to not start.
Shunt Capacitance
Max. Crystal Shunt Capacitance ≤ Oscillator Shunt Capacitance (CSHUNT). Having a crystal with ESR value
higher than the oscillator may cause the oscillator to not start.
36.4.8.2 Printed Circuit Board (PCB)
SAM4N oscillators are low-power oscillators requiring particular attention when designing PCB systems.
36.5 PLL Characteristics
Table 36-26. Supply Voltage Phase Lock L oo p Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDPLLR Supply Voltage Range 1.08 1.2 1.32 V
Vrip(VDDPLL) Allowabl e Voltage Ripple RMS value 10 kHz to 10 MHz
RMS value > 10 MHz 20
10 mV
Table 36-27. PLL Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fIN Input Frequency 8 32 MHz
fOUT Output Frequency 80 240 MHz
IPLL Current Consumption
Active mode @ 80 MHz @ 1.2V
Active mode @ 96 MHz @ 1.2V
Active mode @ 160 MHz @ 1.2V
Active Mode @ 240 MHz @ 1.2V
0.94
1.2
2.1
3.34
1.2
1.5
2.5
4
mA
tsSettling Time 60 150 µs
SAM4N8/SAM4N16 [DATASHEET]
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814
36.6 10-bit ADC Characteristics
Note: 1. The full speed is obtained for an input source impedance < 50 Ω or tTRACK = 500 ns.
Note: 1. Reference voltages must be decoupled externally with large capacitors: 1 µF/10 nF.
Table 36-2 8. Analog Power Supply Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VVDDIN
VVDDcore
ADC Analog Supply
ADC Digital Supply 1.62
1.08 3.0
1.2 3.6
1.32 V
Vrip(max) Max. Voltage Ripple RMS value, 10 kHz to 10 MHz 30 mV
IVDDIN Current Consumption Normal mode
Standby mode 220
1290 µA
IVDD Current Consumption Normal mode
Standby mode 1 10 µA
Table 36-2 9. Channel Conversion Time and ADC Clock
Symbol Parameter Conditions Min Typ Max Unit
fADC ADC Clock Frequency 1 16 MHz
tCP_ADC ADC Clock Period 62.5 1000 ns
tCONV ADC Conversion Time ADC clock frequency = 16MHz 1.45 µs
fSSampling Rate
VVDDIN > 3V @Temperature max
@ fADC = 16 MHz 510
ksps
VVDDIN > 3V
@ fADC = 14 MHz 450
VVDDIN > 2.4V
@ fADC = 14 MHz 380
VVDDIN < 2.4V
@ fADC = 10 MHz 300
tSTART ADC Startup time After normal mode 40 µs
tTRACK Track and Hold T ime VDDIN < 3.0V
3.0V < VDDIN < 3.6V(1) 1000
500 ns
Table 36-30. External Voltage Reference Input
Parameter Conditions Min Typ Max Unit
ADVREFP Input Voltage Range(1) Positive Reference Input Vrefn + 1.62 – VDDIN V
ADVREFN Input Voltage Range(1) Negative Reference Input 0 – – V
ADVREF Current – 250 400 µA
815
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.6.1 Static Performance Characteristics
In the following tables, the LSB is relative to analog scale:
Single Ended (ex: ADVREFP = 3.0V),
Gain = 1, LSB = (3.0V / 1024) = 2.93 mV
Note: 1. Single ended or differential mode, any gain values.
36.6.1.1 Track and Hold Time versus Source Output Impedance
The following figure shows a simplified acquisition path.
Figure 36-1 3. Simplified Acquisi tion Path
During the tracking phase the ADC needs to track the input signal during the tracking time shown below:
10-bit mode: tTRACK = 0.12 × ZSOURCE + 500 (for 3.0V < VDDIO < 3.6V)
10-bit mode: tTRACK = 0.12 × ZSOURCE + 1000 (for VDDIO < 3.0V)
With tTRACK expressed in ns and ZSOURCE expressed in ohms.
Table 36-31. Static Perfo rmance Characteristics (1)
Symbol Parameter Conditions Min Typ Max Unit
Native ADC Resolution 10 bit
Resolution with Digital Averaging See ADC Controller 10 12 bit
INL Integral Non-linearity Native ADC resolution -2 +2 LSB
DNL Differential Non-linearity Native ADC resolution -1 +1 LSB
EOOffset Error Native ADC resolution -5 5 LSB
EGGain Error Native ADC resolution -3 +3 LSB
Table 36-32. Dynamic Performance Characteristics
Symbol Parameter Conditions Min Typ Max Unit
SNR Signal to Noise Ratio 55 60 61 dB
THD Total Harmonic Distortion -68 -55 dB
SINAD Signal to Noise and Distortion 52 59 dB
ENOB Effective Number of Bits 8.3 9.6 10 bit
Sample & HoldMux.
ZSOURCE RON
Ci
ADC
Input
12-bit ADC
SAM4N8/SAM4N16 [DATASHEET]
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816
Note: 1. Input voltage range can be up to VDDIN without destruction or over-consumption.
If VDDIO < VADVREFP max input vo ltage is VDDIO.
Notes: 1. Default value
2. Minimum value
3. Maximum value
Table 36-33. An alog Inputs
Symbol Parameter Min Typ Max Unit
VIR Input Voltage Range(1) 0V
ADVREFP
CiInput Capacitance 6 pF
ZSOURCE Input Source Impedance 50 Ω
Table 36-34. Programmable Voltage Reference Selection Values
ADC_ACR.IRVS Field Value VREF (V)
02.426
(1)
12.305
22.184
32.063
41.941
51.820
61.699
71.578
(2)
83.396
(3)
93.275
10 3.154
11 3.032
12 2.911
13 2.790
14 2.669
15 2.547
817
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.7 10-bit DAC Characteristics
External voltage reference for DAC is ADVREFP. See the ADC voltage reference char acteristics in Table 36 -30 on
page 814.
Table 36-35. Analog Power Supply Characte ristics
Symbol Parameter Conditions Min Typ Max Unit
VVDDIN DAC Analog Supply 1.62 3.0 3.6 V
VVDDcore DAC Digital Supply 1.08 1.2 1.32
IVDDIN Current Consumption On VDDIN 200 280 360 µA
IVREFP Current Consumption On VREF 35 130 180 µA
IDD(standby) Standby Current Consumption On VREF
On VDDIN
On VDDCORE
2.2
1.5
200
µA
µA
nA
Table 36-36. Channel Conve rsion Time and DAC Clock
Symbol Parameter Conditions Min Typ Max Unit
fDAC Clock Frequency Duty cycle is 50% 1 MHz
tCP_DAC Clock Period 1 µs
tSTART Startup time 20 µs
tCONV Conversion Time 1 tCP_DAC
Table 36-37. Static Performance Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Resolution 10 bit
DACin DAC IN RANGE 0 1023 code
INL Integral Non-linearity Code Range [32 to 991] -2 +2 LSB
DNL Differential Non-linearity Code Range [32 to 991] -1 +1 LSB
EOOffset Error DACin = Mid Code -10 +10 LSB
EGGain Error -8 +8 LSB
SAM4N8/SAM4N16 [DATASHEET]
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818
36.8 Voltage Reference Description
Note: Unless otherwise noted, Reference Voltage must be decoupled exte rnally with large capacitors: 1 µF/10 nF.
36.9 Temperature Sensor
The temperature sensor is connected to channel 15 of the ADC.
The temp erature sen sor provides an output voltage (VO_TS) that is proportional to absolute temperature (PTAT).
VO_TS linearly varies with a temperature slope dVO_TS/dT = 4.72 mV/°C.
VO_TS equals 1.44V at TA 27°C, with a ±60 mV accur acy. The VO_TS slope versus temperature d VO_TS/dT = 4.72
mV/°C only shows a ±7% slight variation over process, mismatch and supply voltage.
The user need s to calibrate it (offse t calibration) a t ambient tempe rature to eliminat e the VO_TS spread at ambient
temperature (±15%).
Table 36-38. Voltage Reference Cha racteristics
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Reference Voltage Internal Available 2 3.4 V
VREF Reference Voltage 1.6 3.4 V
VREFACC Reference Voltage Accuracy -50 50 mV
IVDD Current Consumption Active mode 20 30 µA
IDDBIAS Current Consumption Voltage reference Off, ADC On or DAC On 7 10 µA
IDD(standby) Standby Current VDD @ 3.6V, leakage current 700 nA
IVDDI Current Consumption, Digital 70 nA
IVDDI(standby) Standby Current Consumption, Digital 50 n A
tSTART Startup time VDD @ 2V
VDD @ 3V
VDD @ 3.6V 50 100
70
40 µs
Table 36-39. Temperature Sensor Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Power Supply 2.4 3.3 3.6 V
VO_TS Output Voltage TA = 27°C 1.44 V
VO_TS(accuracy) Output Voltage Accuracy TA = 27°C (needs to be calibrated in
application) -60 60 mV
dVO_TS/dT Temperature Sensitivity (Slope
Voltage vs Temperature 4.72 mV/°C
Slope Accuracy Over temperature range -40 to 85 °C -7 7 %
Temperature Accuracy
After offse t cali bration
Over temperature range -40 to 85 °C -8 +8 °C
After offse t cali bration
Over temperature range 0 to 80 °C -4 +4 °C
tSTART Startup Time 510µs
IVDDCORE Current Consumption Active mode 50 70 80 µA
Standby mode 1
819
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10 AC Characteristics
36.10.1 Master Clock Characteristics
36.10.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%–60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Table 36-40. Master Clock Waveform Parameter s
Symbol Parameter Conditions Min Max Unit
1/(tCPMCK) Master Clock Frequency VDDC ORE @ 1.20V 100 MHz
VDDCORE @ 1.08V 80
Table 36-41. I/O Characteristics
Symbol Parameter Conditions Min Max Unit
FreqMax1 Pin Group 1 (1) Maximum Output Frequency 10 pF
VDDIO = 1.62V
70 MHz
25 pF 35
PulseminH1Pin Group 1 (1) High Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
PulseminL1Pin Group 1 (1) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax2 Pin Group 2 (2)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH2Pin Group 2 (2) High Level Pulse Width 10 pF 7.2 ns
25pF 14.2
PulseminL2Pin Group 2 (2) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax3Pin Group 3(3) Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH3Pin Group 3 (3) High Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
PulseminL3Pin Group 3 (3) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax4 Pin Group 4(4)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH4Pin Group 4(4) High Level Pulse Width 10 pF 7.2 ns
25pF 14.2
PulseminL4Pin Group 4(4) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax5 Pin Group 5(5)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
820
Notes: 1. Pin Group 1 = PB0
2. Pin Group 2 = PA[22–17], PB[2–3], PB[13–14], PC[12–13], PC[15], PC[29–3 1]
3. Pin Group 3 = PB[1]
4. Pin Group 4 = PA[0–6], PA[9–11], PA[15–16], PA[23–28], PA[30–31], PB[4–7], PB[10–11], PC[0–11], PC[14], PC[16–28]
5. Pin Group 5 = PA[12]
6. Pin Group 6 = PA[13]
7. Pin Group 7 = PA[14], PA [19]
8. Pin Group 8 = PA[8–7], PB[8 –9]
9. Pin Group 9 = PB[12]
PulseminH5Pin Group 5(5) High Level Pulse Width 10 pF
VDDIO = 1.62V
7.2 ns
25 pF 14.2
PulseminL5Pin Group 5(5) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax6 Pin Group 6(6)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH6Pin Group 6(6) High Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
PulseminL6Pin Group 6(6) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax7 Pin Group 7(7)Maximum Output Frequency 10 pF 70 MHz
30 pF 45
PulseminH7Pin Group 7(7) High Level Pulse Width 10 pF 7.2 ns
30 pF 11
PulseminL7Pin Group 7(7) Low Level Pulse Width 10 pF 7.2 ns
30 pF 11
FreqMax8Pin Group 8(8)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH8Pin Group 8(8) High Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
PulseminL8Pin Group 8(8) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
FreqMax9 Pin Group 9(9)Maximum Output Frequency 10 pF 70 MHz
25 pF 35
PulseminH9Pin Group 9(9) High Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
PulseminL9Pin Group 9(9) Low Level Pulse Width 10 pF 7.2 ns
25 pF 14.2
Table 36-41. I/O Characteristics (Continued)
Symbol Parameter Conditions Min Max Unit
821
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10.3 SPI Characteristics
Figure 36-14. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
Figure 36-15. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
Figure 36-16. SPI Slave Mod e with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1
SPCK
MISO
MOSI
SPI
5
SPI
3
SPI
4
SPCK
MISO
MOSI
SPI
6
SPI
7
SPI
8
NPCSS
SPI
12
SPI
13
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
822
Figure 36-17. SPI Slave Mod e with(CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
36.10.3.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master re ad and w rite mo des an d in Slav e read and w rite
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or
SPI5) timing. Since it gives a maximum fre que ncy abo ve the maximu m p ad speed ( see Se ction 36.1 0.2 “I/O
Characteristics”), the maximum SPI frequency is defined by the pin FreqMax value.
Master Read Mode
tvalid is the slave time r esponse to ou tput data after detectin g an SPCK ed ge. For a non -volati le memor y with
tvalid (or tv) = 12 ns, fSPCKmax = 43 MHz at VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold
timings SPI7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave
read mode is given by SPCK pad.
Slave Write Mode
For 3.3V I/O domain and SPI6, fSPCKMax = 42 MHz. tsetup is the setup time from the master before sampling
data.
SPCK
MISO
MOSI
SPI9
SPI10 SPI11
NPCS0
SPI14
SPI15
fSPCKMax 1
SPI0orSPI3
()tvalid
+
------------------------------------------------------
=
fSPCKMax 1
2xS(PI6max orSPI9max
()tsetup)+
-------------------------------------------------------------------------------------
=
823
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10.3.2 SPI Timings
SPI timings are given for the following domains:
3.3V domain: VVDDIO from 2.85 V to 3.6V, maximum external capacitor = 30 pF
1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF
Table 36-42. SPI Timings
Symbol Parameter Conditions Min Max Unit
SPI0MISO Setup Time before SPCK Rises (Master) 3.3V domain 11.1 ns
1.8V domain 14.4 ns
SPI1MISO Hold Time after SPCK Rises (Master) 3.3V doma in 0 ns
1.8V domain 0 ns
SPI2SPCK Rising to MOSI Delay (Master) 3.3V domain -2.5 3.6 ns
1.8V domain -3.1 3.6 ns
SPI3MISO Setup Time before SPCK Falls (Master) 3.3V domain 20.0 ns
1.8V domain 23.5 ns
SPI4MISO Hold Time after SPCK Falls (Master) 3.3V domain 0 n s
1.8V domain 0 ns
SPI5SPCK Falling to MOSI Delay (Master) 3.3V domain -6.5 -2.4 ns
1.8V domain -6.6 -2.2 ns
SPI6SPCK Falling to MISO Delay (Slave) 3.3V domain 3.8 11.7 ns
1.8V domain 4.4 1 5.3 ns
SPI7MOSI Setup Time before SPCK Rises (Slave) 3.3V domain 0 ns
1.8V domain 0 ns
SPI8MOSI Hold Time after SPCK Rises (Slave) 3.3V domain 0.6 ns
1.8V domain 0.7 ns
SPI9SPCK Rising to MISO Delay (Slave) 3.3V domain 3.8 11.6 ns
1.8V domain 4.3 1 4.8 ns
SPI10 MOSI Setup Time before SPCK Falls (Slave) 3.3V domain 0.1 ns
1.8V domain 0.4 ns
SPI11 MOSI Hold Time after SPCK Falls (Slave) 3.3V domain 0.5 ns
1.8V domain 1.0 ns
SPI12 NPCS Setup to SPCK Rising (Slave) 3.3V domain 5.0 ns
1.8V domain 5.2 ns
SPI13NPCS Hold after SPCK Falling (Slave) 3.3V domain 0 ns
1.8V domain 0 ns
SPI14 NPCS Setup to SPCK Falling (Slave) 3.3V domain 5.2 ns
1.8V domain 5.0 ns
SPI15 NPCS Hold after SPCK Falling (Slave) 3.3V domain 0 ns
1.8V domain 0 ns
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
824
Note that in SPI master mode the SAM4N does not sample the data (MISO) on the opposite edge where data
clocks out (MOSI) but the same edge is used as shown in Figure 36-14 and Figure 36-15.
36.10.4 USART in SPI Mode Ti mings
Timings are given in the following domains:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF
Figure 36-18. USART SPI Master Mode
The full speed is obtained for an input source impedance < 50 Ω or tTRACK = 500 ns.
Figure 36-19. USART SPI Slave Mode (Mode 1 or 2)
NSS
SPI0
MSB LSB
SPI1
CPOL = 1
CPOL = 0
MISO
MOSI
SCK
SPI5
SPI2
SPI3
SPI4
SPI4
• MOSI line is driven by the output pin TXD
• MISO line drives the input pin RXD
• SCK line is driven by the output pin SCK
• NSS line is driven by the output pin RTS
SCK
MISO
MOSI
SPI6
SPI7SPI8
NSS
SPI12 SPI13
• MOSI line drives the input pin RXD
• MISO line is driven by the output pin TXD
• SCK line drives the input pin SCK
• NSS line drives the input pin CTS
825
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10.4.1 USART SPI TImings
USART SPI timings are given for the following domains:
3.3V domain: VDDIO from 2.85 V to 3.6V, maximum external capacitor = 25 pF
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 25 pF
Table 36-43. USART SPI Timings
Symbol Parameter Conditions Min Max Unit
Master Mode
SPI0SCK Period 1.8V domain
3.3V domain MCK/6 ns
SPI1Input Data Setup Time 1.8V domain
3.3V domain 0.5 × MCK + 2.8
0.5 × MCK + 2.1 ns
SPI2Input Data Hold Time 1.8V domain
3.3V domain 1.5 × MCK - 0.3
1.5 × MCK - 0.4 ns
SPI3Chip Select Active to Serial Clock 1.8V domain
3.3V domain 1.5 × SPCK - 2.6
1.5 × SPCK - 2.0 ns
SPI4Output Data Setup Time 1.8V domain
3.3V domain -6.5
-3.3 12.7
10.5 ns
SPI5Serial Clock to Chip Select Inactive 1.8V domain
3.3V domain 1 × SPCK - 5.0
1 × SPCK - 3.1 ns
Slave Mode
SPI6SCK Falling to MISO 1.8V domain
3.3V domain 4.4
3.7 19.7
13.3 ns
SPI7MOSI Setup Time before SCK Rises 1.8V domain
3.3V domain 2 × MCK + 1.9
2 × MCK + 1.4 ns
SPI8MOSI Hold Time after SCK Rises 1.8V domain
3.3V domain 0
0ns
SPI9SCK Rising to MISO 1.8V domain
3.3V domain 4.3
3.8 19.4
13.3 ns
SPI10 MOSI Setup Time before SCK Falls 1.8V domain
3.3Vdomain 2 × MCK + 1.5
2 × MCK + 1.3 ns
SPI11 MOSI Hold Time after SCK Fa lls 1.8V domain
3.3V domain 0
0ns
SPI12 NPCS0 Setup to SCK Rising 1.8V domain
3.3V domain 2.5 × MCK + 2.1
2.5 × MCK + 1.8 ns
SPI13NPCS0 Hold after SCK Falling 1.8V domain
3.3V domain 1.5 × MCK + 1.0
1.5 × MCK + 0.5 ns
SPI14 NPCS0 Setup to SCK Falling 1.8V domain
3.3V domain 2.5 × MCK + 2.0
2.5 × MCK + 1.9 ns
SPI15 NPCS0 Hold after SCK Rising 1.8V domai n
3.3V domain 1.5 × MCK + 0.5
1.5 × MCK + 0.3 ns
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
826
36.10.5 Two-wire Serial Interface Characteristics
Table 36-44 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols
refer to Figure 36-20.
Notes: 1. Required only for fTWCK > 100 kHz.
2. Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
3. The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 4) × tMCK
4. The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 4) × tMCK
5. tCPMCK = MCK bus period.
Table 36-4 4. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Unit
VIL Input Low-voltage -0.3 0.3 × VDDIO V
VIH Input High-voltage 0.7 × VDDIO VCC + 0.3 V
Vhys Hysteresis of Schmitt Trigger Inputs 0.150 – V
VOL Output Low-voltage 3 mA sink current - 0.4 V
trRise Time for both TWD and T WCK 20 + 0.1Cb(1)(2) 300 ns
tof Output Fall T ime from VIHmin to VILmax 10 pF < Cb < 400 pF
Figure 36-20 20 + 0.1Cb(1)(2) 250 ns
Ci(1) Capacitance for each I/O Pin – 10 pF
fTWCK TWCK Clock Frequency 0 400 kHz
Rp Value of Pull-up Resi stor fTWCK ≤ 100 kHz (VDDIO - 0.4V) ÷ 3mA 1000ns ÷ CbΩ
fTWCK > 100 kHz (VDDIO - 0.4V) ÷ 3mA 300ns ÷ CbΩ
tLOW Low Period of the TWCK Clock fTWCK ≤ 100 kHz (3) –µs
fTWCK > 100 kHz (3) –µs
tHIGH High period of the TWCK Clock fTWCK ≤ 100 kHz (4) –µs
fTWCK > 100 kHz (4) –µs
th(start) Hold Time (Repeated) START Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
tsu(start) Set-up Time for a Repeated START
Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
th(data) Data Hold Time fTWCK ≤ 100 kHz 0 3 × tCPMCK(5) µs
fTWCK > 100 kHz 0 3 × tCPMCK(5) µs
tsu(data) Data Setup Time fTWCK ≤ 100 kHz tLOW - 3 × tCPMCK(5) –ns
fTWCK > 100 kHz tLOW - 3 × tCP_MCK(5) –ns
tsu(stop) Setup Time for STOP Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
tBUF Bus Free Time between a STOP and
START Condition fTWCK ≤ 100 kHz tLOW –µs
fTWCK > 100 kHz tLOW –µs
827
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 36-20. Two-wire Serial Bus Timing
36.10.6 Embedded Flash Characteristics
The embedded flash is fully tested during production test. The flash contents are not set to a known state prior to
shipment. Therefore, the flash contents should be erased prior to progr amming an application.
The maximum operating frequency given in Table 36-45 is limited by the embedded Flash access time when the
processor is fetching code out of it. The table provides the device maximum operating frequency defined by the
value of the field FWS in the EEFC_FMR. This field defines the number of wait states required to access the
Embedded Flash Memory.
tsu(start)
tLOW
tHIGH
tLOW
tfo
th(start) th(data) tsu(data) tsu(stop)
tBUF
TWCK
TWD
tr
Table 36-45. Embedded Flash Wait State at 85°C
EEFC_FMR.FWS Read Operations
Maximum Operating Frequency (MHz)
VDDCORE 1.08V VDDCORE 1.2V
VDDIO 1.62–3.6 V VDDIO 2.7–3.6 V VDDIO 1.62–3.6 V VDDIO 2.7–3.6 V
0 1 cycle 16 2 0 17 21
1 2 cycles 33 40 35 42
2 3 cycles 50 60 52 63
3 4 cycles 67 80 70 84
4 5 cycles 84 86 87 106
Table 36-4 6. AC Flash Characteristics
Parameter Conditions Min Typ Max Unit
Program Cycle Time
Erase Page Mode 10 50 ms
Erase Block Mode (by 4 Kbytes) 50 200 ms
Erase Sector Mode 400 950 ms
Write Page Mode: write page 1.5 3 ms
Write Page Mo de: write 64-bit Word 20 40 µs
Write Page Mode: write 128-bit Word 40 80 µs
Erase Pin Assertion Time Erase pin high 220 – – ms
Full Chip Erase
1 Mbyte 9 18
s
512 Kbytes 5.5 11
256 Kbytes 3 6
128 Kbytes 2 4
Data Retention Not powered or powered 20 years
Endurance Write/Erase cycles per page, block or sector @ 85°C 10k cycles
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
828
37. SAM4N Mechanical Characteristics
Figure 37-1. 100-lead LQFP Package Mechanical Drawing
This package respects the recommendations of the NEMI User Group.
Table 37-1. Device and 100-lead LQFP Package Maximum Weight
SAM4N 800 mg
Table 37-2. 100-lead LQFP Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 37-3. 100-lead LQFP Package Characteristics
Moisture Sensitivity Level 3
CONTROL DIMENSIONS ARE IN MILLIMETERS.
Note: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
829
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 37-2. 100 -ball TFBGA Package Drawing
This package respects the recommendations of the NEMI User Group.
Table 37-4. 100-ball TFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land Diameter 0.35 mm
Soldering Mask Opening 350 µm
Table 37-5. Device and 100-ball TFBGA Package Maximum Weight
SAM4N 140 mg
Table 37-6. 100-ball TFBGA Package Characteristics
Moisture Sensitivity Level 3
Table 37-7. 100-ball TFBGA Package Reference
JEDEC Drawing Reference MO-275-DDAC-01
JESD97 Classification e8
0.0433
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
830
Figure 37-3. 100-ball VFBGA Package Drawing
831
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
This package respects the recommendations of the NEMI User Group.
Table 37-8. 100-ball VFBGA Package Refe rence - Soldering Information (Substrate Level)
Ball Land Diameter 0.27 mm
Soldering Mask Opening 275 µm
Table 37-9. Device and 100-ball VFBGA Package Maximum Weight
SAM4N 75 mg
Table 37-10. 100-ball VFBGA Package Characteristics
Moisture Sensitivity Level 3
Table 37-11. 100-ball VFBGA Package Reference
JEDEC Drawing Reference MO-275-BBE-1
JESD97 Classification e8
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
832
Figure 37-4. 64-lead LQFP Package Drawing
833
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
This package respects the recommendations of the NEMI User Group.
Table 37-12. 64-lead LQFP Package Dim ensions (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
A – –1.60– –0.063
A1 0.05 – 0.15 0.002 – 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
D 12.00 BSC 0.472 BSC
D1 10.00 BSC 0.383 BSC
E 12.00 BSC 0.472 BSC
E1 10.00 BSC 0.383 BSC
R2 0.08 – 0.20 0.003 – 0.008
R1 0.08 – – 0.003 – –
q 0°3.5°7° 0°3.5°7°
θ10° – – 0° – –
θ211° 12° 13° 11° 12° 13°
θ311° 12° 13° 11° 12° 13°
c 0.09 – 0.20 0.004 – 0.008
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
S 0.20 – – 0.008 – –
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC. 0.020 BSC.
D2 7.50 0.285
E2 7.50 0.285
Tolerances of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
Table 37-13. Device and 64-lead LQFP Package Maximum Weig ht
SAM4N 750 mg
Table 37-14. 64-lead LQFP Package Refer ence
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 37-15. 64-lead LQFP Package Characteristics
Moisture Sensitivity Level 3
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
834
Figure 37-5. 64-pad QFN Package Drawing
835
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
This package respects the recommendations of the NEMI User Group.
Table 37-16. 64-pad QFN Package Dimensions (in mm)
Symbol Millimeter Inch
Min Nom Max Min Nom Max
A – – 090 – – 0.035
A1 – – 0.05 – – 0.001
A2 – 0.65 0.70 – 0.026 0.028
A3 0.20 REF 0.008 REF
b 0.23 0.25 0.28 0.009 0.010 0.011
D 9.00 BSC 0.354 BSC
D2 6.95 7.10 7.25 0.274 0.280 0.285
E 9.00 BSC 0.354 BSC
E2 6.95 7.10 7.25 0.274 0.280 0.285
L 0.35 0.40 0.45 0.014 0.016 0.018
e 0.50 BSC 0.020 BSC
R 0.125 – – 0.0005 – –
Tolerances of Form and Position
aaa 0.10 0.004
bbb 0.10 0.004
ccc 0.05 0.002
Table 37-17. Device and 64-pad QFN Package Maximum Weight (Preliminary)
SAM4N 280 mg
Table 37-18. 64-pad QFN Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification e3
Table 37-19. 64-pad QFN Package Characteristics
Moisture Sensitivity Level 3
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
836
Figure 37-6. 48-lead LQFP Package Drawing
837
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
This package respects the recommendations of the NEMI User Group.
Table 37-20. 48-lead LQFP Package Dimensions (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
A – –1.60– –0.063
A1 0.05 – 0.15 0.002 – 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
D 9.00 BSC 0.354SC
D1 7.00 BSC 0.276 BSC
E 9.00 BSC 0.354 BSC
E1 7.00 BSC 0.276 BSC
R2 0.08 – 0.20 0.003 – 0.008
R1 0.08 – – 0.003 – –
q 0°3.5°7° 0°3.5°7°
θ10° – – 0° – –
θ211° 12° 13° 11° 12° 13°
θ311° 12° 13° 11° 12° 13°
c 0.09 – 0.20 0.004 – 0.008
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
S 0.20 – – 0.008 – –
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC. 0.020 BSC.
D2 5.50 0.217
E2 5.50 0.217
Tolerances of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
Table 37-21. Device and 48-lead LQFP Package Maximum Weig ht
SAM4N 190 mg
Table 37-22. 48-lead LQFP Package Characteristics
Moisture Sensitivity Level 3
Table 37-23. 48-lead LQFP Package Refer ence
JEDEC Drawing Reference MS-026
JESD97 Classification e3
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
838
Figure 37-7. 48-pad QFN Package Drawing
839
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
This package respects the recommendations of the NEMI User Group.
Table 37-24. 48-pad QFN Package Dimensions (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
A – –0.90– –0.035
A1 – – 0.05 – – 0.002
A2 – 0.65 0.70 – 0.026 0.028
A3 0.20 REF 0.008 REF
b 0.18 0.20 0.23 0.007 0.008 0.009
D 7.00 BSC 0.276 BSC
D2 5.45 5.60 5.75 0.215 0.220 0.226
E 7.00 BSC 0.274 BSC
E2 5.45 5.60 5.75 0.215 0.220 0.226
L 0.35 0.40 0.45 0.014 0.016 0.018
e 0.50 BSC 0.020 BSC
R 0.09 – – 0.004 – –
Tolerances of Form and Position
aaa 0.10 0.004
bbb 0.10 0.004
ccc 0.05 0.002
Table 37-25. Device and 48-pad QFN Package Maximum Weight
SAM4N 142 mg
Table 37-26. 48-pad QFN Package Characteristics
Moisture Sensitivity Level 3
Table 37-27. 48-pad QFN Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification e3
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
840
37.1 Soldering Profile
Table 37-28 gives the recommended soldering profile from J-STD-020C.
Note: The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
37.2 Packaging Resources
Land Pattern Definition.
Refer to the following IPC Standards:
IPC-7351A and IPC-782 (Generic Requirements for Surface Mount Design an d Land Pattern Standards)
http://landpatterns.ipc.org/default.asp
Atmel Green and RoHS Policy and Package Material Declaration Data Sheet available on www.atmel.com
Table 37-28. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/sec. max.
Preheat Temperature 175°C ± 25°C 180 sec. max.
Temperature Maintained above 217°C 60 sec. to 150 sec.
Time with in 5°C of Actual Peak Temperature 20 sec. to 40 sec.
Peak Temperature Range 260°C
Ramp-down Rate 6°C/sec. max.
Time 25°C to Peak Temperature 8 min. max.
841
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
38. Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
where
“YY” manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
YYWW V
XXXXXXXXX ARM
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
842
39. Ordering Information
Table 39-1. Ordering Codes for SAM4N Devices
Ordering Code MRL Flash
(Kbytes) RAM
(Kbytes) Package Carrier Type
Operating
Temperature
Range
ATSAM4N 16CA-CFU A 1024 80 VFBGA 100 Tray
Industrial
-40°C to 85°C
ATSAM4N 16CA-CFUR A 1024 80 VFBGA 100 Re el
ATSAM4N16CA-CU A 1024 80 TFBGA100 Tray
ATSAM4N16CA-CUR A 1024 80 TFBGA100 Reel
ATSAM4N16CA-AU A 1024 80 QFP100 Tray
ATSAM4N16CA-AUR A 1024 80 QFP100 Reel
ATSAM4N16BA-AU A 1024 80 QFP64 Tray
ATSAM4N16BA-AUR A 1024 80 QFP64 Reel
ATSAM4N16BA-MU A 1024 80 QFN64 Tray
ATSAM4N16BA-MUR A 1024 80 QFN64 Reel
ATSAM4N8CA-CFU A 512 64 VFBGA 100 Tray
ATSAM4N8CA-CFUR A 512 64 VFBGA 100 Reel
ATSAM4N8CA-CU A 512 64 TFBGA100 Tray
ATSAM4N8CA-CUR A 512 64 TFBGA100 Reel
ATSAM4N8CA-AU A 512 64 QFP100 Tray
ATSAM4N8CA-AUR A 512 64 QFP100 Reel
ATSAM4N8BA-AU A 512 64 QFP64 Tray
ATSAM4N8BA-AUR A 512 64 QFP64 Reel
ATSAM4N8BA-MU A 512 64 QFN64 Tray
ATSAM4N8BA-MUR A 512 64 QFN64 Reel
ATSAM4N8AA-AU A 512 64 QFP48 Tray
ATSAM4N8AA-AUR A 512 64 QFP48 Reel
ATSAM4N8AA-MU A 512 64 QFN48 Tray
ATSAM4N8AA-MUR A 512 64 QFN48 Reel
843
SAM4E [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
40. Errata
40.1 Watchdog
40.1.1 Get a reset at the Wake up of Wait Mode when the Watchdog is enabled
When the Watchdog is enabled and the bit WAITMODE = 1 (en try in Wait mode through WAITMODE bit in
CKGR_MOR). The wakeup of the low power mode (Wait mode) is done by the reset.
Problem Fix/Workaround
Execute the Wait-For-Event (WFE) instruction of the processor Cortex-M4 to enter in Wait mode when the
watchdog is enabled.
40.2 Brownout Detector
40.2.1 Unpredicta ble Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In Active mode or in Wait mode, if the Brownout Detector is disabled (SUPC_MR.BODDIS = 1) and power is lost
on VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE always needs to be powered.
40.3 Flash
40.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State
Flash read issues leading to wrong instruction fetch o r incorrect data read may occur under the following operating
conditions:
VDDIO < 2.4V and Flash wait state(1) ≥ 1
If the core clock frequency does not require the use of the Flash wait state (2) (FWS = 0 in EEFC_FMR), or if only
data reads are pe rformed on the Flash (e.g., if the co de is running out of SRAM), there ar e no constraints on
VDDIO voltage. The usable voltage range for VDDIO is defined in Table 36-2 “DC Characteristics”.
Notes: 1. Defined in FWS field in EEFC_FMR.
2. See Section 36.10.6 “Embedded Flash Characteristics” for the maximum core clock frequency at zero (0) wait
state.
Problem Fix/Workaround
Two workarounds are available:
Reduce the device speed to decrease the number of wait states to 0.
Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
844
41. Revision History
In the tables that follow, the most recent version of the document appears first.
Table 41-1. SAM4N Datasheet Rev. 11158B Revision History
Issue Date Comments
23-Mar-15
Formatting and editorial changes throughout
“Description”:
- in first paragraph, replaced “an RTC” with “a low-power RT C, a low-power RTT”
- added paragraph relating to low-power modes
- added paragraph relating to Real-time Event Management
Section 1. “Features”
Updated description of “Low-power Modes”
Under “Peripherals”:
- updated RTT and RTC descriptions
- added bullet “256-bit General Purpose Backup Registers (GPBR)”
Table 1-1 ”Configuration Summary”: updated footnotes for 16-bit Timer
Revised Section 2. “Block Diagram”
Section 3. “Signals Description”
Table 3-1 ”Signal Description List”: renamed “ADVREF” to “ADVREFP”
Section 4. “Package and Pinout”
Renamed “ADVREF” to “ADVREFP”
Table 4-3 ”SAM4N8/16 100-ball TFBGA Pinout”: transferred AD13 from ball E7 to A2 (E7 is now PA29 and A2 is now
PC29/AD13)
Table 4-4 ”SAM4N8/16 100-ball VFBGA Pinout”: transferred AD13 from ball D6 to C2 (D6 is now PA29 and C2 is now
PC29/AD13)
Section 5. “Power Considerations”:
Inserted new Section 5.2 “Power-up Cons iderations”
Revised Section 5.3 “Voltage Regulator”
Figure 5-3 “Core Externally Supplied”: corrected rang e “2.4V-3.6V” to “1.6 2–3.6 V” for ADC/DAC supply
Figure 5-4 “Core Extern ally Supplied (Backup Battery)”: deleted captio n “ADC, DAC, Analog Comparator Supply (2.0V-
3.6V)”; below figure, added note “For temperature sensor, VDDIO needs to be greater than 2.4V.”
Section 5.5 “Active Mode”: corrected instances of “WUP” to “WKUP” throughout
Added Section 5.6 “Low-power Modes”
Revised Section 5.6.1 “Backup Mode”
Revised Section 5.6.2 “Wait Mode”
Revised Section 5.6.3 “Sleep Mode”
Table 5-1 ”Low Power Mode Configura ti on Summary”: updated contents in columns “Mode Entry” and “Potential W ake-up
Sources”
Updated Section 5.7 “Wake-up Sources”
Updated Section 5.8 “Fast Start up ”
845
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
23-Mar-15
Section 6. “Input/Output Lines”
Section 6.2 “System I/O Lines”: in first paragraph, deleted sentence “System I/O lines are pins used by oscillators, test
mode, reset and JTAG to name but a few.”
Table 6-1 ”System I/O Configuration” : changed column header “SYSTEM_IO Bit Number” to “CCFG_SYSIO Bit No.”
Section 6.5 “ERASE Pin”: in first paragraph, added details relative to reprogamming Flash content; updated content
concerning ERASE pin assertion time
Added Section 6.6 “Anti-tamper Pins/Low-power Tamper Detection”
Removed section 7. “Processor and Architecture”
Section 7. “Memories”
Added Section 7.1 “Product Mapping” (was previously in section 7. “Processor and Architecture”)
Section 9. “System Controller”
Removed Figure 10-1 “System Controller Block Diagram” (reference diagram provided in Section 17. “Supply Controller
(SUPC)”)
Removed subsection 10.3 “Reset Controller” (reset controller described in Section 13. “Reset Controller (RSTC)”)
Removed subsection 10.5 “Chip Identi fication” (chip identification provided in Section 26. “Chip Identifier (CHIPID)”; JTAG
ID provided in Section 12.5.8 “ID Code Register”)
Section 10. “Peripherals”
Table 10-1 ”Peripheral Identifie r s”: inserted two columns “NVIC Interrupt“ and “PMC Clock Control ”
Table 10-2 ”Multiplexing on PIO Controller A (PIOA)”: added footnotes on selecting extra functions and system functions
Table 10-3 ”Multiplexing on PIO Controller B (PIOB)”: added footnotes on selecting extra functions and system functions
Table 10-4 ”Multiplexing on PIO Controller C (PIOC)”: added footnotes on selecting extra functions
Added Section 10.3.3 “Peripheral DMA Controller (PDC)” (was previously in section 7. “Processor and Architecture”)
Section 10.3 “Embedded Periphe rals Overview”
Section 10.3.1 “ Ana l o g Mu x”: in first sentence, corrected “ADC Channel Register” to “ADC Channel Enable Register”
Section 12. “Debug and Test Features”
Section 12.5.2 “Debug Architecture”: in first paragraph, corrected “Cortex-M4 embeds four functional units” to “Cortex-M4
embeds five fu nctional units”
Section 12.5.8 “ID Code Register”: corrected JTAG ID from ‘0x05B2E03F’ to ‘0x05B3_603F’
Section 18. “General Purpose Backup Registers (GPBR)”
Table 18-1 ”Register Mapping”: corrected offset to ‘0x1C’ for General Purpose Backup Register 7
Section 18.3.1 “General Purpose Backup Register x”: added missing last ad dress “0x400E14AC” for SYS_GPBR7
Section 21. “SAM-BA Boot Program”
Section 21.5.3 “In Application Programming (IAP) Featur e”: replaced two instances of “MC_FSR register ” with
“EEFC_FSR”
Table 41-1 . SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
SAM4N8/SAM4N16 [DATASHEET]
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846
23-Mar-15
Section 25. “Power Management Controller (PMC)”
Section 25.5 “Processor Clock Controller”: updated first paragraph to add content on WFE instruction
Section 25.10 “Fast Start-up”: updated second paragraph to add content on WFE instruction
Section 25.16.4 “PMC Peripheral Clock Enable Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.5 “PMC Peripheral Clock Disable Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.6 “PMC Peripheral Clock Status Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.16 “PMC Fast Start-up Mode Register”: ad ded bit LPM (Low Power Mode)
Section 29. “Two-wire Interface (TWI)”
Section 29.11.5 “TWI Clock Waveform Generator Register”: removed HOLD field (register bits 28:24 now reserved)
Section 32. “Timer Counter (TC)”
Instances of “Master clock” or “MCK” replaced with “peripheral clock”
Section 32.1 “Description”: modified first paragraph to read “A Timer Counter (TC) module includes three identical TC
channels. The number of implemented TC modules is device- specific.”
Section 32.2 “Embedded Characteristics”: deleted “Two global registers th at act on all TC channels” from bullet list
Moved Table 32-1 ”Timer Counter Clock Assignment” from Section 32.1 “Description” to Section 32.3 “Block Diagram”
Section 32.5.2 “Power Management”: ad ded “of each channel” after "to enable the Timer Co unter clock"
Section 32.5.3 “Interrupt Sources”: changed title (was “Interrupt”), updated text and added Table 32-5 ”Peripheral IDs”
Figure 32-5 “Example of Transfer with PDC” replaced instances of “Internal PDC trigger” with “Peripheral trigger”
Section 32.6.2 “16-bit Counter”: in first paragraph, replaced instance of “0xFFFF” with “216-1”
Updated list of internal clock signals in Section 32.6. 3 “Clock Selection”
Section 32.6.12.1 “WAVSEL = 00”: replaced instances of “0xFFFF” with “216-1”
Figure 32-10 “WAVSEL = 10 without Trigger” and Figure 32-11 “WAVSEL = 10 with Trigger”: replaced “0xFFFF” with “2n-1
(n = counter size)”
Section 32.6.12.3 “WAVSEL = 01”: replaced instances of “0xFFFF” with “216-1”
Figure 32-14 “WAVSEL = 11 without Trigger” and Figure 32-15 “WAVSEL = 11 with Trigger”: replaced “0xFFFF” with “2n-1
(n = counter size)”
Section 32.6.15.2 “Input Pre-processing”: deleted sentence “Filters can be disabled using the FILTER bit in the TC_BMR”
Figure 32-17 “Input Stage” : replace d “FILTER” with “MAXFILTER > 0”
Section 32.6.15.3 “Direction Status and Change Detection”: rewrote sixth paragraph for clarity
Section 32.6.15.4 “Position and Rotation Measurement”: rewrote first paragraph for clarity; at end of second paragraph,
defined “External Trigger Edge” and “External Trigger” config uration in TC_CMR
Section 32.6.15.5 “Speed Measurement”:
- replaced sentence “The speed can be read on TC_RA0 register in TC_CMR0” with “The speed can be read on field RA in
register TC_R A0”
- in fifth paragraph, replaced “EDGTRG can be set to 0x01” with “ETRGEDG must be set to 0x01”
Section 32.6.18 “Register Write Protection”: modified title (was “Write Protection System”) and revised content
Section 32.7.2 “TC Channel Mode Register: Capture Mode”: in ‘Na me’ line, replaced “(WAVE = 0)” with
“(CAPTURE_MODE)”; updated names internal clock signals in TCCLKS field description (values 0–4)
Section 32.7.3 “TC Channel Mode Register: Waveform Mode”: in ‘Name’ line, replaced “(WAVE = 1)” with
“(WAVEFORM_MODE)”; updated names internal clock signals in TCCLKS field description (values 0–4)
Table 41-1 . SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
847
SAM4N8/SAM4N16 [DATASHEET]
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23-Mar-15
Section 32. “Timer Counter (TC)” (cont’d)
Section 32.7.5 “TC Counter Value Register”: added notation “IMPORTANT: For 16-bit channels, CV field size is limited to
register bits 15:0”
Section 32.7.6 “TC Register A”: added notation “IMPORTANT: For 16-bit channels, RA field size is limited to register bi ts
15:0”
Section 32.7.7 “TC Register B”: added notation “IMPORTANT: For 16-bit channels, RB field size is limited to register bi ts
15:0”
Section 32.7.8 “TC Register C”: added notation “IMPORTANT: For 16-bit channels, RC field size is limited to register bits
15:0”
Section 32.7.9 “TC Status Register”: updated bit descriptions
Section 32.7.14 “TC Block Mode Register”: removed FILTER bit (register bit 19 now reserved); corrected TC2XC2S field
configuration values: value 2 is TIOA0 (was TIOA1); value 3 is TIOA1 (was TIOA2)
Section 32.7.20 “TC Write Protection Mode Register”: modified register name (was “TC Write Protect Mode Register”);
updated WPEN bit description (replaced list of protectable registers with link to Section 32.6.18 “Register Write Protection”)
Section 36. “SAM4N Electrical Characteristics”
Updated and harmonized parameter symbols
Table 36-2 ”DC Characteristics” : replaced two footnotes with single footnote
Table 36-3 ”1.2V Voltage Regulator Characteristics”: replaced two footnotes with single footnote in VDDIN conditions;
deleted “Cf. External Capacitor Requirements” from CDIN and CDOUT conditions
Table 36-4 ”Core Power Supply Brownout Detector Characteristics”: added parameter “Reset Period”
Table 36-7 ”Zero-Power-On Reset Characteristics”: modi fied parameter name “Reset Time-out Period” to “Reset Period”
Table 36-20 ”4/8/12 MHz RC Oscillators Characteristics”: updated Startup Time conditions
Table 36-21 ”32.768 kHz Crystal Oscillator Characteristics”: added parameter “Allowed Crystal Capacitance Load”
Table 36-23 ”3 to 20 MHz Crystal Oscillator Characteristics”: added “pF” unit for “Internal Load Capacitance” parameter;
deleted all footnotes
Section 36.3.3 “Active Mode Power Consumption”: updated conditions (VDDCORE and ambient temperature) for
“CoreMark Active Power Consumption” tables and for Figure 36-9 “SAM4N8/16 Active Power Consumption with
VDDCORE @ 1.2V, TA = 25°C”
Figure 36-10 “32.768 kHz Crystal Oscillator Schematics”: added caption “Ccrystal” to diagram
Updated Figure 36-12 “XIN Clock Timing”
Table 36-27 ”PLL Characteristics”: changed parameter “Start-up Time” to “Settling Time”
Figure 36-13 “Simplified Acquisition Path”: renamed caption “Csample” to “Ci”; renamed caption “12-bit ADC Core” to “12-
bit ADC”
Figure 36-19 “USART SPI Slave Mode (Mode 1 or 2)”: inserted correct diagram (was previously TWI diagram)
Figure 36-20 “Two-wire Serial Bus Timing”: inserted correct di ag ra m (w as pr evi o usly USART diagram)
Section 36.10.3.1 “Maximum SPI Frequency”: updated contents under “Master Write Mode” and “Master Read Mode”
Added Table 36-34 ”Programmabl e Voltage Reference Selection Values”
Table 36-38 ”Voltage Reference Characteristics”: in bias current consumption, corrected conditions “Voltage reference
OFF, ADC ON OR ADC ON” to “Voltage reference Off, ADC On or DAC On”
Table 36-39 ”Temperature Sensor Characteristics”: deleted “After TSON = 1” from Startup Time cond itions
Table 36-42 ”SPI Timings”: removed footnotes defining 1.8V and 3.3V domains (this information is now found at the
beginning of Section 36.10.3.2 “SPI Timings”)
Table 36-43 ”USART SPI Timings”: removed footnotes defining 1.8V and 3.3V domains (this information is now found at
the beginning of Section 36.10.4.1 “USART SPI TImings”)
Table 36-44 ”Two-wire Serial Bus Requirements”: added parameter “Bus free time between a STOP and START condition”
Table 41-1 . SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
SAM4N8/SAM4N16 [DATASHEET]
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848
23-Mar-15
Section 36. “SAM4N Electrical Characteristics” (cont’d)
Section 36.10.6 “Embedded Flash Characteristics” : inserted content abo ut erasing flash content prior to programming an
application; corrected instance of “field FWS of the MC_FMR” to “field FWS in the EEFC_FMR”; replaced four “Embedded
Flash Wai t State” tables with single Table 36-45 ”Embedded Flash Wait State at 85°C”
Table 36-46 ”AC Flash Characteristics”: added parameter “Erase Pin Assertion Time”; added Program Cycle Time values
for Write Page Mode
Section 37. “SAM4N Mechanical Characteristics”
Figure 37-2 “100-ball TFBGA Package Drawing”: corrected ‘A’ maximum dimension in inches from 0.0575 to 0.0433
Added Section 38. “Marking”
Section 39. “Ordering Information”
Table 39-1 ”Ordering Codes for SAM4N Devices”: updated column heade rs; removed “Package Type” column (this
information is provided on the Atmel website)
Added Section 40. “Errata”
Doc. Rev.
11158A Comments
Change
Request
Ref.
First Issue
Table 41-1 . SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
i
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Configuration Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Overview of the 100-lead LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Overview of the 100-ball TFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Overview of the 100-ball VFBGA Package (7 x 7 x 1 mm - 0.65 mm ball pitch). . . . . . . . . . . . . . . . . 9
4.4 100-lead LQFP, TFBGA and VFBGA Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Overview of the 64-lead LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Overview of the 64-lead QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 64-lead LQFP and QFN Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Overview of the 48-lead LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 Overview of the 48-lead QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10 48-lead LQFP and QFN Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 Typical Powering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 Low-power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7 Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8 Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6. Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 System I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Anti-ta mper Pins/Low-power Tamper Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Product Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8. Real-time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.2 Real-time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1 System Controller and Peripherals Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
ii
9.2 Power-on-Reset, Brownout and Supply Mo nitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3 SysTick Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 Peripherals Signals Multiplexing on I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3 Embedded Peripherals Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. ARM Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.4 Cortex-M4 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.6 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.7 Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
11.8 Nested Vectored Interrupt Controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.9 System Control Block (SCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
11.10 System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.11 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
11.12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
12. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.4 Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
12.5 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.4 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
13.5 Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
14. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.4 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
14.5 Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
15.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
15.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
15.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
15.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
15.5 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
15.6 Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
16. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
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16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.4 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
16.5 Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
17. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
17.4 Supply Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
17.5 Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
18. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.3 General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
19. Embedded Flash Controller (EFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
19.1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
19.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
19.3 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
19.4 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
19.5 Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
20. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
20.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
20.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
20.3 Parallel Fast Flash Pro gramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
21. SAM-BA Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.2 Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.3 Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.4 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.5 SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
22. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
22.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
22.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
22.3 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
22.4 Special Bus Granting Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
22.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
22.6 System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
22.7 Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
22.8 Bus Matrix (MATRIX) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
23. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
23.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
23.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
23.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
23.4 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
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23.5 Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
24. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
24.4 Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
24.5 Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
24.6 Divider and PLL Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
25. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
25.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
25.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
25.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
25.4 Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
25.5 Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
25.6 SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
25.7 Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
25.8 Free Running Processor Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
25.9 Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
25.10 Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
25.11 Main Crystal Clock Fa ilure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
25.12 Slow Crystal Clock Frequency Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
25.13 Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
25.14 Clock Switching Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
25.15 Write Protection Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.16 Power Management Controller (PMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
26. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
26.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
26.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
26.3 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
27. Parallel Input/Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
27.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
27.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
27.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
27.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
27.5 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
27.6 I/O Lines Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
27.7 Parallel Input/Output Con trol ler (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
28. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
28.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
28.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
28.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
28.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
28.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
28.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
28.7 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
28.8 Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
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29. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
29.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
29.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
29.3 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
29.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
29.5 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
29.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
29.7 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
29.8 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
29.9 Multi-master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
29.10 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
29.11 Two-wire Interface (TWI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
30. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 577
30.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
30.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
30.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
30.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
30.5 UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
30.6 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . . 585
31. Universal Synchronous Asynchronous Receiver Transmitter (USART) . . . . . . . . . 596
31.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
31.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
31.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
31.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
31.5 I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
31.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
31.7 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
31.8 Universal Synchronous Asynchronous Receiver Tran smitter (USART) User Interface . . . . . . . . . 628
32. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
32.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
32.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
32.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
32.4 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
32.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
32.6 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
32.7 Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
33. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
33.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
33.2 Embedded characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
33.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
33.4 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
33.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
33.6 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
33.7 Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
34. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
34.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
34.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
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34.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
34.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
34.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
34.6 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
34.7 Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
35. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
35.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
35.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
35.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
35.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
35.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
35.6 Functional Descri ption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
35.7 Digital-to-Analog Converter Controller (DACC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
36. SAM4N Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
36.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
36.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
36.3 Power Consum ption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
36.4 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
36.5 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
36.6 10-bit ADC Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
36.7 10-bit DAC Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
36.8 Voltage Reference Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
36.9 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
36.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
37. SAM4N Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
37.1 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
37.2 Packaging Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
38. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
39. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
40. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
40.1 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
40.2 Brownout Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
40.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
41. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
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Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-11158B-ATARM-SAM4N8-SA M4N16-Datasheet_23-Mar-15.
Atmel®, Atmel logo and combinati ons thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
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authorized, or warranted for use as components in applications intended to support o r sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in con nection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
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