75
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before -
LDMFD, LDMI A Rn{!}, reglist Load Multiple registers, increment after -
LDR Rt, [Rn, #offset] Load Register with word -
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte -
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes -
LDREX Rt, [Rn, #offset] Load Register Exclusive -
LDREXB Rt, [Rn] Load Register Exclusive with byte -
LDREXH Rt, [Rn] Load Register Exclusive with halfword -
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword -
LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte -
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword -
LDRT Rt, [Rn, #of fset] Load Register with word -
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result -
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result -
MOV, MOVS Rd, Op2 Move N,Z,C
MOVT Rd, #imm16 Move Top -
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C
MRS Rd, spec_reg Move from special register to general register -
MSR spec_reg, Rm Move from general register to special register N,Z,C,V
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP - No Operation -
ORN, ORNS {Rd ,} Rn, Op 2 Logical OR NOT N,Z,C
ORR, ORRS {Rd ,} Rn, Op 2 Logical OR N,Z,C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword -
POP reglist Po p re gisters from stack -
PUSH reglist Push register s on to stack -
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16 -
QADD8 {Rd,} Rn, Rm Saturating Add 8 -
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange -
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q
QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange -
QSUB {Rd,} Rn, Rm Saturating Subtract Q
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags