TPS61235RWLR - TEXAS INSTRUMENTS - Datasheet.Directory

February, 2018 − Rev. 4 1Publication Order Number:

NIV1161/D

NIV1161, NIS1161

ESD Protection with

Automotive Short-to-

Battery Blocking

Low Capacitance ESD Protection with

short−to−battery blocking for Automotive

High Speed Data Lines

The NIS/NIV1161 is designed to protect high speed data lines from

ESD as well as short to vehicle battery situations. The ultra−low

capacitance and low ESD clamping voltage make this device an ideal

solution for protecting voltage sensitive high speed data lines while

the low RDS(on) FET limits distortion on the signal lines. The

flow−through style package allows for easy PCB layout and matched

trace lengths necessary to maintain consistent impedance between

high speed differential lines such as USB and LVDS protocols.

Features

•Low Capacitance (0.65 pF Typical, I/O to GND)

•Protection for the Following Standards:

IEC 61000−4−2 (Level 4) & ISO 10605

•Integrated MOSFETs for Short−to−Battery Blocking

•NIV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q101

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Automotive High Speed Signal Pairs

•USB 2.0/3.0

•LVDS

•APIX 2/3

ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Operating Junction Temperature Range TJ(max) −55 to +150 °C

Storage Temperature Range TSTG −55 to +150 °C

Drain−to−Source Voltage VDSS 30 V

Gate−to−Source Voltage VGS ±10 V

Lead Temperature Soldering TSLD 260 °C

IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD) ESD

ESD ±8

±15 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

WDFN6

CASE 511CB

MARKING

DIAGRAM

www.onsemi.com

V6 = Specific Device Code

M = Date Code

V6 M

Device Package Shipping†

ORDERING INFORMATION

NIV1161MTTAG WDFN−6

(Pb−Free) 3000 / Tape & Ree

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Pin 2 − 5 V

Pin 2 − 5 V Pin 5 − GND

Pin 6

Pin 4

D+

D−

Pin 3

D− HOST

Pin 1

D+ HOST

PIN CONFIGURATION

AND SCHEMATICS

(Top View)

NIS1161MTTAG WDFN−6

(Pb−Free) 3000 / Tape & Ree

NIV1161, NIS1161

www.onsemi.com

ELECTRICAL CHARACTERISTICS (TA = 25_C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM I/O Pin to GND 16 V

Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 16.5 23 V

Reverse Leakage Current IRVRWM = 5 V, I/O Pin to GND 1.0 mA

Clamping Voltage VCIPP = 1 A, I/O Pin to GND (8/20 ms pulse) 26 V

Clamping Voltage (Note 1) VCIEC61000−4−2, ±8 KV Contact See Figures 1 & 2

Clamping Voltage TLP (Note 2)

See Figures 5 & 6 VCIPP = 8 A

IPP = 16 A

IPP = −8 A

IPP = −16 A

−5.2

−10

Junction Capacitance Match D CJVR = 0 V, f = 1 MHz between I/O 1 to GND

and I/O 2 to GND 1.0 %

Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and

GND (Pin 4 to GND, Pin 6 to GND) 0.65 pF

Drain−to−Source Breakdown Voltage VBR(DSS) VGS = 0 V, ID = 100 mA 30 V

Drain−to−Source Breakdown Voltage

Temperature Coefficient VBR(DSS)/

TJReference to 25_C, ID = 100 mA 27 mV/_C

Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 30 V 1.0 mA

Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±5 V ±1.0 mA

Gate Threshold Voltage (Note 3) VGS(TH) VDS = VGS, ID = 100 mA 0.1 1.0 1.5 V

Gate Threshold Voltage Temperature

Coefficient VGS(TH)/TJReference to 25_C, ID = 100 mA−2.5 mV/_C

Drain−to−Source On Resistance RDS(on) VGS = 4.5 V, ID = 125 mA 1.4 7.0 W

VGS = 2.5 V, ID = 125 mA 2.3 7.5

Forward Transconductance gFS VDS = 3.0 V, ID = 125 mA 80 mS

Switching Turn−On Delay Time (Note 4) td(ON) VGS = 4.5 V, VDS = 24 V

ID = 125 mA, RG = 10 VW

9 nS

Switching Turn−On Rise Time (Note 4) tr41 nS

Switching Turn−Off Delay Time (Note 4) td(OFF) 96 nS

Switching Turn−Off Fall Time (Note 4) tf72 nS

Drain−to−Source Forward Diode Voltage VSD VGS = 0 V, Is = 125 mA 0.79 0.9 V

3 dB Bandwidth fBW RL = 50 W5 GHz

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. For test procedure see Figures 3 and 4 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 * Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

3. Pulse test: pulse width ≤ 300 mS, duty cycle ≤ 2%

4. Switching characteristics are independent of operating junction temperatures.

NIV1161, NIS1161

www.onsemi.com

Figure 1. Typical IEC61000−4−2 +8kV Contact

ESD Clamping Voltage Figure 2. Typical IEC61000−4−2 −8kV Contact

ESD Clamping Voltage

VOLTAGE (V)

TIME (ns)

−20

140

−25 0 25 50 75 100 125

100

150 175

VOLTAGE (V)

TIME (ns)

−120

−100

−80

−60

−40

−20

−25 0 25 50 75 100 125

150 175

120

IEC61000−4−2 Spec.

Level Test V olt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Figure 4. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

DUT Oscilloscope

ESD Gun

The following is taken from Application Note

AND8307/D − Characterization of ESD Clamping

Performance.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping

voltage at the device level. ON Semiconductor has

developed a way to examine the entire voltage waveform

across the ESD protection diode over the time domain of

an ESD pulse in the form of an oscilloscope screenshot,

which can be found on the datasheets for all ESD protection

diodes. For more information on how ON Semiconductor

creates these screenshots and how to interpret them please

refer to AND8307/D.

NIV1161, NIS1161

www.onsemi.com

-16

Figure 5. Positive TLP I−V Curve Figure 6. Negative TLP I−V Curve

NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage

stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description

below for more information.

0 102030405060

Equivalent VIEC [kV]

TLP Current [A]

V [V]

-14

-12

-10

-8

-6

-4

-2

0102030405060

Equivalent VIEC [kV]

TLP Current [A]

V [V]

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 7. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 8 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels. For more

information on TLP measurements and how to interpret

them please refer to AND9007/D.

Figure 7. Simplified Schematic of a Typical TLP

System

DUT

LS÷

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

NIV1161, NIS1161

www.onsemi.com

TYPICAL MOSFET PERFORMANCE CURVES

TJ = 150°C

0.9

4.00.5

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

DRAIN CURRENT (A)

0.7

0.2

Figure 9. On−Region Characteristics

0 2.0 4.0

Figure 10. Transfer Characteristics

VGS, GATE−TO−SOURCE VOL TAGE (V)

1.0

8.0

Figure 11. On−Resistance vs. Gate−to−Source

Voltage

VGS, GATE VOLTAGE (V)

DS(on),

DRAIN−T O−SOURCE RESISTANCE (

)

ID, DRAIN CURRENT (A)

Figure 12. On−Resistance vs. Drain Current

and Gate Voltage

−50 0−25 25

1.2

0.7

0.6 50 150

Figure 13. On−Resistance Variation with

Temperature

TJ, JUNCTION TEMPERATURE (°C)

2.0

TJ = −55°C

ID = 125 mA

VGS = 4.5 V

DS(on),

DRAIN−TO−SOURCE

RESISTANCE (NORMALIZED)

TJ = 25°C

RDS(on), DRAIN−T O−SOURCE RESISTANCE (W)

1.3

VGS = 2.5 V

VGS = 4.5 V

1.5 3.5

0.1 25

Figure 14. Drain−to−Source Leakage Current

vs. Voltage

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

IDSS, LEAKAGE (nA)

TJ = 150°C

TJ = 125°C

100

VDS = 5 V

2.0 V

0.5

1.8 V

3.0

1.2

1.0

VGS = 10 V

125100 0

5.0

105

3.01.5 1.5

5.0

4.5

TJ = 25°C

ID = 125 mA

ID, DRAIN CURRENT (A)

1.9 1000

2.4 V

3.51.0

1.0

8.0

0.10 0.70.5

4.0

0.8

1.4

0.9

1.6

1.1

1.8

0.8

0.6

0.1

0.3

0.9

0.6

0.1

0.4

1.2

0.5 3.0

0.4

1.1

1.0 2.0 2.5 3.5 4.5

2.2 V

2.8 V

2.6 V

3.0 V

3.5 V

4.0 V

5.0 V 4.5 V

2.5 4.

0.2

0.3

0.5

0.7

0.8

1.0

1.1

2.5 4.0

2.0

3.0

4.0

6.0

7.0

9.0

0.2 0.3 0.4 0.6 0.8 0.9 1.0 1.1

2.0

3.0

5.0

6.0

7.0

9.0 TJ = 125°CTJ = −55°C

TJ = 25°C

TJ = 125°C

TJ = 25°C

TJ = −55°C

1.0

1.5

1.7

TJ = 85°C

NIV1161, NIS1161

www.onsemi.com

APPLICATION INFORMATION

Today’s connected cars are using multiple high speed

signal pair interfaces for various applications such as

infotainment, connectivity and ADAS. The electrical

hazards likely to be encountered in these automotive high

speed signal interfaces include damaging ESD and

transient events which occur during manufacturing and

assembly, by vehicle occupants or other electrical circuits

in the vehicle. The major documents discussing ESD and

transient events as far as road vehicles are concerned are

ISO 10605 (Road vehicles − Test methods for electrical

disturbances from electrostatic discharge) which describes

ESD test methods and ISO 7637 (Road vehicles − Electrical

disturbances from conduction and coupling) for effects

caused by other electronics in the vehicle. IS0 10605 is

based on IEC 61000−4−2 Industry Standard, which

specifies the various levels of ESD signal characteristics,

but also includes additional vehicle−specific requirements.

Further, OEM specific test requirements are usually also

imposed. In addition, these high speed signal pairs require

protection from short−to−battery (which goes up to

16 VDC) and short−to−ground faults.

A suitable protection solution must satisfy well known

constraints, such as low capacitive loading of the signal

lines to minimize signal attenuation, and also respond

quickly to s u rges and transients with low clamping voltage.

In addition, small package sizes help to minimize demand

for board−space while providing the ability to route the

trace signals with minimal bending to maintain signal

integrity.

NIV1161

D+

D−

USB

Transceiver

*R optional

PCB Layout Guidelines

It is optional to route both pins 4 & 6 to their respective

belly pads with a top metal trace as both pins are internally

connected respectively. Also, steps must be taken for

proper placement and signal trace routing of the ESD

protection device in order to ensure the maximum ESD

survivability and signal integrity for the application. Such

steps are listed below.

•Place the ESD protection device as close as possible to

the I/O connector to reduce the ESD path to ground

and improve the protection performance.

•Make sure to use differential design methodology and

impedance matching of all high speed signal traces.

♦Use curved traces when possible to avoid unwanted

reflections.

♦Keep the trace lengths equal between the positive

and negative lines of the differential data lanes to

avoid common mode noise generation and

impedance mismatch.

♦Place grounds between high speed pairs and keep

as much distance between pairs as possible to

reduce crosstalk.

Modes of Operation

There are two distinct modes of operation of the

NIV1161: normal (steady state) and short−to−battery

event. The below describes each of these in more detail.

Normal Operation (Steady State)

In normal operation, the MOSFETs operate in linear

mode, with all source and drain voltages nearly equal,

passing the signal levels effectively from the USB

transceiver . To ensure successful link communication, the

applied gate voltage must be greater than the maximum

signal level from the data line plus the maximum threshold

voltage of the MOSFET device. Due to the NIV1161’ s l o w

gate−threshold voltage of 1.5 V, both 3.3 and 5 V gate

drives are suitable to provide headroom for most

communication protocols.

An optional addition to the application may be a pull−up

resistor from the MOSFET source to the gate. A low value

resistor ( < 5 k W) effectively level−shifts the common mode

voltage on the individual data lines up to the gate voltage.

This action is cancelled out when an appropriate NIV1161

is used on the opposite side of the data line to level−shift the

common−mode voltage back down to the levels

appropriate for the reader. If a NIV1161 is not used on the

opposite side of the data line, the pull−up resistor may

either not be populated or populated with a high value

resistor (15 kW+); differential data signal integrity is

maintained.

Short−to−Battery (STB) Event

While the NIV1161 and data channel are of f, one pair of

MOSFET body diodes passively protects the USB

transceiver’s ports. While the data channel is on during an

event, the NIV1161 actively uses the internal MOSFETs to

clamp in a manner akin to level−shifting as the MOSFET

operates in the saturation region. The source node will

increase to a threshold voltage minus a very small working

voltage below the gate potential thus allowing current to

flow into the data port, limited by the port impedance until

the gate−source voltage comes to rest just above the

threshold voltage. In this way, the NIV1161 protects the

data port by limiting the termination current as well as

clamping the STB voltage itself.

NIV1161, NIS1161

www.onsemi.com

PACKAGE DIMENSIONS

ÍÍ

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.25

mm FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

SEATING

PLANE

0.10 C

WDFN6 2x2, 0.65P

CASE 511CB

ISSUE O

DIM

MIN MAX

MILLIMETERS

0.70 0.80

A1 0.00 0.05

A3 0.20 REF

b0.25 0.35

D2.00 BSC

D2 0.55 0.65

0.55 0.65

E2.00 BSC

e0.65 BSC

0.20 0.30

PIN ONE

REFERENCE

0.08 C

0.10 C

NOTE 4

A0.10 C

0.05 C

MOUNTING FOOTPRINT

BOTTOM VIEW

RECOMMENDED

DIMENSIONS: MILLIMETERS

DETAIL A

ALTERNATE

CONSTRUCTIONS

DET AIL A

DETAIL B

T OP VIEW

SIDE VIEW

--- 0.15

0.44 2.30

0.80

1.72 0.65

PITCH

5X 0.35 1

PACKAGE

OUTLINE

ÉÉÉ

ÇÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

ÇÇ

A0.10 CB

ÇÇÇ

b2 0.35 0.45

0.55 0.65

F0.52 BSC

G0.20 BSC

0.67

0.48

0.67 0.54

NIV1161/D

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