DDR2 SDRAM RDIMM
MT18HTF12872PDZ – 1GB
MT18HTF25672PDZ – 2GB
MT18HTF51272PDZ – 4GB
Features
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 1GB (128 Meg x 72), 2GB (256 Meg x 72), 4GB (512
Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Dual rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Halogen-free
Figure 1: 240-Pin RDIMM (MO-237 R/C G)
Module height: 30mm (1.181in)
Options Marking
• Parity P
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C) None
– Industrial (–40°C ≤ TA ≤ +85°C)1T
• Package
– 240-pin DIMM (halogen-free) Z
• Frequency/CL2
– 2.5ns @ CL = 5 (DDR2-800) -80E
– 2.5ns @ CL = 6 (DDR2-800) -800
– 3.0ns @ CL = 5 (DDR2-667) -667
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1: Key Timing Parameters
Speed
Grade
Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)CL = 6 CL = 5 CL = 4 CL = 3
-80E PC2-6400 800 800 533 400 12.5 12.5 55
-800 PC2-6400 800 667 533 400 15 15 55
-667 PC2-5300 – 667 553 400 15 15 55
-53E PC2-4200 – – 553 400 15 15 55
-40E PC2-3200 – – 400 400 15 15 55
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
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htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing
Parameter 1GB 2GB 4GB
Refresh count 8K 8K 8K
Row address 16K A[13:0] 16K A[13:0] 32K A[14:0]
Device bank address 4 BA[1:0] 8 BA[2:0] 8 BA[2:0]
Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) 2Gb (256 Meg x8)
Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]
Module rank address 2 S#[1:0] 2 S#[1:0] 2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 1GB
Base device: MT47H64M8,1 512Mb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18HTF12872PDZ-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF12872PTZ-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF12872PDZ-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF12872PTZ-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF12872PDZ-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTF12872PTZ-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
Table 4: Part Numbers and Timing Parameters – 2GB
Base device: MT47H128M8,1 1Gb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18HTF25672PDZ-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF25672PTZ-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF25672PDZ-800__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF25672PTZ-800__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF25672PDZ-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTF25672PTZ-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
Table 5: Part Numbers and Timing Parameters – 4GB
Base device: MT47H256M8,1 2Gb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18HTF51272PDZ-80E__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF51272PTZ-80E__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF51272PDZ-800__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF51272PTZ-800__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
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htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 5: Part Numbers and Timing Parameters – 4GB (Continued)
Base device: MT47H256M8,1 2Gb DDR2 SDRAM
Part Number2
Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18HTF51272PDZ-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT18HTF51272PTZ-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
Notes: 1. Data sheets for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MT18HTF25672PDZ-80EM1.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Pin Assignments
Table 6: Pin Assignments
240-Pin RDIMM Front 240-Pin RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5/
DQS14
2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NF/
DQS14#
3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS
4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46
5 VSS 35 VSS 65 VSS 95 DQ42 125 DM0/
DQS9
155 DM3/
DQS12
185 CK0 215 DQ47
6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NF/
DQS9#
156 NF/
DQS12#
186 CK0# 216 VSS
7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52
8 VSS 38 VSS 68 Par_In 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53
9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS
10 DQ3 40 DQ27 70 A10/AP 100 VSS 130 VSS 160 VSS 190 BA1 220 NC
11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 CB4 191 VDDQ 221 NC
12 DQ8 42 CB0 72 VDDQ 102 NC 132 DQ13 162 CB5 192 RAS# 222 VSS
13 DQ9 43 CB1 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6/
DQS15
14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1/
DQS10
164 DM8/
DQS17
194 VDDQ 224 NF/
DQS15#
15 DQS1# 45 DQS8# 75 VDDQ 105 DQS6 135 NF/
DQS10#
165 NF/
DQS17#
195 ODT0 225 VSS
16 DQS1 46 DQS8 76 S1# 106 VSS 136 VSS 166 VSS 196 A13 226 DQ54
17 VSS 47 VSS 77 ODT1 107 DQ50 137 NC 167 CB6 197 VDD 227 DQ55
18 RESET# 48 CB2 78 VDDQ 108 DQ51 138 NC 168 CB7 198 VSS 228 VSS
19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60
20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61
21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 CKE1 201 VSS 231 VSS
22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4/
DQS13
232 DM7/
DQS16
23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 A15 203 NF/
DQS13#
233 NF/
DQS16#
24 DQ16 54 BA2 84 DQS4 114 DQS7 144 DQ21 174 A14 204 VSS 234 VSS
25 DQ17 55 Err_Out# 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62
26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2/
DQS11
176 A12 206 DQ39 236 DQ63
27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NF/
DQS11#
177 A9 207 VSS 237 VSS
28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD
29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments
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htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 6: Pin Assignments (Continued)
240-Pin RDIMM Front 240-Pin RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQS#x
I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Descriptions
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 7: Pin Descriptions (Continued)
Symbol Type Description
SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out# Output
(open drain)
Parity error output: Parity error found on the command and address bus.
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.
NF – No function: These pins are connected within the module, but provide no functional-
ity.
NU – Not used: These pins are not used in specific module configurations/operations.
RFU – Reserved for future use.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Descriptions
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Functional Block Diagram
Figure 2: Functional Block Diagram
R
e
g
i
s
t
e
r
s
S0#
S1#
BA[2:0]
A[15:0]
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
Par_In
RESET#
RS0#: Rank 0
RS1#: Rank 1
RBA[2/1:0]: DDR2 SDRAM
RA[14/13:0]: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: Rank 0
RCKE1: Rank 1
RODT0: Rank 0
RODT1: Rank 1
Err_Out#
U6, U17
VREF
VSS
DDR2 SDRAM
DDR2 SDRAM
VDD/VDDQ
VDDSPD SPD EEPROM
DDR2 SDRAM
A0
SPD EEPROM
A1 A2
SA0 SA1 SA2
SDASCL
WP
PLL
CK0
CK0#
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
Register x 2
RESET#
U8
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U22
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U16
DQS0
DQS0#
DM0/DQS9
NF/DQS9#
DQS4
DQS4#
DM4/DQS13
NF/DQS13#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U21
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U15
DQS1
DQS1#
DM1/DQS10
NF/DQS10#
DQS5
DQS5#
DM5/DQS14
NF/DQS14#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U20
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U14
DQS2
DQS2#
DM2/DQS11
NF/DQS11#
DQS6
DQS6#
DM6/DQS15
NF/DQS15#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U13
DQS3
DQS3#
DM3/DQS12
NF/DQS12#
DQS7
DQS7#
DM7/DQS16
NF/DQS16#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NF/ CS# DQS DQS#
RDQS RDQS#
U18
DQS8
DQS8#
DM8/DQS17
NF/DQS17#
RS1#
RS0#
VSS
VDDSPD
Rank 0: U1–U5, U9–U12
Rank 1: U13–U16, U18–U22
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagram
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htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
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General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is
transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
Register and PLL Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2
SDRAM devices on the following rising clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives and redrives the differential
clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize
system and clock loading. PLL clock timing is defined by JEDEC specifications and en-
sured by use of the JEDEC clock reference board. Registered mode will add one clock
cycle to CL.
Parity Operations
The registering clock driver can accept a parity bit from the system’s memory control-
ler, providing even parity for the control, command, and address bus. Parity errors are
flagged on the Err_Out# pin. Systems not using parity are expected to function without
issue if Par_In and Err_Out# are left as no connects (NC) to the system.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
General Description
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htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V
IIInput leakage current; Any input 0V ≤ VIN ≤
VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other
pins not under test = 0V)
Command/Address RAS#,
CAS#, WE# S#, CKE, ODT, BA
–5 5 µA
CK, CK# –250 250
IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ;
DQs and ODT are disabled
DQ, DQS, DQS# –10 10 µA
IVREF VREF leakage current; VREF = Valid VREF level –36 36 µA
TC1DDR2 SDRAM device operating case tem-
perature2
Commercial 0 85 °C
Industrial –40 95
TAModule ambient operating temperature Commercial 0 70 °C
Industrial –40 85
Notes: 1. The refresh rate is required to double when TC exceeds 85°C < TC ≤ 95°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
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DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-1GA -187E
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DRAM Operating Conditions
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IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G)
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD01648 603 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
IDD11738 693 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
IDD2P2126 126 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
IDD2Q2432 396 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
IDD2N2504 450 mA
Active power-down current: All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P2324 270 mA
Slow PDN exit
MR[12] = 1
162 162
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD3N2594 540 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
IDD4W21188 1098 mA
Operating burst read current: All device banks open; Continuous burst read, IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4R21143 1053 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
IDD52918 873 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
IDD62126 126 mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
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© 2009 Micron Technology, Inc. All rights reserved.
Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G) (Continued)
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating bank interleave read current: All device banks interleaving reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC =
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
IDD711413 1323 mA
Notes: 1. Value calculated as one module rank in this operating condition. All other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD01648 603 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
IDD11738 693 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
IDD2P2126 126 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
IDD2Q2432 432 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
IDD2N2504 432 mA
Active power-down current: All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P2360 270 mA
Slow PDN exit
MR[12] = 1
180 180
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD3N2594 540 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
IDD4W21188 1098 mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
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© 2009 Micron Technology, Inc. All rights reserved.
Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating burst read current: All device banks open; Continuous burst read, IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4R21143 1053 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
IDD521368 1323 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
IDD62126 126 mA
Operating bank interleave read current: All device banks interleaving reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC =
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
IDD711953 1728 mA
Notes: 1. Value calculated as one module rank in this operating condition. All other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD01675 630 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
IDD11765 720 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
IDD2P2180 180 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
IDD2Q2432 432 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
IDD2N2504 432 mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
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© 2009 Micron Technology, Inc. All rights reserved.
Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Active power-down current: All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P2540 540 mA
Slow PDN exit
MR[12] = 1
360 360
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD3N2594 540 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
IDD4W21215 1125 mA
Operating burst read current: All device banks open; Continuous burst read, IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4R21170 1080 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
IDD521485 1440 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
IDD62126 126 mA
Operating bank interleave read current: All device banks interleaving reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC =
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
IDD711980 1755 mA
Notes: 1. Value calculated as one module rank in this operating condition. All other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD01783 738 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
IDD11882 882 mA
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
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© 2009 Micron Technology, Inc. All rights reserved.
Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C) (Continued)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
IDD2P2216 216 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
IDD2Q2540 450 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
IDD2N2630 540 mA
Active power-down current: All device banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P2450 450 mA
Slow PDN exit
MR[12] = 1
252 252
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD3N2900 810 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
IDD4W21278 1098 mA
Operating burst read current: All device banks open; Continuous burst read, IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4R21278 1098 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
IDD521638 1593 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
IDD62216 216 mA
Operating bank interleave read current: All device banks interleaving reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC =
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
IDD712088 1908 mA
Notes: 1. Value calculated as one module rank in this operating condition. All other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
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Register and PLL Specifications
Table 14: Register Specifications
SSTU32866 devices or equivalent
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage
VIH(DC) Control, command,
address
SSTL_18 VREF(DC) + 125 VDDQ + 250 mV
DC low-level
input voltage
VIL(DC) Control, command,
address
SSTL_18 0 VREF(DC) - 125 mV
AC high-level
input voltage
VIH(AC) Control, command,
address
SSTL_18 VREF(DC) + 250 – mV
AC low-level
input voltage
VIL(AC) Control, command,
address
SSTL_18 – VREF(DC) - 250 mV
Output high
voltage
VOH Parity output LVCMOS 1.2 – V
Output low voltage VOL Parity output LVCMOS – 0.5 V
Input current IIAll pins VI = VDD or VSS – ±0.5 µA
Static standby IDD All pins RESET# = VSSQ (IO = 0) – 100 µA
Static operating IDD All pins RESET# = VSS; VI = VIH(AC)
or VIL(DC) IO = 0
– 40 mA
Dynamic operating
(clock tree)
IDDD N/A RESET# = VDD;
VI = VIH(DC) or VIL(AC),
IO = 0; CK and CK#
switching 50% duty cy-
cle
– Varies by
manufacturer
µA
Dynamic operating
(per each input)
IDDD N/A RESET# = VDD;
VI = VIH(AC) or VIL(DC),
IO = 0; CK and CK#
switching 50% duty
cycle; One data in/out
switching at tCK/2,
50% duty cycle
– Varies by
manufacturer
µA
Input capacitance
(per device, per pin)
CIN All inputs except
RESET#
VI = VREF ±250mV;
VDD = 1.8V
2.5 3.5 pF
Input capacitance
(per device, per pin)
CIN RESET# VI = VDD or VSS Varies by
manufacturer
Varies by
manufacturer
pF
Note: 1. Timing and switching specifications for the register listed are critical for proper opera-
tion of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available
in JEDEC standard JESD82.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
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Table 15: PLL Specifications
CU877 device or equivalent
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage
VIH RESET# LVCMOS 0.65 × VDD – V
DC low-level
input voltage
VIL RESET# LVCMOS – 0.35 × VDD V
Input voltage (limits) VIN RESET#, CK,
CK#
– - 0.3 VDD + 0.3 V
DC high-level
input voltage
VIH CK, CK# Differential input 0.65 × VDD – V
DC low-level
input voltage
VIL CK, CK# Differential input – 0.35 × VDD V
Input differential-pair
cross voltage
VIX CK, CK# Differential input (VDDQ/2) - 0.15 (VDD/2) + 0.15 V
Input differential
voltage
VID(DC) CK, CK# Differential input 0.3 VDD + 0.4 V
Input differential
voltage
VID(AC) CK, CK# Differential input 0.6 VDD + 0.4 V
Input current IIRESET# VI = VDD or VSS –10 10 µA
CK, CK# VI = VDD or VSS –250 250 µA
Output disabled
current
IODL RESET# = VSS; VI = VIH(AC)
or VIL(DC)
100 – µA
Static supply current IDDLD CK = CK# = LOW – 500 µA
Dynamic supply IDD N/A CK, CK# = 270 MHz, all
outputs open (not con-
nected to PCB)
– 300 mA
Input capacitance CIN Each input VI = VDD or VSS 2 3 pF
Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time tL – 15 μs
Input clock slew rate slr(i) 1.0 4.0 V/ns
SSC modulation frequency – 30 33 kHz
SSC clock input frequency deviation – 0.0 –0.5 %
PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz
Note: 1. PLL timing and switching specifications are critical for proper operation of the DDR2
DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information
is available in JEDEC standard JESD82.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
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Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 17: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL – 0.4 V
Input leakage current: VIN = GND to VDD ILI 0.1 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA
Table 18: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time bus must be free before a new transition can start tBUF 1.3 – µs
Data-out hold time tDH 200 – ns
SDA and SCL fall time tF – 300 ns 2
SDA and SCL rise time tR – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tHD:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI – 50 ns
Clock LOW period tLOW 1.3 – µs
SCL clock frequency tSCL – 400 kHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 240-Pin DDR2 RDIMM
Pin 1
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.840)
TYP
1.0 (0.039)
TYP
0.8 (0.031)
TYP
2.0 (0.079) R
(4X)
0.76 (0.03) R
Pin 120
Front view
133.5 (5.256)
133.2 (5.244)
63.0 (2.48)
TYP
55.0 (2.165)
TYP
10.0 (0.394)
TYP
Back view
Pin 240 Pin 121
1.37 (0.054)
1.17 (0.046)
4.0 (0.157)
MAX
70.66 (2.782)
TYP
2.21 (0.087) TYP
3.04 (0.1197)
TYP
1.0 (0.039) TYP
30.5 (1.2)
29.85 (1.175)
U1 U2 U3 U4 U5
U8
U6
U9 U10 U11 U12
U13 U14 U15 U16
U17
U18 U19 U20 U21 U22
45° (4X)
U7
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Module Dimensions
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. F 4/14 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
