PRELIMINARY FM25H20
2-Mbit (256 K × 8) Serial (SPI) F-RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-85935 Rev. *D Revised January 24, 2014
2-Mbit (256 K × 8) Serial (SPI) F-RAM
Features
■2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 256 K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (See the Data Retention and Endur-
ance table)
❐NoDelay™ writes
❐Advanced high-reliabili ty ferroelectric process
■Very fast serial peripheral interface (SPI)
❐Up to 40-MHz frequency
❐Direct hardware replacement for serial flash and EEPROM
❐Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■Sophistica ted write protection sc he me
❐Hardware protection using the Write Protect (WP) pin
❐Software protection using Write Disable instruction
❐Software block protection for 1/4, 1/2, or entire array
■Low power consumption
❐1 mA active current at 1 MHz
❐80 A (typ) standby current
❐3 A sleep mode current
■Low-voltage operation: VDD = 2.7 V to 3.6 V
■Industrial temperature –40 C to +85 C
■Packages
❐8-pin small outline integrated circuit (SOIC) package
❐8-pin thin dual flat no leads (TDFN) package
■Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM25H20 is a 2-Mbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by seri al flash, EEPROM, and othe r
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25H20 performs write
operations at bus speed. No write delays are incurred. Data is
written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endura nce compared with othe r
nonvolatile memories. The FM25H20 is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the FM25H20 ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25H20 provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25H20 uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
Logic Block Diagram
Instruction Decoder
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
256 K x 8
F-RAM Array
18
Data I/ O Register
8
Nonvolatile Status
Register
3
WP
CS
HOLD
SCK
SOSI
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 2 of 22
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Overview............................................................................ 4
Memory Architecture....................... ................................. 4
Serial Peripheral Interface – SPI Bus................... ... ........ 4
SPI Overview.......... ... ... ............................................... 4
SPI Modes........... ... .............. .............. .............. ........... 5
Power Up to First Access............................................ 6
Command Structure.................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch............................... 6
Status Register and Write Protection............................. 7
RDSR - Read Status Register..................................... 8
WRSR - Write Status Register.................................... 8
Memory Operation....... .............. .............. .............. ........... 8
Write Operation......... ... .............. .............. .............. ..... 8
Read Operation........................................................... 9
HOLD Pin Operation ........................ ......................... 10
Sleep Mode............................................................... 10
Endurance............................ .......................... ........... 11
Maximum Ratings........................................................... 12
Operating Range............................................................. 12
DC Electrical Characteristics ....... ... .............................. 12
Data Retention and Endurance..................................... 13
Capacitance .................................................................... 13
Thermal Resistance........................................................ 13
AC Test Conditions........................................................ 13
AC Switching Characteristics ....................................... 14
Power Cycle Timing ....................................................... 16
Ordering Information...................................................... 17
Ordering Code Definitions......................................... 17
Package Diagrams.......................................................... 18
Acronyms........................................................................ 20
Document Conventions.. ... ... ......................................... 20
Units of Measure....................................................... 20
Document History Page...................... ........................... 21
Sales, Solutions, and Legal Information...................... 22
Worldwide Sales and Design Support....................... 22
Products.................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community................................. 22
Technical Support ..................................................... 22
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 3 of 22
Pinouts Figure 1. 8-pin SOIC pinout
Figure 2. 8-pin TDF N pinout
Pin Definitions
Pin Name I/O Type Description
CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other i nputs, and the outpu t is tristated. When LOW, the device intern ally
activates the SCK signal. A falling edge on CS must occur before every opcode.
SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising
edge and outputs occur on the falling edge. Because the device is synchronous, the clock
frequency may be any value between 0 and 40 MHz and may be interrupted at any time.
SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of
SCK and is ignored at other times. It should always be dri ven to a valid log ic level to meet IDD
specifications.
SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all
other times including w hen HOLD is LOW. Data transitions are driven on the falling edge of the
serial clock.
WP Input Write Protect. This Active LOW pin prevents write opera tion to the Status Register when WPEN
is set to ‘1’. This is critical because other write protection features are controlled through the St atus
Register. A complete explanation of write protection is provided in “Status Register and Write
Protection” on page 7. This pin must be tied to VDD if not used.
HOLD Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for
another task. When HOLD is LOW, th e current operation is suspended . The device ignores any
transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW . This pin must be
tied to VDD if not used.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The
EXPOSED PAD should be left floating.
HOLD
SCK
1
2
3
4 5
CS 8
7
6
VDD
SI
SO
Top View
not to scale
V
SS
WP
SO
CS
V
SS
WP
SI
VDD
SCK
HOLD
1
2
4
3
5
6
7
8
PAD
EXPOSED
Top View
not to scale
Note
1. SI may be connected to SO for a single pin data interface.
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PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 4 of 22
Overview
The FM25H20 is a serial F-RAM memory. The memory array is
logically organized as 262,144 × 8 bits and is accessed using an
industry-standard serial peripheral interface (SPI) bus. The
functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the FM25H20
and a serial flash or EEPROM with the same pinout is the
F-RAM's superior write performance, high endurance, and low
power consumption.
Memory Architecture
When accessing the FM25H20, the user addresses 256K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode, and a three -byte address. The upp er 6
bits of the address range are 'don't care' values. The complete
address of 18 bits specifies each byte address uniquely.
Most functions of the FM25H20 are either controlled by the SPI
interface or handled by on-board circuitry. The access time for
the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition beca us e wr it es oc cur at b us sp eed . B y the time a n ew
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
Serial Peripheral Interface – SPI Bus
The FM25H20 is a SPI slave device and operates at speeds up
to 40 MHz. This high-speed serial bus provides
high-performance serial communication to a SPI master. Many
common microcontrollers have hardware SPI ports allowing a
direct interface. It is quite simple to emulate the port using
ordinary port pins for microcontrollers that do not. The FM25H20
operates in SPI Mode 0 and 3.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and su pports multiple devices on
the data bus. A device on the SPI bus is ac tivated using the CS
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave devi ce.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is comple te and befo re a new opcod e can be issue d.
The commonly used terms in the SPI protocol are as follows:
SPI Master
The SPI master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW . The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The FM25H20 operates as an SPI slave and may share the SPI
bus with other SPI slave devices.
Chip Select (CS)
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedan ce state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued fo r each active Chip
Select cycle.
Serial Clock (SCK)
The Serial Clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The FM25H20 enables SPI modes 0 and 3 for data
communication. In both of these modes, the inputs are latched
by the slave device on the rising edge of SCK and ou tputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of a SPI instruction on
the SI pin. Further, al l data inputs and outputs are synchronized
with SCK.
Data Transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
the slave responds through the SO pin. Multiple slave devices
may share the SI and SO line s as de scri b ed ea rl i er.
The FM25H20 has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 5 of 22
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller , it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 4 shows such a configuration, which uses only three pins.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data tra n smi ssi on .
The 2-Mbit serial F-RAM requires a 3-byte address for any read
or write operation. Because the ad dress is only 1 8 bits, the first
six bits, which are fed in are ignored by the device. Although
these six bits are ‘don’t care’, Cypress recommends that these
bits be set to 0s to enable seamless transition to higher memory
densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
FM25H20 uses the standard opcodes for memory accesses.
Invalid Opcode
If an invalid opcode i s received, the opcode is ignored and the
device ignores any additio nal serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
Status Register
FM25H20 has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
SPI Modes
FM25H20 may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■SPI Mode 0 (CPOL = 0, CPHA = 0)
■SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these mode s, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
Figure 3. System Configuration with SPI Port
CS1
CS2
HOLD1
HOLD2
FM25H20 FM25H20
WP1
WP2
SCK SI SO SCK SI SO
CS HOLD WP CS HOLD WP
SCK
MOSI
MISO
SPI
Microcontroller
Figure 4. System Configuration without SPI Port
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 6 of 22
The two SPI modes are shown in Figure 5 on page 6 and Figure
6 on page 6. The status of the clock when the bus master is not
transferring data is:
■SCK remains at 0 for Mode 0
■SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringi ng the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Power Up to First Access
The FM25V20 is not accessible for a tPU time after power-up.
Users must comply with the timing parameter, tPU, which is the
minimum time from VDD (min) to the first CS LOW.
Command Structure
There are seven commands, called opcodes, that can be issued
by the bus master to the FM25H20. They are listed in Table 1.
These opcodes control the functions performed by the memory.
WREN - Set Write Enable Latch
The FM25H20 will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = ’1’ indicates that writes are
permitted. Attempting to write the WEL bit in the Status Regi ster
has no effect on the state of this bit – only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a W RDI, a WRSR, or a WRIT E o peratio n.
This preve nts furth er writ es to the Status Register or the F-RAM
array without another WREN command. Figure 7 illustrates the
WREN command bus configuration.
WRDI - Reset Write Enable Latch
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’. Figure 8 illustrates the WRDI command bus
configuration.
Figure 5. SPI Mode 0
Figure 6. SPI Mode 3
Table 1. Opcode Commands
Name Description Opcode
WREN Set write enable latch 0000 0110b
WRDI Reset write enable latch 0000 0100b
RDSR Read Status Register 0000 0101b
WRSR Write Status Register 0000 0001b
READ Read memory data 0000 0011b
WRITE Write memory data 0000 0010b
SLEEP Enter sleep mode 1011 1001b
LSB
MSB
76543210
CS
SCK
SI
012 3 4 567
CS
SCK
SI 76543210
LSB
MSB
012 3 4 567
Figure 7. WREN Bus Configuration
Figure 8. WRDI Bus Configuration
0 0 0 0 0 1 1 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
0 0 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
00
001
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 7 of 22
Status Register and Write Protection
The write protection features of the FM25H20 are multi-tiered
and are enabled through the status register . The S tatus Register
is organized as follows. (The default value shipped from the
factory for bit 0, WEL, BP0, BP1, bits 4–5, WPEN i s ‘0’, a nd fo r
bit 6 is ‘1’.)
Bits 0 and 4-5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these
bits can be modified. Note that bit 0 ("Ready or Write in progress”
bit in serial flash and EEPROM) is unnecessary, as the F-RAM
writes in real-time and is never busy, so it reads out as a ‘0’. An
exception to this is when the device is waking up from sleep
mode, which is descri bed in Sleep Mode on page 10. The BP1
and BP0 control the software write-protection features and are
nonvolatile bits. The WEL flag indicates the state of the Write
Enable Latch. Attempting to directly write the WEL bit in the
S tatus Register has no effect on it s state. This bit is internally set
and cleared via the WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They
specify portions of memory that are write-protected as shown in
Table 4.
The BP1 and BP0 bits and the Write Enable L atch are the only
mechanisms that protect the memory from writes. The remaining
write protection features protect inadvertent changes to the block
protect bits.
The write protect enable bit (WPEN) in the Status Register
controls the effect of the hardware write protect (WP) pin. When
the WPEN bit is set to '0', the status of the WP pin is ignored.
When the WPEN bit is set to '1', a LOW on the WP pin inhibits a
write to the Status Register. Thus the Status Register is
write-protected only when WPEN = '1' and WP = '0'.
Table 5 summarizes the write protection conditions.
Table 2. Stat us Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN (0) X (1) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0)
Table 3. Status Register Bit Definition
Bit Definition Description
Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read.
Bit 1 (WEL) Write Enable WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEL = '1' --> Write enabled
WEL = '0' --> Write disabled
Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7.
Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7.
Bit 4-5 Don’t care These bits are non-writable and always return ‘0’ upon read.
Bit 6 Don’t care This bit is non-writable and always returns ‘1’ upon read.
Bit 7 (WPEN) Write Protect Enabl e bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5 on page 7.
Table 4. Block Memory Write Protection
BP1 BP0 Protected Addres s Ran ge
0 0 None
0 1 30000h to 3FFFFh (upper 1/4)
1 0 20000h to 3FFFFh (upper 1/2)
1 1 00000h to 3FFFFh (all)
Table 5. Write Protection
WEL WPEN WP Protected
Blocks Unprotected
Blocks Status
Register
0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 8 of 22
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
FM25H20 will return one byte with the contents of the Status
Register.
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
setting the WPEN, BP0 and BP1 bits as required. Before issuing
a WRSR command, the WP pin must be HIGH or inactive. Note
that on the FM25H20, WP only prevents writing to the Status
Register, not the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
Memory Operation
The SPI interface, which is capable of a high clock frequency,
highlights the fast write capability of the F-RAM technology.
Unlike serial flash and EEPROMs, the FM25H20 can perform
sequential writes at b us speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN opcode with CS
being asserted and deasserted. The next opcode is WRITE. The
WRITE opcode is followed by a three-byte address containing
the 18-bit address (A17-A0) of the first data byte to be written into
the memory. The upper six bits of the three-byte address are
ignored. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as
the bus master continues to issue clocks and keeps CS LOW. If
the last address of 3FFFFh is reached, the counter will roll over
to 00000h. Data is written MSB first. The rising edge of CS
terminates a write operation. A write operation is shown in
Figure 11.
Note When a burst write reaches a protected block address, the
automatic address increment stops and all the subsequent data
bytes received fo r write will be ignored by the device.
EEPROMs use page buffers to increase their write throughput.
This compensates for the technology's inherently slow write
operations. F-RAM memories do not have page buffers because
each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of
bytes to be written without page buffer delays.
Note If the power is lost in the middle of the write operation, only
the last completed byte will be written.
Figure 9. RDSR Bus Configuration
Figure 10. WRSR Bus Configuration (WREN not shown)
CS
SCK
SO
01234567
SI
000001 0 0
1
HI-Z
012345 67
LSB
D0D1D2D3D4D5D6
MSB
D7
Opcode
Data
CS
SCK
SO
01 23 4567
SI
00000001
MSB LSB
D2D3D7
HI-Z
012345 67
Opcode Data
XX
XX
X
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PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 9 of 22
Read Operation
After the falling edge of CS, the bus master can issue a READ
opcode. Following the READ command is a three-b yte address
containing the 18-bit address (A17-A0) of the first byte of the
read operation. The upper six bits of the address are ignored.
After the opcode and address are issued, the device drives out
the read data on the next eight clocks. The SI input is ignored
during read data bytes. Subsequent bytes are data bytes, which
are read out sequenti ally. Addresses are incremented inte rnally
as long as the bus master con tinues to issue clocks and CS is
LOW. If the last add ress of 3FFFFh is reached, the counter will
roll over to 00000h. Data is read MSB first. The rising edge of CS
terminates a read operation and tristates the SO pin. A read
operation is shown in Figure 12.
Figure 11. Memory Write (WREN not shown) Operation
Figure 12. Memory Read Operation
~
~
CS
SCK
SO
01234 5 6 70 7654321 2021222301234567
MSB LSB
Data
D0D1D2D3D4D5D6D7
SI
~
~
Opcode
0000001
X X X X X A17
0
X
A16 A3 A1A2 A0
18-bit Address
MSB LSB
HI-Z
~
~
CS
SCK
SO
01 23456 70 7654321 20212223012345 6 7
MSB LSB
Data
SI
~
~
Opcode
0000001
X X X X X A17
1
X
A16 A3 A1A2 A0
18-bit Address
MSB LSB
D0D1D2D3D4D5D6D7
HI-Z
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 10 of 22
HOLD Pin Operation
The HOLD pin can be used to interrupt a serial operation without
aborting it. If the bus master pulls the HOLD pin LOW wh ile SCK
is LOW, the current operation will pause. Taking the HOLD pin
HIGH while SCK is LOW will resume an operation. The
transitions of HOLD must occur while SCK is LOW , but the SCK
and CS pin can toggle during a hold state.
Sleep Mode
A low-power sleep mode is implemented on the FM25V20
device. The device will enter the low-power state when the
SLEEP opcode B9h is clocked in and a rising edge of CS is
applied. When in sleep mode, the SCK and SI pins are ign ored
and SO will be HI-Z, but the device continues to monitor the CS
pin. On the next falling edge of CS, the device will return to
normal operation within tREC time. The SO pin remains in a HI-Z
state during the wakeup period. The device does not necessarily
respond to an opcode within the wakeup period. To start the
wakeup procedure, the controller may send a “dummy” read, for
example, and wait the remaining tREC time.
Figure 13. HOLD Operation[2]
CS
SCK
HOLD
SO
~
~
~
~
SI VALID IN VALID IN
~
~
~
~
~
~
Figure 14. Sleep Mode Operation
CS
SCK
SI
SO
HI-Z
0
Enters Sleep Mode
VALID IN
tSU
tREC Recovers from Sleep Mode
1011 1 00 1
1 2 3 4 5 6 7
Note
2. Figure shows HOLD operation for input mode and output mode.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 11 of 22
Endurance
The FM25H20 devices are capable of being accessed at least
1014 times, reads or writes. An F-RAM memory operates with a
read and restore mechan ism. Therefo re, an endurance cycl e is
applied on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on an array of
rows and columns of 32K rows of 64-bits each. The entire row is
internally accessed each time a byte in that row is read or written.
All 8 bytes in the row are co unted separately for each access in
an endurance calculation. Table 7 shows endurance calculations
for a 256-byte repeating loop, which includes an opcode, a
starting address (3 bytes), and a sequential 256-byte data
stream. This causes each byte to experience eight endurance
cycle through the loop. F-RAM read and write endurance is
virtually unlimited even at a 40-MHz clock rate.
Table 6. Time to Reach Endurance Limit for Repeating
256-byte Loop
SCK Freq
(MHz) Endurance
Cycles/sec Endurance
Cycles/year Years to Reach
Limit
40 153,848 4.85 × 1012 20.6
20 76,924 2.43 × 1012 41.2
10 38,462 1.21 × 1012 82.4
5 19,231 6.06 × 1011 164.8
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 12 of 22
Maximum Rat ings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum junction temperature ................................... 95 C
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Input voltage ........... –1.0 V to +4.5 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in High-Z state .............. ... ...................–0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential .................–2.0 V to VDD + 2.0 V
Package power dissipation
capability (TA = 25 °C) ...................... ... ........................1.0 W
Surface mount lead soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) ....15 mA
Electrostatic Discharge Voltage
Human Body Model (JEDEC Std JESD22-A114-B) .............. 2 kV
Charged Device Model (JEDEC Std JESD22-C101-A) .......... 1 kV
Machine Model (JEDEC Std JESD22-A115-A)......................200 V
Latch-up current ......................................................> 50 mA
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Co nditions Min Typ[3] Max Unit
VDD Power supply 2.7 3.3 3.6 V
IDD VDD supply current SCK toggling
between VDD – 0.2 V
and VSS, other inputs
VSS or VDD – 0.2 V.
SO = Open
fSCK = 1 MHz; ––1mA
fSCK = 40 MHz; – – 10 mA
ISB VDD standby current CS = VDD. All other
inputs VSS or VDD.TA = 25 C–80150A
TA = 85 C– –270A
IZZ Sleep mode current CS = VDD.
All other inputs VSS or
VDD.
TA = 25 C–35A
TA = 85 C––8A
ILI Input leakage current VSS < VIN < VDD ––±1A
ILO Output leakage current VSS < VOUT < VDD ––±1A
VIH Input HIGH vol tage 0.7 × VDD –V
DD + 0.5 V
VIL Input LOW voltage – 0.4 – 0.3 × VDD V
VOH Output HIGH voltage IOH = –100 AV
DD – 0.2 – – V
VOL Output LOW voltage IOL = 1.6 mA – – 0.4 V
Note
3. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 13 of 22
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times ...................................................3 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance ..............................................30 pF
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Dat a re tention TA = 85 C 10 – Years
TA = 75 C38–
TA = 65 C 151 –
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter [4] Description Test Conditions Max Unit
COOutput pin capacitance (SO) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF
CIInput pin capacitance 6pF
Thermal Resist ance
Parameter Description Test Conditions 8-pin SOIC 8-pin TDFN Unit
JA Thermal resistance
(junction to ambient) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
112 16 C/W
JC Thermal resistance
(junction to case) 37 10 C/W
Note
4. This parameter is characterized but not 100% tested.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 14 of 22
AC Switching Characteristics
Over the Operating Range
Parameters [5]
Description VDD = 2. 7 V to 3.6 V Unit
Cypress
Parameter Alt. Parameter Min Max
fSCK –SCK clock frequency 040 MHz
tCH –Clock HIGH time 11 –ns
tCL –Clock LOW time 11 –ns
tCSU tCSS Chip select setup 10 –ns
tCSH tCSH Chip select hold 10 –ns
tOD[6, 7] tHZCS Output disable time –12 ns
tODV tCO Output data valid time – 9 ns
tOH –Output hold time 0 – ns
tD–Deselect time 40 –ns
tR[8, 9] –Data in rise time –50 ns
tF[8, 9] –Data in fall time –50 ns
tSU tSD Data setup time 5 – ns
tHtHD Data hold time 5 – ns
tHS tSH HOLD setup time 10 –ns
tHH tHH HOLD hold time 10 –ns
tHZ[6, 7] tHHZ HOLD LOW to HI-Z –20 ns
tLZ[7] tHLZ HOLD HIGH to data active –20 ns
Notes
5. Test conditions assume a signal transition time of 3 n s or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and ou tput loading of
the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 13.
6. tOD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state
7. This para meter is characterized but not 100% tested.
8. Rise and fall times measured between 10% and 90% of waveform.
9. These parameters are guaranteed by design and are not tested.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 15 of 22
Figure 15. Synchronous Data Timing (Mode 0)
Figure 16. HOLD Timing
HI-Z
VALID IN
HI-Z
CS
SCK
SI
SO
tCL
tCH
tCSU
tSU tH
tODV tOH
t
D
tCSH
tOD
VALID IN VALID IN
CS
SCK
HOLD
SO
tHS
tHZ tLZ
tHH
tHS
tHH
~
~
~
~
SI
tSU
VALID IN VALID IN
~
~
~
~
~
~
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 16 of 22
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up VDD(min) to first access (CS LOW) 1 – ms
tPD Last access (CS HIGH) to power-down (VDD(min)) 0 – µs
tVR [10] VDD power-up ramp rate 50 –µs/V
tVF [10] VDD power-down ramp rate 100 –µs/V
tREC [11] Recovery time from sleep mode –450 µs
Figure 17. Power Cycle Timing
CS
~
~
~
~
tPU
tVR tVF
VDD
VDD(min)
tPD
VDD(min)
Notes
10.Slope measured at any point on the VDD waveform.
11. Guarante ed by design. Re fe r to Figure 14 for sleep mode recovery timing.
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 17 of 22
Ordering Code Definitions
Ordering Information
Ordering Code Package
Diagram Package Type Operating
Range
FM25H20-G 001-85261 8-pin SOIC Industrial
FM25H20-GTR 001-85261 8-pin SOIC
FM25H20-DG 001-85579 8-pin TDFN
FM25H20-DGTR 001-85579 8-pin TDFN
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Option:
blank = Standard; TR = Tape and Reel
Package Type:
G = 8-pin SOIC; DG = 8-pin TDFN
Density: 20 = 2-Mbit
Voltage: H = 2.7 V to 3.6 V
SPI F-RAM
Cypress
25FM H 20 - DG TR
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 18 of 22
Package Diagrams Figure 18. 8-pin SOIC (208 Mils) Package Outline, 001-85261
001-85261 **
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 19 of 22
Figure 19. 8-pin DFN (5 mm × 6 mm× 0.60 mm) Package Outline, 001-85579
Package Diagrams (continued)
001-85579 **
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 20 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
CPHA Clock Phase
CPOL Clock Polarity
EEPROM Electrically Erasable Programmable Read-Only
Memory
EIA Electronic Industries Alliance
F-RAM Ferroelectric Random Access Memory
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
JESD JEDEC Standards
LSB Least Significant Bit
MSB Most Significant Bit
RoHS Restriction of Hazardous Substances
SPI Serial Peripheral Interface
SOIC Small Outline Integrated Circuit
TDFN Thin Dual Flat No-lead
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
Mbit megabit
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Not Recommended for New Designs
PRELIMINARY FM25H20
Document Number: 001-85935 Rev. *D Page 21 of 22
Document History Page
Document Title: FM25H20, 2-Mbit (256 K × 8) Serial (SPI) F-RAM
Document Number: 00 1-85935
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 3902952 GVCH 02/25/13 New spec
*A 3924836 GVCH 03/07/13 Move datasheet to external web
*B 3994285 GVCH 05/14/2013 Added Appendix A - Errata for FM25H20
*C 4045438 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*D 4226252 GVCH 01/24/2014 Converted to Cypress standard format
Updated Pinouts
- Updated Figure 2 (Added EXPOSED PAD details)
Updated Pin Definitions
- Added EXPOSED PAD details.
Updated Maximum Ratings table
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance table
- Added data retention value at 65 C and 75 C temperature
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
Updated Figure 19
Removed Ramtron revision history
Completing Sunset Review
Added watermark as “Not Recommended for New Designs”.
Not Recommended for New Designs
Document Number: 001-85935 Rev. *D Revised January 24, 2014 Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
PRELIMINARY FM25H20
© Cypress Semicondu ctor Corpor ation, 2013-2014. The informatio n cont ained herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot warranted nor int e nd ed to be used fo r
medical, life supp or t, lif e savi n g, critical control o r saf ety ap pli cations, unless pur suan t to a n express written agre em en t w it h Cy press. Fu rth er mor e, Cypre ss does not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypr ess products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress agains t all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s t o license e a pers onal, no n-excl usive , non-tr ansferab le license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only i n conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this Sour ce Code except as spe cified above is p rohibited wit hout
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTA BILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials des cribed herein. Cypress does n ot
assume any liabil ity arisi ng ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts for use as critical compon ent s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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