dBCool
®
Remote Thermal
Controller and Voltage Monitor
ADT7468
©2010 SCILLC. All rights reserved. Publication Order Number:
May 2010 – Rev. 3 ADT7468/D
FEATURES
Monitors up to 5 voltages
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic T
MIN
control mode intelligently optimizes system
acoustics
Automatic fan speed control mode manages system
cooling based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium
®
4 processor
Thermal control circuit via THERM input
2-wire, 3-wire, and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1-compliant)
GENERAL DESCRIPTION
The ADT7468 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise sensitive or power
sensitive applications requiring active system cooling. The
ADT7468 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so that they operate at
the lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique, dynamic T
MIN
control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution can
be monitored using the THERM input. The ADT7468 also
provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
FUNCTIONAL BLOCK DIAGRAM
04499-0-001
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
GND
SERIAL BUS
INTERFACE
SCL SDA
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMP SENSOR
V
CC
TOADT7468
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
V
CC
D1+
D1–
D2+
D2–
+5V
IN
THERMAL
PROTECTION
PERFORMANCE
MONITORING
PWM REGISTERS
AND
CONTROLLERS
HF & LF
PWM1
PWM2
PWM3
ACOUSTIC
ENHANCEMENT
CONTROL
BAND GAP
REFERENCE
10-BIT
ADC
ADT7468
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
FAN SPEED
COUNTER
TACH1
TACH2
TACH3
TACH4
ACOUSTIC
ENHANCEMENT
CONTROL
SRC
+12V
IN
+2.5V
IN
V
CCP
VID5
VID4
VID3
VID2
VID1
VID0
THERM
SMBALERT
Figure 1.
ADT7468
Rev. 3 | Page 2 of 81 | www.onsemi.com
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 8
Product Description ....................................................................... 10
Comparison between ADT7463 and ADT7468 ..................... 10
Recommended Implementation ............................................... 11
Serial Bus Interface ......................................................................... 12
Write Operations ........................................................................ 13
Read Operations ......................................................................... 14
SMBus Timeout .......................................................................... 14
VID Code Monitoring ................................................................... 15
VID Code Registers.................................................................... 15
Analog-to-Digital Converter ........................................................ 16
Voltage Measurement Input ...................................................... 16
Additional ADC Functions for Voltage Measurements ........ 16
Temperature Measurement ....................................................... 18
Additional ADC Functions for
Temperature Measurement ....................................................... 21
Limits, Status Registers, and Interrupts ....................................... 22
Limit Values ................................................................................. 22
Status Registers ........................................................................... 23
Interrupts ..................................................................................... 23
Active Cooling ................................................................................ 28
Driving the Fan Using PWM Control ..................................... 28
Laying Out 2-Wire and 3-Wire Fans ....................................... 30
Fan Speed Measurement ............................................................ 31
Fan Spin-Up ................................................................................ 33
PWM Logic State ........................................................................ 33
Fan Speed Control ...................................................................... 34
Miscellaneous Functions ............................................................... 35
Operating from 3.3 V Standby.................................................. 35
XNOR Tree Test Mode............................................................... 35
Power-On Default ...................................................................... 35
Automatic Fan Control Overview ................................................ 37
Dynamic T
MIN
Control Mode .................................................... 38
Programming the Automatic Fan Speed Control Loop ............ 40
Step 1: Hardware Configuration .............................................. 40
Step 2: Configuring the Mux .................................................... 43
Step 3: T
MIN
Settings for Thermal Calibration Channels ....... 45
Step 4: PWM
MIN
for Each PWM (Fan) Output ...................... 46
Step 5: PWM
MAX
for PWM (Fan) Outputs .............................. 46
Step 6: T
RANGE
for Temperature Channels ................................ 47
Step 7: T
THERM
for Temperature Channels ............................... 50
Step 8: T
HYST
for Temperature Channels .................................. 51
Step 9: Operating Points for Temperature Channels ............. 52
Step 10: High and Low Limits for Temperature Channels ... 53
Step 11: Monitoring THERM ................................................... 56
Step 12: Ramp Rate for Acoustic Enhancement ..................... 57
Enhancing System Acoustics ......................................................... 59
Acoustic Enhancement Mode Overview ................................ 59
Register Tables................................................................................. 61
ADT7468 Programming Block Diagram .................................... 80
Outline Dimensions ....................................................................... 81
Ordering Guide .......................................................................... 81
REVISION HISTORY
ADT7468
Rev. 3 | Page 3 of 81 | www.onsemi.com
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at T
A
= 25°C and represent most likely parametric
norms. Logic inputs accept input high voltages up to V
MAX
even when device is operating down to V
MIN
. Timing specifications are tested at
logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and are
not production tested.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 5.5 V
Supply Current, I
CC
3 mA Interface inactive, ADC active
20 µA Standby mode
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±1.5 °C 0°C ≤ T
A
≤ 70°C
−3.5 +2 °C −40°C ≤ T
A
≤ +100°C
−4 +2 °C −40°C ≤ T
A
≤ +120°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±1.5 °C 0°C ≤ T
A
≤ 70°C; 0°C ≤ T
D
≤ 120°C
−3.5 +2 °C −40°C ≤ T
A
≤ +100°C; 0°C ≤ T
D
≤ +120°C
−4.5 +2 °C −40°C ≤ T
A
≤ +120°C; 0°C ≤ T
D
≤ +120°C
Resolution 0.25 °C
Remote Sensor Source Current 6 µA First current
36 µΑ Second current
96 µΑ Third current
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE) ±2 % For 12 V and 5 V channels
±1.5 % For all other channels
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
Total Monitoring Cycle Time 19 ms Averaging disabled
Input Resistance 40 70 100 kΩ For V
CC
channel
80 140 200 kΩ For all other channels
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±5 % 0°C ≤ T
A
≤ 70°C , 3.3 V
±7 % −40°C ≤ T
A
≤ +120°C , 3.3 V
±10 % −40°C ≤ T
A
≤ +120°C , 5.5 V
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10000 RPM Fan count = 0x021C
Internal Clock Frequency 85.5 90 94.5 kHz 0°C ≤ T
A
≤ 70°C, V
CC
= 3.3 V
83.7 90 96.3 kHz −40°C ≤ T
A
≤ +120°C, V
CC
= 3.3 V
81 90 99 kHz −40°C ≤ T
A
≤ +120°C, V
CC
= 5.5 V
ADT7468
Rev. 3 | Page 4 of 81 | www.onsemi.com
Parameter Min Typ Max Unit Test Conditions/Comments
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, I
OL
8.0 mA
Output Low Voltage, V
OL
0.4 V I
OUT
= −8.0 mA, V
CC
= +3.3 V
High Level Output Current, I
OH
0.1 1.0 µA V
OUT
= V
CC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V I
OUT
= −4.0 mA, V
CC
= +3.3 V
High Level Output Current, I
OH
0.1 1.0 µA V
OUT
= V
CC
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
2.0 V
5.5 V Maximum input voltage
Input Low Voltage, V
IL
0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
0.75 × V
CCP
V
Input Low Voltage, V
IL
0.4 V
DIGITAL INPUT CURRENT
Input High Current, I
IH
−1 µA V
IN
= V
CC
Input Low Current, I
IL
1 µA V
IN
= 0
Input Capacitance, C
IN
5 pF
SERIAL BUS TIMING
See Figure 2
Clock Frequency, f
SCLK
10 400 kHz
Glitch Immunity, t
SW
50 ns
Bus Free Time, t
BUF
4.7 µs
Start Setup Time, t
SU;STA
4.7 µs
Start Hold Time, t
HD;STA
4.0 µs
SCL Low Time, t
LOW
4.7 µs
SCL High Time, t
HIGH
4.0 50 µs
SCL, SDA Rise Time, t
R
1000 ns
SCL, SDA Fall Time, t
F
300 µs
Data Setup Time, t
SU;DAT
250 ns
Data Hold Time, t
HD;DAT
300 ns
Detect Clock Low Timeout, t
TIMEOUT
15 35 ms Can be optionally disabled
SCL
SDA
P S S P
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
04499-0-002
Figure 2. Serial Bus Timing Diagram
ADT7468
Rev. 3 | Page 5 of 81 | www.onsemi.com
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (V
CC
) 5.5 V
Maximum Voltage on 12 V
IN
Pin 20 V
Voltage on Any Input or Output Pin −0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (T
JMAX
) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 220°C
For Pb-free 260°C
Lead Temperature (Soldering 10 sec) 300°C
ESD Rating 1000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Thermal Characteristics
24-lead QSOP package:
θ
JA
= 150°C/W
θ
JC
= 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADT7468
Rev. 3 | Page 6 of 81 | www.onsemi.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04499-0-003
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
VID0
VID1
VID2
VID3
TACH1
TACH2
+5V
IN
/THERM
VID4
D1+
TACH3
PWM2/SMBALERT
D1–
1
2
3
4
24
23
22
21
SDA
SCL
GND
V
CC
PWM1/XTO
V
CCP
+2.5V
IN
+12V
IN
/VID5
D2+
D2–
PWM3
TACH4/GPIO/THERM/SMBALERT
ADT7468
TOP VIEW
(NOT TO SCALE)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires pull-up resistor.
2 SCL Digital Input (Open Drain). SMBus serial clock input. Requires pull-up resistor.
3 GND Ground Pin.
4 V
CC
Power Supply. Can be powered by 3.3 V standby, if monitoring in low power states is required. V
CC
is also monitored
through this pin. The ADT7468 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1
(Reg. 0x40) rescales the V
CC
input attenuators to correctly measure a 5 V supply.
5 VID0 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
6 VID1 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
7 VID2 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
8 VID3 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input
(AIN3) to measure the speed of 2-wire fans.
10 PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed.
Can be configured as a high or low frequency drive.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input
(AIN1) to measure the speed of 2-wire fans.
12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input
(AIN2) to measure the speed of 2-wire fans.
13 PWM3 Digital I/O (Open Drain). Pulse width modulated output to control speed of Fan 3 and Fan 4. Requires 10 kΩ typical
pull-up. Can be configured as a high or low frequency drive.
14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input
(AIN4) to measure the speed of 2-wire fans.
GPIO General Purpose Open Drain Digital I/O.
THERM Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions
on the THERM input. For example, this pin can be connected to the PROCHOT output of an Intel Pentium 4 processor
or to the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature
conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
15 D2– Cathode Connection to Second Thermal Diode.
ADT7468
Rev. 3 | Page 7 of 81 | www.onsemi.com
Pin
No. Mnemonic Description
16 D2+ Anode Connection to Second Thermal Diode.
17 D1– Cathode Connection to First Thermal Diode.
18 D1+ Anode Connection to First Thermal Diode.
19 VID4 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
20 +5V
IN
Analog Input. Monitors +5 V power supply.
THERM Alternatively, this pin can be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions
on the THERM input. For example, it can be connected to the PROCHOT output of an Intel Pentium 4 processor or to
the output of a trip point temperature sensor. This pin can also be used as an output to signal overtemperature
conditions.
21 +12V
IN
Analog Input. Monitors +12 V power supply.
VID5 Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
Supports VRM10 solutions.
22 +2.5V
IN
Analog Input. Monitors +2.5 V supply, typically a chipset voltage.
23 V
CCP
Analog Input. Monitors processor core voltage (0 V to 3 V).
24 PWM1 Digital Output (Open Drain). Pulse width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
XTO Also functions as the output from the XOR tree in XOR test mode.
ADT7468
Rev. 3 | Page 8 of 81 | www.onsemi.com
TYPICAL PERFORMANCE CHARACTERISTICS
04499-0-045
CAPACITANCE (nF)
1 4.73.3 100 2.2
TEMPERATURE ERROR (°C)
–60
0
–20
–50
–30
–10
–40
Figure 4. Temperature Error vs. Capacitance between D+ and D−
04499-0-046
CAPACITANCE (nF) 250 10 205 15
TEMPERATURE ERROR (°C)
–100
0
–20
–50
–30
–60
–70
–80
–90
–10
–40
Figure 5. External Temperature Error vs. D+/D− Capacitance
04499-0-047
RESISTANCE (MΩ)1000 3.3 201 10
TEMPERATURE ERROR (°C)
–80
60
20
–40
0
–60
40
–20
D+ TO GND
D+ TO VCC
Figure 6. Remote Temperature Error vs. PCB Resistance
04499-0-048
FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–10
20
15
0
10
–5
5
100mV
40mV
60mV
Figure 7. Remote Temperature Error vs. Common Mode Noise Frequency
04499-0-049
FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–4
6
4
–2
2
–3
0
5
–1
3
1
10mV
20mV
Figure 8. Remote Temperature Error vs. Differential Mode Noise Frequency
04499-0-050
POWER SUPPLY VOLTAGE (V)
3.0 3.8 5.23.4 4.43.6 4.83.2 4.0 5.44.6 5.04.2
I
DD
(mA)
1.05
1.40
1.30
1.20
1.15
1.10
1.35
1.25
Figure 9. Normal I
DD
vs. Power Supply
ADT7468
Rev. 3 | Page 9 of 81 | www.onsemi.com
04499-0-051
POWER SUPPLY VOLTAGE (V)
3.0 3.8 5.23.4 4.43.6 4.83.2 4.0 5.44.6 5.04.2
I
DD
(µA)
0
7
5
3
2
1
6
4
Figure 10. Shutdown I
DD
vs. Power Supply
04499-0-052
POWER SUPPLY NOISE FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–20
20
10
–5
5
–10
–15
15
0
INT ERROR, 100mV
INT ERROR, 250mV
Figure 11. Internal Temperature Error vs. Power Supply
04499-0-053
POWER SUPPLY NOISE FREQUENCY (kHz) 1G10 100 1M 10M 100M
TEMPERATURE ERROR (°C)
–20
20
10
–5
5
–10
–15
15
0
EXT ERROR, 100mV
EXT ERROR, 250mV
Figure 12. Remote Temperature Error vs. Power Supply Noise Frequency
04499-0-091
TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100
ERROR (°C)
1.0
0
0.5
–1.0
–0.5
–2.0
–1.5
–2.5
–3.5
–3.0
–4.0
Figure 13. Internal Temperature Error vs. ADT7468 Temperature
04499-0-092
TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100
ERROR (°C)
1.0
0
0.5
–1.0
–0.5
–2.0
–1.5
–2.5
–3.5
–3.0
–4.0
Figure 14. Remote Temperature Error vs. ADT7468 Temperature
ADT7468
Rev. 3 | Page 10 of 81 | www.onsemi.com
PRODUCT DESCRIPTION
The ADT7468 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 1), and
an input line for the serial clock (Pin 2). All control and
programming functions for the ADT7468 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
COMPARISON BETWEEN ADT7463 AND ADT7468
The ADT7468 is an upgrade to the ADT7463. The ADT7468
and ADT7463 are almost pin and register map compatible. The
ADT7468 and ADT7463 have the following differences:
1. On the ADT7468, the PWM drive signals can be config-
ured as either high frequency or low frequency drives. The
low frequency option is programmable between 10 Hz and
100 Hz. The high frequency option is 22.5 kHz. On the
ADT7463, only the low frequency option is available.
2. Once V
CC
is powered up, monitoring of temperature and
fan speeds is enabled on the ADT7468 when V
CCP
is
powered up. If V
CCP
is never powered up, this is enabled
when the first SMBus transaction with the ADT7468 is
completed. On the ADT7463, the STRT bit in Configur-
ation Register 1 must be set to enable monitoring.
3. The fans are switched off by default upon power-up. On
the ADT7463, the fans run at full speed on power-up.
Fail-safe cooling is provided such that when the measured
temperature exceeds the THERM limit (100°C), the fans
run at full speed.
Fail-safe cooling is also provided 4.6 secs after V
CCP
is
powered-up (see Figure 48). The fans operate at full speed
if the ADT7468 has not been addressed via the SMBus
within 4.6 secs of when the V
CCP
is powered up. This
protects the system in the event that the SMBus fails. The
ADT7468 can be programmed at any time, and it behaves
as programmed. If V
CCP
is never powered-up, fail-safe
cooling is effectively disabled. If V
CCP
is disabled, writing to
the ADT7468 at any time causes the ADT7468 to operate
normally.
4. Series resistance cancellation (SRC) is provided on the
remote temperature channels on the ADT7468, but not on
the ADT7463. SRC automatically cancels linear offset
introduced by a series resistance between the thermal
diode and the sensor.
5. The ADT7468 has an extended temperature measurement
range. The measurement range goes from–64°C to +191°C.
On the ADT7463, the measurement range is from −127°C
to +127°C. This means that the ADT7468 can measure
higher temperatures. The ADT7468 also includes the
ADT7463 temperature range; the temperature measure-
ment range can be switched by setting Bit 0 of
Configuration Register 5.
6. The ADT7468 maximum fan speed (% duty cycle) in the
automatic fan speed control loop can be programmed. The
maximum fan speed is 100% duty cycle on the ADT7463
and is not programmable.
7. The offset register in the ADT7468 is programmable up to
±64°C with 0.50°C resolution. The offset register of the
ADT7463 is programmable up to ±32°C with 0.25°C
resolution.
8. V
CCP
is monitored on Pin 23 of the ADT7468 and can be
used to set the threshold for THERM (PROCHOT) (2/3 of
V
CCP
). The threshold for THERM (PROCHOT) is set at
V
IH
= 1.7 V and V
IL
= 0.8 V on the ADT7463.
9. On the ADT7463, Pin 22 can be reconfigured as SMBus
ALERT. This is not available on the ADT7468; instead,
SMBALERT can be enabled on Pin 14.
10. A GPIO can also be made available on Pin 14 on the
ADT7468. This is not available on the ADT7463. Set the
GPIO polarity and direction in Configuration Register 5.
The GPIO status bit is Bit 5 of Status Register 2 (shared
with TACH4 and THERM, because only one can be
enabled at a time).
11. The ADT7463 has three possible SMBus addresses, which
are selectable using the address select and address enable
pins. The ADT7468 has one SMBus address available at
Address 0x2E.
Due to the inclusion of extra functionality, the register map has
changed, including an additional configuration register:
Configuration Register 5 at Address 0x7C.
Configuration Register 5
Bit 0: If Bit 0 is set to 1, in terms of temperature the ADT7468 is
backward-compatible with the ADT7463. Measurements
including the T
MIN
calibration circuit, and fan control work in
the range of −127°C to +127°C. Also, care should be taken in
reprogramming the temperature limits (T
MIN
, operating point,
and THERM limits) to their desired twos complement value,
because the power-on default for them is at Offset 64. The
extended temperature range is −64°C to 191°C. The default is 1,
which is in the −64°C to +191°C temperature range.
ADT7468
Rev. 3 | Page 11 of 81 | www.onsemi.com
Bit 1= 0 is the high frequency (22.5 kHz) fan drive signal.
Bit 1 = 1 switches the fan drive to low frequency PWM,
programmable between 10 Hz and 100 Hz, the same as the
ADT7463. The default = 0 = HF PWM.
Bit 2 sets the direction for the GPIO: 0 = input, 1 = output.
Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high.
Setting the Functionality of Pin 14
Pin 14 on the ADT7468 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D.
Table 4. Pin 14 Settings
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7468 as in Figure 15 allows the system
designer to use the following features:
• Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
• Three TACH fan speed measurement inputs.
• V
CC
measured internally through Pin 3.
• CPU temperature measured using Remote 1 temperature
channel.
• Ambient temperature measured through Remote 2
temperature channel.
• Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. Alternatively, it can be
programmed as an SMBALERT system interrupt output.
TACH2
PWM3
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
GND
ADT7468
SCL
SDA
D2+
D2–
TACH1
VID[0:4]/VID[0:5]
PWM1
AMBIENT
TEMPERATURE
SMBALERT
THERM
04499-0-004
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
5(VRM9)/6(VRM10)
ADP316x
VRM
CONTROLLER
V
COMP
PROCHOT
CPU FAN
CPU
ICH
Figure 15. ADT7468 Configuration
ADT7468
Rev. 3 | Page 12 of 81 | www.onsemi.com
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7468 is carried out
using the serial system management bus (SMBus). The
ADT7468 is connected to this bus as a slave device, under the
control of a master controller, which is usually (but not
necessarily) the ICH.
The ADT7468 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge bit from the slave device. Transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition might be interpreted as a stop signal when the clock
is high. The number of data bytes that can be transmitted over
the serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse, and then high during the 10th clock pulse
to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7468, write operations contain either one or two
bytes, and read operations contain one byte and perform the
following functions. To write data to one of the device data
registers or read data from it, the address pointer register must
be set so that the correct data register is addressed, then data
can be written into that register or read from it. The first byte of
a write operation always contains an address that is stored in
the address pointer register. If data is to be written to the device,
then the write operation contains a second data byte that is
written to the register selected by the address pointer register.
This write operation is illustrated in Figure 16. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
• If the ADT7468’s address pointer register value is unknown
or not the desired value, it must be set to the correct value
before data can be read from the desired data register. This
is done by performing a write to the ADT7468, but only
the data byte containing the register address is sent, since
no data is written to the register. This is shown in
Figure 17.
A read operation is then performed consisting of the serial
bus address, R/W, bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 18.
• If the address pointer register is known to be at the desired
address, data can be read from the corresponding data
register without first writing to the address pointer register,
as shown in Figure 18
R/W
0
SCL
SDA 1 0 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468
START BY
MASTER
1 9 1
ACK. BY
ADT7468
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468 STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
04499-0-005
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
ADT7468
Rev. 3 | Page 13 of 81 | www.onsemi.com
R/W
0
SCL
SDA 1 0 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7468 STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2
ADDRESS POINTER REGISTER BYTE
1 19
ACK. BY
ADT7468
9
04499-0-006
Figure 17. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA
1 0 1110 D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2
DATA BYTE FROM ADT7468
1 19
ACK. BY
ADT7468
9
04499-0-007
Figure 18. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is not
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7468 also supports the read byte protocol.
(See Intel’s System Management Bus Specifications Rev. 2 for
more information.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7468 are discussed below. The following abbreviations are
used in the diagrams:
S: START
P: STOP
R: READ
W: WRITE
A: ACKNOWLEDGE
A: NO ACKNOWLEDGE
The ADT7468 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7468, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is illustrated in Figure 19.
SLAVE
ADDRESS W AS A P
REGISTER
ADDRESS
2
3
1
5
6
4
04499-0-008
Figure 19. Setting a Register Address for a Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
ADT7468
Rev. 3 | Page 14 of 81 | www.onsemi.com
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This operation is illustrated in Figure 20.
SLAVE
ADDRESS SLAVE
ADDRESS DATAAAWS A P
2
4
6
5
3
1
7
8
04499-0-009
Figure 20. Single Byte Write to a Register
READ OPERATIONS
The ADT7468 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up previously.
In this operation, the master device receives a single byte from a
slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7468, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is illustrated in Figure 21.
SLAVE
ADDRESS
S R A A PDATA
2
1
3
5
6
4
04499-0-010
Figure 21. Single Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7468 has responded to the alert response
address, the master must read the status registers and the
SMBALERT is cleared only if the error condition is absent.
SMBUS TIMEOUT
The ADT7468 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7468 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Configuration Register 1 (Reg. 0x40)
<6> TODIS = 0, SMBus timeout enabled (default).
<6> TODIS = 1, SMBus timeout disabled.
ADT7468
Rev. 3 | Page 15 of 81 | www.onsemi.com
VID CODE MONITORING
The ADT7468 has five dedicated voltage ID (VID code)
inputs. These are digital inputs that can be read back through
the VID register (Reg. 0x43) to determine the processor voltage
required or being used in the system. Five VID code inputs
support VRM9.x solutions. In addition, Pin 21 (12 V input)
can be reconfigured as a sixth VID input to satisfy future
VRM requirements.
VID CODE REGISTERS
VID Code Register 0x43
<0> = VID0, reflects the logic state of Pin 5.
<1> = VID1, reflects the logic state of Pin 6.
<2> = VID2, reflects the logic state of Pin 7.
<3> = VID3, reflects the logic state of Pin 8.
<4> = VID4, reflects the logic state of Pin 19.
<5> = VID5, reconfigurable 12 V input. This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
<6> THLD = 0, VID switching threshold = 1 V,
V
OL
< 0.8 V, V
IH
> 1.7 V, V
MAX
= 3.3 V
THLD = 1, VID switching threshold = 0.6 V,
V
OL
< 0.4 V, V
IH
> 0.8 V, V
MAX
= 3.3 V
<7> VIDSEL = 0, Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1, Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID Code Input Threshold Voltage
The switching threshold for the VID code inputs is approxi-
mately 1 V. To enable future compatibility, it is possible to
reduce the VID code input threshold to 0.6 V. Bit 6 (THLD)
of the VID register (Reg. 0x43) controls the VID input
threshold voltage.
Reconfiguring Pin 21 as VID5 Input
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Because the pin is configured
as VID5, it is not possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
Status Register 2 (Reg. 0x42
<0> 12 V/VC = 0, if Pin 21 is configured as VID5, then Logic 0
denotes no change in VID code within the last 11 µs.
<0> 12 V/VC = 1, if Pin 21 is configured as VID5, then Logic 1
means that a change has occurred on the VID code inputs
within the last 11 µs. An SMBALERT is generated, if this
function is enabled.
VID Code Change Detect Function
The ADT7468 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7468. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12 V/VC bit and denotes a VID
change when set. The VID code change bit is set when the logic
states on the VID inputs are different than they were 11 µs
previously. The change of VID code can be used to generate an
SMBALERT interrupt. If an SMBALERT interrupt is not
required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VID
code changes.
ADT7468
Rev. 3 | Page 16 of 81 | www.onsemi.com
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter, which has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
inputs have built-in attenuators to allow measurement of 2.5 V,
3.3 V, 5 V, 12 V, and the processor core voltage V
CCP
without any
external components. To allow for the tolerance of these supply
voltages, the ADC produces an output of 3/4 full scale (decimal
768 or 300 hex) for the nominal input voltage and therefore has
adequate headroom to cope with overvoltages.
VOLTAGE MEASUREMENT INPUT
The ADT7468 has four external voltage measurement channels
and can measure its own supply voltage, V
CC
. Pins 20 to 23 can
measure 5 V, 12 V, 2.5 V supplies, and the processor core voltage
V
CCP
(0 V to 3 V input). The V
CC
supply voltage measurement is
carried out through the V
CC
pin (Pin 4). Setting Bit 7 of Config-
uration Register 1 (Reg. 0x40) allows a 5 V supply to power the
ADT7468 and be measured without overranging the V
CC
measurement channel. The 2.5 V input can be used to monitor a
chipset supply voltage in computer systems.
Input Circuitry
The internal structure for the analog inputs is shown in
Figure 22. The input circuit consists of an input protection
diode, an attenuator, and a capacitor to form a first-order low-
pass filter that gives input immunity to high frequency noise.
V
CCP
17.5kΩ
52.5kΩ35pF
2.5V
IN
45kΩ
94kΩ30pF
3.3V
IN
68kΩ
71kΩ30pF
5V
IN
93kΩ
47kΩ30pF
12V
IN
120k
Ω
20kΩ30pF
04499-0-011
MUX
Figure 22. Structure of Analog Inputs
Voltage Measurement Registers
Reg. 0x20, 2.5 V reading = 0x00 default
Reg. 0x21, V
CCP
reading = 0x00 default
Reg. 0x22, V
CC
reading = 0x00 default
Reg. 0x23, 5 V reading = 0x00 default
Reg. 0x24, 12 V reading = 0x00 default
Voltage Limit Registers
Associated with each voltage measurement channel is a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Reg. 0x44, 2.5 V low limit = 0x00 default
Reg. 0x45, 2.5 V high limit = 0xFF default
Reg. 0x46, V
CCP
low limit = 0x00 default
Reg. 0x47, V
CCP
high limit = 0xFF default
Reg. 0x48, V
CC
low limit = 0x00 default
Reg. 0x49, V
CC
high limit = 0xFF default
Reg. 0x4A, 5 V low limit = 0x00 default
Reg. 0x4B, 5 V high limit = 0xFF default
Reg. 0x4C, 12 V Low Limit = 0x00 default
Reg. 0x4D, 12 V High Limit = 0xFF default
Table 6 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 0.7 ms and averages 16 conversions to reduce noise; a
measurement takes nominally 11 ms.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7468 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. For
instance, where faster conversions are needed, setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off. This
effectively gives a reading 16 times faster (0.7 ms), but the
reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the 2.5 V, V
CCP
, V
CC
, 5 V, and 12 V
inputs, which allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
ADT7468
Rev. 3 | Page 17 of 81 | www.onsemi.com
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7468 into single-channel ADC conversion mode. In this
mode, the ADT7468 can be made to read a single voltage
channel only. If the internal ADT7468 clock is used, the selected
input is read every 0.7 ms. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 minimum high
byte register (0x55).
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<5> = 1, bypass input attenuators.
<6> = 1, single-channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC channel for single-channel convert mode.
Table 5. Programming the Single Channel ADC Function
Bits <7:5> Reg. 0x55 Channel Selected
000 2.5 V
001 V
CCP
010 V
CC
011 5 V
100 12 V
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Table 6. 10-Bit A/D Output Code vs. V
IN
Input Voltage A/D Output
12 V
IN
5 V
IN
V
CC
(3.3 V
IN
)
1
2.5 V
IN
V
CCP
Decimal Binary (10 Bits)
<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00
0.0156–0.0312 0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 0.0293–0.0058 1 00000000 01
0.0312–0.0469 0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 0.0058–0.0087 2 00000000 10
0.0469–0.0625 0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 0.0087–0.0117 3 00000000 11
0.0625–0.0781 0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 0.0117–0.0146 4 00000001 00
0.0781–0.0937 0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 0.0146–0.0175 5 00000001 01
0.0937–0.1093 0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 0.0175–0.0205 6 00000001 10
0.1093–0.1250 0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 0.0205–0.0234 7 00000001 11
0.1250–0.1406 0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 0.0234–0.0263 8 00000010 00
4.0000–4.0156 1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 0.7500–0.7529 256 (1/4 scale) 01000000 00
8.0000–8.0156 3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 1.5000–1.5029 512 (1/2 scale) 10000000 00
12.0000–12.0156 5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 2.2500–2.2529 768 (3/4 scale) 11000000 00
15.8281–15.8437 6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 2.9677–2.9707 1013 11111101 01
15.8437–15.8593 6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 2.9707–2.9736 1014 11111101 10
15.8593–15.8750 6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 2.9736–2.9765 1015 11111101 11
15.8750–15.8906 6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 2.9765–2.9794 1016 11111110 00
15.8906–15.9062 6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 2.9794–2.9824 1017 11111110 01
15.9062–15.9218 6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 2.9824–2.9853 1018 11111110 10
15.9218–15.9375 6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 2.9853–2.9882 1019 11111110 11
15.9375–15.9531 6.6439–6.6504 4.3828–4.3871 3.3169–3.3202 2.9882–2.9912 1020 11111111 00
15.9531–15.9687 6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 2.9912–2.9941 1021 11111111 01
15.9687–15.9843 6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 2.9941–2.9970 1022 11111111 10
>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11
1
The V
CC
output codes listed assume that V
CC
is 3.3 V. If V
CC
input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the V
CC
output
codes are the same as for the 5 V
IN
column.
ADT7468
Rev. 3 | Page 18 of 81 | www.onsemi.com
TEMPERATURE MEASUREMENT
A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the base-
emitter voltage (V
BE
) of a transistor, operated at constant
current. Unfortunately, this technique requires calibration to
null the effect of the absolute value of V
BE
, which varies from
device to device.
The technique used in the ADT7468 is to measure the change in
V
BE
when the device is operated at three currents. Previous
devices have used only two operating currents, but the use of a
third current allows automatic cancellation of resistances in
series with the external temperature sensor.
Figure 24 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the
collector is not grounded and should be linked to the base. To
prevent ground noise from interfering with the measurement,
the more negative terminal of the sensor is not referenced to
ground, but is biased above ground by an internal diode at the
D− input. C1 can optionally be added as a noise filter (the
recommended maximum value is 1000 pF). However, a better
option in noisy environments is to add a filter, as described in
the Noise Filtering section.
Local Temperature Measurement
The ADT7468 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip 10-bit ADC.
The 8-bit MSB temperature data is stored in the local tempera-
ture register (Address 0x26). Because both positive and negative
temperatures can be measured, the temperature data is stored in
Offset 64 format or twos complement format, as shown in
Table 7 and Table 8. Theoretically, the temperature sensor and
ADC can measure temperatures from −128°C to +127°C (or
−61°C to +191°C in the extended temperature range) with a
resolution of 0.25°C. However, this exceeds the operating
temperature range of the device, so local temperature
measurements outside the ADT7468 operating temperature
range are not possible.
Remote Temperature Measurement
The ADT7468 can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pins 17 and 18, or Pins 15 and 16.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute
value of V
BE
varies from device to device and individual
calibration is required, and therefore the technique is unsuitable
for mass production. The technique used in the ADT7468 is to
measure the change in V
BE
when the device is operated at three
currents.
This is given by
(
)
N
n
q
KT
V
BE
1
/
×
=
∆
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
Figure 23 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors. It could also
be a discrete transistor such as a 2N3904/2N3906.
N2 × II N1 × I I
BIAS
D+
D– LPF
V
DD
V
OUT+
V
OUT–
f
C
= 65kHz
TO ADC
04499-0-012
REMOTE
SENSING
TRANSISTOR
Figure 23. Signal Conditioning for Remote Diode Temperature Sensors
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter is connected
to the D+ input. If an NPN transistor is used, the emitter is
connected to the D– input and the base to the D+ input. Figure
25 and Figure 26 show how to connect the ADT7468 to an NPN
or PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D– input.
To measure ∆V
BE
, the operating current through the sensor is
switched among three related currents. Shown in Figure 23,
N1 × I and N2 × I are different multiples of the current I. The
currents through the temperature diode are switched between
I and N1 × I, giving ∆V
BE1
, and then between I and N2 × I,
giving ∆V
BE2
. The temperature can then be calculated using
the two ∆V
BE
measurements. This method can also cancel the
effect of any series resistance on the temperature measurement.
The resulting ∆V
BE
waveforms are passed through a 65 kHz
low-pass filter to remove noise and then sent to a chopper-
stabilized amplifier that amplifies and rectifies the waveform to
ADT7468
Rev. 3 | Page 19 of 81 | www.onsemi.com
produce a dc voltage proportional to ∆V
BE
. The ADC digitizes
this voltage, and a temperature measurement is produced. To
reduce the effects of noise, digital filtering is performed by
averaging the results of 16 measurement cycles.
The results of remote temperature measurements are stored in
10-bit, twos complement format, as illustrated in Table 7. The
extra resolution for the temperature measurements is held in
the Extended Resolution Register 2 (Reg. 0x77). This gives
temperature readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ and D−
pins to decrease the effects of noise. However, large capacitances
affect the accuracy of the temperature measurement, leading to a
recommended maximum capacitor value of 1000 pF. A capacitor
of this value reduces the noise, but does not eliminate it, making
use of the sensor difficult in a very noisy environment.
The ADT7468 has a major advantage over other devices for
eliminating the effects of noise on the external sensor. Using the
series resistance cancellation feature, a filter can be constructed
between the external temperature sensor and the part. The effect
of any filter resistance seen in series with the remote sensor is
automatically canceled from the temperature result.
The construction of a filter allows the ADT7468 and the remote
temperature sensor to operate in noisy environments. Figure 24
shows a low-pass R-C-R filter, with the following values:
R = 100 Ω, C = 1 nF.
This filtering reduces both common-mode noise and
differential noise.
04499-0-093
D+
1nF
100
Ω
REMOTE
TEMPERATURE
SENSOR D–
100Ω
Figure 24. Filter Between Remote Sensor and ADT7468
Series Resistance Cancellation
Parasitic resistance to the ADT7468 D+ and D− inputs (seen in
series with the remote diode) is caused by a variety of factors,
including PCB track resistance and track length. This series
resistance appears as a temperature offset in the remote sensor’s
temperature measurement. This error typically causes a
0.5°C offset per Ω of parasitic resistance in series with the
remote diode.
The ADT7468 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result, without the need for user characterization of this
resistance. The ADT7468 is designed to automatically cancel,
typically, up to 3 kΩ of resistance. By using an advanced
temperature measurement method, this is transparent to the
user. This feature allows resistances to be added to the sensor
path to produce a filter, allowing the part to be used in noisy
environments. See the Noise Filtering section for details.
Factors Affecting Diode Accuracy
Remote Sensing Diode
The ADT7468 is designed to work with either substrate
transistors built into processors or with discrete transistors.
Substrate transistors are generally PNP types with the collector
connected to the substrate. Discrete types can be either PNP or
NPN transistors connected as a diode (base-shorted to the
collector). If an NPN transistor is used, the collector and base
are connected to D+, and the emitter is connected to D−. If a
PNP transistor is used, the collector and base are connected to
D− and the emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
• The ideality factor, n
f
, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7468 is trimmed for an n
f
value of 1.008. Use the
following equation to calculate the error introduced at a
temperature T (°C), when using a transistor whose n
f
does
not equal 1.008. See the processor data sheet for the
n
f
values.
∆T = (n
f
− 1.008) × (273.15 K + T)
To correct for this error, the user can write the ∆T value to
the offset register. The ADT7468 then automatically adds
or subtracts it from the temperature measurement.
• Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7468, I
HIGH
, is 96 µA and the low level current,
I
LOW
, is 6 µA. If the ADT7468 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU’s data
sheet should advise whether this offset needs to be
removed and how to calculate it. This offset can be
programmed to the offset register. It is important to note
that, if more than one offset must be considered, the
algebraic sum of these offsets must be programmed to the
offset register.
If a discrete transistor is used with the ADT7468, the best
accuracy is obtained by choosing devices according to the
following criteria:
ADT7468
Rev. 3 | Page 20 of 81 | www.onsemi.com
• Base-emitter voltage greater than 0.25 V at 6 µA, with the
highest operating temperature.
• Base-emitter voltage less than 0.95 V at 100 µA, with the
lowest operating temperature.
• Base resistance less than 100 Ω.
• Small variation in h
FE
(from 50 to 150), which indicates
tight control of V
BE
characteristics.
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Table 7. Temperature Data Format
Temperature Digital Output (10-Bit)
1
–128°C 1000 0000 00
–125°C 1000 0011 00
–100°C 1001 1100 00
–75°C 1011 0101 00
–50°C 1100 1110 00
–25°C 1110 0111 00
–10°C 1111 0110 00
0°C 0000 0000 00
10.25°C 0000 1010 01
25.5°C 0001 1001 10
50.75°C 0011 0010 11
75°C 0100 1011 00
100°C 0110 0100 00
125°C 0111 1101 00
127°C 0111 1111 00
1
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
Table 8. Extended Range, Temperature Data Format
Temperature Digital Output (10-Bit)
1
–64°C 0000 0000 00
–1°C 0011 1111 00
0°C 0100 0000 00
1°C 0100 0001 00
10°C 0100 1010 00
25°C 0101 1001 00
50°C 0111 0010 00
75°C 1000 1001 00
100°C 1010 0100 00
125°C 1011 1101 00
191°C 1111 1111 00
1
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
2N3904
NPN
ADT7468
D+
D–
04499-0-013
Figure 25. Measuring Temperature Using an NPN Transistor
2N3906
PNP
ADT7468
D+
D–
04499-0-014
Figure 26. Measuring Temperature Using a PNP Transistor
Nulling Temperature Errors
As CPUs are developed that run faster, it is getting more
difficult to avoid high frequency clocks when routing the
D+/D– traces around a system board. Even when
recommended layout guidelines are followed, some temperature
errors may still be attributed to noise coupled onto the D+/D–
lines. Constant high frequency noise usually attenuates or
increases temperature measurements by a linear, constant value.
The ADT7468 has temperature offset registers at Addresses 0x70
and 0x72 for the Remote 1 and Remote 2 temperature channels.
By doing a one-time calibration of the system, the user can
determine the offset caused by system board noise and null it
using the offset registers. The offset registers automatically add
an Offset 64/twos complement 8-bit reading to every
temperature measurement. The LSBs add 0.5°C offset to the
temperature reading; therefore, the 8-bit register effectively
allows temperature offsets up to ±64°C with a resolution of
0.5°C. This ensures that the readings in the temperature
measurement registers are as accurate as possible.
Temperature Offset Registers
Reg. 0x70, Remote 1 temperature offset = 0x00 (0°C default)
Reg. 0x71, Local temperature offset = 0x00 (0°C default)
Reg. 0x72, Remote 2 temperature offset = 0x00 (0°C default)
ADT7463/ADT7468 Backwards Compatible Mode
By setting Bit 1 of Configuration Register 5 (0x7C), all
temperature measurements are stored in the zone temperature
value registers (0x25, 0x26, and 0x27) in twos complement in the
range of −64°C to +127°C (the ADT7468 makes calculations based
on the Offset 64 extended range and clamps the results, if
necessary.) The temperature limits must be reprogrammed in twos
complement. If a twos complement temperature below −63°C is
entered, the temperature is clamped to −63°C. In this mode, the
diode fault condition remains at −128°C = 1000 0000, while in the
extended temperature range (−64°C to +191°C) the fault condition
is represented by −64°C = 0000 0000.
Temperature Measurement Registers
Reg. 0x25, Remote 1 temperature
Reg. 0x26, Local temperature
Reg. 0x27, Remote 2 temperature
Reg. 0x77, Extended Resolution 2 = 0x00 default
<7:6> TDM2, Remote 2 temperature LSBs
<5:4> LTMP, local temperature LSBs
<3:2> TDM1, Remote 1 temperature LSBs
ADT7468
Rev. 3 | Page 21 of 81 | www.onsemi.com
Temperature Measurement Limit Registers
Each temperature measurement channel is associated with high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Reg. 0x4E, Remote 1 temperature low limit = 0x01 default
Reg. 0x4F, Remote 1 temperature high limit = 0x7F default
Reg. 0x50, local temperature low limit = 0x01 default
Reg. 0x51, local temperature high limit = 0x7F default
Reg. 0x52, Remote 2 temperature low limit = 0x01 default
Reg. 0x53, Remote 2 temperature high limit = 0x7F default
Reading Temperature from the ADT7468
It is important to note that temperature can be read from the
ADT7468 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is
required, the temperature readings can be read back at any
time and in no particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read and
vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7468 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings are made internally and the results are averaged
before being placed into the value register. Sometimes it is
necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off.
Table 9. Conversion Time with Averaging Disabled
Channel Measurement Time
Voltage Channels 0.7 ms
Remote Temperature 1 7 ms
Remote Temperature 2 7 ms
Local Temperature 1.3 ms
Table 10. Conversion Time with Averaging Enabled
Channel Measurement Time
Voltage Channels 11 ms
Remote Temperature 39 ms
Local Temperature 12 ms
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places
the ADT7468 into single-channel ADC conversion mode. In
this mode, the ADT7468 can be made to read a single temp-
erature channel only. The appropriate ADC channel is selected
by writing to Bits <7:5> of the TACH1 minimum high byte
register (0x55).
Table 11. Channel Selection
Bits <7:5> Reg. 0x55 Channel Selected
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<6> = 1, single-channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> selects ADC channel for single-channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
temperature limits. When a temperature exceeds its THERM
temperature limit, all PWM outputs run at the maximum PWM
duty cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A). This
effectively runs the fans at the fastest allowed speed. The fans
stay running at this speed until the temperature drops below
THERM minus hysteresis. (This can be disabled by setting the
boost bit in Configuration Register 3, Bit 2, Reg. 0x78.) The
hysteresis value for that THERM temperature limit is the value
programmed into Reg. 0x6D and Reg. 0x6E (hysteresis
registers). The default hysteresis value is 4°C.
FANS
TEMPERATURE
100%
HYSTERESIS (°C)
THERM LIMIT
04499-0-015
Figure 27. THERM Temperature Limit Operation
ADT7468
Rev. 3 | Page 22 of 81 | www.onsemi.com
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Each measurement channel on the ADT7468 is associated with
high and low limits. These can form the basis of system status
monitoring; a status bit can be set for any out-of-limit condition
and detected by polling the device. Alternatively, SMBALERT
interrupts can be generated to flag a processor or micro-
controller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7468.
Voltage Limit Registers
Reg. 0x44, 2.5 V low limit = 0x00 default, Register 0x44 2.5 V
low limit = 0x00 default
Reg. 0x45, 2.5 V high limit = 0xFF default
Reg. 0x46, V
CCP
low limit = 0x00 default
Reg. 0x47, V
CCP
high limit = 0xFF default
Reg. 0x48, V
CC
low limit = 0x00 default
Reg. 0x49, V
CC
high limit = 0xFF default
Reg. 0x4A, 5 V low limit = 0x00 default
Reg. 0x4B, 5 V high limit = 0xFF default
Reg. 0x4C, 12 V low limit = 0x00 default
Reg. 0x4D, 12 V high limit = 0xFF default
Reg. 0x46, V
CCP
low limit = 0x00 default
Reg. 0x47, V
CCP
high limit = 0xFF default
Reg. 0x48, V
CC
low limit = 0x00 default
Reg. 0x49, V
CC
high limit = 0xFF default
Temperature Limit Registers
Reg. 0x4E, Remote 1 temperature low limit = 0x01 default
Reg. 0x4F, Remote 1 temperature high limit = 0x7F default
Reg. 0x6A, Remote 1 THERM limit = 0x64 default
Reg. 0x50, local temperature low limit = 0x01 default
Reg. 0x51, local temperature high limit = 0x7F default
Reg. 0x6B, local THERM limit = 0x64 default
Reg. 0x52, Remote 2 temperature low limit = 0x01 default
Reg. 0x53, Remote 2 Temperature high limit = 0x7F default
Reg. 0x6C, Remote 2 THERM limit = 0x64 default
THERM Limit Register
Reg. 0x7A, THERM limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because slow or stalled fans are normally the only conditions of
interest, only high limits exist for fan TACHs. Because the fan
TACH period is measured, exceeding the limit indicates a slow
or stalled fan.
Fan Limit Registers
Reg. 0x54, TACH1 minimum low byte = 0x00 default
Reg. 0x55, TACH1 minimum high byte = 0x00 default
Reg. 0x56, TACH2 minimum low byte = 0x00 default
Reg. 0x57, TACH2 minimum high byte = 0x00 default
Reg. 0x58, TACH3 minimum low byte = 0x00 default
Reg. 0x59, TACH3 minimum high byte = 0x00 default
Reg. 0x5A, TACH4 minimum low byte = 0x00 default
Reg. 0x5B, TACH4 minimum high byte = 0x00 default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7468 can be
enabled for monitoring. The ADT7468 measures all voltage and
temperature measurements in a round-robin format and sets
the appropriate status bit for out-of-limit conditions. TACH
measurements are not part of this round-robin cycle. Compari-
sons are done differently depending on whether the measured
value is compared to a high or low limit.
High limit: > comparison performed
Low limit: ≤ comparison performed
Voltage and temperature channels use a window comparator for
error detecting and therefore have high and low limits. Fan
speed measurements use only a low limit, which is needed only
in manual fan control mode.
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). By
default, the ADT7463 powers up with this bit set. The ADC
measures each analog input and as each measurement is
completed, the result is automatically stored in the appropriate
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
Since the ADC normally runs freely in this manner, the time
taken to monitor all the analog inputs is usually not of interest,
because the most recently measured value of any input can be
read at any time.
ADT7468
Rev. 3 | Page 23 of 81 | www.onsemi.com
For applications where the monitoring cycle time is important,
it can be calculated easily.
The measured channels are
• Four dedicated supply voltage inputs
• Supply voltage (V
CC
pin)
• Local temperature
• Two remote temperatures
As mentioned previously, the ADC performs round-robin
conversions and takes 11 ms for each voltage measurement,
12 ms for a local temperature reading, and 39 ms for each
remote temperature reading. The total monitoring cycle time
for averaged voltage and temperature monitoring is, therefore,
nominally
(5 × 11) + 12 + (2 × 39) = 145 ms
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
STATUS REGISTERS
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out-of-limit,
the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event
has been flagged in Status Register 2. This means that the user
also needs to read Status Register 2. Alternatively, Pin 10 or
Pin 14 can be configured as an SMBALERT output. This hard
interrupt automatically notifies the system supervisor of an out-
of-limit condition. Reading the status registers clears the appro-
priate status bit as long as the error condition that caused the
interrupt has cleared. Status register bits are sticky. The status
bits are referred to as sticky, because they remain set until read
by software. Whenever a status bit is set, indicating an out-of-
limit condition, it remains set even if the event that caused it
has ceased (until read). The only way to clear the status bit is to
read the status register after the event has ceased. Interrupt
status mask registers (0x74, and 0x75) allow individual inter-
rupt sources to be masked from causing an SMBALERT. How-
ever, if one of these masked interrupt sources goes out-of-limit,
its associated status bit is set in the interrupt status registers.
Status Register 1 (Reg. 0x41)
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1, local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded.
Bit 2 (V
CC
) = 1, V
CC
high or low limit has been exceeded.
Bit 1 (V
CCP
) = 1, V
CCP
high or low limit has been exceeded.
Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded.
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates that the THERM limit has been
exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum
speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has
been exceeded.
Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been
exceeded. If the VID code change function is used, this bit
indicates a change in VID code on the VID0 to VID5 inputs.
INTERRUPTS
SMBALERT Interrupt Behavior
The ADT7468 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
“STICKY”
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
04499-0-022
Figure 28. SMBALERT and Status Bit Behavior
ADT7468
Rev. 3 | Page 24 of 81 | www.onsemi.com
Figure 28 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. This ensures that an out-
of-limit event cannot be missed, if software is polling the device
periodically. Note that the SMBALERT output remains low for
the entire duration that a reading is out-of-limit and until the
status register has been read. This has implications on how
software handles the interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
4. Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74 and
Reg. 0x75).
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 29.
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses 0x74
and 0x75. These allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
“STICKY”
STATUS BIT
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
SMBALERT
04499-0-023
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 29. How Masking the Interrupt Source Affects SMBALERT Output
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (V
CC
) = 1, masks SMBALERT for V
CC
channel.
Bit 0 (V
CCP
) = 1, masks SMBALERT for V
CCP
channel.
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM temperature limits).
Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or for
a VID code change, depending on the function used.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default.
Pin 10 or Pin 14 can be reconfigured as an SMBALERT output
to signal out-of-limit conditions.
Table 12. Configuring Pin 10 as SMBALERT Output
Register Bit Setting
Configuration Register 3
(Reg. 0x78)
<0> Pin 10 = alert
<1> Pin 10 = PWM2
Assigning THERM Functionality to a Pin
Pin 14 on the ADT7468 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D.
ADT7468
Rev. 3 | Page 25 of 81 | www.onsemi.com
If THERM is enabled (Bit 1, Configuration Register 3 at
Address 0x78):
• Pin 20 becomes THERM.
• If Pin 14 is configured as THERM (Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D), then THERM
is enabled on this pin.
If THERM is not enabled:
• Pin 20 becomes a 5 V measurement input.
• If Pin 14 is configured as THERM, then THERM is
disabled on this Pin.
Table 13. Configuring Pin 14
Bit 0 Bit 1 Function
0 0 TACH4
0 1 THERM
1 0 SMBALERT
1 1 GPIO
THERM as an Input
When THERM is configured as an input, the user can
time assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge
system performance.
The user can also set up the ADT7468 to run the fans at 100%
whenever the THERM pin is driven low externally by setting
the boost bit (Bit 2) in Configuration Register 3 (Address 0x78)
to 1. Note that to set this up, the fan must be already running,
for example, in manual mode when the current duty cycle is
above 0x00, or in automatic mode when the temperature is
above T
MIN
. If the temperature is below T
MIN
or if the duty cycle
in manual mode is set to 0x00, then pulling the THERM low
externally has no effect. See Figure 30 for more information.
THERM
T
MIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS BELOW T
MIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS ABOVE T
MIN
AND FANS
ARE ALREADY RUNNING
04499-0-024
Figure 30. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
THERM Timer
The ADT7468 has an internal timer to measure THERM
assertion time. The THERM input can be connected to the
PROCHOT output of a Pentium 4 CPU to measure system
performance or be connected to the output of a trip point
temperature sensor, to name a couple of functions of the timer.
The timer is started on the assertion of the ADT7468’s THERM
input and stopped when THERM is unasserted. The timer
counts THERM times cumulatively, that is, the timer resumes
counting on the next THERM assertion. The THERM timer
continues to accumulate THERM assertion times until the
timer is read (it is cleared on read) or until it reaches full scale.
If the counter reaches full scale, it stops at that reading until
cleared.
The 8-bit THERM timer register (Reg. 0x79) is designed such
that Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 now becomes the LSB of
the timer with a resolution of 22.76 ms (see Figure 31).
When using the THERM timer, be aware of the following after a
THERM timer read (Reg. 0x79):
1. The contents of the timer are cleared on read.
2. The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
If the THERM timer is read during a THERM assertion, then
the following happens:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3. The THERM timer increments from 0.
4. If the THERM timer limit (Reg. 0x7A) = 0x00, then the
F4P bit is set.
ADT7468
Rev. 3 | Page 26 of 81 | www.onsemi.com
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7468 can generate SMBALERTs when a programma-
ble THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 secs (first THERM assertion) to 5.825 secs to be set
before an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Status Register 2 is set and an
SMBALERT is generated. Note that the F4P bit (Bit 5) of Mask
Register 2 (Reg. 0x75) masks out SMBALERTs if this bit is set to
1, although the F4P bit of Interrupt Status Register 2 stays set if
the THERM timer limit is exceeded.
THERM
THERM
TIMER
(REG. 0x79) THERM ASSERTED
≤ 22.76ms
7 6 5 3 2 1 04
0 0 0 0 0 0 10
THERM
TIMER
(REG. 0x79) THERM ASSERTED
≥ 45.52ms
7 6 5 3 2 1 04
0 0 0 0 0 1 00
THERM
TIMER
(REG. 0x79) THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
7 6 5 3 2 1 04
0 0 0 0 1 0 10
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
04499-0-025
Figure 31.Understanding the THERM Timer
Figure 32 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM timer
limit value of 0x01 generates an SMBALERT, once cumulative
THERM assertions exceed 45.52 ms.
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
IN OUT
RESET
LATCH
CLEARED
ON READ
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
1 = MASK
F4P BIT (BIT 5)
STATUS REGISTER 2
COMPARATOR
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
7
6
543
2
10 765 4 3 21 0
THERM LIMIT
(REG. 0x7A) THERM TIMER
(REG. 0x79)
THERM TIMER CLEARED ON READ
SMBALERT
THERM
04499-0-026
Figure 32. Functional Block Diagram of THERM Monitoring Circuitry
ADT7468
Rev. 3 | Page 27 of 81 | www.onsemi.com
Configuring the Relevant THERM Behavior
1. Configure the desired pin as the THERM timer input.
Setting Bit 1 (THERM timer enable) of Configuration
Register 3 (Reg. 0x78) enables the THERM timer
monitoring functionality. This is disabled on Pins 14 and
20 by default.
Setting Bits 0 and 1 (PIN14FUNC) of Configuration
Register 4 (Reg. 0x7D) enables THERM timer output
functionality on Pin 20 (Bit 1 of Configuration Register 3,
THERM, must also be set). Pin 14 can also be used
as TACH4.
2. Select the desired fan behavior for THERM timer events.
Assuming that the fans are running, setting Bit 2 (BOOST
bit) of Configuration Register 3 (Reg. 0x78) causes all fans
to run at 100% duty cycle whenever THERM is asserted.
This allows fail-safe system cooling. If this bit is 0, the
fans run at their current settings and are not affected by
THERM events. If the fans are not already running when
THERM is asserted, the fans do not run to full speed.
3. Select whether THERM timer events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks
out SMBALERTs when the THERM timer limit value is
exceeded. This bit should be cleared, if SMBALERTs based
on THERM events are required.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative
THERM assertion time limit is exceeded. A value of 0x00
causes an SMBALERT to be generated on the first THERM
assertion.
5. Select a THERM monitoring time.
This value specifies how often OS or BIOS level software
checks the THERM timer. For example, BIOS could read
the THERM timer once an hour to determine the cumula-
tive THERM assertion time. If, for example, the total
THERM assertion time is <22.76 ms in Hour 1, >182.08
ms in Hour 2, and >5.825 secs in Hour 3, this can indicate
that system performance is degrading significantly, because
THERM is asserting more frequently on an hourly basis.
Alternatively, OS or BIOS level software can timestamp
when the system is powered on. If an SMBALERT is
generated due to the THERM timer limit being exceeded,
another timestamp can be taken. The difference in time
can be calculated for a fixed THERM timer limit time. For
example, if it takes one week for a THERM timer limit of
2.914 secs to be exceeded and the next time it takes only
one hour, then this is an indication of a serious
degradation in system performance.
Configuring the THERM Pin as an Output
In addition to monitoring THERM as an input, the ADT7468
can optionally drive THERM low as an output. In cases where
PROCHOT is bidirectional, THERM can be used to throttle the
processor by asserting PROCHOT. The user can preprogram
system-critical thermal limits. If the temperature exceeds a
thermal limit by 0.25°C, THERM asserts low. If the temperature
is still above the thermal limit on the next monitoring cycle,
THERM stays low. THERM remains asserted low until the
temperature is equal to or below the thermal limit. Because the
temperature for that channel is measured only once for every
monitoring cycle, after THERM asserts it is guaranteed to
remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low, if the
Remote 1, local, or Remote 2 THERM temperature limits are
exceeded by 0.25°C. The THERM temperature limit registers
are at Registers 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3
of Registers 0x5F, 0x60, and 0x61 enables the THERM output
feature for the Remote 1, local, and Remote 2 temperature
channels, respectively. Figure 33 shows how the THERM
pin asserts low as an output in the event of a critical
overtemperature.
ADT7468
MONITORING
CYCLE
TEMP
THERM LIMIT
+0.25°C
THERM LIMIT
THERM
04499-0-027
Figure 33. Asserting THERM as an Output, Based on Tripping THERM Limits
An alternative method of disabling THERM is to program the
THERM temperature limit to –64°C or less in Offset 64 mode,
or −128°C or less in twos complement mode; that is, for
THERM temperature limit values less than –63°C or –128°C,
respectively, THERM is disabled.
ADT7468
Rev. 3 | Page 28 of 81 | www.onsemi.com
ACTIVE COOLING
DRIVING THE FAN USING PWM CONTROL
The ADT7468 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. For 4-wire fans, the PWM drive might need
only a pull-up resistor. In many cases, the 4-wire fan PWM
input has a built-in pull-up resistor.
The ADT7468 PWM frequency can be set to a selection of low
frequencies or a single high PWM frequency. The low fre-
quency options are usually used for 2-wire and 3-wire fans,
while the high frequency option is usually used with 4-wire
fans.
For 2-wire or 3-wire fans, a single N-channel MOSFET is the
only drive device required. The specifications of the MOSFET
depend on the maximum current required by the fan being
driven and the input capacitance of the FET. Because a 10 kΩ
(or greater) resistor must be used as a PWM pull-up, an FET
with large input capacitance can cause the PWM output to
become distorted and adversely affect the fan control range.
This is a requirement only when using high frequency
PWM mode.
Typical notebook fans draw a nominal 170 mA, and so SOT
devices can be used where board space is a concern. In
desktops, fans can typically draw 250 mA to 300 mA each. If
you drive several fans in parallel from a single PWM output or
drive larger server fans, the MOSFET must handle the higher
current requirements. The only other stipulation is that the
MOSFET should have a gate voltage drive, V
GS
< 3.3 V, for direct
interfacing to the PWM_OUT pin. V
GS
can be greater than 3.3 V
as long as the pull-up on the gate is tied to 5 V. The MOSFET
should also have a low on resistance to ensure that there is not
significant voltage drop across the FET, which would reduce the
voltage applied across the fan and, therefore, the maximum
operating speed of the fan.
Figure 34 shows how to drive a 3-wire fan using PWM control.
ADT7468
TACH/AIN
PWM
12V
FAN
Q1
NDT3055L
3.3V
12V 12V
10kΩ
4.7kΩ
10kΩ
10kΩ
1N4148
04499-0-028
Figure 34. Driving a 3-Wire Fan Using an N-Channel MOSFET
Figure 34 uses a 10 kΩ pull-up resistor for the TACH signal.
This assumes that the TACH signal is an open-collector from
the fan. In all cases, the TACH signal from the fan must be kept
below 5 V maximum to prevent damaging the ADT7468. If in
doubt as to whether the fan has an open-collector or totem-pole
TACH output, use one of the input signal conditioning circuits
shown in the Fan Speed Measurement section.
Figure 35 shows a fan drive circuit using an NPN transistor,
such as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher on resistance than MOSFETs. When
choosing a transistor, care should be taken to ensure that it
meets the fan’s current requirements. Ensure that the base
resistor is chosen such that the transistor is saturated when the
fan is powered on.
Because 4-wire fans are powered continuously, the fan speed is
not switched on or off as with previous PWM driven/powered
fans. This enables it to perform better than 3-wire fans,
especially for high frequency applications.
ADT7468
TACH TACH
PWM
12V
FAN
Q1
MMBT2222
3.3V
12V 12V
665Ω
4.7kΩ
10kΩ
10kΩ
1N4148
04499-0-029
Figure 35. Driving a 3-Wire Fan Using an NPN Transistor
Figure 36 shows a typical drive circuit for 4-wire fans.
04499-0-041
ADT7468
TACH/AIN
PWM
12V, 4-WIRE FAN
3.3V
12V 12V
2kΩ
4.7kΩ
10kΩ
10kΩVCC
TACH
TACH PWM
Figure 36. Driving a 4-Wire Fan
ADT7468
Rev. 3 | Page 29 of 81 | www.onsemi.com
Driving Two Fans from PWM3
The ADT7468 has four TACH inputs available for fan speed
measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the
PWM3 output in parallel with the third fan. Figure 37 shows
how to drive two fans in parallel using low cost NPN
transistors. Figure 38 shows the equivalent circuit using a
MOSFET.
Because the MOSFET can handle up to 3.5 A, a second fan can
be connected directly in parallel with the first. Care should be
taken in designing drive circuits with transistors and FETs to
ensure that the PWM pins are not required to source current
and that they sink less than the 5 mA maximum current
specified in the data sheet.
Driving up to Three Fans from PWM3
TACH measurements for fans are synchronized to particular
PWM channels; for example, TACH1 is synchronized to
PWM1. TACH3 and TACH4 are both synchronized to PWM3,
and therefore PWM3 can drive two fans. Alternatively, PWM3
can be programmed to synchronize TACH2, TACH3, and
TACH4 to the PWM3 output. This allows PWM3 to drive two
or three fans. In this case, the drive circuitry is as shown in
Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables
this function.
Synchronization is not required in high frequency mode when
used with 4-wire fans.
<4> (SYNC) Enhance Acoustics Register 1 (Reg. 0x62)
SYNC = 1, synchronizes TACH2, TACH3, and TACH4 to
PWM3.
ADT7468
PWM3
3.3V 3.3V
12V
04499-0-030
1N4148
Q1
MMBT3904
Q2
MMBT2222
Q3
MMBT2222
10Ω
10Ω
2.2kΩ
1kΩ
TACH3 TACH4
Figure 37. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
ADT7468
PWM3
TACH3
TACH4
3.3V
3.3V
3.3V
04499-0-031
+V +V
TACH TACH
Q1
NDT3055L
1N4148 5V OR
12V FAN
5V OR
12V FAN
10kΩ
TYPICAL
10kΩ
TYPICAL
10kΩ
TYPICAL
Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
ADT7468
Rev. 3 | Page 30 of 81 | www.onsemi.com
Driving 2-Wire Fans
The ADT7468 can support 2-wire fans only when the low
frequency PWM mode is selected in Configuration Register 5,
Bit 2. If this bit is not set to 1, the ADT7468 cannot measure the
speed of 2-wire fans.
Figure 39 shows how a 2-wire fan can be connected to the
ADT7468. This circuit allows the speed of a 2-wire fan to be
measured, although the fan has no dedicated TACH signal. A
series resistor, R
SENSE
, in the fan circuit converts the fan
commutation pulses into a voltage, which is ac-coupled into the
ADT7468 through the 0.01 µF capacitor. On-chip signal
conditioning allows accurate monitoring of fan speed. The
value of R
SENSE
chosen depends upon the programmed input
threshold and the current drawn by the fan. For fans drawing
approximately 200 mA, a 2 Ω R
SENSE
value is suitable when the
threshold is programmed as 40 mV.
04499-0-032
ADT7468
PWM
TACH
5V OR
12V FAN
Q1
NDT3055L
3.3V
+V
10kΩ
TYPICAL
1N4148
0.01µFR
SENSE
2Ω
TYPICAL
Figure 39. Driving a 2-Wire Fan
Figure 40 shows a typical plot of the sensing waveform at the
TACH/AIN pin.
04499-0-033
Figure 40. Fan Speed Sensing Waveform at TACH/AIN Pin
For fans that draw more current, such as larger desktop or
server fans, R
SENSE
can be reduced for the same programmed
threshold. The smaller the threshold programmed the better,
because more voltage is developed across the fan and the fan
spins faster. Note that when the voltage spikes (either negative
or positive) are more than 40 mV in amplitude, the fan speed
can be reliably determined.
LAYING OUT 2-WIRE AND 3-WIRE FANS
Figure 41 shows how to lay out a common circuit arrangement
for 2-wire and 3-wire fans. Some components are not
populated, depending on whether a 2-wire or 3-wire fan is used.
04499-0-042
Q1
MMBT2222
R2
R1
R3 R4
R5
PWM
1N4148
3.3V OR 5V
12V OR 5V
C1
TACH FOR 3-WIRE FANS:
POPULATE R1, R2, R3
R4 = 0W
C1 = UNPOPULATED
FOR 2-WIRE FANS:
POPULATE R4, C1
R1, R2, R3 UNPOPULATED
Figure 41. Planning for 2-Wire or 3-Wire Fans on a PCB
TACH Inputs
Pins 9, 11, 12, and 14 (when configured as TACH inputs) are
open-drain TACH inputs intended for fan speed measurement.
Signal conditioning in the ADT7468 accommodates the slow
rise and fall times typical of fan tachometer outputs. The
maximum input signal range is 0 V to 5 V, even when V
CC
is less
than 5 V. When these inputs are supplied from fan outputs that
exceed 0 V to 5 V, either resistive attenuation of the fan signal or
diode clamping must be included to keep inputs within an
acceptable range.
Figure 42 to Figure 45 show circuits for most common fan
TACH outputs.
If the fan TACH output has a resistive pull-up to V
CC
, it can be
connected directly to the fan input, as shown in Figure 42.
12V
V
CC
04499-0-034
PULL-UP
4.7kΩ
TYPICAL TACH
OUTPUT FAN SPEED
COUNTER
TACH
ADT7468
Figure 42. Fan with TACH Pull-Up to V
CC
ADT7468
Rev. 3 | Page 31 of 81 | www.onsemi.com
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V) then the fan output can be clamped with a
Zener diode, as shown in Figure 43. The Zener diode voltage
should be chosen so that it is greater than V
IH
of the TACH
input but less than 5 V, allowing for the voltage tolerance of the
Zener. A value of between 3 V and 5 V is suitable.
12V V
CC
04499-0-035
PULL-UP
4.7kΩ
TYPICAL TACH
OUTPUT FAN SPEED
COUNTER
TACH
ADT7468
ZD1*
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V
CC
Figure 43. Fan with TACH Pull-Up Greater than 5 V, for example, 12 V),
Clamped with Zener Diode
If the fan has a strong pull-up (<1 kΩ) to 12 V or a totem-pole
output, then a series resistor can be added to limit the Zener
current, as shown in Figure 44.
5V OR 12V V
CC
04499-0-036
PULL-UP TYP
<1kΩ OR
TOTEM POLE
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7468
ZD1
ZENER*
FAN
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V
CC
R1
10kΩ
Figure 44. Fan with Strong TACH Pull-Up Greater than V
CC
or Totem-Pole
Output, Clamped with Zener and Resistor
Alternatively, a resistive attenuator can be used, as shown in
Figure 45. R1 and R2 should be chosen such that
2 V < V
PULL-UP
× R2/(R
PULL-UP
+ R1 + R2) < 5 V
The fan inputs have an input resistance of nominally 160 kΩ to
ground, which should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and
47 kΩ, respectively. This gives a high input voltage of 3.83 V.
12V V
CC
04499-0-037
<1kΩ
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
ADT7468
R2*
*SEE TEXT
R1*
Figure 45. Fan with Strong TACH Pull-Up Greater than V
CC
or Totem-Pole
Output, Attenuated with R1/R2
FAN SPEED MEASUREMENT
The fan counter does not count the fan TACH output pulses
directly, because the fan speed could be less than 1,000 RPM
and it would take several seconds to accumulate a reasonably
large and accurate count. Instead, the period of the fan revo-
lution is measured by gating an on-chip 90 kHz oscillator into
the input of a 16-bit counter for N periods of the fan TACH
output (see Figure 46), so the accumulated count is actually
proportional to the fan tachometer period and inversely
proportional to the fan speed.
N, the number of pulses counted, is determined by the settings
of Register 0x7B (TACH pulses per revolution register). This
register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
1
2
3
4
CLOCK
PWM
TACH
04499-0-038
Figure 46. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7468.
Reg. 0x28, TACH1 low byte = 0x00 default
Reg. 0x29, TACH1 high byte = 0x00 default
Reg. 0x2A, TACH2 low byte = 0x00 default
Reg. 0x2B, TACH2 high byte = 0x00 default
Reg. 0x2C, TACH3 low byte = 0x00 default
Reg. 0x2D, TACH3 high byte = 0x00 default
Reg. 0x2E, TACH4 low byte = 0x00 default
Reg. 0x2F, TACH4 high byte = 0x00 default
Reading Fan Speed from the ADT7468
The measurement of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read, preventing erroneous TACH readings.
ADT7468
Rev. 3 | Page 32 of 81 | www.onsemi.com
The fan tachometer reading registers report back the number of
11.11 µs period clocks (90 kHz oscillator) gated to the fan speed
counter, from the rising edge of the first fan TACH pulse to the
rising edge of the third fan TACH pulse (assuming two pulses
per revolution are being counted). Because the device is essen-
tially measuring the fan TACH period, the higher the count
value, the slower the fan is actually running. A 16-bit fan tach-
ometer reading of 0xFFFF indicates either that the fan has
stalled or is running very slowly (<100 RPM).
High limit: >comparison performed
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of two
bytes.
Reg. 0x54, TACH1 minimum low byte = 0xFF default
Reg. 0x55, TACH1 minimum high byte = 0xFF default
Reg. 0x56, TACH2 minimum low byte = 0xFF default
Reg. 0x57, TACH2 minimum high byte = 0xFF default
Reg. 0x58, TACH3 minimum low byte = 0xFF default
Reg. 0x59, TACH3 minimum high byte = 0xFF default
Reg. 0x5A, TACH4 minimum low byte = 0xFF default
Reg. 0x5B, TACH4 minimum high byte = 0xFF default
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every
second.
The fast bit (Bit 3) of Configuration Register 3 (Reg. 0x78),
when set, updates the fan TACH readings every 250 ms.
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, their associated dc bit in
Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source. For optimal results, the associated dc bit
should always be set when using 4-wire fans.
Calculating Fan Speed
Assuming a fan with a two pulses per revolution (and two
pulses per revolution being measured), fan speed is calculated
by
Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading
where the Fan TACH reading is the 16-bit fan tachometer
reading.
Example:
TACH1 high byte (Reg. 0x29) = 0x17
TACH1 low byte (Reg. 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
RPM = (f × 60)/Fan 1 TACH Reading
RPM = (90000 × 60)/6143
Fan Speed = 879 RPM
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 TACH pulses
per revolution. Once the number of fan TACH pulses has been
determined, it can be programmed into the fan pulses per
revolution register (Reg. 0x7B) for each fan. Alternatively, this
register can be used to determine the number or pulses per
revolution output by a given fan. By plotting fan speed measure-
ments at 100% speed with different pulses per revolution
setting, the smoothest graph with the lowest ripple determines
the correct pulses per revolution value.
Fan Pulses per Revolution Register
<1:0> Fan 1 default = 2 pulses per revolution
<3:2> Fan 2 default = 2 pulses per revolution
<5:4> Fan 3 default = 2 pulses per revolution
<7:6> Fan 4 default = 2 pulses per revolution
00 = 1 pulse per revolution
01 = 2 pulses per revolution
10 = 3 pulses per revolution
11 = 4 pulses per revolution
2-Wire Fan Speed Measurements
(Low Frequency Mode Only)
The ADT7468 is capable of measuring the speed of 2-wire fans,
that is, fans without TACH outputs. To do this, the fan must be
interfaced as shown in the Driving 2-Wire Fans section. In this
case, the TACH inputs should be reprogrammed as analog
inputs, AIN.
Configuration Register 2 (Reg. 0x73)
Bit 3 (AIN4) = 1, Pin 14 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 2 (AIN3) = 1, Pin 9 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 1 (AIN2) = 1, Pin 12 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 0 (AIN1) = 1, Pin 11 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
AIN Switching Threshold
Having configured the TACH inputs as AIN inputs for 2-wire
measurements, a user can select the sensing threshold for the AIN
signal.
ADT7468
Rev. 3 | Page 33 of 81 | www.onsemi.com
Configuration Register 4 (Reg. 0x7D)
<3:2> AINL, input threshold for 2-wire fan speed
measurements.
00 = ±20 mV
01 = ±40 mV
10 = ±80 mV
11 = ±130 mV
FAN SPIN-UP
The ADT7468 has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two TACH pulses have been
detected, the PWM duty cycle goes to the expected running
value, for example, 33%. The advantage is that fans have
different spin-up characteristics and take different times to
overcome inertia. The ADT7468 runs the fans just fast enough
to overcome inertia and is quieter during spin-up than fans
programmed to spin up for a given spin-up time.
Fan Start-Up Timeout
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7468 includes a
fan start-up timeout function. During this time, the ADT7468
looks for two TACH pulses. If two TACH pulses are not
detected, then an interrupt is generated.
Using Configuration Register 4 (0x40) Bit 5 (FSPDIS), this
functionality can be changed (see the Disabling Fan Start-Up
Timeout section).
PWM1 Configuration (Reg. 0x5C)
<2:0> spin, startup timeout for PWM1.
000 = No startup timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
PWM2 Configuration (Reg. 0x5D)
<2:0> spin, startup timeout for PWM2.
000 = No startup timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
PWM3 Configuration (Reg. 0x5E)
<2:0> spin, start-up timeout for PWM3.
000 = No startup timeout
001 = 100 ms
010 = 250 ms default
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
Disabling Fan Start-Up Timeout
Although fan start-up times make fan spin-ups much quieter
than fixed-time spin-up times, the option exists to use fixed
spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration
Register 1 (Reg. 0x40) disables the spin-up for two TACH
pulses. Instead, the fan spins up for the fixed time as selected in
Reg. 0x5C to Reg. 0x5E.
PWM LOGIC STATE
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
0 = Logic high for 100% PWM duty cycle
1 = Logic low for 100% PWM duty cycle
PWM2 Configuration (Reg. 0x5D)
<4> INV
0 = Logic high for 100% PWM duty cycle
1 = Logic low for 100% PWM duty cycle
PWM3 Configuration (Reg. 0x5E)
<4> INV
0 = Logic high for 100% PWM duty cycle
1 = Logic low for 100% PWM duty cycle
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Register 0x5F to Register 0x61 configure the PWM frequency
for PWM1 to PWM3, respectively. In high frequency mode,
the PWM drive frequency is always 22.5 kHz and cannot
be changed.
ADT7468
Rev. 3 | Page 34 of 81 | www.onsemi.com
PWM1 Frequency Registers (Reg. 0x5F to Reg. 0x61)
<2:0> frequency
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz default
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
FAN SPEED CONTROL
The ADT7468 controls fan speed using two modes: automatic
and manual.
In automatic fan speed control mode, fan speed automatically
varies with temperature, without CPU intervention, once initial
parameters are set up. The advantage is that, if the CPU hangs,
the user is guaranteed that the system is protected from
overheating. The automatic fan speed control incorporates a
feature called dynamic T
MIN
calibration, which reduces the
design effort required to program the automatic fan speed
control loop. See the Programming the Automatic Fan Speed
Control Loop section.
In manual fan speed control mode, the ADT7468 allows the
duty cycle of any PWM output to be manually adjusted. This
can be useful if the user wants to change fan speed in the
software or adjust PWM duty cycle output for test purposes.
Bits <7:5> of Reg. 0x5C to Reg. 0x5E (PWM Configuration)
control the behavior of each PWM output.
PWM Configuration Register (Reg. 0x5C to Reg. 0x5E)
<7:5> BHVR
111 = manual mode
Once under manual control, each PWM output can be
manually updated by writing to Reg. 0x30 to Reg. 0x32 (PWMx
current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%. The value to be program-
med into the PWM
MIN
register is given by
Value (decimal) = PWM
MIN
/0.39
Example 1: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWM Duty Cycle Registers
Reg. 0x30 PWM1 duty cycle = 0x00 (0% default)
Reg. 0x31 PWM2 duty cycle = 0x00 (0% default)
Reg. 0x32 PWM3 duty cycle = 0x00 (0% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.
ADT7468
Rev. 3 | Page 35 of 81 | www.onsemi.com
MISCELLANEOUS FUNCTIONS
OPERATING FROM 3.3 V STANDBY
The ADT7468 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states. If
using the dynamic T
MIN
mode, lowering the core voltage of the
processor changes the CPU temperature and changes the
dynamics of the system under dynamic T
MIN
control. Likewise,
when monitoring THERM, the THERM timer should be
disabled during these states.
Dynamic T
MIN
Control Register 1 (Reg. 0x36)
<1> VCCPLO = 1
When the power is supplied from 3.3 V STBY and the V
CCP
voltage drops below the V
CCP
low limit, the following occurs:
1. Status Bit 1 (V
CCP
) in Status Register 1 is set.
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
4. Dynamic T
MIN
control is disabled. This prevents T
MIN
from
being adjusted due to an S3 or S5 state.
5. The ADT7468 is prevented from entering the shutdown
state.
Once the core voltage, V
CCP
, goes above the V
CCP
low limit,
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7468 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying a stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
The XNOR tree test is invoked by setting Bit 0 (XEN) of the
XNOR tree test enable register (Reg. 0x6F).
Figure 47 shows the signals that are exercised in the XNOR tree
test mode.
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
VID4
VID3
VID2
VID1
VID0
04499-0-040
Figure 47. XNOR Tree Test
POWER-ON DEFAULT
When the ADT7468 is powered up, it polls the V
CCP
input.
If V
CCP
stays below 0.75 V (the system CPU power rail is not
powered-up), then the ADT7468 assumes the functionality of
the default registers after the ADT7468 is addressed via any
valid SMBus transaction.
If V
CCP
goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7468 is not addressed by any valid SMBus transaction
before the fail-safe timeout (4.6 s) lapses, then the ADT7468
drives the fans to full speed. If the ADT7468 is addressed by a
valid SMBus transaction after this point, the fans stop, and the
ADT7468 assumes its default settings and begins normal
operation.
If V
CCP
goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7468 has been addressed by a valid SMBus transaction
before the fail-safe timeout (4.6 sec) lapsed, then the ADT7468
operates normally, assuming the functionality of all the default
registers. See the flow chart in Figure 48.
ADT7468
Rev. 3 | Page 36 of 81 | www.onsemi.com
ADT7468 IS POWERED UP
HAS THE ADT7468 BEEN
ACCESSED BY A VALID
SMBUS TRANSACTION?
IS V
CCP
ABOVE 0.75V? CHECK V
CCP
START FAIL-SAFE TIMER
HAS THE ADT7468 BEEN
ACCESSED BY A VALID
SMBUS TRANSACTION?
FAIL-SAFE TIMER ELAPSES
AFTER THE FAIL-SAFE TIMEOUT
HAS THE ADT7468 BEEN
ACCESSED BY A VALID
SMBUS TRANSACTION?
START UP THE
ADT7468 NORMALLY
RUN THE FANS TO FULL SPEED
HAS THE ADT7468 BEEN
ACCESSED BY A VALID
SMBUS TRANSACTION?
SWITCH OFF FANS
N
N
N
N
N
Y
Y
Y
Y
Y
04499-0-043
Figure 48. Power-On Flow Chart
ADT7468
Rev. 3 | Page 37 of 81 | www.onsemi.com
AUTOMATIC FAN CONTROL OVERVIEW
The ADT7468 can automatically control the speed of fans based
upon the measured temperature. This is done independently of
CPU intervention once initial parameters are set up.
The ADT7468 has a local temperature sensor and two remote
temperature channels that can be connected to a CPU on-chip
thermal diode (available on Intel Pentium class and other
CPUs). These three temperature channels can be used as the
basis for automatic fan speed control to drive fans using pulse-
width modulation (PWM).
Automatic fan speed control reduces acoustic noise by
optimizing fan speed according to accurately measured
temperature. Reducing fan speed can also decrease system
current consumption. The automatic fan speed control mode is
very flexible, owing to the number of programmable para-
meters, including T
MIN
and T
RANGE
. The T
MIN
and T
RANGE
values
for a temperature channel and, therefore, for a given fan are
critical, because they define the thermal characteristics of the
system. The thermal validation of the system is one of the most
important steps in the design process, so these values should be
selected carefully.
Figure 49 gives a top level overview of the automatic fan control
circuitry on the ADT7468. From a systems-level perspective, up
to three system temperatures can be monitored and used to
control three PWM outputs. The three PWM outputs can be
used to control up to four fans. The ADT7468 allows the speed
of four fans to be monitored. Each temperature channel has a
thermal calibration block, allowing the designer to individually
configure the thermal characteristics of each temperature
channel. For example, one can decide to run the CPU fan when
the CPU temperature increases above 60°C and a chassis fan
when the local temperature increases above 45°C. At this stage,
the designer has not assigned these thermal calibration settings
to a particular fan drive (PWM) channel. The right side of
Figure 49 shows controls that are fan-specific. The designer has
individual control over parameters such as minimum PWM
duty cycle, fan speed failure thresholds, and even ramp control
of the PWM outputs. Automatic fan control, then, ultimately
allows graceful fan speed changes that are less perceptible to the
system user.
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
REMOTE 1
TEMP
LOCAL
TEMP
REMOTE 2
TEMP
04499-0-054
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
PWM1
TACH1
TACH2
TACH3
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
PWM2
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
PWM3
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 49. Automatic Fan Control Block Diagram
ADT7468
Rev. 3 | Page 38 of 81 | www.onsemi.com
DYNAMIC T
MIN
CONTROL MODE
In addition to the automatic fan speed control mode described
in the Automatic Fan Control Overview section, the ADT7468
has a mode that extends the basic automatic fan speed control
loop. Dynamic T
MIN
control allows the ADT7468 to intelligently
adapt the system’s cooling solution for best system performance
or lowest possible system acoustics, depending on user or
design requirements. Use of dynamic T
MIN
control alleviates the
need to design for worst-case conditions and significantly
reduces system design and validation time.
Designing for Worst-Case Conditions
System design must always allow for worst-case conditions. In
PC design, the worst-case conditions include, but are not
limited to the following:
• Worst-Case Altitude
A computer can be operated at different altitudes. The
altitude affects the relative air density, which alters the
effectiveness of the fan cooling solution. For example,
comparing 40°C air temperature at 10,000 ft. to 20°C air
temperature at sea level, relative air density is increased by
40%. This means that the fan can spin 40% slower and
make less noise at sea level than at 10,000 ft., while keeping
the system at the same temperature at both locations.
• Worst-Case Fan
Due to manufacturing tolerances, fan speeds in RPM are
normally quoted with a tolerance of ±20%. The designer
needs to assume that the fan RPM can be 20% below
tolerance. This translates to reduced system airflow and
elevated system temperature. Note that fans 20% out of
tolerance can negatively impact system acoustics, because
they run faster and generate more noise.
• Worst-Case Chassis Airflow
The same motherboard can be used in a number of
different chassis configurations. The design of the chassis
and the physical location of fans and components
determine the system thermal characteristics. Moreover,
for a given chassis, the addition of add-in cards, cables, or
other system configuration options can alter the system
airflow and reduce the effectiveness of the system cooling
solution. The cooling solution can also be inadvertently
altered by the end user. For example, placing a computer
against a wall can block the air ducts and reduce system
airflow.
FAN
I/O CARDS
POOR CPU
AIRFLOW
VENTS POWER
SUPPLY
CPU
DRIVE
BAYS
GOOD VENTING =
GOOD AIR EXCHANGE POOR VENTING =
POOR AIR EXCHANGE
04499-0-072
VENTS
FAN
I/O CARDS
GOOD CPU AIRFLOW
FAN
VENTS
POWER
SUPPLY
CPU
DRIVE
BAYS
Figure 50. Chassis Airflow Issues
• Worst-Case Processor Power Consumption
This data sheet maximum does not necessarily reflect the
true processor power consumption. Designing for worst-
case CPU power consumption can result in a processor
becoming overcooled (generating excess system noise).
• Worst-Case Peripheral Power Consumption
The tendency is to design to data sheet maximums for
peripheral components (again overcooling the system).
• Worst-Case Assembly
Every system manufactured is unique because of
manufacturing variations. Heat sinks may be loose fitting
or slightly misaligned. Too much or too little thermal
grease might be used, or variations in application pressure
for thermal interface material could affect the efficiency of
the thermal solution. Accounting for manufacturing
variations in every system is difficult; therefore, the system
must be designed for the worst case.
SUBSTRATE
HEAT
SINK
THERMAL
INTERFACE
MATERIAL
INTEGRATED
HEAT
SPREADER
EPOXY
THERMAL INTERFACE MATERIAL
PROCESSOR
T
A
T
J
θ
CA
θ
SA
θ
TIMS
θ
CTIM
θ
TIMC
θ
JTIM
θ
CS
T
C
T
TIM
T
S
T
TIM
θ
JA
04499-0-073
Figure 51. Thermal Model
Although a design usually accounts for worst-case conditions in
all these cases, the actual system is almost never operated at
worst-case conditions. The alternative to designing for the worst
case is to use the dynamic T
MIN
control function.
ADT7468
Rev. 3 | Page 39 of 81 | www.onsemi.com
Dynamic T
MIN
Control Overview
Dynamic T
MIN
control mode builds upon the basic automatic
fan control loop by adjusting the T
MIN
value based on system
performance and measured temperature. This is important,
because, instead of designing for the worst case, the system
thermals can be defined as operating zones. ADT7468 can self-
adjust its fan control loop to maintain either an operating zone
temperature or a system target temperature. For example, one
can specify that the ambient temperature in a system should be
maintained at 50°C. If the temperature is below 50°C, the fans
might not need to run or might run very slowly. If the
temperature is higher than 50°C, the fans need to throttle up.
The challenge presented by any thermal design is finding the
right settings to suit the system’s fan control solution. This can
involve designing for the worst case, followed by weeks of
system thermal characterization, and finally fan acoustic
optimization (for psycho-acoustic reasons). Getting the most
benefit from the automatic fan control mode involves character-
izing the system to find the best T
MIN
and T
RANGE
settings for the
control loop, and the best PWM
MIN
value for the quietest fan
speed setting. Using the ADT7468’s dynamic T
MIN
control
mode, however, shortens the characterization time and
alleviates tweaking the control loop settings, because the device
can self-adjust during system operation.
Dynamic T
MIN
control mode is operated by specifying the
operating zone temperatures required for the system.
Associated with this control mode are three operating point
registers, one for each temperature channel. This allows the
system thermal solution to be broken down into distinct
thermal zones. For example, CPU operating temperature is
70°C, VRM operating temperature is 80°C, and ambient
operating temperature is 50°C. The ADT7468 dynamically
alters the control solution to maintain each zone temperature as
closely as possible to its target operating point.
Operating Point Registers
Reg. 0x33, Remote 1 operating point = 0xA4 (100°C default)
Reg. 0x34, local operating point = 0xA4 (100°C default)
Reg. 0x35, Remote 2 operating point = 0xA4 (100°C default)
Figure 52 shows an overview of the parameters that affect the
operation of the dynamic T
MIN
control loop.
PWM DUTY CYCLE
T
LOW
T
MIN
OPERATING
POINT T
HIGH
T
RANGE
TEMPERATURE
04499-0-074
T
THERM
Figure 52. Dynamic T
MIN
Control Loop
Table 14 provides a brief description of each parameter.
Table 14. T
MIN
Control Loop Parameters
Parameter Description
T
LOW
If the temperature drops below the T
LOW
limit, an
error flag is set in a status register and an
SMBALERT interrupt can be generated.
T
HIGH
If the temperature exceeds the T
HIGH
limit, an
error flag is set in a status register and an
SMBALERT interrupt can be generated.
T
MIN
The temperature at which the fan turns on
under automatic fan speed control.
Operating
point
The target temperature for a particular
temperature zone. The ADT7468 attempts to
maintain system temperature at about the
operating point by adjusting the T
MIN
parameter
of the control loop.
T
THERM
If the temperature exceeds this critical limit, the
fans can be run at 100% for maximum cooling.
T
RANGE
Programs the PWM duty cycle vs. temperature
control slope.
Dynamic T
MIN
Control Programming
Because the dynamic T
MIN
control mode is a basic extension of
the automatic fan control mode, program the automatic fan
control mode parameters first, as described in Step 1 to Step 8,
then proceed with dynamic T
MIN
control mode programming.
ADT7468
Rev. 3 | Page 40 of 81 | www.onsemi.com
PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
Note that to more efficiently understand the automatic fan speed
control loop, it is strongly recommended to use the ADT7468
evaluation board and software while reading this section.
This section provides the system designer with an understanding
of the automatic fan control loop, and provides step-by-step
guidance for effectively evaluating and selecting critical system
parameters. To optimize the system characteristics, the designer
needs to give some thought to system configuration, including the
number of fans, where they are located, and what temperatures are
being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at the
beginning of the process.
STEP 1: HARDWARE CONFIGURATION
During system design, the motherboard sensing and control
capabilities should be addressed early in the design stages.
Decisions about how these capabilities are used should involve
the system thermal/mechanical engineer. Ask the following
questions:
1. What ADT7468 functionality will be used?
• PWM2 or SMBALERT?
• TACH4 fan speed measurement or overtemperature
THERM function?
• 5 V voltage monitoring or overtemperature THERM
function?
• 12 V voltage monitoring or VID5 input?
The ADT7468 offers multifunctional pins that can be
reconfigured to suit different system requirements and
physical layouts. These multifunction pins are software
programmable.
2. How many fans will be supported in system, three or four?
This influences the choice of whether to use the TACH4
pin or to reconfigure it for the THERM function.
3. Is the CPU fan to be controlled using the ADT7468 or will
it run at full speed 100% of the time?
If it runs at 100%, this frees up a PWM output, but the
system is louder.
4. Where will the ADT7468 be physically located in the
system?
This influences the assignment of the temperature
measurement channels to particular system thermal zones.
For example, locating the ADT7468 close to the VRM
controller circuitry allows the VRM temperature to be
monitored using the local temperature channel.
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
REMOTE 1 =
AMBIENT TEMP
LOCAL =
VRM TEMP
REMOTE 2 =
CPU TEMP
04499-0-055
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 53. Hardware Configuration Example
ADT7468
Rev. 3 | Page 41 of 81 | www.onsemi.com
Recommended Implementation 1
Configuring the ADT7468 as shown in Figure 54 provides the
system designer with the following features:
1. Six VID inputs (VID0 to VID5) for VRM10 support.
2. Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
3. Three TACH fan speed measurement inputs.
4. V
CC
measured internally through Pin 4.
5. CPU core voltage measurement (V
CORE
).
6. 2.5 V measurement input used to monitor CPU current
(connected to V
COMP
output of ADP316x VRM controller).
This is used to determine CPU power consumption.
7. 5 V measurement input.
8. VRM temperature using local temperature sensor.
9. CPU temperature measured using the Remote 1
temperature channel.
10. Ambient temperature measured through the Remote 2
temperature channel.
11. If not using VID5, this pin can be reconfigured as the 12 V
monitoring input.
12. Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel P4 processor, for
example, or can be used as an overtemperature THERM
output.
13. SMBALERT system interrupt output.
FRONT
CHASSIS
FAN TACH2
ADT7468
PWM3
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
ADP316x
VRM
CONTROLLER
V
COMP
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
GND
PWM1
TACH1
VID[0:4]/VID[0.5]
D2+
D2–
THERM
SMBALERT
SDA
SCL
PROCHOT
5(VRM9)/6(VRM10)
04499-0-056
CPU FAN
CPU
ICH
Figure 54. Recommended Implementation 1
ADT7468
Rev. 3 | Page 42 of 81 | www.onsemi.com
Recommended Implementation 2
Configuring the ADT7468 as in Figure 55 provides the system
designer with the following features:
1. Six VID inputs (VID0 to VID5) for VRM10 support.
2. Three PWM outputs for fan control of up to three fans.
(All three fans can be individually controlled.)
3. Three TACH fan speed measurement inputs.
4. V
CC
measured internally through Pin 4.
5. CPU core voltage measurement (V
CORE
).
6. 2.5 V measurement input used to monitor CPU current
(connected to V
COMP
output of ADP316x VRM controller).
This is used to determine CPU power consumption.
7. 5 V measurement input.
8. VRM temperature using local temperature sensor.
9. CPU temperature measured using the Remote 1
temperature channel.
10. Ambient temperature measured through the Remote 2
temperature channel.
11. If not using VID5, this pin can be reconfigured as the 12 V
monitoring input.
12. Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel P4 processor, for
example, or can be used as an overtemperature THERM
output.
FRONT
CHASSIS
FAN TACH2
ADT7468
PWM3
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
ADP316x
VRM
CONTROLLER
V
COMP
TACH3
D1+
D1–
3.3VSB
5V
12V/VID5
CURRENT
V
CORE
GND
PWM1
TACH1
VID[0:4]/VID[0.5]
D2+
D2–
THERM
SDA
SCL
PROCHOT
5(VRM9)/6(VRM10)
04499-0-057
CPU FAN
CPU
ICH
Figure 55. Recommended Implementation 2
ADT7468
Rev. 3 | Page 43 of 81 | www.onsemi.com
STEP 2: CONFIGURING THE MUX
After the system hardware configuration is determined, the fans
can be assigned to particular temperature channels. Not only
can fans be assigned to individual channels, but the behavior of
the fans is also configurable. For example, fans can run under
automatic fan control, they can run manually (under software
control), or they can run at the fastest speed calculated by
multiple temperature channels. The mux is the bridge between
temperature measurement channels and the three PWM
outputs.
Bits <7:5> (BHVR) of Registers 0x5C, 0x5D, and 0x5E (PWM
configuration registers) control the behavior of the fans
connected to the PWM1, PWM2, and PWM3 outputs. The
values selected for these bits determine how the mux connects a
temperature measurement channel to a PWM output.
Automatic Fan Control MUX Options
<7:5> (BHVR), Registers 0x5C, 0x5D, 0x5E.
000 = Remote 1 temperature controls PWMx
001 = local temperature controls PWMx
010 = Remote 2 temperature controls PWMx
101 = Fastest speed calculated by local and Remote 2
temperature controls PWMx
110 = Fastest speed calculated by all three temperature
channels controls PWMx
The fastest speed calculated options pertain to controlling one
PWM output based on multiple temperature channels. The
thermal characteristics of the three temperature zones can be
set to drive a single fan. An example would be the fan turning
on when Remote 1 temperature exceeds 60°C or if the local
temperature exceeds 45°C.
Other MUX Options
<7:5> (BHVR), Registers 0x5C, 0x5D, 0x5E.
011 = PWMx runs full speed
100 = PWMx disabled (default)
111 = manual mode. PWMx is runner under software
control. In this mode, PWM duty cycle registers
(Registers 0x30 to 0x32) are writable and control the
PWM outputs.
MUX
04499-0-058
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
REMOTE 1 =
AMBIENT TEMP
LOCAL =
VRM TEMP
REMOTE 2 =
CPU TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 56. Assigning Temperature Channels to Fan Channels
ADT7468
Rev. 3 | Page 44 of 81 | www.onsemi.com
Mux Configuration Example
This is an example of how to configure the mux in a system
using the ADT7468 to control three fans. The CPU fan sink is
controlled by PWM1, the front chassis fan is controlled by
PWM2, and the rear chassis fan is controlled by PWM3. The
MUX is configured for the following fan control behavior:
• PWM1 (CPU fan sink) is controlled by the fastest speed
calculated by the local (VRM temperature) and Remote 2
(processor) temperature. In this case, the CPU fan sink is
also being used to cool the VRM.
• PWM2 (front chassis fan) is controlled by the Remote 1
temperature (ambient).
• PWM3 (rear chassis fan) is controlled by the Remote 1
temperature (ambient).
Example Mux Settings
<7:5> (BHVR), PWM1 Configuration Register 0x5C.
101 = Fastest speed calculated by local and Remote 2
temperature controls PWM1
<7:5> (BHVR), PWM2 Configuration Register 0x5D.
000 = Remote 1 temperature controls PWM2
<7:5> (BHVR), PWM3 Configuration Register 0x5E.
000 = Remote 1 temperature controls PWM3
These settings configure the mux, as shown in Figure 57.
04499-0-059
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
MUX
Figure 57. Mux Configuration Example
ADT7468
Rev. 3 | Page 45 of 81 | www.onsemi.com
STEP 3: T
MIN
SETTINGS FOR THERMAL
CALIBRATION CHANNELS
T
MIN
is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at T
MIN
is
programmed later. The T
MIN
values chosen are temperature
channel specific, for example, 25°C for ambient channel, 30°C
for VRM temperature, and 40°C for processor temperature.
T
MIN
is an 8-bit value, either twos complement or Offset 64, that
can be programmed in 1°C increments. There is a T
MIN
register
associated with each temperature measurement channel:
Remote 1 local, and Remote 2 temperature. Once the T
MIN
value
is exceeded, the fan turns on and runs at the minimum PWM
duty cycle. The fan turns off once the temperature has dropped
below T
MIN
– T
HYST
.
To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Start-Up Timeout
section for more details. In some cases, primarily for psycho-
acoustic reasons, it is desirable that the fan never switch off
below T
MIN
. Bits <7:5> of Enhanced Acoustics Register 1
(Reg. 0x62), when set, keep the fans running at the PWM
minimum duty cycle, if the temperature should fall below T
MIN
.
T
MIN
Registers
Reg. 0x67, Remote 1 temperature T
MIN
= 0x9A (90°C)
Reg. 0x68, Local temperature T
MIN
= 0x9A (90°C)
Reg. 0x69, Remote 2 temperature T
MIN
= 0x9A (90°C)
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below T
MIN
– T
HYST
.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below T
MIN
– T
HYST
.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below T
MIN
– T
HYST
.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below T
MIN
– T
HYST
.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below T
MIN
– T
HYST
.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below T
MIN
– T
HYST
.
04499-0-060
0%
100%
PWM DUTYCYCLE
T
MIN
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 58. Understanding the T
MIN
Parameter
ADT7468
Rev. 3 | Page 46 of 81 | www.onsemi.com
STEP 4: PWM
MIN
FOR EACH PWM (FAN) OUTPUT
PWM
MIN
is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above T
MIN
.
For maximum system acoustic benefit, PWM
MIN
should be as
low as possible. Depending on the fan used, the PWM
MIN
setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.
TEMPERATURE
T
MIN
100%
PWM
MIN
0%
PWM DUTY CYCLE
04499-0-061
Figure 59. PWM
MIN
Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, then the fan
characteristics can be set up differently. As a result, Fan 1 driven
by PWM1 can have a different PWM
MIN
value than that of Fan 2
connected to PWM2. Figure 60 illustrates this as PWM1
MIN
(front fan) is turned on at a minimum duty cycle of 20%, while
PWM2
MIN
(rear fan) turns on at a minimum of 40% duty cycle.
Note, however, that both fans turn on at exactly the same
temperature, defined by T
MIN
.
TEMPERATURE
T
MIN
100%
PWM1
MIN
0%
PWM DUTY CYCLE
PWM1
PWM2
PWM2
MIN
04499-0-062
Figure 60. Operating Two Different Fans from a Single Temperature Channel
Programming the PWM
MIN
Registers
The PWM
MIN
registers are 8-bit registers that allow the mini-
mum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWM
MIN
register is given
by
Value (decimal) = PWM
MIN
/0.39
Example 1: For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal)l or 54 (hex)
PWM
MIN
Registers
Reg. 0x64, PWM1 minimum duty cycle = 0x80 (50% default)
Reg. 0x65 PWM2 minimum duty cycle = 0x80 (50% default)
Reg. 0x66, PWM3 minimum duty cycle = 0x80 (50% default)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
10% ×= cycledutyPWMfanspeed
STEP 5: PWM
MAX
FOR PWM (FAN) OUTPUTS
PWM
MAX
is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For
maximum system acoustic benefit, PWM
MAX
should be as low
as possible, but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to 100%
for fail-safe cooling.
There is a PWM
MAX
limit for each fan channel. The default value
of this register is 0xFF and so has no effect unless it is
programmed.
ADT7468
Rev. 3 | Page 47 of 81 | www.onsemi.com
TEMPERATURET
MIN
100%
PWM
MIN
0%
PWM DUTY CYCLE
PWM
MAX
04499-0-063
Figure 61. PWM
MAX
Determines Maximum PWM Duty Cycle Below the
THERM Temperature Limit
Programming the PWM
MAX
Registers
The PWM
MAX
registers are 8-bit registers that allow the
maximum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWM
MAX
register is given
by
Value (decimal) = PWM
MAX
/0.39
Example 1: For a maximum PWM duty cycle of 50%,
Value (decimal) – 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 75%,
Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or C0 (hex)
PWM
MAX
Registers
Reg. 0x38, PWM1 Maximum Duty Cycle = 0xFF (100% default)
Reg. 0x39, PWM2 Maximum Duty Cycle = 0xFF (100% default)
Reg. 0x3A, PWM3 Maximum Duty Cycle = 0xFF
(100% default)
See the Note on Fan Speed and PWM Duty Cycle.
STEP 6: T
RANGE
for Temperature Channels
T
RANGE
is the range of temperature over which automatic fan
control occurs once the programmed T
MIN
temperature has
been exceeded. T
RANGE
is a temperature slope, not an arbitrary
value; that is, a T
RANGE
of 40°C holds true only for PWM
MIN
=
33%. If PWM
MIN
is increased or decreased, the effective T
RANGE
changes.
TEMPERATURE
T
MIN
100%
PWM
MIN
0%
PWM DUTY CYCLE
T
RANGE
04499-0-064
Figure 62. T
RANGE
Parameter Affects Cooling Slope
The T
RANGE
or fan control slope is determined by the following
procedure:
1. Determine the maximum operating temperature for that
channel (for example, 70°C).
2. Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worst-
case operating points. (For example, 70°C is reached when
the fans are running at 50% PWM duty cycle.)
3. Determine the slope of the required control loop to meet
these requirements.
4. Using the ADT7468 evaluation software, you can
graphically program and visualize this functionality. Ask
your local Analog Devices representative for details.
T
MIN
100%
33%
0%
PWM DUTY CYCLE
50%
30°C40°C
04499-0-065
Figure 63. Adjusting PWM
MIN
Affects T
RANGE
T
RANGE
is implemented as a slope, which means that as PWM
MIN
is changed, T
RANGE
changes, but the actual slope remains the
same. The higher the PWM
MIN
value, the smaller the effective
T
RANGE
, that is, the fan reaches full speed (100%) at a lower
temperature.
ADT7468
Rev. 3 | Page 48 of 81 | www.onsemi.com
04499-0-066
T
MIN
100%
33%
0%
PWM DUTY CYCLE
50%
30°C
40°C
25%
10%
45°C
54°C
Figure 64. Increasing PWM
MIN
Changes Effective T
RANGE
For a given T
RANGE
value, the temperature at which the fan runs
at full speed for different PWM
MIN
values can be easily
calculated:
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170
where:
T
MAX
is the temperature at which the fan runs full speed.
T
MIN
is the temperature at which the fan turns on.
Max DC is the maximum duty cycle (100%) = 255 decimal.
Min DC is equal to PWM
MIN
.
T
RANGE
is the duty PWM duty cycle vs. temperature slope.
Example: Calculate T, given that T
MIN
= 30°C, T
RANGE
= 40°C,
and PWM
MIN
= 10% duty cycle = 26 (decimal).
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170
T
MAX
= 30°C + (100% − 10%) × 40°C/170
T
MAX
= 30°C + (255 − 26) × 40°C/170
T
MAX
= 84°C (effective T
RANGE
= 54°C)
Example: Calculate T
MAX
, given that T
MIN
= 30°C, T
RANGE
= 40°C,
and PWM
MIN
= 25% duty cycle = 64 (decimal).
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170
T
MAX
= 30°C + (100% − 25%) × 40°C/170
T
MAX
= 30°C + (255 − 64) × 40°C/170
T
MAX
= 75°C (effective T
RANGE
= 45°C)
Example: Calculate T
MAX
, given that T
MIN
= 30°C, T
RANGE
= 40°C,
and PWM
MIN
= 33% duty cycle = 85 (decimal).
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170
T
MAX
= 30°C + (100% − 33%) × 40°C/170
T
MAX
= 30°C + (255 − 85) × 40°C/170
T
MAX
= 70°C (effective T
RANGE
= 40°C)
Example: Calculate T
MAX
, given that T
MIN
= 30°C, T
RANGE
= 40°C,
and PWM
MIN
= 50% duty cycle = 128 (decimal).
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170
T
MAX
= 30°C + (100% − 50%) × 40°C/170
T
MAX
= 30°C + (255 − 128) × 40°C/170
T
MAX
= 60°C (effective T
RANGE
= 30°C)
Selecting a T
RANGE
Slope
The T
RANGE
value can be selected for each temperature channel:
Remote 1, local, and Remote 2 temperature. Bits <7:4> (T
RANGE
)
of Registers 0x5F to 0x61 define the T
RANGE
value for each
temperature channel.
Table 15. Selecting a T
RANGE
Value
Bits <7:4>
1
T
RANGE
(°C)
0000 2
0001 2.5
0010 3.33
0011 4
0100 5
0101 6.67
0110 8
0111 10
1000 13.33
1001 16
1010 20
1011 26.67
1100 32 (default)
1101 40
1110 53.33
1111 80
1
Register 0x5F configures Remote 1 T
RANGE
. Register 0x60 configures Local
T
RANGE
. Register 0x61 configures Remote 2 T
RANGE
.
Summary of T
RANGE
Function
When using the automatic fan control function, the
temperature at which the fan reaches full speed can be
calculated by
T
MAX
= T
MIN
+ T
RANGE
(1)
Equation 1 holds true only when PWM
MIN
is equal to 33%
PWM duty cycle.
ADT7468
Rev. 3 | Page 49 of 81 | www.onsemi.com
Increasing or decreasing PWM
MIN
changes the effective T
RANGE
,
although the fan control still follows the same PWM duty cycle
to temperature slope. The effective T
RANGE
for different PWM
MIN
values can be calculated using Equation 2:
T
MAX
= T
MIN
+ (Max DC − Min DC) × T
RANGE
/170 (2)
where:
(Max DC − Min DC) × T
RANGE
/170 is the effective T
RANGE
value.
See the Note on Fan Speed and PWM Duty Cycle.
Figure 65 shows PWM duty cycle versus temperature for each
T
RANGE
setting. The lower graph shows how each T
RANGE
setting
affects fan speed versus temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.
TEMPERATURE ABOVE T
MIN
0 20 40 60 80 100 120
0
FAN SPEED (% OF MAX)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
0 20 40 60 80 100 120
0
PWM DUTY CYCLE (%)
10
20
30
40
50
60
70
80
90
100
04499-0-067
2°C
80°C
53.3°C
40°C
32°C
26.6°C
20°C
16°C
13.3°C
10°C
8°C
6.67°C
5°C
4°C
3.33°C
2.5°C
2°C
80°C
53.3°C
40°C
32°C
26.6°C
20°C
16°C
13.3°C
10°C
8°C
6.67°C
5°C
4°C
3.33°C
2.5°C
Figure 65. T
RANGE
vs. Actual Fan Speed Profile
The graphs in Figure 65 assume that the fan starts from 0%
PWM duty cycle. Clearly, the minimum PWM duty cycle,
PWM
MIN
, needs to be factored in to see how the loop actually
performs in the system. Figure 66 shows how T
RANGE
is affected
when the PWM
MIN
value is set to 20%. It can be seen that the
fan actually runs at about 45% fan speed when the temperature
exceeds T
MIN
.
TEMPERATURE ABOVE T
MIN
0 20 40 60 80 100 120
0
PWM DUTY CYCLE (%)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
0 20 40 60 80 100 120
0
FAN SPEED (% OF MAX)
10
20
30
40
50
60
70
80
90
100
04499-0-068
2°C
80°C
53.3°C
40°C
32°C
26.6°C
20°C
16°C
13.3°C
10°C
8°C
6.67°C
5°C
4°C
3.33°C
2.5°C
2°C
80°C
53.3°C
40°C
32°C
26.6°C
20°C
16°C
13.3°C
10°C
8°C
6.67°C
5°C
4°C
3.33°C
2.5°C
Figure 66. T
RANGE
and % Fan Speed Slopes with PWM
MIN
= 20%
Example: Determining T
RANGE
for Each Temperature Channel
The following example shows how the different T
MIN
and T
RANGE
settings can be applied to three different thermal zones. In this
example, the following T
RANGE
values apply:
T
RANGE
= 80°C for ambient temperature
T
RANGE
= 53.3°C for CPU temperature
T
RANGE
= 40°C for VRM temperature
This example uses the MUX configuration described in Step 2,
with the ADT7468 connected as shown in Figure 57. Both CPU
temperature and VRM temperature drive the CPU fan
connected to PWM1. Ambient temperature drives the front
chassis fan and rear chassis fan connected to PWM2 and
PWM3. The front chassis fan is configured to run at PWM
MIN
=
20%. The rear chassis fan is configured to run at PWM
MIN
=
30%. The CPU fan is configured to run at PWM
MIN
= 10%.
ADT7468
Rev. 3 | Page 50 of 81 | www.onsemi.com
Note on 4-Wire Fans
The control range for 4-wire fans is much wider than that of
2-wire or 3-wire fans. In many cases, 4-wire fans can start with
a PWM drive of as little as 20%.
TEMPERATURE ABOVE T
MIN
0 10 20 30 40 10050 60 70 80 90
0
PWM DUTY CYCLE (%)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE T
MIN
0
FAN SPEED (% MAX RPM)
10
20
30
40
50
60
70
80
90
100
0 10 20 30 40 10050 60 70 80 90
04499-0-069
Figure 67. T
RANGE
and % Fan Speed Slopes for VRM, Ambient, and
CPU Temperature Channels
STEP 7: T
THERM
FOR TEMPERATURE CHANNELS
T
THERM
is the absolute maximum temperature allowed on a
temperature channel. Above this temperature, a component
such as the CPU or VRM might be operating beyond its safe
operating limit. When the temperature measured exceeds
T
THERM
, all fans are driven at 100% PWM duty cycle (full speed)
to provide critical system cooling.
The fans remain running at 100% until the temperature drops
below T
THERM
minus hysteresis, where hysteresis is the number
programmed into the hysteresis Registers 0x6D and 0x6E. The
default hysteresis value is 4°C.
The T
THERM
limit should be considered the maximum worst-case
operating temperature of the system. Because exceeding any
T
THERM
limit runs all fans at 100%, it has very negative acoustic
effects. Ultimately, this limit should be set up as a fail-safe, and
one should ensure that it is not exceeded under normal system
operating conditions.
Note that the T
THERM
limits are nonmaskable and affect the fan
speed regardless of how automatic fan control settings are
configured. This allows some flexibility, because a T
RANGE
value
can be selected based on its slope, while a hard limit (such as
70°C), can be programmed as T
MAX
(the temperature at which
the fan reaches full speed) by setting T
THERM
to that limit (for
example, 70°C).
THERM Registers
Reg. 0x6A, Remote 1 THERM limit = 0xA4 (100°C default)
Reg. 0x6B, Local THERM limit = 0xA4 (100°C default)
Reg. 0x6C, Remote 2 THERM limit = 0xA4 (100°C default)
Hysteresis Registers
Reg. 0x6D, Remote 1, local hysteresis register
<7:4>, Remote 1 temperature hysteresis (4°C default)
<3:0>, Local temperature hysteresis (4°C default)
Reg. 0x6E, Remote 2 Temperature Hysteresis Register
<7:4>, Remote 2 temperature hysteresis (4°C default)
Because each hysteresis setting is four bits, hysteresis values are
programmable from 1°C to 15°C. It is recommended that
hysteresis values never be programmed to 0°C, because this
disables hysteresis. In effect, this would cause the fans to cycle
between normal speed and 100% speed, creating unsettling
acoustic noise.
ADT7468
Rev. 3 | Page 51 of 81 | www.onsemi.com
04499-0-070
T
MIN
PWM DUTYCYCLE
0%
100%
T
THERM
T
RANGE
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 68. How T
THERM
Relates to Automatic Fan Control
STEP 8: T
HYST
FOR TEMPERATURE CHANNELS
T
HYST
is the amount of extra cooling a fan provides after the
temperature measured has dropped back below T
MIN
before the
fan turns off. The premise for temperature hysteresis (T
HYST
) is
that, without it, the fan would merely chatter or cycle on and off
regularly whenever temperature is hovering at about the T
MIN
setting.
The T
HYST
value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of T
HYST
prevent the fans from chattering
on and off. The T
HYST
default value is set at 4°C.
The T
HYST
setting applies not only to the temperature hysteresis
for fan on/off, but the same setting is used for the T
THERM
hysteresis value, described in Step 6. Therefore, programming
Registers 0x6D and 0x6E sets the hysteresis for both fan on/off
and the THERM function.
Hysteresis Registers
Reg. 0x6D, Remote 1, local hysteresis register
<7:4>, Remote 1 temperature hysteresis (4°C default).
<3:0>, local temperature hysteresis (4°C default).
Reg. 0x6E, Remote 2 temperature hysteresis register
<7:4>, Remote 2 temperature hysteresis (4°C default).
In some applications, it is required that fans not turn off below
T
MIN
, but remain running at PWM
MIN
. Bits <7:5> of Enhanced
Acoustics Register 1 (Reg. 0x62) allow the fans to be turned off
or to be kept spinning below T
MIN
. If the fans are always on, the
T
HYST
value has no effect on the fan when the temperature drops
below T
MIN
.
ADT7468
Rev. 3 | Page 52 of 81 | www.onsemi.com
04499-0-071
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
T
MIN
PWM DUTYCYCLE
0%
100%
T
RANGE
T
THERM
Figure 69. The T
HYST
Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when the
temperature is below T
MIN
− T
HYST
.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below T
MIN
− T
HYST
.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when the
temperature is below T
MIN
− T
HYST
.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below T
MIN
− T
HYST
.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when the
temperature is below T
MIN
− T
HYST
.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below T
MIN
− T
HYST
.
STEP 9: OPERATING POINTS FOR TEMPERATURE
CHANNELS
The operating point for each temperature channel is the
optimal temperature for that thermal zone. The hotter each
zone is allowed to be, the quieter the system, because the fans
are not required to run as fast. The ADT7468 increases or
decreases fan speeds as necessary to maintain the operating
point temperature, allowing for system-to-system variation and
removing the need for worst-case design. If a sensible operating
point value is chosen, any T
MIN
value can be selected in the
system characterization. If the T
MIN
value is too low, the fans run
sooner than required, and the temperature is below the operat-
ing point. In response, the ADT7468 increases T
MIN
to keep the
fans off longer and to allow the temperature zone to get closer
to the operating point. Likewise, too high a T
MIN
value causes
the operating point to be exceeded, and in turn, the ADT7468
reduces T
MIN
to turn the fans on sooner to cool the system.
Programming Operating Point Registers
There are three operating point registers, one for each
temperature channel. These 8-bit registers allow the operating
point temperatures to be programmed with 1°C resolution.
Operating Point Registers
Reg. 0x33, Remote 1 operating point = 0xA4 (100°C default)
Reg. 0x34, local operating point = 0xA4 (100°C default)
Reg. 0x35, Remote 2 operating point = 0xA4 (100°C default)
ADT7468
Rev. 3 | Page 53 of 81 | www.onsemi.com
04499-0-075
OPERATING
POINT
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 70. Operating Point Value Dynamically Adjusts Automatic Fan Control Settings
STEP 10: HIGH AND LOW LIMITS FOR
TEMPERATURE CHANNELS
The low limit defines the temperature at which the T
MIN
value
starts to be increased, if temperature falls below this value. This
has the net effect of reducing the fan speed, allowing the system
to get hotter. An interrupt can be generated when the tempera-
ture drops below the low limit.
The high limit defines the temperature at which the T
MIN
value
starts to be reduced, if temperature increases above this value.
This has the net effect of increasing fan speed to cool down the
system. An interrupt can be generated when the temperature
rises above the high limit.
Programming High and Low Limits
There are six limit registers; a high limit and low limit are
associated with each temperature channel. These 8-bit registers
allow the high and low limit temperatures to be programmed
with 1°C resolution.
Temperature Limit Registers
Reg. 0x4E, Remote 1 temperature low limit = 0x01
Reg. 0x4F, Remote 1 temperature high limit = 0x7F
Reg. 0x50, Local temperature low limit = 0x01
Reg. 0x51, Local temperature high limit = 0x7F
Reg. 0x52, Remote 2 temperature low limit = 0x01
Reg. 0x53, Remote 2 temperature high limit = 0x7F
How Dynamic T
MIN
Control Works
The basic premise is as follows:
1. Set the target temperature for the temperature zone, which
could be, for example, the Remote 1 thermal diode. This
value is programmed to the Remote 1 operating
temperature register.
2. As the temperature in that zone (Remote 1 temperature)
rises toward and exceeds the operating point temperature,
T
MIN
is reduced and the fan speed increases.
3. As the temperature drops below the operating point
temperature, T
MIN
is increased and the fan speed is
reduced.
However, the loop operation is not as simple as described in
these steps. A number of conditions govern the situations in
which T
MIN
can increase or decrease.
Short Cycle and Long Cycle
The ADT7468 implements two loops: a short cycle and a long
cycle. The short cycle takes place every n monitoring cycles.
The long cycle takes place every 2n monitoring cycles. The
value of n is programmable for each temperature channel. The
bits are located at the following register locations:
Remote 1 = CYR1 = Bits <2:0> of calibration control Register 2
(Address = 0x37).
ADT7468
Rev. 3 | Page 54 of 81 | www.onsemi.com
Local = CYL = Bits <5:3> of Calibration Control Register 2
(Address = 0x37).
Remote 2 = CYR2 = Bits <7:6> of Calibration Control Register 2
and Bit 0 of Calibration Control Register 1 (Address = 0x36).
Table 16. Cycle Bit Assignments
Code Short Cycle
Duration
(sec) Long Cycle
Duration
(sec)
000 8 cycles 1 16 cycles 2
001 16 cycles 2 32 cycles 4
010 32 cycles 4 64 cycles 8
011 64 cycles 8 128 cycles 16
100 128 cycles 16 256 cycles 32
101 256 cycles 32 512 cycles 64
110 512 cycles 64 1024 cycles 128
111 1024 cycles 128 2048 cycles 256
Care should be taken when choosing the cycle time. A long
cycle time means that T
MIN
is updated less often. If your system
has very fast temperature transients, the dynamic T
MIN
control
loop will always be lagging. If you choose a cycle time that is too
fast, the full benefit of changing T
MIN
might not be realized and
would need to change again on the next cycle. In effect, it is
overshooting. It is necessary to carry out some calibration to
identify the most suitable response time.
Figure 71 shows the steps taken during the short cycle.
IS T1(n) – T1(n – 1) = 0.5 – 0.75°C
IS T1(n) – T1(n – 1) = 1.0 – 1.75°C
IS T1(n) – T1(n – 1) > 2.0°C
IS T1(n) >
(OP1 – HYS)
YES
IS T1(n) – T1(n – 1)
≤0.25°C
DO NOTHING
(SYSTEM IS
COOLING OF
FOR CONSTANT)
YES
NO
NO DO NOTHING
WAIT n
MONITORING
CYCLES
PREVIOUS
TEMPERATURE
MEASUREMENT
T1 (n – 1)
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
OPERATING
POINT
TEMPERATURE
OP1
DECREASE T
MIN
BY 1°C
DECREASE T
MIN
BY 2°C
DECREASE T
MIN
BY 4°C
04499-0-077
Figure 71. Short Cycle Steps
Figure 72 shows the steps taken during the long cycle.
The following examples illustrate some of the circumstances
that might cause T
MIN
to increase, decrease, or stay the same.
Normal Operation—No T
MIN
Adjustment
1. If measured temperature never exceeds the programmed
operating point minus the hysteresis temperature, then
T
MIN
is not adjusted, that is, remains at its current setting.
2. If measured temperature never drops below the low
temperature limit, then T
MIN
is not adjusted.
WAIT 2n
MONITORING
CYCLES
IS T1(n) < LOW TEMP LIMIT
AND
T
MIN
< HIGH TEMP LIMIT
AND
T
MIN
< OP1
AND
T1(n) > T
MIN
IS T1(n) > OP1 YES
INCREASE
T
MIN
BY 1°C
YES
NO
NO
DECREASE T
MIN
BY 1°C
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
OPERATING
POINT
TEMPERATURE
OP1
DO NOT
CHANGE
04499-0-078
Figure 72. Long Cycle Steps
T
MIN
THERM LIMIT
OPERATING
POINT
HIGH TEMP
LIMIT
LOW TEMP
LIMIT
ACTUAL
TEMP
HYSTERESIS
04499-0-079
Figure 73. Temperature Between Operating Point and Low Temperature Limit
Because neither the operating point minus the hysteresis
temperature nor the low temperature limit has been exceeded,
the T
MIN
value is not adjusted, and the fan runs at a speed
determined by the fixed T
MIN
and T
RANGE
values defined in the
automatic fan speed control mode.
Operating Point Exceeded—T
MIN
Reduced
When the measured temperature is below the operating point
temperature minus the hysteresis, T
MIN
remains the same.
Once the temperature exceeds the operating temperature minus
the hysteresis (OP − Hyst), T
MIN
starts to decrease. This occurs
during the short cycle (see Figure 71). The rate at which T
MIN
decreases depends on the programmed value of n. It also
depends on how much the temperature has increased between
this monitoring cycle and the last monitoring cycle, that is, if
the temperature has increased by 1°C, then T
MIN
is reduced by
2°C. Decreasing T
MIN
has the effect of increasing the fan speed,
thus providing more cooling to the system.
If the temperature is slowly increasing only in the range
(OP − Hyst), that is, ≤0.25°C per short monitoring cycle, then
T
MIN
does not decrease. This allows small changes in temp-
erature in the desired operating zone without changing T
MIN
.
The long cycle makes no change to T
MIN
in the temperature
range (OP − Hyst), because the temperature has not exceeded
the operating temperature.
ADT7468
Rev. 3 | Page 55 of 81 | www.onsemi.com
Once the temperature exceeds the operating temperature, the
long cycle causes T
MIN
to be reduced by 1°C every long cycle
while the temperature remains above the operating
temperature. This takes place in addition to the decrease in T
MIN
that would occur due to the short cycle. In Figure 74, because
the temperature is increasing at a rate ≤0.25°C per short cycle,
no reduction in T
MIN
takes place during the short cycle.
Once the temperature has fallen below the operating temp-
erature, T
MIN
stays the same. Even when the temperature starts
to increase slowly, T
MIN
stays the same, because the temperature
increases at a rate ≤0.25°C per cycle.
Increasing the T
MIN
Cycle
When the temperature drops below the low temperature limit,
T
MIN
can increase in the long cycle. Increasing T
MIN
has the
effect of running the fan slower and, therefore, quieter. The long
cycle diagram in Figure 74 shows the conditions that need to be
true for T
MIN
to increase. Here is a quick summary of those
conditions and the reasons they need to be true.
T
MIN
can increase if
• The measured temperature has fallen below the low
temperature limit. This means the user must choose the
low limit carefully. It should not be so low that the temp-
erature never falls below it, because T
MIN
would never
increase and the fans would run faster than necessary.
• T
MIN
is below the high temperature limit. T
MIN
is never
allowed to increase above the high temperature limit. As a
result, the high limit should be carefully chosen, because it
determines how high T
MIN
can go.
• T
MIN
is below the operating point temperature. T
MIN
should
never be allowed to increase above the operating point
temperature, because the fans would not switch on until
the temperature rose above the operating point.
• The temperature is above T
MIN
. The dynamic T
MIN
control
is turned off below T
MIN
.
T
MIN
THERM
LIMIT
OPERATING
POINT
HIGH TEMP
LIMIT
LOW TEMP
LIMIT
HYSTERESIS
DECREASE HERE DUE TO
SHORT CYCLE ONLY
T1(n) – T1 (n – 1) = 0.5°C
OR 0.75°C = > T
MIN
DECREASES BY 1°C
EVERY SHORT CYCLE
DECREASE HERE DUE TO
LONG CYCLE ONLY
T1(n) – T1 (n – 1) ≤ 0.25°C
AND T1(n) > OP = > T
MIN
DECREASES BY 1°C
EVERY LONG CYCLE
NO CHANGE IN T
MIN
HERE
DUE TO ANY CYCLE, BECAUSE
T1(n) – T1 (n – 1) ≤ 0.25°C
AND T1(n) < OP = > T
MIN
STAYS THE SAME
04499-0-080
ACTUAL
TEMP
Figure 74. Effect of Exceeding Operating Point Minus Hysteresis Temperature
Figure 75 shows how T
MIN
increases when the current tempera-
ture is above T
MIN
and below the low temperature limit, and
T
MIN
is below the high temperature limit and below the
operating point. Once the temperature rises above the low
temperature limit, T
MIN
stays the same.
T
MIN
THERM
LIMIT
OPERATING
POINT
HIGH TEMP
LIMIT
LOW TEMP
LIMIT
ACTUAL
TEMP
HYSTERESIS
04499-0-081
Figure 75. Increasing T
MIN
for Quieter Operation
ADT7468
Rev. 3 | Page 56 of 81 | www.onsemi.com
Preventing T
MIN
from Reaching Full Scale
Because T
MIN
is dynamically adjusted, it is undesirable for T
MIN
to reach full scale (127°C), because the fan would never switch
on. As a result, T
MIN
is allowed to vary only within a specified
range:
1. The lowest possible value for T
MIN
is –127°C (twos
complement mode) or −64°C (Offset 64 mode).
2. T
MIN
cannot exceed the high temperature limit.
3. If the temperature is below T
MIN
, the fan is switched off or
is running at minimum speed, and dynamic T
MIN
control is
disabled.
T
MIN
PREVENTED
FROM INCREASING
T
MIN
THERM
LIMIT
OPERATING
POINT
HIGH TEMP
LIMIT
LOW TEMP
LIMIT
ACTUAL
TEMP
HYSTERESIS
04499-0-082
Figure 76. T
MIN
Adjustments Limited by the High Temperature Limit
STEP 11: MONITORING THERM
Using the operating point limit ensures that the dynamic T
MIN
control mode is operating in the best possible acoustic position
while ensuring that the temperature never exceeds the
maximum operating temperature. Using the operating point
limit allows T
MIN
to be independent of system level issues
because of its self-corrective nature. In PC design, the
operating point for the chassis is usually the worst-case
internal chassis temperature.
The optimal operating point for the processor is determined by
monitoring the thermal monitor in the Intel Pentium 4 proces-
sor. To do this, the PROCHOT output of the Pentium 4 is
connected to the THERM input of the ADT7468.
The operating point for the processor can be determined by
allowing the current temperature to be copied to the operating
point register when the PROCHOT output pulls the THERM
input low on the ADT7468. This gives the maximum
temperature at which the Pentium 4 can run before clock
modulation occurs.
Enabling the THERM Trip Point as the Operating Point
Bits <4:2> of dynamic T
MIN
control Register 1 (Reg. 0x36)
enable/disable THERM monitoring to program the operating
point.
Dynamic T
MIN
Control Register 1 (0x36)
<2> PHTR2 = 1, copies the Remote 2 current temperature to
the Remote 2 operating point register, if THERM is asserted.
The operating point contains the temperature at which THERM
is asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTR2 = 0, ignores any THERM assertions. The Remote 2
operating point register reflects its programmed value.
<3> PHTL = 1, copies the local current temperature to the local
temperature operating point register, if THERM is asserted. The
operating point contains the temperature at which THERM is
asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTL = 0, ignores any THERM assertions. The local
temperature operating point register reflects its programmed
value.
<4> PHTR1 = 1, copies the Remote 1 current temperature to
the Remote 1 operating point register, if THERM is asserted.
The operating point contains the temperature at which THERM
is asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTR1 = 0, ignores any THERM assertions. The Remote 1
operating point register reflects its programmed value.
Enabling Dynamic T
MIN
Control Mode
Bits <7:5> of dynamic T
MIN
control Register 1 (Reg. 0x36)
enable/disable dynamic T
MIN
control on the temperature
channels.
Dynamic
TMIN
Control Register 1 (0x36)
<5> R2T = 1, enables dynamic T
MIN
control on the Remote 2
temperature channel. The chosen T
MIN
value is dynamically
adjusted based on the current temperature, operating point, and
high and low limits for this zone.
R2T = 0, disables dynamic T
MIN
control. The T
MIN
value chosen
is not adjusted and the channel behaves as described in the
Automatic Fan Control Overview section.
<6> LT = 1, enables dynamic T
MIN
control on the local temp-
erature channel. The chosen T
MIN
value is dynamically adjusted
based on the current temperature, operating point, and high
and low limits for this zone.
LT = 0, disables dynamic T
MIN
control. The T
MIN
value chosen is
not adjusted and the channel behaves as described in the
Automatic Fan Control Overview section.
<7> R1T = 1, enables dynamic T
MIN
control on the Remote 1
temperature channel. The chosen T
MIN
value is dynamically
adjusted based on the current temperature, operating point, and
high and low limits for this zone.
R1T = 0, disables dynamic T
MIN
control. The T
MIN
value chosen
is not adjusted and the channel behaves as described in the
Automatic Fan Control Overview section.
ADT7468
Rev. 3 | Page 57 of 81 | www.onsemi.com
STEP 12: RAMP RATE FOR ACOUSTIC
ENHANCEMENT
The optimal ramp rate for acoustic enhancement can be found
through system characterization after the thermal optimization
has been finished. The effect of each ramp rate should be
logged, if possible, to determine the best setting for a given
solution.
Enhanced Acoustics Register 1 (Reg. 0x62)
<2:0> ACOU, selects the ramp rate for PWM1.
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots =3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
Enhance Acoustics Register 2 (Reg. 0x63)
<2:0> ACOU3, selects the ramp rate for PWM3.
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots = 3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
<6:4> ACOU2, selects the ramp rate for PWM2.
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots = 3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
Another way to view the ramp rates is to measure the time it
takes for the PWM output to ramp up from 0% to 100% duty
cycle for an instantaneous change in temperature. This can be
tested by putting the ADT7468 into manual mode and changing
the PWM output from 0% to 100% PWM duty cycle. The PWM
output takes 35 secs to reach 100%, when a ramp rate of one
time slot is selected.
Figure 77 shows remote temperature plotted against PWM duty
cycle for enhanced acoustics mode. The ramp rate is set to 48,
which corresponds to the fastest ramp rate. Assume that a new
temperature reading is available every 115 ms. With these
settings, it takes approximately 0.76 secs to go from 33% duty
cycle to 100% duty cycle (full speed). Even though the
temperature increases very rapidly, the fan ramps up to full
speed gradually.
TIME (s)
140
0 0.76
120
100
80
60
40
20
0
120
100
80
60
40
20
0
R
TEMP
(°C)
PWM CYCLE (%)
04499-0-086
Figure 77. Enhanced Acoustics Mode with Ramp Rate = 48
Figure 78 shows how changing the ramp rate from 48 to 8
affects the control loop. The overall response of the fan is
slower. Because the ramp rate is reduced, it takes longer for the
fan to achieve full running speed. In this case, it takes
approximately 4.4 sec for the fan to reach full speed.
TIME (s)
120
04.4
140
120
100
80
60
40
0
20
100
80
60
40
20
0
R
TEMP
(°C)
PWM DUTY CYCLE (%)
04499-0-087
Figure 78. Enhanced Acoustics Mode with Ramp Rate = 8
Figure 79 shows the PWM output response for a ramp rate of 2.
In this instance, the fan took about 17.6 sec to reach full
running speed.
TIME (s)
140
017.6
120
100
80
60
40
20
0
120
100
80
60
40
20
0
R
TEMP
(°C)
PWM DUTY CYCLE (%)
04499-0-088
Figure 79. Enhanced Acoustics Mode with Ramp Rate = 2
ADT7468
Rev. 3 | Page 58 of 81 | www.onsemi.com
Figure 80 shows how the control loop reacts to temperature
with the slowest ramp rate. The ramp rate is set to 1, while all
other control parameters remain the same. With the slowest
ramp rate selected, it takes 35 sec for the fan to reach full speed.
TIME (s)
035
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
PWM DUTY CYCLE (%)
R
TEMP
(°C)
04499-0-089
Figure 80. Enhanced Acoustics Mode with Ramp Rate = 1
As Figure 77 to Figure 80 show, the rate at which the fan reacts
to temperature change is dependent on the ramp rate selected in
the enhanced acoustics registers. The higher the ramp rate, the
faster the fan reaches the newly calculated fan speed.
Figure 81 shows the behavior of the PWM output as tempera-
ture varies. As the temperature increases, the fan speed ramps
up. Small drops in temperature do not affect the ramp-up
function, because the newly calculated fan speed is still higher
than the previous PWM value. Enhanced acoustics mode allows
the PWM output to be made less sensitive to temperature
variations. This is dependent on the ramp rate selected and
programmed into the enhanced acoustics registers.
90
80
70
60
50
40
0
30
20
10
PWM DUTY CYCLE (%)
R
TEMP
(°C)
04499-0-090
Figure 81. How Fan Reacts to Temperature Variation
in Enhanced Acoustics Mode
Slower Ramp Rates
The ADT7468 can be programmed for much longer ramp times
by slowing the ramp rates. Each ramp rate can be slowed by a
factor of 4.
PWM1 Configuration Register (Reg. 0x5C)
<3> slow, 1 slows the ramp rate for PWM1 by 4.
PWM2 Configuration Register (Reg. 0x5D)
<3> slow, 1 slows the ramp rate for PWM2 by 4.
PWM3 Configuration Register (Reg. 0x5E)
<3> slow, 1 slows the ramp rate for PWM3 by 4.
The following sections list the ramp-up times when the slow bit
is set for each PWM output.
Enhanced Acoustics Register 1 (Reg. 0x62)
<2:0> ACOU, selects the ramp rate for PWM1.
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
Enhance Acoustics Register 2 (Reg. 0x63)
<2:0> ACOU3, selects the ramp rate for PWM3.
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
<6:4> ACOU2, selects the ramp rate for PWM2.
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
ADT7468
Rev. 3 | Page 59 of 81 | www.onsemi.com
ENHANCING SYSTEM ACOUSTICS
Automatic fan speed control mode reacts instantaneously to
changes in temperature, that is, the PWM duty cycle responds
immediately to temperature change. Any impulses in temp-
erature can cause an impulse in fan noise. For psycho-acoustic
reasons, the ADT7468 can prevent the PWM output from
reacting instantaneously to temperature changes. Enhanced
acoustic mode controls the maximum change in PWM duty
cycle at a given time. The objective is to prevent the fan from
cycling up and down, annoying the user.
ACOUSTIC ENHANCEMENT MODE OVERVIEW
Figure 82 gives a top-level overview of the automatic fan control
circuitry on the ADT7468 and shows where acoustic enhance-
ment fits in. Acoustic enhancement is intended as a postdesign
tweak made by a system or mechanical engineer evaluating best
settings for the system. Having determined the optimal settings
for the thermal solution, the engineer can adjust the system
acoustics. The goal is to implement a system that is acoustically
acceptable without causing user annoyance due to fan cycling. It
is important to realize that although a system might pass an
acoustic noise requirement specification (for example, 36 dB), if
the fan is annoying, it fails the consumer test.
04499-0-083
ACOUSTIC
ENHANCEMENT
REAR CHASSIS
FRONT CHASSIS
CPU FAN SINK
LOCAL =
VRM TEMP
PWM1
PWM2
TACH1
TACH2
TACH3
PWM3
REMOTE 1 =
AMBIENT TEMP
REMOTE 2 =
CPU TEMP
MUX
THERMAL CALIBRATION
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
THERMAL CALIBRATION 100%
0%
T
MIN
T
RANGE
TACHOMETER 1
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM
CONFIG
PWM
MIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
GENERATOR
100%
Figure 82. Acoustic Enhancement Smoothes Fan Speed Variations under Automatic Fan Speed Control
ADT7468
Rev. 3 | Page 60 of 81 | www.onsemi.com
Approaches to System Acoustic Enhancement
There are two different approaches to implementing system
acoustic enhancement: temperature-centric and fan-centric. The
ADT7468 uses the fan-centric approach.
The temperature-centric approach involves smoothing transient
temperatures as they are measured by a temperature source (for
example, Remote 1 temperature). The temperature values used to
calculate the PWM duty cycle values are smoothed, reducing fan
speed variation. However, this approach causes an inherent delay
in updating fan speed and causes the thermal characteristics of
the system to change. It also causes the system fans to stay on
longer than necessary, because the fan’s reaction is merely
delayed. The user has no control over noise from different fans
driven by the same temperature source. Consider, for example, a
system in which control of a CPU cooler fan (on PWM1) and a
chassis fan (on PWM2) use Remote 1 temperature. Because the
Remote 1 temperature is smoothed, both fans are updated at
exactly the same rate. If the chassis fan is much louder than the
CPU fan, there is no way to improve its acoustics without
changing the thermal solution of the CPU cooling fan.
The fan-centric approach to system acoustic enhancement
controls the PWM duty cycle, driving the fan at a fixed rate (for
example, 6%). Each time the PWM duty cycle is updated, it is
incremented by a fixed 6%. As a result, the fan ramps smoothly
to its newly calculated speed. If the temperature starts to drop,
the PWM duty cycle immediately decreases by 6% at every
update. Therefore, the fan ramps smoothly up or down without
inherent system delay. Consider, for example, controlling the
same CPU cooler fan (on PWM1) and chassis fan (on PWM2)
using Remote 1 temperature. The T
MIN
and T
RANGE
settings have
already been defined in automatic fan speed control mode, that
is, thermal characterization of the control loop has been
optimized. Now the chassis fan is noisier than the CPU cooling
fan. Using the fan-centric approach, PWM2 can be placed into
acoustic enhancement mode independently of PWM1. The
acoustics of the chassis fan can, therefore, be adjusted without
affecting the acoustic behavior of the CPU cooling fan,
although both fans are controlled by Remote 1 temperature.
Enabling Acoustic Enhancement for Each PWM Output
Enhance Acoustics Register 1 (Reg. 0x62)
<3> = 1, enables acoustic enhancement on PWM1 output
Enhance Acoustics Register 2 (Reg. 0x63)
<7> = 1, enables acoustic enhancement on PWM2 output
<3> = 1, enables acoustic enhancement on PWM3 output
Effect of Ramp Rate on Enhanced Acoustics Mode
The PWM signal driving the fan has a period, T, given by the
PWM drive frequency, f, because T = 1/f. For a given PWM
period, T, the PWM period is subdivided into 255 equal time
slots. One time slot corresponds to the smallest possible incre-
ment in the PWM duty cycle. A PWM signal of 33% duty cycle
is, therefore, high for 1/3 × 255 time slots and low for 2/3 × 255
time slots. Therefore, a 33% PWM duty cycle corresponds to a
signal that is high for 85 time slots and low for 170 time slots.
170
TIME SLOTS
85
TIME SLOTS
PWM OUTPUT
(ONE PERIOD)
= 255 TIME SLOTS
PWM_OUT
33% DUTY
CYCLE
04499-0-084
Figure 83. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable
from the values 1, 2, 3, 5, 8, 12, 24, and 48. The ramp rates are
discrete time slots. For example, if the ramp rate is 8, then eight
time slots are added to the PWM high duty cycle each time
the PWM duty cycle needs to be increased. If the PWM duty
cycle value needs to be decreased, it is decreased by eight time
slots. Figure 84 shows how the enhanced acoustics mode
algorithm operates.
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
IS NEW PWM
VALUE >
PREVIOUS
VALUE?
INCREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
YES
NO DECREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
04499-0-085
Figure 84. Enhanced Acoustics Algorithm
The enhanced acoustics mode algorithm calculates a new PWM
duty cycle based on the temperature measured. If the new
PWM duty cycle value is greater than the previous PWM value,
then the previous PWM duty cycle value is incremented by
either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the
settings of the enhance acoustics registers. If the new PWM
duty cycle value is less than the previous PWM value, then the
previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24,
or 48 time slots. Each time the PWM duty cycle is incremented
or decremented, its value is stored as the previous PWM duty
cycle for the next comparison.
A ramp rate of 1 corresponds to one time slot, which is 1/255 of
the PWM period. In enhanced acoustics mode, incrementing or
decrementing by 1 changes the PWM output by 1/255 × 100%.
ADT7468
Rev. 3 | Page 61 of 81 | www.onsemi.com
REGISTER TABLES
Table 17. Register Map
Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable
0x20 R 2.5 V measurement 9 8 7 6 5 4 3 2 0x00 No
0x21 R V
CCP
measurement 9 8 7 6 5 4 3 2 0x00 No
0x22 R V
CC
measurement 9 8 7 6 5 4 3 2 0x00 No
0x23 R 5 V measurement 9 8 7 6 5 4 3 2 0x00 No
0x24 R 12 V measurement 9 8 7 6 5 4 3 2 0x00 No
0x25 R Remote 1
Temperature
9 8 7 6 5 4 3 2 0x01 No
0x26 R Local Temperature 9 8 7 6 5 4 3 2 0x01 No
0x27 R Remote 2
Temperature
9 8 7 6 5 4 3 2 0x01 No
0x28 R TACH1 Low Byte 7 6 5 4 3 2 1 0 0x00 No
0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00 No
0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 0x00 No
0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00 No
0x2C R TACH3 Low Byte 7 6 5 4 3 2 1 0 0x00 No
0x2D R TACH3 High Byte 15 14 13 12 11 10 9 8 0x00 No
0x2E R TACH4 Low Byte 7 6 5 4 3 2 1 0 0x00 No
0x2F R TACH4 High Byte 15 14 13 12 11 10 9 8 0x00 No
0x30 R/W PWM1 Current Duty
Cycle
7 6 5 4 3 2 1 0 0x00 No
0x31 R/W PWM2 Current Duty
Cycle
7 6 5 4 3 2 1 0 0x00 No
0x32 R/W PWM3 Current Duty
Cycle
7 6 5 4 3 2 1 0 0x00 No
0x33 R/W Remote 1 Operating
Point
7 6 5 4 3 2 1 0 0xA4 Yes
0x34 R/W Local Temp
Operating Point
7 6 5 4 3 2 1 0 0xA4 Yes
0x35 R/W Remote 2 Operating
Point
7 6 5 4 3 2 1 0 0xA4 Yes
0x36 R/W Dynamic T
MIN
Control
Reg. 1
R2T LT R1T PHTR2 PHTL PHTR1 V
CCP
LO CYR2 0x00 Yes
0x37 R/W Dynamic T
MIN
Control
Reg. 2
CYR2 CYR2 CYL CYL CYL CYR1 CYR1 CYR1 0x00 Yes
0x38 R/W Max PWM 1 Duty
Cycle
7 6 5 4 3 2 1 0 0xFF Yes
0x39 R/W Max PWM 2 Duty
Cycle
7 6 5 4 3 2 1 0 0xFF Yes
0x3A R/W Max PWM 3 Duty
Cycle
7 6 5 4 3 2 1 0 0xFF Yes
0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x68 No
0x3E R Company ID Number 7 6 5 4 3 2 1 0 0x41 No
0x3F R Revision Number VER VER VER VER STP STP STP STP 0x71/0x72 No
0x40 R/W Configuration 1 V
CC
=
5 V
TODIS FSPDIS VxI FSPD RDY LOCK STRT 0x01 Yes
0x41 R Interrupt Status 1 OOL R2T LT R1T 5 V/THERM
Timer
Limit
V
CC
V
CCP
2.5 V 0x00 No
0x42 R Interrupt Status 2 D2
FAULT
D1
FAULT
FAN4/
THERM
FAN3 FAN2 FAN1 THERM
Temp
Limit
12 V/VC 0x00 No
0x43 R/W VID Config VIDSEL THLD VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 0x00 No
0x44 R/W 2.5 V Low Limit 7 6 5 4 3 2 1 0 0x00 No
0x45 R/W 2.5 V High Limit 7 6 5 4 3 2 1 0 0xFF No
0x46 R/W V
CCP
Low Limit 7 6 5 4 3 2 1 0 0x00 No
0x47 R/W V
CCP
High Limit 7 6 5 4 3 2 1 0 0xFF No
ADT7468
Rev. 3 | Page 62 of 81 | www.onsemi.com
Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable
0x48 R/W V
CC
Low Limit 7 6 5 4 3 2 1 0 0x00 No
0x49 R/W V
CC
High Limit 7 6 5 4 3 2 1 0 0xFF No
0x4A R/W 5 V Low Limit 7 6 5 4 3 2 1 0 0x00 No
0x4B R/W 5 V High Limit 7 6 5 4 3 2 1 0 0xFF No
0x4C R/W 12 V Low Limit 7 6 5 4 3 2 1 0 0x00 No
0x4D R/W 12 V High Limit 7 6 5 4 3 2 1 0 0xFF No
0x4E R/W Remote 1 Temp Low
Limit
7 6 5 4 3 2 1 0 0x01 No
0x4F R/W Remote 1 Temp High
Limit
7 6 5 4 3 2 1 0 0x7F No
0x50 R/W Local Temp Low
Limit
7 6 5 4 3 2 1 0 0x01 No
0x51 R/W Local Temp High
Limit
7 6 5 4 3 2 1 0 0x7F No
0x52 R/W Remote 2 Temp Low
Limit
7 6 5 4 3 2 1 0 0x01 No
0x53 R/W Remote 2 Temp High
Limit
7 6 5 4 3 2 1 0 0x7F No
0x54 R/W TACH1 Minimum
Low Byte
7 6 5 4 3 2 1 0 0xFF No
0x55 R/W TACH1 Minimum
High Byte
15 14 13 12 11 10 9 8 0xFF No
0x56 R/W TACH2 Minimum
Low Byte
7 6 5 4 3 2 1 0 0xFF No
0x57 R/W TACH2 Minimum
High Byte
15 14 13 12 11 10 9 8 0xFF No
0x58 R/W TACH3 Minimum
Low Byte
7 6 5 4 3 2 1 0 0xFF No
0x59 R/W TACH3 Minimum
High Byte
15 14 13 12 11 10 9 8 0xFF No
0x5A R/W TACH4 Minimum
Low Byte
7 6 5 4 3 2 1 0 0xFF No
0x5B R/W TACH4 Minimum
High Byte
15 14 13 12 11 10 9 8 0xFF No
0x5C R/W PWM1 Configuration
Register
BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes
0x5D R/W PWM2 Configuration
Register
BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes
0x5E R/W PWM3 Configuration
Register
BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x82 Yes
0x5F R/W Remote 1
T
RANGE
/PWM 1
Frequency
RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes
0x60 R/W Local T
RANGE
/PWM 2
Frequency
RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes
0x61 R/W Remote 2
T
RANGE
/PWM3
Frequency
RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0XC4 Yes
0x62 R/W Enhance Acoustics
Reg. 1
MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0X00 Yes
0x63 R/W Enhance Acoustics
Reg. 2
EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0X00 Yes
0x64 R/W PWM1 Min Duty
Cycle
7 6 5 4 3 2 1 0 0X80 Yes
0x65 R/W PWM2 Min Duty
Cycle
7 6 5 4 3 2 1 0 0X80 Yes
0x66 R/W PWM3 Min Duty
Cycle
7 6 5 4 3 2 1 0 0X80 Yes
0x67 R/W Remote 1 Temp T
MIN
7 6 5 4 3 2 1 0 0X9A Yes
0x68 R/W Local Temp T
MIN
7 6 5 4 3 2 1 0 0X9A Yes
0x69 R/W Remote 2 Temp T
MIN
7 6 5 4 3 2 1 0 0X9A Yes
ADT7468
Rev. 3 | Page 63 of 81 | www.onsemi.com
Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable
0x6A R/W Remote 1 THERM
Temp Limit
7 6 5 4 3 2 1 0 0XA4 Yes
0x6B R/W Local THERM Temp
Limit
7 6 5 4 3 2 1 0 0XA4 Yes
0x6C R/W Remote 2 THERM
Temp Limit
7 6 5 4 3 2 1 0 0XA4 Yes
0x6D R/W Remote 1 and Local
Temp/T
MIN
Hysteresis
HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0X44 Yes
0x6E R/W Remote 2 Temp/T
MIN
Hysteresis
HYSR2 HYSR2 HYSR2 HYRS RES RES RES RES 0X40 Yes
0x6F R/W XNOR Tree Test
Enable
RES RES RES RES RES RES RES XEN 0X00 Yes
0x70 R/W Remote 1
Temperature Offset
7 6 5 4 3 2 1 0 0X00 Yes
0x71 R/W Local Temperature
Offset
7 6 5 4 3 2 1 0 0X00 Yes
0x72 R/W Remote 2
Temperature Offset
7 6 5 4 3 2 1 0 0X00 Yes
0x73 R/W Configuration
Register 2
SHDN CONV ATTN AVG AIN4 AIN3 AIN2 AIN1 0X00 Yes
0x74 R/W Interrupt Mask 1
Register
OOL R2T LT RIT 5 V V
CC
V
CCP
2.5 V 0X00 No
0x75 R/W Interrupt Mask 2
Register
D2 D1 F4P FAN3 FAN2 FAN1 OVT 12 V / VC 0X00 No
0x76 R/W Extended Resolution
1
5 V 5 V V
CC
V
CC
V
CCP
V
CCP
2.5 V 2.5 V 0X00 No
0x77 R/W Extended Resolution
2
TDM2 TDM2 LTMP LTMP TDM1 TDM1 12 V 12 V 0X00 No
0x78 R/W Configuration
Register 3
DC4 DC3 DC2 DC1 FAST BOOST THERM ALERT
Enable
0X00 Yes
0x79 R THERM Timer Status
Register
TMR TMR TMR TMR TMR TMR TMR ASRT/TMRO 0X00 No
0x7A R/W THERM Timer Limit
Register
LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0X00 No
0x7B R/W TACH Pulses per
Revolution
FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0X55 No
0x7C R/W Configuration
Register 5
RES RES RES RES GPIOP GPIOD LF/HF TWOS
COMPL
0X00 Yes
0x7D R/W Configuration
Register 4
BpAtt
12 V
BpAtt
5 V
BpAtt
V
CCP
BpAtt
2.5 V
AINL AINL Pin 14
Func
Pin 14 Func 0X00 Yes
0x7E R Test Register 1 DO NOT WRITE TO THESE REGISTERS 0X00 Yes
0x7F R Test Register 2 DO NOT WRITE TO THESE REGISTERS 0X00 Yes
Table 18. Voltage Reading Registers (Power-On Default = 0x00)
1
Register Address R/W Description
0x20 Read only Reflects the voltage measurement at the 2.5 V input on Pin 22 (8 MSBs of reading).
0x21 Read only Reflects the voltage measurement
2
at the V
CCP
input on Pin 23 (8 MSBs of reading).
0x22 Read only Reflects the voltage measurement
3
at the V
CC
input on Pin 4 (8 MSBs of reading).
0x23 Read only Reflects the voltage measurement at the 5 V input on Pin 20 (8 MSBs of reading.
0x24 Read only Reflects the voltage measurement at the 12 V input on Pin 21 (8 MSBs of reading).
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are
frozen.
2
If V
CCP
Low (Bit 1 of the Dynamic T
MIN
Control Register 1, 0x36) is set, V
CCP
can control the sleep state of the ADT7468.
3
V
CC
(Pin 4) is the supply voltage for the ADT7468.
ADT7468
Rev. 3 | Page 64 of 81 | www.onsemi.com
Table 19. Temperature Reading Registers (Power-On Default = 0x01)
1, 2, 3
Register Address R/W Description
0x25 Read only Remote 1 temperature reading
3, 4
(8 MSBs of reading).
0x26 Read only Local temperature reading (8 MSBs of reading).
0x27 Read only Remote 2 temperature reading
3, 4
(8 MSBs of reading).
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
2
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
3
In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
4
In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)
1
Register Address R/W Description
0x28 Read only TACH1 low byte
0x29 Read only TACH1 high byte
0x2A Read only TACH2 low byte
0x2B Read only TACH2 high byte
0x2C Read only TACH3 low byte
0x2D Read only TACH3 high byte
0x2E Read only TACH4 low byte
0x2F Read only TACH4 high byte
1
These registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately
measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until
read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts
from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following:
• Stalled or blocked (object jamming the fan).
• Failed (internal circuitry destroyed).
• Not populated. (The ADT7468 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.)
• Alternate function, for example, TACH4 reconfigured as THERM pin.
• 2-wire instead of 3-wire fan.
Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0x00)
1
Register Address R/W Description
0x30 Read/write PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x31 Read/write PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x32 Read/write PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7468 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 22. Operating Point Registers (Power-On Default = 0x64)
1, 2, 3
Register Address R/W
3
Description
0x33 Read/write Remote 1 operating point register (default = 100°C).
0x34 Read/write Local temperature operating point register (default = 100°C).
0x35 Read/write Remote 2 operating point register (default = 100°C).
1
These registers set the target operating point for each temperature channel when the dynamic T
MIN
control feature is enabled.
2
The fans being controlled are adjusted to maintain temperature about an operating point.
3
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
ADT7468
Rev. 3 | Page 65 of 81 | www.onsemi.com
Table 23. Register 0x36—Dynamic T
MIN
Control Register 1 (Power-On Default = 0x00)
1
Bit Name
R/W Description
<0>
CYR2 Read/write
MSB of 3-bit remote 2 cycle value. The other two bits of the code reside in Dynamic T
MIN
Control Register 2
(Reg. 0x37). These three bits define the delay time between making subsequent T
MIN
adjustments in the
control loop, in terms of the number of monitoring cycles. The system has associated thermal time constants
that need to be found to optimize the response of fans and the control loop.
<1>
V
CCP
LO
Read/write
V
CCP
LO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (V
CCP
) drops below its V
CCP
low limit value (Reg. 0x46), the following occurs:
• Status Bit 1 in Status Register 1 is set.
• SMBALERT is generated, if enabled.
• PROCHOT monitoring is disabled.
• Dynamic T
MIN
control is disabled.
• The device is prevented from entering shutdown.
• Everything is re-enabled once V
CCP
increases above the V
CCP
low limit.
<2>
PHTR1
Read/write
PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register, if THERM is
asserted. The operating point contains the temperature at which THERM is asserted, which allows the system
to run as quietly as possible without affecting system performance.
PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point register reflects its
programmed value.
<3>
PHTL Read/write
PHTL = 1 copies the local channel’s current temperature to the local operating point register, if THERM is
asserted. The operating point contains the temperature at which THERM is asserted, which allows the system
to run as quietly as possible without affecting system performance.
PHTL = 0 ignores any THERM assertions on the THERM pin. The local operating temperature point register
reflects its programmed value.
<4>
PHTR2
Read/write
PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register, if THERM is
asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to
run as quietly as possible without affecting system performance.
PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point register reflects its
programmed value.
<5>
R1T Read/write
R1T = 1 enables dynamic T
MIN
control on the Remote 1 temperature channel. The chosen T
MIN
value is
dynamically adjusted based on the current temperature, operating point, and high and low limits for this
zone.
R1T = 0 disables dynamic T
MIN
control. The T
MIN
value chosen is not adjusted, and the channel behaves as
described in the Fan Speed Control section.
<6>
LT Read/write
LT=1 enables dynamic T
MIN
control on the local temperature channel. The chosen T
MIN
value is dynamically
adjusted based on the current temperature, operating point, and high and low limits for this zone.
LT = 0 disables dynamic T
MIN
control. The T
MIN
value chosen is not adjusted, and the channel behaves as
described in the Fan Speed Control section.
<7>
R2T Read/write
R2T = 1 enables dynamic T
MIN
control on the Remote 2 temperature channel. The chosen T
MIN
value is
dynamically adjusted based on the current temperature, operating point, and high and low limits for this
zone.
R2T = 0 disables dynamic T
MIN
control. The T
MIN
value chosen is not adjusted, and the channel behaves as
described in the Fan Speed Control section.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
ADT7468
Rev. 3 | Page 66 of 81 | www.onsemi.com
Table 24. Register 0x37—Dynamic T
MIN
Control Register 2 (Power-On Default = 0x00)
1
Bit Name
R/W Description
<2:0>
CYR1 Read/write
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent T
MIN
adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles. The
system has associated thermal time constants that need to be found to optimize the response of fans and
the control loop.
Bits Decrease Cycle Increase Cycle
000 8 cycles (1 sec) 16 cycles (2 sec)
001 16 cycles (2 sec ) 32 cycles (4 sec)
010 32 cycles (4 sec) 64 cycles (8 sec)
011 64 cycles (8 sec) 128 cycles (16 sec)
100 128 cycles (16 sec) 256 cycles (32 sec)
101 256 cycles (32 sec) 512 cycles (64 sec)
110 512 cycles (64 sec) 1024 cycles (128 sec)
111 1024 cycles (128 sec) 2048 cycles (256 sec)
<5:3>
CYL Read/write 3-bit local temperature cycle value. These three bits define the delay time between making subsequent T
MIN
adjustments in the control loop for the local temperature channel, in terms of number of monitoring cycles.
The system has associated thermal time constants that need to be found to optimize the response of fans
and the control loop.
Bits Decrease Cycle Increase Cycle
000 8 cycles (1 sec) 16 cycles (2 sec)
001 16 cycles (2 sec) 32 cycles (4 sec)
010 32 cycles (4 sec) 64 cycles (8 sec)
011 64 cycles (8 sec) 128 cycles (16 sec)
100 128 cycles (16 sec) 256 cycles (32 sec)
101 256 cycles (32 sec) 512 cycles (64 sec)
110 512 cycles (64 sec) 1024 cycles (128 sec)
111 1024 cycles (128 sec) 2048 cycles (256 sec)
<7:6>
CYR2 Read/write
2 LSBs of 3-bit Remote 2 cycle value. The MSB of the 3-bit code resides in Dynamic T
MIN
Control Register 1
(Reg. 0x36). These three bits define the delay time between making subsequent T
MIN
adjustments in the
control loop for the Remote 2 channel, in terms of number of monitoring cycles. The system has associated
thermal time constants that need to be found to optimize the response of fans and the control loop.
Bits Decrease Cycle Increase Cycle
000 8 cycles (1 sec) 16 cycles (2 sec)
001 16 cycles (2 sec) 32 cycles (4 sec)
010 32 cycles (4 sec) 64 cycles (8 sec)
011 64 cycles (8 sec) 128 cycles (16 sec)
100 128 cycles (16 sec) 256 cycles (32 sec)
101 256 cycles (32 sec) 512 cycles (64 sec)
110 512 cycles (64 sec) 1024 cycles (128 sec)
111 1024 cycles (128 sec) 2048 cycles (256 sec)
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 25. Maximim PWM Duty Cycle (Power-On Default = 0xFF)
1, 2
Register Address R/W
2
Description
0x38 Read/write Maximum duty cycle for PWM1 output, default = 100% (0xFF).
0x39 Read/write Maximum duty cycle for PWM2 output, default = 100% (0xFF).
0x3A Read/write Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1
These registers set the maximum PWM duty cycle of the PWM output .
2
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
ADT7468
Rev. 3 | Page 67 of 81 | www.onsemi.com
Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x01)
Bit Name R/W Description
<0> STRT Read/write Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the
default settings are enabled. This bit becomes read-only and cannot be changed once Bit 1 (LOCK bit)
has been written. All limit registers should be programmed by BIOS before setting this bit to 1.
(Lockable.)
<1>
LOCK Write once Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read-only and cannot be modified until the ADT7468 is powered down and powered up again. This
prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.)
<2> RDY Read-only This bit is set to 1 by the ADT7468 to indicate only that the device is fully powered-up and ready to
begin system monitoring.
<3> FSPD Read/write When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit never gets locked.
<4>
VxI Read/write BIOS should set this bit to a 1 when the ADT7468 is configured to measure current from an ADI ADOPT™
VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display
CPU watts usage. (lockable.)
<5> FSPDIS Read/write Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan
spin-up timeout selected.
<6> TODIS Read/write When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7468 to be used with
SMBus controllers that cannot handle SMBus timeouts. (lockable.)
<7> V
CC
Read/write When this bit is set to 1, the ADT7468 rescales its V
CC
pin to measure 5 V supply. If this bit is 0, the
ADT7468 measures V
CC
as a 3.3 V supply. (lockable.)
Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit Name R/W Description
<0> 2.5 V Read only 2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<1> V
CCP
Read only V
CCP
= 1 indicates that the V
CCP
high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<2>
V
CC
Read only V
CC
= 1 indicates that the V
CC
high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<3> 5 V/
THERM
timer
Read only A one indicates the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided. If Pin 20 is configured as THERM, this bit is asserted when
the timer limit has been exceeded.
<4> R1T Read only R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
<5> LT Read only LT =1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<6>
R2T Read only R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
<7> OOL Read only OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR
of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of
the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which
saves the need to read Status Register 2 during every interrupt or polling cycle.
ADT7468
Rev. 3 | Page 68 of 81 | www.onsemi.com
Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)
Bit Name R/W Description
<0> 12V/VC Read only A one indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided. If Pin 21 is configured as VID5, this bit is the VID change
bit. This bit is set when the levels on VID0 to VID5 are different than they were 11 µs previously. This pin
can be used to generate an SMBALERT whenever the VID code changes.
<1>
OVT Read only OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a
read of the status register when the temperature drops below THERM − T
HYST
.
<2>
FAN1 Read only FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when
the PWM 1 output is off.
<3>
FAN2 Read only FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when
the PWM 2 output is off.
<4>
FAN3 Read only FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when
the PWM 3 output is off.
<5>
F4P Read only When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped below minimum
speed or has stalled. This bit is not set when the PWM3 output is off.
Read/write When Pin 14 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO.
Read only If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A).
<6> D1 Read only D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7>
D2 Read only D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 29. Register 0x43-VID Register (Power-On Default = 0x00)
Bit Name R/W Description
<4:0> VID[4:0] Read-only The VID[4:0] inputs from the CPU indicate the expected processor core voltage. On power-up, these bits
reflect the state of the VID pins, even if monitoring is not enabled.
<5> VID5 Read-only Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always reads back 0 (power-on
default).
<6> THLD Read/write
Selects the input switching threshold for the VID inputs.
THLD = 0 selects a threshold of 1 V (V
OL
< 0.8 V, V
IH
> 1.7 V).
THLD = 1 lowers the switching threshold to 0.6 V (V
OL
< 0.4 V, V
IH
> 0.8 V).
<7> VIDSEL Read/write
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
Table 30. Voltage Limit Registers
1
Register Address R/W Description
2
Power-On Default
0x44 Read/write 2.5 V 0x00
0x45 Read/write 2.5 V 0xFF
0x46 Read/write V
CCP
low limit 0x00
0x47 Read/write V
CCP
high limit 0xFF
0x48 Read/write V
CC
low limit 0x00
0x49 Read/write V
CC
high limit 0xFF
0x4A Read/write 5 V low limit 0x00
0x4B Read/write 5 V high limit 0xFF
0x4C Read/write 12 V low limit 0x00
0x4D Read/write 12 V high limit 0xFF
1
Setting the Configuration Register 1 lock bit has no effect on these registers.
2
High Limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low
limit (≤comparison).
ADT7468
Rev. 3 | Page 69 of 81 | www.onsemi.com
Table 31. Temperature Limit Registers
1
Register Address R/W Description
2
Power-On Default
0x4E Read/write Remote 1 temperature low limit 0x81
0x4F Read/write Remote 1 temperature high limit 0x7F
0x50 Read/write Local temperature low limit 0x81
0x51 Read/write Local temperature high limit 0x7F
0x52 Read/write Remote 2 temperature low limit 0x81
0x53 Read/write Remote 2 temperature high limit 0x7F
1
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
2
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤comparison).
Table 32. Fan Tachometer Limit Registers
1
Register Address R/W Description Power-On Default
0x54 Read/write TACH1 minimum low byte 0xFF
0x55 Read/write TACH1 minimum high byte/Single channel ADC
channel select 0xFF
0x56 Read/write TACH2 minimum low byte 0xFF
0x57 Read/write TACH2 minimum high byte 0xFF
0x58 Read/write TACH3 minimum low byte 0xFF
0x59 Read/write TACH3 minimum high byte 0xFF
0x5A Read/write TACH4 minimum low byte 0xFF
0x5B Read/write TACH4 minimum high byte 0xFF
1
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2
to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 33. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF)
Bits Name R/W Description
<4:0>
Reserved
Read only These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode).
Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
<7:5>
SCADC Read/write When Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode), these bits are used to select the
only channel from which the ADC makes measurements. Otherwise, these bits represent Bits <7:5> of
the TACH1 minimum high byte.
ADT7468
Rev. 3 | Page 70 of 81 | www.onsemi.com
Table 34. PWM Configuration Registers
Register Address R/W
1
Description Power-On Default
0x5C Read/write PWM1 configuration. 0x82
0x5D Read/write PWM2 configuration. 0x82
0x5E Read/write PWM3 configuration. 0x82
Bit Name R/W Description
<2:0> SPIN Read/write These bits control the startup timeout for PWMx. The PWM output stays high until
two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal
during the fan TACH measurement directly after the fan startup timeout period, then
the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If
the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Status
Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 secs
111 = 4 secs
<3> SLOW Read/write SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
<4> INV Read/write This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100%
duty cycle corresponds to a logic low output.
<7:5> BHVR Read/write These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = fastest speed calculated by all three temperature channel controls PWMx.
111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become
writable.
1
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
ADT7468
Rev. 3 | Page 71 of 81 | www.onsemi.com
Table 35. TEMP T
RANGE
/PWM Frequency Registers
Register Address R/W
1
Description Power-On Default
0x5F Read/write Remote 1 T
RANGE
/PWM1 frequency. 0xC4
0x60 Read/write Local temperature T
RANGE
/PWM2 frequency. 0xC4
0x61 Read/write Remote 2 T
RANGE
/PWM3 frequency. 0xC4
Bit Name R/W Description
<2:0> FREQ Read/write These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
<3> THRM Read/write THRM = 1 causes the THERM pin (Pin 14/20) to assert low as an output when this
temperature channel’s THERM limit has been exceeded by 0.25°C. The THERM pin
remains asserted until the temperature is equal to or below the THERM limit. The
minimum time that THERM asserts is one monitoring cycle. This allows clock
modulation of devices that incorporate this feature.
THRM = 0 makes the THERM pin act as an input only, for example, for Pentium 4
PROCHOT monitoring, when Pin 14/20 is configured as THERM.
<7:4> RANGE Read/write These bits determine the PWM duty cycle vs. the temperature slope for automatic fan
control.
0000 = 2°C
0001 = 2.5°C
0010 = 3.33°C
0011 = 4°C
0100 = 5°C
0101 = 6.67°C
0110 = 8°C
0111 = 10°C
1000 = 13.33°C
1001 = 16°C
1010 = 20°C
1011 = 26.67°C
1100 = 32°C (Default)
1101 = 40°C
1110 = 53.33°C
1111 = 80°C
1
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
ADT7468
Rev. 3 | Page 72 of 81 | www.onsemi.com
Table 36. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00)
Bit Name
R/W
1
Description
<2:0>
ACOU
Read/write
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to
its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature
enhances the acoustics of the fan being driven by the PWM1 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 sec
001 = 2 17.6 sec
010 = 3 11.8 sec
011 = 4 7 sec
100 = 8 4.4 sec
101 = 12 3 sec
110 = 24 1.6 sec
111 = 48 0.8 sec
<3> EN1 Read/write
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
<4> SYNC Read/write
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to
three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.
<5> MIN1 Read/write
When the ADT7468 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or
at PWM1 minimum duty cycle when the controlling temperature is below its T
MIN
– hysteresis value.
0 = 0% duty cycle below T
MIN
– hysteresis.
1 = PWM1 minimum duty cycle below T
MIN
– hysteresis.
<6> MIN2 Read/write
When the ADT7468 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty
cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its T
MIN
– hysteresis
value.
0 = 0% duty cycle below T
MIN
– hysteresis.
1 = PWM 2 minimum duty cycle below T
MIN
– hysteresis.
<7> MIN3 Read/write
When the ADT7468 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty
cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its T
MIN
– hysteresis
value.
0 = 0% duty cycle below T
MIN
– hysteresis.
1 = PWM3 minimum duty cycle below T
MIN
– hysteresis.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7468
Rev. 3 | Page 73 of 81 | www.onsemi.com
Table 37. Register 0x63 – Enhanced Acoustics Register 2 (Power-On Default = 0x00)
Bit Name R/W
1
Description
<2:0>
ACOU3
Read/write
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to
its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect
enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 sec
001 = 2 17.6 sec
010 = 3 11.8 sec
011 = 5 7 sec
100 = 8 4.4 sec
101 = 12 3 sec
110 = 24 1.6 sec
111 = 48 0.8 sec
< 3 > EN3 Read/write
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
<6:4>
ACOU2
Read/write
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to
its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect
enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 sec
001 = 2 17.6 sec
010 = 3 11.8 sec
011 = 5 7 sec
100 = 8 4.4 sec
101 = 12 3 sec
110 = 24 1.6 sec
<7> EN2 Read/write
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 38. PWM Minimum Duty Cycle Registers
Register Address R/W
1
Description Power-On Default
0x64 Read/write PWM1 minimum duty cycle. 0x80 (50% duty cycle)
0x65 Read/write PWM2 minimum duty cycle. 0x80 (50% duty cycle)
0x66 Read/write PWM3 minimum duty cycle. 0x80 (50% duty cycle)
Bit Name R/W
1
Description
<7:0> PWM duty cycle Read/write These bits define the PWM
MIN
duty cycle for PWMx.
0x00 = 0% duty cycle (fan off).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
1
These registers become read-only when the ADT7468 is in automatic fan control mode.
Table 39. T
MIN
Registers
1
Register Address R/W
2
Description Power-On Default
0x67 Read/write Remote 1 temperature T
MIN
.
0x5A (90°C)
0x68 Read/write Local temperatue T
MIN
.
0x5A (90°C)
0x69 Read/write Remote 2 temperature T
MIN
.
0x5A (90°C)
1
These are the T
MIN
registers for each temperature channel. When the temperature measured exceeds T
MIN
, the appropriate fan runs at minimum speed and increases
with temperature according to T
RANGE
.
2
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
ADT7468
Rev. 3 | Page 74 of 81 | www.onsemi.com
Table 40. THERM Limit Registers
1
Register Address R/W
2
Description Power-On Default
0x6A Read/write Remote 1 THERM limit. 0x64 (100°C)
0x6B Read/write Local THERM limit. 0x64 (100°C)
0x6C Read/write Remote 2 THERM limit. 0x64 (100°C)
1
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below THERM limit – hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 41. Temperature/T
MIN
Hysteresis Registers
1
Register Address R/W
2
Description Power-On Default
0x6D Read/write Remote 1 and local temperature hysteresis. 0x44
<3:0> HYSL Local temperature hyseresis. 0°C to 15°C of
hysteresis can be applied to the local temperature
AFC and dynamic T
MIN
control loops.
<7:4> HYSR1 Remote 1 temperature hyseresis. 0°C to 15°C of
hysteresis can be applied to the Remote 1
temperature AFC and dynamic T
MIN
control loops.
0x6E Read/write Remote 2 temperature hysteresis. 0x40
<7:4> HYSR2 Local temperature hyseresis. 0°C to 15°C of
hysteresis can be applied to the local temperature
AFC and dynamic T
MIN
control loops.
1
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its T
MIN
value, the fan remains running at PWM
MIN
duty cycle until the temperature = T
MIN
– hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel.
The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM
limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be
programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to T
MIN
.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 42. XNOR Tree Test Enable
Register Address R/W
1
Description Power-On Default
0x6F Read/write XNOR tree test enable register. 0x00
<0> XEN If the XEN bit is set to 1, the device enters the XNOR
tree test mode. Clearing the bit removes the device
from the XNOR tree test mode.
<7:1> Reserved Unused. Do not write to these bits.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 43. Remote 1 Temperature Offset
Register Address R/W
1
Description Power-On Default
0x70 Read/write Remote 1 temperature offset. 0x00
<7:0> Read/write Allows a twos complement offset value to be
automatically added to or subtracted from the
Remote 1 temperature reading. This is to
compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.5°C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7468
Rev. 3 | Page 75 of 81 | www.onsemi.com
Table 44. Local Temperature Offset
Register Address R/W
1
Description Power-On Default
0x71 Read/write Local temperature offset. 0x00
<7:0> Read/write Allows a twos complement offset value to be
automatically added to or subtracted from the local
temperature reading. LSB value = 0.5°C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 45. Remote 2 Temperature Offset
Register Address R/W
1
Description Power-On Default
0x72 Read/write Remote 2 temperature offset. 0x00
<7:0> Read/write Allows a twos complement offset value to be
automatically added to or subtracted from the
Remote 2 temperature reading. This is to
compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.5°C.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 46. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)
Bit Name R/W
1
Description
0 AIN1 Read/write AIN1 = 0, speed of 3-wire fans measured using the TACH output from the fan.
AIN1 = 1, Pin 6 is reconfigured to measure the speed of 2-wire fans using an external sensing
resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg.
0x7D). Only relevant in low frequency mode.
1 AIN2 Read/write AIN2 = 0, speed of 3-wire fans measured using the TACH output from the fan.
AIN2 = 1, Pin 7 is reconfigured to measure the speed of 2-wire fans using an external sensing
resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg.
0x7D). Only relevant in low frequency mode.
2 AIN3 Read/write AIN3 = 0, speed of 3-wire fans measured using the TACH output from the fan.
AIN3 = 1, Pin 4 is reconfigured to measure the speed of 2-wire fans using an external sensing
resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg.
0x7D). Only relevant in low frequency mode.
3 AIN4 Read/write AIN4 = 0, speed of 3-wire fans measured using the TACH output from the fan.
AIN4 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external sensing
resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg.
0x7D). Only relevant in low frequency mode.
4 AVG Read/write AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows
measurements on each channel to be made much faster.
5 ATTN Read/write ATTN = 1, the ADT7468 removes the attenuators from the 2.5 V, V
CCP
, 5 V, and 12 V inputs.
These inputs can be used for other functions such as connecting up external sensors. It is
possible to remove attenuators from individual channels using Bits <7:4> of Configuration
Register 4 (0x7D).
6 CONV Read/write CONV = 1, the ADT7468 is put into a single-channel ADC conversion mode. In this mode, the
ADT7468 can be made to read continuously from one input only, for example, Remote 1
temperature. The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1
minimum high byte register (0x55).
Bits <7:5> Reg. 0x55
000 2.5 V
001 V
CCP
010 V
CC
(3.3 V)
011 5 V
100 12 V
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
7 SHDN Read/write SHDN = 1, ADT7468 goes into shutdown mode. All PWM outputs assert low (or high
depending on state of INV bit) to switch off all fans. The PWM current duty cycle registers
read 0x00 to indicate that the fans are not being driven.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7468
Rev. 3 | Page 76 of 81 | www.onsemi.com
Table 47. Register 0x74—Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit Name R/W Description
0 2.5V Read/write 2.5 V = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V channel.
1 V
CCP
Read/write V
CCP
= 1, masks SMBALERT for out-of-limit conditions on the V
CCP
channel.
2 V
CC
Read/write V
CC
= 1, masks SMBALERT for out-of-limit conditions on the V
CC
channel.
3 5V Read/write 5 V = 1, masks SMBALERT for out-of-limit conditions on the 5 V channel.
4 RIT Read/write RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
5 LT Read/write LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
6 R2T Read/write R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
7 OOL Read/write OOL = 1, masks SMBALERT for any out-of-limit condition in Status Register 2.
Table 48. Register 0x75—Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit Name R/W Description
0 12V/VC Read/write
When Pin 21 is configured as a 12 V input, 12V/VC = 1 masks SMBALERT for out-of-limit conditions
on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT, if the VID5
VID code bit changes.
1 OVT Read only OVT = 1, masks SMBALERT for overtemperature THERM conditions.
2 FAN1 Read/write FAN1 = 1, masks SMBALERT for a Fan 1 fault.
3 FAN2 Read/write FAN2 = 1, masks SMBALERT for a Fan 2 fault.
4 FAN3 Read/write FAN3 = 1, masks SMBALERT for a Fan 3 fault.
5 F4P Read/write If Pin 14 is configured as TACH 4, F4P = 1 masks SMBALERT for a Fan 4 fault.
If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit.
If Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is
asserted.
6 D1 Read/write D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.
7 D2 Read/write D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 49. Register 0x76—Extended Resolution Register 1
1
Bit Name R/W Description
<1:0> 2.5V Read only 2.5 V
LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.
<3:2>
V
CCP
Read only V
CCP
LSBs. Holds the 2 LSBs of the 10-bit V
CCP
measurement.
<5:4>
V
CC
Read only V
CC
LSBs. Holds the 2 LSBs of the 10-bit V
CC
measurement.
<7:6> 5 V Read only 5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 50. Register 0x77—Extended Resolution Register 2
1
Bit Name R/W Description
<1:0> 12V Read only 12 V
LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.
<3:2> TDM1 Read only Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
<5:4> LTMP Read only Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
<7:6> TDM2 Read only Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
ADT7468
Rev. 3 | Page 77 of 81 | www.onsemi.com
Table 51. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit Name R/W
1
Description
<0> ALERT Read/write ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate
out-of-limit error conditions.
ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output.
<1> THERM Read/write THERM Enable = 1 enables THERM functionality on Pin 20 and Pin 14, if Pin 14 is configured as
THERM, determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is
asserted, if the fans are running and the boost bit is set, the fans run at full speed. Alternatively,
THERM can be programmed so that a timer is triggered to time how long THERM has been asserted.
<2> BOOST Read/write When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
<3> FAST Read/write FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement
rate from once per second to once every 250 ms (4 ×).
<4> DC1 Read/write DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by
dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<5> DC2 Read/write DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by
dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<6> DC3 Read/write DC3 = 1, enables TACH measurements to be continuously made on TACH3. Setting this bit prevents
pulse stretching, because it is not required for dc-driven motors.
<7> DC4 Read/write DC4 = 1, enables TACH measurements to be continuously made on TACH4. Setting this bit prevents
pulse stretching, because it is not required for dc-driven motors.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 52. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit Name R/W Description
<7:1>
TMR Read only Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time
exceeds 45.52 ms.
<0> ASRT/
TMR0
Read only This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This
allows THERM assertion times from 45.52 ms to 5.82 secs to be reported back with a resolution of
22.76 ms.
Table 53. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit Name R/W Description
<7:0>
LIMT Read/write Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 secs to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register
2 (Reg. 0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately on the
assertion of the THERM input.
ADT7468
Rev. 3 | Page 78 of 81 | www.onsemi.com
Table 54. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit Name R/W Description
<1:0>
FAN1 Read/write Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<3:2>
FAN2 Read/write Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<5:4>
FAN3 Read/write Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
<7:6>
FAN4 Read/write Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Table 55. Register 0x7C—Configuration Register 5 (Power-On Default = 0x00)
Bit Name R/W
1
Description
<0> 2sC Read/write 2sC = 1, sets the temperature range to twos complement temperature range.
2sC = 0, changes the temperature range to Offset 64. When this bit is changed, the ADT7468
interprets all relevant temperature register values as defined by this bit.
<1> HF/LF Sets the PWM drive frequency to high frequency mode (0) or low frequency mode (1).
<2> GPIOD GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an
output (1).
<3> GPIOP GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit
determines whether the GPIO is active low (0) or high (1).
<4:7>
RES Unused.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
ADT7468
Rev. 3 | Page 79 of 81 | www.onsemi.com
Table 56. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)
Bit Name R/W
1
Description
<1:0>
PIN14FUNC
Read/write These bits set the functionality of Pin 14:
00 = TACH4 (default)
01 = Bidirectional THERM
10 = SMBALERT
11 = GPIO
<3:2>
AINL Read/write These two bits define the input threshold for 2-wire fan speed measurements (low frequency mode
only):
00 = ±20 mV
01 = ±40 mV
10 = ±80 mV
11 = ±130 mV
<4> BpAtt2.5V Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF).
<5> BpAttV
CCP
Bypass V
CCP
attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF).
<6> BpAtt5V Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF).
<7> BpAtt12V Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF).
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 57. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit Name R/W Description
<7:0>
Reserved Read only Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Table 58. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit Name R/W Description
<7:0>
Reserved Read only Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
ADT7468
Rev. 3 | Page 80 of 81 | www.onsemi.com
PROGRAMMING BLOCK DIAGRAM
TEMPERATURE
MEASURED IS
OUT OF LIMITS
DIODE FAULT.
FOR REMOTE
CHANNELS ONLY
FAN FAULT
CONFIGURATION 2
(0X73)
DRIVE PWM
OUTPUTS
HIGH/LOW
V
CC
LOW LIMIT
(0x48)
V
CC
HIGH LIMIT
(0x49)
T
HYST
T
HYST
MIN PWM
0% DUTY CYCLE T
MIN
T
THERM
PWM DUTY CYCLE/RELATIVE FAN SPEED
T
RANGE
= SLOPE HEATINGCOOLING
AUTOMATIC FAN CONTROL
TEMPERATURE
100% DUTY CYCLE
MAX PWM
AUTOMATIC FAN
CONTROL
THERM IS
INPUT/OUTPUT
PWM 2
SMBALERT
V
CCP
MEASUREMENT
(0x47)
8 CYCLES (1s)
16 CYCLES (2s)
32 CYCLES (4s)
64 CYCLES (8s)
128 CYCLES (16s)
256 CYCLES (32s)
512 CYCLES (64s)
1024 CYCLES (128s)
TEMP T
RANGE
,PWM
FREQ,THERM
ENABLE
(0x5F, 0x60, 0x61)
INTERRUPTS
ON STATUS
REGISTER 2
THERM TIMER
LIMIT HAS BEEN
EXCEEDED
SOFTWARE INTERRUPTS
HARDWARE INTERRUPTS
RESCALE V
CC
(5V/3.3V)
START
MONITORING
LOCK
SETTINGS
RUN FANS AT
FULLSPEED
READY
CONFIGURATION 1
(0X40)
AVERAGE TEMP
AND VOLTAGE
MEASUREMENTS
MEASURE
FROM 2- OR 3-
WIRE FANS
SINGLE CHANNEL
ADC MODE
RESCALE V
CCP
INPUT (5V/3.3V)
V
CC
REMOTE TEMP1
REMOTE TEMP2
LOCAL TEMP MEASUREMENT MSBs
(0x25-0x27)
MEASUREMENT LSBs
(0X77)
IF THESE REGISTERS ARE USED,
ALL TEMPERATURE MEASUREMENT
MSB REGISTERS ARE FROZEN
UNTIL ALL TEMPERATURE
MEASUREMENT MSB REGISTERS
ARE READ.
TEMPERATURE
MEASUREMENT
HIGH LIMIT
LOW LIMIT
(0X4E-0X53)
TEMPERATURE
MEASUREMENT
(0X25, 0X26,0X27)
TEMPERATURE
OFFSET
(0x70-0x72)
GPIO POLARITY
TEMPERATURE
RANGE
GPIO DIRECTION
FAN DRIVE
HIGH/LOW
FREQUENCY
MODE
CONFIGURATION 5
(0X7C)
TWOS COMPLEMENT
OFFSET 64
INCREASE
CYCLE TIME
CHANGE
CYCLE TIME
DECREASE
CYCLE TIME
16 CYCLES (2s)
32 CYCLES (4s)
64 CYCLES (8s)
128 CYCLES (16s)
256 CYCLES (32s)
512 CYCLES (64s)
1024 CYCLES (128s)
2048 CYCLES (256s)
THERM AS
(TIMER) INPUT
THERM TIMER
LIMIT (0x7A)
THERM TEMP
LIMITS
(0x6A, 0x6B, 0x6C)
THERM TIMER
STATUS (0x79)
V
CCP
LOW LIMIT
(0x46)
V
CCP
HIGH LIMIT
(0x47)
DYNAMIC T
MIN
CONTROL
(0x36, 0x37)
V
CCP
LOW
(SLEEP)
PHTXX
CURRENT TEMPERATURE OF SELECTED
CHANNEL IS COPIED TO RELEVANT OPERATING
POINT REGISTER ON ASSERTION OF THERM
ENABLE DYNAMIC T
MIN
CONTROL ON INDIVIDUAL
CHANNEL
CYXX
T
MIN
ADJUSTMENT
CYCLE TIME
SELECTED PWM
RAMP-UP SPEED 35s (33%-100%)
17.6s (33%-100%)
18s (33%-100%)
7s (33%-100%)
4.4s (33%-100%)
3s (33%-100%)
1.6s (33%-100%)
0.8s (33%-100%)
ENHANCE
ACOUSTICS
(0x62,0x63)
ALLOW SELECTED
PWM TO TURN OFF
WHEN TEMP IS BELOW
T
MIN
–HYST
ENABLE
SELECTED PWM
RAMP-UP SPEED
SYNC FAN SPEED
MEASUREMENTS
V
CC
MEASUREMENT
(0x22)
FAST TACH
MEASUREMENTS
ENABLE THERM
THERM BOOST
(FAN MUST BE RUNNING)
CONFIGURATION 3
(0x78)
ENABLE CONTINUOUS
FAN SPEED
MEASUREMENT
(ONLY USED WHEN FANS ARE
POWERED BY DC AND NOT PWM)
REMOTE 1 TEMP CONTROLS
SELECTED PWM DRIVE (AFC MODE)
LOCAL TEMP CONTROLS SELECTED
PWM DRIVE (AFC MODE)
REMOTE 2 TEMP CONTROLS
SELECTED PWM DRIVE (AFC MODE)
SELECTED PWM DRIVE
RUNS FULL SPEED
SELECTED PWM DRIVE
DISABLED (DEFAULT)
FASTEST SPEED CALCULATED
BY LOCAL AND REMOTE 2 TEMP
CONTROLS SELECTED PWM DRIVE
FASTEST SPEED CALCULATED BY ALL
3 TEMPERATURE CHANNEL CONTROLS
MANUAL MODE. PWM DUTY CYCLE
REGISTERS (0x30-0x32) BECOME WRITABLE
FAN BEHAVIOR
FAN SPINUP
TIMEOUT
NO TIMEOUT
100ms
250ms (DEFAULT)
400ms
667ms
1s
2s
4s
PWM CONFIGURATION
(0x5C-0x5E)
1 PULSE PER REV
FAN TACH
PULSES PER REV
(0x7B) 2 PULSE PER REV
3 PULSE PER REV
4 PULSE PER REV
FAN 16-BIT MEASUREMENT
(0x28-0x2F)
LOW BYTE MUST BE READ FIRST.
WHEN THE LOW BYTE IS READ,
REGISTERS ARE LOCKED UNTIL THE
ASSOCIATED HIGH BYTE IS READ.
PWM
MIN
DUTY CYCLE
(AUTOMATIC MODE ONLY)
(0X64-0X66)
FANTACH 16-BIT
MINIMUM LIMIT
(0X54-0X5B)
PWM DUTY CYCLE
(MANUAL MODE ONLY)
(0x30-0x32)
8°C
10°C
13.33°C
16°C
20°C
26.67°C
32°C
40°C
53.33°C
80°C
2.5°C
2°C
3.33°C
4°C
5°C
6.67°C
PWM
FREQUENCY
±20mV
INPUT THRESHOLD
FOR 2-WIRE FANS
(AINL)
±40mV
±80mV
±130mV
BYPASS V
CCP
ATTENUATOR
THERM
SMBALERT
GPIO
MASK INTERRUPT?
(0x74,0x75)
INTERRUPT STATUS
(0x41, 0x42)
SMBALERT
SHUTDOWN
TACH 4
SET PIN 14/20
FUNCTIONALITY
CONFIGURATION 4
(0x7D)
INTERRUPT
GENERAL
VOLTAGES
FANS
TEMPERATURE
THERM
XNOR Test
(0x6F)
OPERATING
POINT
(0x33-0x35)
THERM AS
OVERTEMP
OUTPUT
THERM
F4P
AVERAGE TEMP
AND VOLTAGE
MEASUREMENTS
(SEE CONFIGURATION 2,
0x73)
SLOW IMPROVED
ACOUSTIC RAMP-UP
MAX FAN SPEED
(MAX PWM DUTY CYCLE)
(0x38-0x3A)
INVERT PWM
OUTPUT
V
CCP
T
MIN
. MIN TEMP THAT CAUSES
SELECTED FANS TO RUN
(0x67-0x69)
TEMPERATURE HYSTERESIS
(THYST)
(0x6D, 0x6E)
CONFIGURE
PIN 10
T
RANGE
11.0Hz
14.7Hz
22.1Hz
29.4Hz
35.3Hz
44.1Hz
58.8Hz
88.2Hz
ADT7467/ADT7468 PROGRAMMING BLOCK DIAGRAM
04498-0-044
Figure 85.
ADT7468
Rev. 3 | Page 81 of 81 | www.onsemi.com
OUTLINE DIMENSIONS
24 13
12
10.236
BSC
PIN 1
0.154
BSC
SEATING
PLANE
0.010
0.004 0.012
0.008
0.025
BSC
0.069
0.053
0.010
0.006
0.050
0.016
8°
0°
0.065
0.049
COPLANARITY
0.004
0.341
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AE
Figure 86. 24-Lead Shrink Small Outline Package [QSOP]
(RQ-24)
Dimensions shown in inches
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADT7468ARQ –40°C to +120°C 24-Lead QSOP RQ-24
ADT7468ARQ-REEL –40°C to +120°C 24-Lead QSOP RQ-24
ADT7468ARQ-REEL7 –40°C to +120°C 24-Lead QSOP RQ-24
ADT7468ARQZ
1
–40°C to +120°C 24-Lead QSOP RQ-24
ADT7468ARQZ-REEL
1
–40°C to +120°C 24-Lead QSOP RQ-24
ADT7468ARQZ-RL7
1
–40°C to +120°C 24-Lead QSOP RQ-24
EVAL-ADT7468EB Evaluation Board
1
Z = Pb-free part.
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products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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