16-Bit, Isolated,
Sigma-Delta Modulator
Data Sheet ADuM7701
Rev. 0 Document Feedback
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FEATURES
5 MHz to 21 MHz master clock input frequency
Offset drift vs. temperature: ±0.6 μV/°C maximum
SNR: 86 dB typical
16 bits, no missing codes
Full-scale analog input voltage range: ±320 mV
ENOB: 14 bits typical
IDD1: 10 mA maximum
On-board digital isolator
Operating temperature range: −40°C to +125°C
High common-mode transient immunity: 150 kV/μs minimum,
VDD2 = 3.3 V
Wide-body SOICs
16-lead SOIC_W
8-lead SOIC_IC with increased creepage
Safety and regulatory approvals (pending)
UL recognition
5700 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10: VIORM = 1270 VPEAK
DIN V VDE V 0884-11: VIORM = 1060 VPEAK
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Analog-to-digital and optoisolator replacement
FUNCTIONAL BLOCK DIAGRAM
V
DD1
ADuM7701
V
DD2
MCLKIN
MDAT
GND
2
GND
1
DATA
DECODER
CLK
ENCODER
DATA
ENCODER
Σ-Δ ADC
GAIN
V
IN+
V
IN–
CLK
DECODER
16234-001
Figure 1.
GENERAL DESCRIPTION
The ADuM7701 is a high performance, second-order, Σ-Δ
modulator that converts an analog input signal into a high
speed, single-bit data stream, with on-chip digital isolation
based on Analog Devices, Inc., iCoupler® technology. The
device operates from a 4.5 V to 5.5 V power supply range
(VDD1) and accepts a pseudo differential input signal of
±250 mV (±320 mV full-scale). The pseudo differential input
is ideally suited to shunt voltage monitoring in high voltage
applications where galvanic isolation is required.
The analog input is continuously sampled by a high performance
analog modulator and converted to a ones density digital output
stream with a data rate of up to 21 MHz. The original information
can be reconstructed with an appropriate sinc3 digital filter to
achieve an 86 dB signal-to-noise ratio (SNR) at 78.1 kSPS with a
256 decimation rate and a 20 MHz master clock. The serial
input and output operates from a 5 V or a 3 V supply (VDD2).
The serial interface is digitally isolated. High speed complementary
metal-oxide semiconductor (CMOS) technology, combined with
monolithic transformer technology, results in the on-chip
isolation providing outstanding performance characteristics,
superior to alternatives such as optocoupler devices. The
ADuM7701 device is available in both a 16-lead and an 8-lead
wide-body SOIC and has an operating temperature range of
−40°C to +125°C.
ADuM7701 Data Sheet
Rev. 0 | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 5
Insulation and Safety Related Specifications ............................ 5
Regulatory Information (Pending) ............................................ 5
DIN V VDE V 0884-10 Insulation Characteristics (Pending) .... 6
DIN V VDE V 0884-11 Insulation Characteristics (Pending) ..... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Insulation Ratings ......................................................................... 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ............................................ 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information .................................................................... 16
Analog Input ............................................................................... 16
Applications Information .............................................................. 18
Current Sensing Applications ................................................... 18
Voltage Sensing Applications .................................................... 18
Input Filter ................................................................................... 18
Digital Filter ................................................................................ 19
Interfacing to ADSP-CM4xx ..................................................... 20
Grounding and Layout .............................................................. 20
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
3/2019—Revision 0: Initial Versi on
Data Sheet ADuM7701
Rev. 0 | Page 3 of 22
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +125°C, MCLKIN frequency (fMCLKIN) =
20 MHz, tested with a sinc3 filter, and a 256 decimation rate, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits Filter output truncated to 16 bits
Integral Nonlinearity (INL)1 ±2 ±4 LSB
Differential Nonlinearity (DNL)1 ±0.99 LSB Guaranteed no missed codes to 16 bits
Offset Error1 ±0.05 ±0.13 mV Initial at TA = 25°C
±0.1 ±0.18 mV
Offset Drift vs. Temperature1 ±0.1 ±0.6 μV/°C
Offset Drift vs. VDD1 ±2.5 μV/V
Gain Error1 ±0.2 % FSR Initial at TA = 25°C
Gain Error Drift vs. Temperature1 ±12.5 ±28 ppm/°C
±8 ±18 μV/°C
Gain Error Drift vs. VDD1 ±5 ppm/V
ANALOG INPUT
Input Voltage Range −320 +320 mV Full-scale range
−250 +250 mV For specified performance
Input Common-Mode Voltage Range −0.2 to +0.8 V
Dynamic Input Current ±1 ±2 μA VIN+ = ±250 mV, VIN− = 0 V
0.05 μA VIN+ = 0 V, VIN− = 0 V
DC Leakage Current ±0.01 μA
Input Capacitance 25 pF
DYNAMIC SPECIFICATIONS VIN+ = 1 kHz
Signal-to-Noise-and-Distortion Ratio (SINAD)1 82 86 dB
SNR1 83 86 dB
Total Harmonic Distortion (THD)1 −84 −99 dB
Peak Harmonic or Spurious-Free Dynamic
Range Noise (SFDR)1
−97 dB
Effective Number of Bits (ENOB)1 13.3 14 Bits
ISOLATION COMMON-MODE TRANSIENT
IMMUNITY (CMTI)1
Common-mode voltage (|VCM|) = 2 kV
Static and Dynamic 75 150 kV/μs VDD2 = 5.5 V
150 kV/μs VDD2 = 3.3 V
LOGIC INPUTS CMOS with Schmitt trigger
Input High Voltage (VIH) 0.7 × VDD2 V
Input Low Voltage (VIL) 0.3 × VDD2 V
Input Current (IIN) ±0.6 μA
Input Capacitance (CIN) 10 pF
LOGIC OUTPUTS
Output High Voltage (VOH) VDD2 − 0.4 VDD2 − 0.2 V Output current (IOUT) = −4 mA
Output Low Voltage (VOL) 0.2 0.4 V IOUT = 4 mA
ADuM7701 Data Sheet
Rev. 0 | Page 4 of 22
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS VIN+ > 320 mV
VDD1 4.5 5.5 V
VDD2 3 5.5 V
VDD1 Current (IDD1) 8.2 10 mA
VDD2 Current (IDD2) 2 3 mA
Power Dissipation 51 71.5 mW VDD2 = 4.5 V to 5.5 V
47.6 66 mW VDD2 = 3 V to 3.6 V
1 See the Terminology section.
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, and TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to
ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit Description Min Typ Max
fMCLKIN 5 20 21 MHz Master clock input frequency
tMCLKIN 48 50 200 ns Master clock input period
t11 16 ns Data access time after MCLKIN rising edge
t21 5 ns Data hold time after MCLKIN rising edge
t3 0.4 × tMCLKIN ns Master clock low time
t4 0.4 × tMCLKIN ns Master clock high time
1 Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.5 × VDD2 as outlined in Figure 2. Measured with a ±20 μA load and a 25 pF
load capacitance.
Timing Diagram
MCLKIN
MDAT
1
SEE NOTE 1 OF TABLE 2 FOR FURTHER DETAILS.
t
4
t
MCLKIN
t
1
t
2
t
3
80%
0.5 × V
DD21
16234-002
Figure 2. Data Timing Diagram
Data Sheet ADuM7701
Rev. 0 | Page 5 of 22
PACKAGE CHARACTERISTICS
Table 3.
Parameter
1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Resistance (Input to Output) RI-O 1012 Ω
Capacitance (Input to Output) CI-O 1 pF Frequency = 1 MHz
1 The device is considered a 2-terminal device. For the 16-lead SOIC_W, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. For the 8-lead
SOIC_IC, Pin 1 to Pin 4 are shorted together and Pin 5 to Pin 8 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Test Conditions/Comments
Input to Output Momentary Withstand Voltage VISO 5700 min V rms 1 minute duration
Minimum External Air Gap (Clearance)
1, 2
16-Lead SOIC_W L(I01) 7.8 min mm Measured from input terminals to output
terminals, shortest distance through air
8-Lead SOIC_IC L(I01) 8.1 min mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage)1
16-Lead SOIC_W L(I02) 7.8 min mm
Measured from input terminals to output
terminals, shortest distance path along body
8-Lead SOIC_IC L(I02) 8.1 min mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.041 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >600 V DIN IEC 112/VDE 0303 Part 1
Isolation Group I Material Group (DIN VDE 0110, 1/89, Table I)
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤ 2000 m.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION (PENDING)
Table 5.
UL (Pending) CSA (Pending) VDE (Pending)
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component Acceptance
Notice 5A
Certified according to DIN V VDE V 0884-102,
reinforced insulation, VIORM = 1270 VPEAK,
VIOSM = 8000 VPEAK
5700 V rms Isolation Voltage Single
Protection
Basic insulation per CSA 60950-1-07 and IEC
60950-1, ADuM7701: 780 V rms (1102 VPEAK),
ADuM7701-8: 810 V rms (1145 VPEAK) maximum
working voltage3
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1. ADuM7701: 390 V rms (551 VPEAK),
ADuM7701-8 : 405 V rms (572 VPEAK) maximum
working voltage3
Certified according to DIN V VDE V 0884-11,
reinforced insulation, VIORM = 1060 VPEAK,
VIOSM = 8000 VPEAK
Reinforced insulation per IEC 60601-1, 250 V rms
(353 VPEAK) maximum working voltage
1 In accordance with UL 1577, each ADuM7701 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM7701 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
3 Rating is calculated for a pollution degree of 2 and a Material Group III. The ADuM7701 package material is rated by CSA to a CTI of >600 V and, therefore, Material Group I.
ADuM7701 Data Sheet
Rev. 0 | Page 6 of 22
DIN V VDE V 0884-10 INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms I to IV
For Rated Mains Voltage ≤450 V rms I to IV
For Rated Mains Voltage ≤600 V rms I to IV
CLIMATIC CLASSIFICATION 40/125/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE VIORM 1270 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC VPD(M) 2344 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD A VPR(M)
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 2032 VPEAK
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC 1524 VPEAK
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VIOTM 8000 VPEAK
SURGE ISOLATION VOLTAGE
1.2 µs Rise Time, 50 µs, 50% Fall Time VIOSM 8000 VPEAK
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE)1
Case Temperature TS 150 °C
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation PSO
16-Lead SOIC_W 1.43 W
8-Lead SOIC_IC 1.19 W
INSULATION RESISTANCE AT TS, VOLTAGE INPUT TO OUTPUT (VIO) = 500 V RIO >109 Ω
1 See Figure 3.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0050 100
AMBIENT TEMPERAT URE ( °C)
SAFE OPERATING POWER (W)
150 200
16-L E AD S O IC_W
8-L E AD S O IC_IC
16234-003
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10
Data Sheet ADuM7701
Rev. 0 | Page 7 of 22
DIN V VDE V 0884-11 INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 7.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms I to IV
For Rated Mains Voltage ≤450 V rms I to IV
For Rated Mains Voltage ≤600 V rms I to IV
CLIMATIC CLASSIFICATION 40/125/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE VIORM 1060 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPD(M) 1987 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD A VPR(M)
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 1696 VPEAK
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC 1272 VPEAK
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VIOTM 8000 VPEAK
SURGE ISOLATION VOLTAGE
1.2 µs Rise Time, 50 μs, 50% Fall Time VIOSM 8000 VPEAK
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE)1
Case Temperature TS 150 °C
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation PSO
16-Lead SOIC_W 1.43 W
8-Lead SOIC_IC 1.19 W
INSULATION RESISTANCE AT TS, VIO = 500 V RIO >109 Ω
1 See Figure 4.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0050 100
AMBIENT TEMPERAT URE ( °C)
SAFE OPERATING POWER (W)
150 200
16234-004
16-L E AD S O IC_W
8-L E AD S O IC_IC
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-11
ADuM7701 Data Sheet
Rev. 0 | Page 8 of 22
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective GNDx.
Table 8.
Parameter Rating
VDD1 to GND1 −0.3 V to +6 V
VDD2 to GND2 −0.3 V to +6 V
Analog Input Voltage to GND1 −1 V to 4.3 V
Digital Input Voltage to GND2 −0.3 V to VDD2 + 0.5 V
Digital Output Voltage to GND
2
−0.5 V to V
DD2
+ 0.5 V
Input Current to Any Pin Except Supplies1 ±10 mA
Output Current from Any Pin Except
Supplies
±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb-Free Temperature, Soldering
Reflow 260°C
Electrostatic Discharge (ESD)
Field Induced Charged Device Model
(FICDM)2
±1250 V
Human Body Model (HBM)3 ±4000 V
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) to latch up.
2 JESD22-C101, resistor, capacitor (RC) network,1 Ω, package capacitance, and
Class IV.
3 ESDA/JEDEC JS-001-2011, RC network: 1.5 kΩ, 100 pF, and Class 3A.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 9. Thermal Resistance
Package Type1 θJA2 ΨJC3 Unit
RI-8-1 105 9.25 °C/W
RW-16 87.25 10.4 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD-51.
2 θJA was calculated using the total power and maximum junction
temperature.
3 ΨJC was calculated using the package center case temperature.
ESD CAUTION
INSULATION RATINGS
The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the
Insulation Lifetime section for more details.
Table 10. Maximum Continuous Working Voltage
Parameter Insulation Rating1 Lifetime Conditions
Basic Insulation
AC Voltage
Bipolar Waveform 1129 VPEAK 20 years to 1000 ppm failure at 1129 VPEAK (798 V rms, 50 Hz/60 Hz sine wave)
Reinforced Insulation
AC Voltage
Bipolar Waveform 1060 VPEAK 20 years to 1 ppm failure at 1060 VPEAK (750 V rms, 50 Hz/60 Hz sine wave)
1 Insulation capability without regard to creepage limitations. Working voltage may be limited by the PCB creepage when considering rms voltages for components
soldered to a PCB (assumes Material Group I up to 1270 V rms), or package: RI-8-1 package creepage of 8.1 mm, and RW-16 package creepage of 7.8 mm, when
considering rms voltages for Material Group I.
Data Sheet ADuM7701
Rev. 0 | Page 9 of 22
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC1
NIC1
NIC1
VIN+
VDD1
GND1
VIN–
GND1
GND2
NOTES
1. NI C 1 = NOT INTE RNALLY CONNE CTED. THESE PINS ARE NOT INTERNAL LY CONNECTE D.
CONNECT TO VDD1, GND1, OR LEAVE F L OATING.
2. NI C 2 = NOT INTE RNALLY CONNE CTED. THESE PINS ARE NOT INTERNAL LY CONNECTE D.
CONNECT TO VDD2, GND2, OR LEAVE F L OATING.
NIC2
MDAT
NIC2
NIC2
GND2
VDD2
MCLKIN
1
2
3
4
8
7
6
5
16
15
14
13
9
10
11
12
ADuM7701
(No t t o Scale)
TOP VIEW
16234-005
Figure 5. 16-Lead SOIC_W Pin Configuration
Table 11. 16-Lead SOIC_W Pin Function Descriptions
Pin No. Mnemonic Description
1, 5, 6 NIC1 Not Internally Connected. These pins are not internally connected. Connect these pins to VDD1, GND1, or leave
floating.
2 VIN+ Positive Analog Input.
3 VIN− Negative Analog Input.
4, 8 GND1 Ground 1. These pins are the ground reference point for all circuitry on the isolated side.
7 VDD1 Supply Voltage, 4.5 V to 5.5 V. This pin is the supply voltage for the isolated side of the ADuM7701 and is relative to
GND1. For device operation, connect the supply voltage to Pin 7. Decouple the supply pin to GND1 with a 10 µF
capacitor in parallel with a 100 nF capacitor as close to the pin as possible.
9, 16
GND
2
Ground 2. These pins are the ground reference point for all circuitry on the nonisolated side.
10, 12, 15 NIC2 Not Internally Connected. These pins are not internally connected. Connect these pins to VDD2, GND2, or leave
floating.
11 MDAT Serial Data Output. The single-bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge.
13 MCLKIN Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on
the rising edge of the MCLKIN.
14 VDD2 Supply Voltage, 3 V to 5.5 V. This pin is the supply voltage for the nonisolated side and is relative to GND2.
Decouple this supply to GND2 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the pin as
possible.
ADuM7701 Data Sheet
Rev. 0 | Page 10 of 22
VDD1 1
VIN+ 2
VIN– 3
GND14
MDAT
8
GND2
7
VDD2
6
MCLKIN
5
ADuM7701
(No t t o Scale)
TOP VIEW
16234-006
Figure 6. 8-Lead SOIC_IC Pin Configuration
Table 12. 8-Lead SOIC_IC Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage, 4.5 V to 5.5 V. This pin is the supply voltage for the isolated side of the ADuM7701 and is relative to
GND1. For device operation, connect the supply voltage to Pin 1. Decouple the supply pin to GND1 with a 10 µF
capacitor in parallel with a 100 nF capacitor as close to the pin as possible.
2 VIN+ Positive Analog Input.
3 VIN− Negative Analog Input.
4 GND1 Ground 1. This pin is the ground reference point for all circuitry on the isolated side.
5 GND2 Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side.
6 MDAT Serial Data Output. The single-bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge.
7 MCLKIN
Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on
the rising edge of the MCLKIN.
8 VDD2 Supply Voltage, 3 V to 5.5 V. This pin is the supply voltage for the nonisolated side and is relative to GND2.
Decouple this supply to GND2 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the pin as
possible.
Data Sheet ADuM7701
Rev. 0 | Page 11 of 22
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, V DD2 = 5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, a n d f MCLKIN = 20 MHz, using a sinc3 filter with a
256 oversampling ratio (OSR), unless otherwise noted.
–140
–120
–100
–80
–60
–40
–20
0
0200 400 600 800 1000
PSRR (dB)
SUPPLY RIPPLE FREQUENCY (kHz)
16234-107
Figure 7. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Frequency
–140
–120
–100
–80
–60
–40
–20
0
0.1 110 100 1000
CMRR (dB)
COMMON-MODE RIPPLE FREQUENCY (kHz)
SHORTED V
IN±
INPUTS
200mV p - p SINE WAV E ON INPUTS
MCL KIN = 10MHz, SI NC3 OSR = 256
MCL KIN = 20MHz, SI NC3 OSR = 256
16234-108
Figure 8. Common-Mode Rejection Ration (CMRR) vs. Common-Mode Ripple
Frequency
70
72
74
76
78
80
82
84
86
88
90
0.1 110
SINAD (dB)
ANALOG I NP UT FRE QUENCY (KHz)
SINAD 10 MHz MCL KIN
SINAD 20 MHz MCL KIN
16234-109
Figure 9. SINAD vs. Analog Input Frequency
–160
–140
–120
–100
–80
–60
–40
–20
0
0510 15 20 25 30
MAG NITUDE ( dB)
FREQUENCY (kHz)
f
IN
= 1kHz
SNR = 86. 6dB
SINAD = 86.3dB
THD = –97.5dB
16234-110
Figure 10. Typical Fast Fourier Transform (FFT)
–1.0
–0.8
–0.6
–0.4
0.4
–0.2
0.2
0
0.6
0.8
1.0
010 20 30 40 50 60
DNL ERRO R ( LSB)
CODE (In Thousands)
16234-111
Figure 11. Typical DNL Error
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
010 20 30 40 50 60
INL ERROR ( LSB)
CODE (In Thousands)
16234-112
Figure 12. Typical INL Error
ADuM7701 Data Sheet
Rev. 0 | Page 12 of 22
0797
5006
12162 12251
4829
819
0
0
2
4
6
8
10
12
14
32765 32766 32767 32768 32769 32770 32771 32772
HITS PER CODE (K)
CODE
V
IN+
= V
IN–
= 0V
16234-113
Figure 13. Histogram of Codes at the Code Center
60
70
80
90
100
–40 –25 –10 520 35 50 65 80 95 110 125
SNR AND SI NAD ( dB)
TEMPERATURE (°C)
SNR
SINAD
f
IN = 1kHz
16234-114
Figure 14. SNR and SINAD vs. Temperature
–120
–110
–100
–90
–80
–70
–60
–40 –25 –10 520 35 50 65 80 95 110 125
THD AND S FDR (dB)
TEMPERATURE (°C)
THD
SFDR
16234-115
Figure 15. THD and SFDR vs. Temperature
–100
–80
–60
–40
–20
0
20
40
60
80
100
–40 –25 –10 520 35 50 65 80 95 110 125
OFF SET (µV)
TEMPERATURE (°C)
VIN+ = VIN– = GNDx
DEVICE 1
DEVICE 2
DEVICE 3
16234-116
Figure 16. Offset vs. Temperature
–100
–80
–60
–40
–20
0
20
40
60
80
100
4.50 4.75 5.00 5.25 5.50
OFF SET (µV)
V
DD1
(V)
16234-117
Figure 17. Offset vs. VDD1
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
–40 –25 –10 520 35 50 65 80 95 110 125
GAI N E RROR (mV)
TEMPERATURE (°C)
DEVICE 1
DEVICE 2
DEVICE 3
16234-118
Figure 18. Gain Error vs. Temperature
Data Sheet ADuM7701
Rev. 0 | Page 13 of 22
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
4.50 4.75 5.00 5.25 5.50
GAI N E RROR (%F S R)
V
DD1
(V)
16234-119
Figure 19. Gain Error vs. VDD1
0
2
4
6
8
10
12
14
16
4.50 4.75 5.00 5.25 5.50
IDD1 (mA)
VDD1 (V)
MCL KIN = 20MHz, –40°C
MCL KIN = 20MHz, +25° C
MCL KIN = 20MHz, +125° C
MCL KIN = 10MHz, –40°C
MCL KIN = 10MHz, +25° C
MCL KIN = 10MHz, +125° C
16234-120
Figure 20. IDD1 vs. VDD1 at Various Temperatures and Clock Rates
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
–250 –125 0125 250
I
DD1
(mA)
V
IN+
(mV)
T
A
= –40° C
T
A
= 0° C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
DC INPUT
16234-121
Figure 21. IDD1 vs. VIN+ DC Input at Various Temperatures
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3.0 3.5 4.0 4.5 5.0 5.5
IDD2 (mA)
VDD2 (V)
MCL KIN = 20MHz, –40°C
MCL KIN = 20MHz, +25° C
MCL KIN = 20MHz, +125° C
MCL KIN = 10MHz, –40°C
MCL KIN = 10MHz, +25° C
MCL KIN = 10MHz, +125° C
16234-122
Figure 22. IDD2 vs. VDD2 at Various Temperatures and Clock Rates
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–250 –125 0125 250
IDD2 (mA)
VIN+ (mV)
DC INPUT
TA = –40° C
TA = 0° C
TA = +25°C
TA = +85°C
TA = +125°C
16234-123
Figure 23. IDD2 vs. VIN+ DC Input at Various Temperatures
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
–320 –240 –160 –80 080 160 240 320
I
IN+
(u A)
V
IN+
(mV)
MCL KIN = 10MHz
MCL KIN = 20MHz DC INPUT
16234-124
Figure 24. VIN+ Current (IIN+) vs. VIN+ DC Input
ADuM7701 Data Sheet
Rev. 0 | Page 14 of 22
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the analog-
to-digital converter (ADC).
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16-bit level,
and specified positive full scale, +250 mV (VIN+ − VIN−),
Code 58,368 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (32,768 for
the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Offset Drift vs. Temperature
The offset drift is calculated using the box method, as shown
by the following equation:
Offset Drift = ((VoltageMAX − VoltageMIN)/TΔ)
where:
VoltageMAX is the maximum offset error point recorded.
VoltageMIN is the minimum offset error point recorded.
TΔ is the difference in temperature between the maximum
and minimum operating range.
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset
error is adjusted out. Negative full-scale gain error is the deviation
of the specified negative full-scale code (7168 for the 16-bit level)
from the ideal VIN+ − VIN− (−250 mV) aer the oset error is
adjusted out.
Gain Error Drift vs. Temperature
The gain error drift (GED) is calculated using the box method,
as shown by the following equation:
GED (ppm) = ((VoltageMAX − VoltageMIN)/(VoltageFS ×
TΔ)) × 106
where:
VoltageMAX is the maximum gain error point recorded.
VoltageMIN is the minimum gain error point recorded.
VoltageFS is the analog input range full scale.
TΔ is the difference in temperature between the maximum
and minimum operating range.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fS/2), including harmonics,
but excluding dc.
Signal-to-Noise Ratio (SNR)
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process: the greater the number of levels, the smaller
the quantization noise. The theoretical SNR for an ideal N-bit
converter with a sine wave input is given by
SNR = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Common-Mode Transient Immunity (CMTI)
The isolation CMTI specifies the rate of the rise and fall of a
transient pulse applied across the isolation boundary, beyond
which clock or data is corrupted. Both the rate of change and
the absolute common-mode voltage of the pulse are recorded.
The ADuM7701 is tested under both static and dynamic CMTI
conditions. Static testing detects single-bit errors from the
device. Dynamic testing monitors the filtered data output for
variations in noise performance to a randomized application
of the CMTI pulse.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the
fundamental. It is defined as
22222
++++
(dB) = 20log V2 V3 V4 V5 V6
THD V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious-Free Dynamic Range (SFDR) Noise
Peak harmonic or SFDR noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2, excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it is a noise peak.
Data Sheet ADuM7701
Rev. 0 | Page 15 of 22
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution for
an N-bit converter is defined as
Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise)
The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at ±250 mV
frequency, f, to the power of a +250 mV p-p sine wave applied
to the common-mode voltage of VIN+ and VIN− of frequency, fS, as
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale (±250 mV) transition point due to a
change in power supply voltage from the nominal value.
ADuM7701 Data Sheet
Rev. 0 | Page 16 of 22
THEORY OF OPERATION
CIRCUIT INFORMATION
The ADuM7701 isolated Σ-Δ modulator converts an analog
input signal to a high speed (21 MHz maximum), single-bit data
stream. The time average single-bit data from the modulator is
directly proportional to the input signal. Figure 25 shows a
typical application circuit where the ADuM7701 provides
isolation between the analog input, a current sensing resistor
or shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
ANALOG INPUT
The pseudo differential analog input of the ADuM7701 is
implemented with a switched capacitor circuit. This circuit
implements a second-order modulator stage that digitizes the
input signal to a single-bit output stream. The sample clock
(MCLKIN) provides the clock signal for the conversion process
as well as the output data framing clock. This clock source is
externally supplied to the ADuM7701. The analog input signal
is continuously sampled by the modulator and compared to
an internal voltage reference. A digital stream that accurately
represents the analog input over time appears at the output of
the converter (see Figure 26).
A differential signal of 0 V ideally results in a stream of
alternating 1s and 0s at the MDAT output pin. This output is
high 50% of the time and low 50% of the time. A differential
input of 250 mV produces a stream of 1s and 0s that are high
89.06% of the time. A differential input of −250 mV produces a
stream of 1s and 0s that are high 10.94% of the time.
A differential input of 320 mV ideally results in a stream of all
1s. A differential input of −320 mV ideally results in a stream of
all 0s. The ADuM7701 absolute full-scale range is ±320 mV, and
the specified full-scale performance range is ±250 mV, as shown
in Table 13.
Table 13. Analog Input Range
Analog Input Voltage Input (mV)
Positive Full-Scale (+FS) Value +320
Positive Specified Performance +250
Zero 0
Negative Specified Performance −250
Negative Full-Scale (−FS) Value −320
GATED
DRIVE
CIRCUIT
GATED
DRIVE
CIRCUIT
FLOATING
POWER SUPPLY
FL
O
A
TING
POWER SUPPLY NONISOLATED
5V/3.3V
R
SHUNT
–400V
–400V
MOTOR
5.1V
V
DD1
V
IN+
Σ-Δ
MOD/
ENCODER
DECODER ENCODER
DECODER
V
IN–
GND
1
V
DD2
MDAT
CS
SCLK
SDAT
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP
MCLKIN
GND
2
V
DD
SINC3 FILTER*
MDAT
MCLK
10µF100nF
GND
ADuM7701
10Ω
220pF
10µF 100nF
10Ω
220pF
16234-007
Figure 25. Typical Application Circuit
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
16234-008
Figure 26. Analog Input vs. Modulator Output
Data Sheet ADuM7701
Rev. 0 | Page 17 of 22
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because this filter is one order higher than that of the ADuM7701
modulator, which is a second-order modulator. When a
256 decimation rate is used, the resulting 16-bit word rate is
78.1 kSPS, assuming a 20 MHz external clock frequency. See the
Digital Filter section for more detailed information on the sinc
filter implementation. Figure 27 shows the transfer function of
the ADuM7701 relative to the 16-bit output.
65535
58368
SPECIFIED RANG E
ANALOG I NP UT
7168
–320mV –250mV +250mV +320mV
0
ADC CODE
16234-009
Figure 27. Filtered and Decimated 16-Bit Transfer Function
ADuM7701 Data Sheet
Rev. 0 | Page 18 of 22
APPLICATIONS INFORMATION
CURRENT SENSING APPLICATIONS
The ADuM7701 is ideally suited for current sensing applications
where the voltage across a shunt resistor (RSHUNT) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the ADuM7701.
The ADuM7701 provides isolation between the analog input
from the current sensing resistor and the digital outputs. By
selecting the appropriate shunt resistor value, a variety of current
ranges can be monitored.
Choosing RSHUNT
The shunt resistor (RSHUNT) values used in conjunction with
the ADuM7701 are determined by the specific application
requirements in terms of voltage, current, and power. Small
resistors minimize power dissipation, whereas low inductance
resistors prevent any induced voltage spikes, and high tolerance
devices reduce current variations. The final values chosen are
a compromise between low power dissipation and accuracy.
Higher value resistors use the full performance input range of
the ADC, thus achieving maximum SNR performance. Low
value resistors dissipate less power but do not use the full
performance input range. The ADuM7701, however, delivers
excellent performance, even with lower input signal levels,
allowing low value shunt resistors to be used while maintaining
system performance.
To choose a suitable shunt resistor, first determine the current
through the shunt. Calculated the shunt current for a 3-phase
induction motor as
IRMS = PW/(1.73 × V × EF × PF)
where:
IRMS is the motor phase current (A rms).
PW is the motor power (W).
V is the motor supply voltage (V ac).
EF is the motor efficiency (%).
PF is the power efficiency (%).
To determine the shunt peak sense current (ISENSE), consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the ADuM7701 (±250 mV) by the peak sense
current to yield a maximum shunt value.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced, and less of the ADC input
range can be used. Figure 28 shows the SINAD performance
characteristics and the ENOB of resolution for the ADuM7701
for different input signal amplitudes. The performance of the
ADuM7701 at lower input signal ranges allows smaller shunt
values to be used while still maintaining a high level of
performance and overall system efficiency.
90
85
80
75
SINAD (dB)
70
65
60
050 100 150
V
IN+
(mV)
200 250
fIN
= 1kHz
MCL KIN = 20MHz
V
DD1
= 5V
V
DD2
= 3V
T
A
= 25° C
14-BIT
ENOB
13-BIT
ENOB
12-BIT
ENOB
11-BIT
ENOB
16234-010
Figure 28. SINAD vs. VIN+ AC Input Signal Amplitude
RSHUNT must dissipate the current2 × resistance (I2R) power
losses. If the power dissipation rating of the resistor is exceeded,
the value may drift, or the resistor may be damaged, resulting in
an open circuit. This open circuit can result in a differential
voltage across the terminals of the ADuM7701, in excess of the
absolute maximum ratings. If ISENSE has a large high frequency
component, choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The ADuM7701 can also be used for isolated voltage
monitoring. For example, in motor control applications, the
device can be used to sense the bus voltage. In applications where
the voltage being monitored exceeds the specified analog input
range of the ADuM7701, a voltage divider network can be used
to reduce the voltage being monitored to the required range.
INPUT FILTER
In a typical use case for directly measuring the voltage across a
shunt resistor, the ADuM7701 can be connected directly across
the shunt resistor with a simple RC low-pass filter on each input.
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure 29. An
RC low-pass filter is placed on both the analog input pins.
Recommended values for the resistors and capacitors are 10 Ω and
220 pF, respectively. If possible, equalize the source impedance
on each analog input to minimize offset.
R
V
IN–
R
V
IN+
C
C
ADuM7701
16234-012
Figure 29. RC Low-Pass Filter Input Network
Data Sheet ADuM7701
Rev. 0 | Page 19 of 22
The input filter configuration for the ADuM7701 is not limited
to the low-pass structure shown in Figure 29. The differential RC
filter configuration shown in Figure 30 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
R
V
IN–
R
V
IN+
C
ADuM7701
16234-011
Figure 30. Differential RC Filter Network
DIGITAL FILTER
The output of the ADuM7701 is a continuous digital bit stream.
To reconstruct the original input signal information, this output
bit stream must be digitally filtered and decimated. A sinc filter
is recommended due to simplicity of the filter. A sinc3 filter is
recommended because the filter is one order higher than that of
the ADuM7701 modulator, which is a second-order modulator.
The type of filter selected, the decimation rate, and the modulator
clock used determines the overall system resolution and
throughput rate. The higher the decimation rate, the greater the
system accuracy, as shown in Figure 31. However, there is a
trade-off between accuracy and throughput rate and, therefore,
higher decimation rates result in lower throughput solutions.
Note that for a given bandwidth requirement, a higher MCLKIN
frequency can allow higher decimation rates to be used, resulting
in higher SNR performance.
100
80
60
40
SNR (dB)
20
010 100
DECIMATION RATE (MHz)
1000
f
IN
= 1kHz
16234-013
Figure 31. SNR vs. Decimation Rate of Sinc3 Filter Order
A sinc3 filter is recommended for the ADuM7701. This filter
can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP). Equation 1
describes the transfer function of a sinc filter.
DR
1
1
1
()= 1
N
Z
HZ DR Z
(1)
where:
Z is the sample.
DR is the decimation rate.
N is the sinc filter order.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
Throughput = MCLK/DR (2)
where MCLK is the modulator clock frequency
As the decimation rate increases, the data output size from
the sinc filter increases. The output data size is expressed in
Equation 3. The 16 most significant bits are used to return a
16-bit result.
Data Size = N × log2 DR (3)
For a sinc3 filter, the −3 dB lter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc filter are summarized in Table 14.
Table 14. Sinc3 Filter Characteristics for 20 MHz MCLKIN
Decimation Ratio (DR) Throughput Rate (kHz) Output Data Size (Bits) Filter Response (kHz)
32 625 15 163.7
64 312.5 18 81.8
128 156.2 21 40.9
256 78.1 24 20.4
512 39.1 27 10.2
ADuM7701 Data Sheet
Rev. 0 | Page 20 of 22
INTERFACING TO ADSP-CM4xx
The ADSP-CM4xx family of mixed-signal control processors
contains an on-chip sinc filter and clock generation modules for
direct connection to the ADuM7701 MCLKIN and MDAT pins.
The ADSP-CM4xx can process bit streams from four
ADuM7701 devices using a pair of configurable sinc filters for
each bit stream. The primary sinc filter of each pair produces the
filtered and decimated output for the pair. The output can be
decimated to any integer rate between 8 times and 256 times
lower than the input rate. The four secondary sinc filters are low
latency filters with programmable positive and negative
overrange detection comparators that can detect system fault
conditions
Figure 32 shows the typical interface between the ADuM7701
and the ADSP-CM4xx. Additional information on the
configuration of the sinc filter modules in the ADSP-CM4xx
can be found in the AN-1265 Application Note.
SINC PAIR n
PRIMARY
SECONDARY
LIMIT
CONTROL FOR GROUP n
MODULATOR CLOCK n
ADSP-CM40xF
1
ADuM7701
1
MDAT
MCLKIN SINC0_CLK0
SINC0_D0
1
ADDITIONAL PINS OMITTED FOR CLARITY
16234-014
Figure 32. Interfacing the ADuM7701 to the ADSP-CM4xx
GROUNDING AND LAYOUT
It is recommended to decouple the VDD1 supply with a 10 μF
capacitor in parallel with a 100 nF capacitor to GND1. Decouple
the VDD2 supply with a 10 μF capacitor in parallel with a 100 nF
capacitor to GND2. In applications involving high common-
mode transients, ensure that board coupling across the isolation
barrier is minimized. Furthermore, design the board layout so
that any coupling that occurs equally affects all pins on a given
component side. Failure to ensure equal coupling can cause
voltage differentials between pins to exceed the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. Place any decoupling used as close to the supply pins as
possible.
Minimize series resistance in the analog inputs to avoid any
distortion effects, especially at high temperatures. If possible,
equalize the source impedance on each analog input to minimize
offset. Check for mismatch and thermocouple effects on the analog
input PCB tracks to reduce offset drift.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM7701.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to failure
at the actual working voltage. The values shown in Table 10
summarize the peak voltage for 37.5 years of (reinforced) service
life for a bipolar, ac operating condition and the maximum VDE
approved working voltages.
These tests subjected the ADuM7701 to continuous cross isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time to failure values of these units were recorded and used to
calculate the acceleration factors. These factors were then used
to calculate the time to failure under the normal operating
conditions. The values shown in Table 10 are the lesser of the
following two values:
The value that ensures at least a 37.5 year lifetime of
continuous (reinforced) use.
The maximum VDE approved working voltage.
The lifetime of the ADuM7701 is guaranteed using a bipolar
ac waveform as shown in Figure 33.
0V
R
A
TED PEAK VOLT
A
GE
16234-015
Figure 33. Bipolar AC Waveform, 50 Hz or 60 Hz
Data Sheet ADuM7701
Rev. 0 | Page 21 of 22
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
09-17-2014-B
85
4
1
SEATING
PLANE
COPLANARITY
0.10
1.27 BSC
1.04
BSC
6.05
5.85
5.65
7.60
7.50
7.40
2.65
2.50
2.35
0.75
0.58
0.40
0.30
0.20
0.10
2.45
2.35
2.25
10.51
10.31
10.11
0.51
0.41
0.31
PIN 1
MARK
8°
0°
0.33
0.27
0.20
0.75
0.50
0.25 45°
Figure 35. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
ADuM7701 Data Sheet
Rev. 0 | Page 22 of 22
ORDERING GUIDE
Model1, 2 Temperature Range Package Description
Package
Option
ADuM7701BRWZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADuM7701BRWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADuM7701BRWZ-RL7 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADuM7701-8BRIZ −40°C to +125°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1
ADuM7701-8BRIZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1
ADuM7701-8BRIZ-RL7 −40°C to +125°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1
EV-ADuM7701-8FMCZ Evaluation Board
1 Z = RoHS-Compliant Part.
2 The EV-ADuM7701-8FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board.
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D16234-0-3/19(0)
